JP4387753B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a technique for incorporating a row relief circuit into a read-only memory (ROM).

  In the conventional semiconductor memory device, the data content of the ROM is determined by the presence or absence of vias or contacts. Alternatively, the dose amount in the ion implantation for adjusting the threshold voltage (Vth) of the transistor can be made large or small. Since the data content of the ROM can be freely designed for each product, the circuit for relieving the data content of the ROM is required to be versatile. In the prior art, the relief circuit is configured by an additional circuit such as an error code correction (ECC) circuit. However, when an ECC circuit is to be configured, the increase in circuit scale becomes so large that it cannot be ignored. For example, if an ECC circuit is attached to an 8-bit output (IO) ROM, an additional 4 bits are required. This means that the total number of memory cells is 1.5 times. Therefore, the area increase is not normally allowed. Since the user programs the program via, configuring the relief circuit is considered to be a significant circuit increase such as addition of an ECC bit.

  On the other hand, since an additional circuit is inserted into the data path with respect to the access time, a data delay occurs in the additional circuit. Further, since an operation between different bits is required in the additional circuit, the access time is further delayed, and the increase in the access time is increased to an unacceptable level.

    On the other hand, when the number of memory cells discharging one bit line exceeds half of the memory cells connected to the bit line, the logical data opposite to the write request is stored in the memory cell connected to the bit line. A method of writing data in a read-only memory, which is characterized by writing data, has already been disclosed (Patent Document 1). This read-only memory has a feature in that the logic is inverted so that many cells that are turned off are arranged in the bit line direction, and there is a contact at the end of the bit line that selects whether to pass the inverter or to bypass. . Also disclosed is stability by reducing the off-leakage current of the memory cell transistor.

    Alternatively, the number of memory cells that can be controlled to be turned on / off is reduced to reduce power consumption, and the memory cells are configured so that a load (charge) capacity is not applied to the bit line and the word line as much as possible in the always-off memory cell. Also, a semiconductor memory device having a higher access time has already been disclosed (Patent Document 2). In this semiconductor memory device, a plurality of bit lines are bundled into one line via a switch controlled by the Y decoder output, and whether or not the sense amplifier output is inverted is set by the contact of the input line, and is turned off when selected. It is characterized in that power consumption is reduced by setting the number of cells in the state to increase in the bit line direction.

Furthermore, as a basic structure of the semiconductor memory device, a “conventional diffusion layer programming ROM”, a “VIA-2 contact programming ROM” that contacts a via in the second layer in a structure having a two-layer via, “New (NEW) VIA-2 contact programming ROM” in which the memory cell layout is devised is known (Non-patent Document 1).
JP 7-249297 A JP-A-9-120893 Wai Kai Chen, “VLSI Handbook”, IEEE Press, p. 48-6 to 48-7, 2000 (WAI-KAI CHEN Editor in-Chief, “THE VLSI HANDBOOK”, A CRC Handbook Published in Cooperation with IEEE Press, pp.48-6-48-7, 2000)

  Generally, very few ROMs are provided with a relief circuit because of the above problems. In a conventional ROM, the drain and bit line of a memory cell transistor composed of an n-channel transistor are connected by a contact or via, whereby the precharged bit line is discharged and the low (L) level is read and not connected. Thus, the ROM data is determined by reading the high (H) level of the precharge level with the sense amplifier. Here, in the conventional circuit configuration, when there is a bit line in which most of the ROM data is set to logic “0”, this bit line has the following problems. When an attempt is made to read a high (H) level in this bit line, most of the ROM data is set to logic “0”, and therefore flows to the n-channel transistor of the memory cell that is turned off (OFF). The total off-leakage current increases. For this reason, although power consumption increases, there is a possibility that the high (H) level cannot be read correctly because the total off-leakage current is further increased. If most of the ROM data is set to logic “0”, if the number of program vias or contacts is large, it becomes sensitive to a process failure caused by contacts, leading to a decrease in product yield.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device using ROM macro row redundancy.

In order to achieve the above object, the present invention is characterized in that (a) a plurality of word lines extending in the row direction and a plurality of bit lines extending in the column direction are provided. A memory cell array in which memory cells composed of series circuits of switching elements and program elements are arranged at the intersecting positions, and (b) the same number of spare word lines and bit lines as the outputs extending in the row direction, respectively. A redundancy memory cell array in which series circuits are arranged; (c) a row decoder that drives a plurality of word lines of the memory cell array; (d) a row decoder additional circuit that drives a plurality of spare word lines; and (e) a plurality of bits. A precharge circuit for precharging the line, a column select circuit connected to the (f) precharge circuit for selecting the bit line, and (g) a column select. And a sense amplifier circuit for detecting data stored in the memory cell and driving the word line and the spare word line simultaneously to relieve the low-level reading of the bit line. It is a summary.

  According to the semiconductor memory device of the present invention, since the number of relief rows is the same as the number of outputs (IO), the occupancy rate of the relief circuit is extremely small as compared with a method such as ECC, and the movement of the relief row depends on user data. Therefore, it is represented by a certain program via, and therefore, data can be easily created as compared with ECC or the like. Furthermore, since no additional circuit is generated in the column system, the influence on the access time is extremely small. Further, by combining with a signal inversion output circuit for inverting the signal of the bit line, the number of program vias or contacts for setting ROM data to logic “0” can be reduced. Thereby, the yield of the semiconductor device can be improved.

  The semiconductor memory device according to the embodiment of the present invention is characterized in that it is applied to a ROM redundancy circuit. In order to save the row address, the same number of rows as the number of output lines (number of IO lines) is used, and row (L) data is programmed for each output (IO) in each row. By driving the relief row simultaneously with the normal operation row by the signal comparing the row address signal and the relief information, and forcibly driving the corresponding bit line BL to the low (L) level, the “0” data read failure, that is, The operation mode in which the bit line BL does not become low (L) is relieved. In a relief circuit that realizes row redundancy of a mask ROM assuming a via program, each data output (IO) has a transistor that extracts a precharged charge on a bit line (BL).

 Next, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or similar parts are denoted by the same or similar reference numerals. Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
FIG. 1 shows an overall block configuration of a ROM according to a first embodiment of the present invention. As shown in FIG. 1, the ROM includes a ROM area composed of a memory cell array 10 and a redundancy memory cell array 26, a row decoder 20 for selecting a row, and a row decoder adding circuit 28 for selecting the redundancy memory cell array 26. , An address control circuit 22 for row address control, a precharge circuit 12 for precharging the bit line in the column direction, a column select circuit 14 for selecting the bit line in the column direction, and a signal are detected. A sense amplifier circuit 16, an output buffer circuit 18 for amplifying and reproducing the detected signal, a read control circuit 24, a signal from the address control circuit 22 and a signal from the read control circuit 24 are compared, and a row decoder And a relief address comparison circuit 30 for outputting to the additional circuit 28.

  The address control circuit 22 is connected to y row address signal lines for transmitting row address signals RA (y-1) -RA (0), and y output lines are connected to a row decoder. Yes. To the read control circuit 24, x column address signal lines for transmitting column address signals CA (x-1) to CA (0) are connected, and a clock signal CLK and a chip enable signal CEN are input. ing. Further, the read control circuit 24 includes a precharge signal PRECH for the precharge circuit 12, a column select signal CLS for the column select circuit 14, a sense amplifier enable signal SAE for the sense amplifier circuit 16, and an output buffer circuit. 18 is provided with an output buffer enable signal OLE, and column address signals CA (x−1) −CA (0) and row address signals RA (y−1) −RA ( 0) and a signal corresponding to the clock signal CLK are provided, and a row address signal is output to the row decoder adding circuit 28. The row decoder addition circuit 28 receives the row address signal from the relief address comparison circuit 30 and selects the designated word line WL in the redundancy memory cell array 26. As shown in FIG. 1, the number of output lines of the row decoder adding circuit 28 is m, which is equal to the number m of output data lines. Further, m output signal lines O (m−1) -O (0) are connected to the output buffer circuit 18.

  In the ROM, a column address signal line to which column address signals CA (x−1) −CA (0) are transmitted is selected, and the selected bit line is charged while the selected bit line BL is determined. Is done. Thereafter, when the clock signal CLK is input, the word line WL at the address specified by the row address signals RA (y−1) −RA (0) is selected, and the n-channel transistor of the corresponding memory cell is turned on. At that time, it is determined whether or not the bit line BL is discharged with or without vias. Then, the data of the bit line BL is read through the column select circuit 14, the sense amplifier circuit 16, and the output buffer circuit 18 to m output signal lines O (m-1) -O (0). The chip enable signal CEN is a signal for selecting either ROM operation or standby. If the chip enable signal CEN is disabled (standby), the read operation can be performed even if the clock signal CLK is input. Not done.

  The characteristic relief operation of the ROM of the present invention is as follows. That is, the input address signals (RA, CA) determined by the row address signals RA (y-1) -RA (0) and the column address signals CA (x-1) -CA (0) are determined and the clock signal CLK is input. When reading data, if a defective address (that is, not “0”) is selected, the corresponding address of the redundancy memory cell array 26 provided with the same ROM code is selected for relief. The correct data (“0”) is read out.

  The function of each block is as follows. The address control circuit 22 takes in the row address signal in the row address signals RA (y−1) −RA (0). The row decoder 20 selects a designated word line WL by decoding a row address signal. As described above, the read control circuit 24 sends an internal control signal to each block. The memory cell array 10 corresponds to a ROM code storage block. The precharge circuit 12 precharges the bit line BL before reading data from the memory cell array 10. For example, a high (H) level is set. The column select circuit 14 selects the bit line BL designated by the input column address signals CA (x−1) −CA (0). The sense amplifier circuit 16 amplifies the data read from the memory cell array 10 to the bit line BL and transmits it to the output buffer circuit 18. The output buffer circuit 18 outputs data from the sense amplifier circuit 16.

  When the defective address is selected, the relief address comparison circuit 30 sends a row address signal for selecting the redundancy memory cell array 26 to the row decoder addition circuit 28. The row decoder addition circuit 28 receives the row address signal from the relief address comparison circuit 30 and selects the designated word line WL in the redundancy memory cell array 26.

The redundancy memory cell array 26 constitutes a spare memory cell array for relieving a defective address.

(Basic cell structure)
The basic memory cell structure of the semiconductor memory device according to the first embodiment of the present invention includes “conventional diffusion layer programming ROM”, “VIA-2 contact programming ROM”, “ Any of the “new (NEW) VIA-2 contact programming ROM” structures can be applied. Further, it is of course possible to apply a ROM structure using the most basic fuse cutting instead of the “conventional diffusion layer programming ROM”. In the semiconductor memory device using the ROM redundancy repair circuit according to the embodiment of the present invention, any of the conventionally known basic structures of memory cells can be applied.

As shown in FIG. 2, the basic circuit configuration of the memory element used in the semiconductor memory device according to the first embodiment of the present invention is connected to the intersection of the bit line BL _j and the word line WL _i. A metal oxide semiconductor (MOS) transistor N _ij, and program elements (PGV) 32 and 34 connected between the drain of the MOS transistor N _ij and the bit line BL _j . Bit line BL _j are connected through a bit line contact hole 36 precharge circuit 12 which is an external circuit of the memory cell array 10, column select circuit 14, the sense amplifier circuit 16 or the like. The word line WL _i is connected to the row decoder 20 which is an external circuit of the memory cell array 10 through the word line contact hole 38. 2A corresponds to a circuit representation in the case where the program element 32 in the open state is provided, and FIG. 2B corresponds to a circuit representation in the case where the program element 34 in the short state is provided.

In FIG. 2, ROM data is held depending on the presence / absence of conduction of the program element (PGV). That is, for example, as shown in the circuit diagram of FIG. 2A, when the open program element 32 is provided, the bit line BLj is in a high level (H) state, and ROM data “1” is stored. The As shown in the circuit diagram of FIG. 2B, when the program element 34 is in a short state, the bit line BL _j is in a low level (L) state, and ROM data “0” is stored.

FIG. 3 shows a 1 × 4 matrix circuit representation of a portion of the memory cell array 10 of the semiconductor memory device according to the first embodiment of the present invention. In FIG. 3, MOS transistors N _ij−1 , N _ij , N _{ij + 1} , N _{ij + 2} are commonly connected to a word line WL _i and each drain has a bit line BL _j via a program element (PGV). _-1 , BL _j , BL _{j + 1} , and BL _{j + 2} constitute a 1 × 4 matrix circuit.

The example of FIG. 3 shows an example in which open, open, short, and short state program elements are connected to the MOS transistors N _ij−1 , N _ij , N _{ij + 1} , and N _{ij + 2} from the left. Has been.

FIG. 4 is a schematic plan pattern diagram corresponding to a 2 × 4 matrix circuit representation obtained by extracting a part of the memory cell array 10 of the semiconductor memory device according to the first embodiment of the present invention. The portion of the 1 × 4 matrix related to the word line WL _i corresponds to FIG. 3, and the portion related to the word line WL _{i + 1} is also drawn. MOS transistors N _ij−1 , N _ij , N _{ij + 1} , and N _{ij + 2} having gates commonly connected to the word line WL _i have the program element PGV corresponding to FIG. Since it is programmed to a short state and a short state, the open / short state is expressed by the presence / absence of the bit line contact CB representing the program via with the bit line in the plan pattern diagram of FIG. The sources of the respective MOS transistors are commonly connected to the ground line (GND) via the source line contact CS. The word lines WL _i and WL _{i + 1} are formed of polysilicon and are arranged in directions orthogonal to the bit lines BL _j−1 , BL _j , BL _{j + 1} and BL _{j + 2} , respectively.

FIGS. 5A and 5B are schematic element cross-sectional structure diagrams taken along lines II and II-II in the plan pattern diagram of FIG. The structure shown in FIG. 5 shows the most basic schematic structure diagram that defines the memory state of the ROM by the presence or absence of program vias or program contacts. Further, it can be expanded to the aforementioned VIA-2 contact programming ROM structure or the new (NEW) VIA-2 contact programming ROM structure. Of course, as described above, the conventional diffusion layer programming ROM structure may be applied. The structure shown in FIG. 5A corresponds to FIG. 2A in terms of circuit representation, and represents an example having an open program element 32, and the structure shown in FIG. Corresponds to FIG. 2B and represents an example having the program element 34 in a short state. 5A and 5B, the structure of the n-channel MOS transistor portion is common. 5A and 5B, the MOS transistor portion includes a p-type semiconductor substrate 300 and a shallow trench isolation (STI) disposed as an element isolation region 302 with respect to the p-type semiconductor substrate 300. An n-type source / drain diffusion layer 304, a gate electrode 306 disposed on the gate insulating film, a ground line (GND) connected to the source electrode, and a word line WLi connected to the gate electrode 306. Prepare. In the open state of FIG. 5A, the program element (PGV) is substantially arranged by connecting nothing between the bit line and the drain electrode, and the program element (PGV) in the short state of FIG. In some cases, the via (VIA) contact 310 is set between the bit line BL _j and the drain electrode to be substantially disposed. Via (VIA) contact 310, between the bit lines BL _j and the drain region of the MOS transistor are electrically connected, forms a program element 34 of the short state, as a result, FIG. 2 (b) A circuit configuration is realized.

(Row redundancy relief process in product manufacturing process)
In the semiconductor memory device according to the first embodiment of the present invention, a row redundancy repair process will be described. The flow from the determination of the user ROM data to the shipment of the product can be schematically represented as a flowchart from step ST0 to ST12 as shown in FIG.

(A) After starting in step ST0, the user creates ROM data in step ST1.

(B) In step ST2, a mask for program contact is created based on the ROM data created by the user.

(C) In step ST3, silicon pellets are produced through a manufacturing process including a mask process for program contact in one process of the manufacturing process of the semiconductor memory device of the present invention.

(D) In step ST4, after creating the LSI, it is determined whether there is a defect that does not become “0” in the ROM function test.

If the result of the ROM function test in step ST4 is OK, the relief process is unnecessary, and the process proceeds to the assembly process ST9.

(E) If the result of the ROM function test is NG in step ST4, the process proceeds to step ST5.

(F) If there is a defect that does not become “0” in step ST5, the process proceeds to step ST6, and the redundancy memory cell array 26 relieves the defective address. Specifically, for example, the program element of the memory cell corresponding to the defective address and input / output (IO) in the redundancy memory cell array 26 is opened.

(G) If there is no defect that does not become “0” in step ST5, the process proceeds to step ST8, stops, the semiconductor memory device is discarded, and the process proceeds to step ST12 and ends.

(H) After the relief process in step ST6, a ROM function test is executed in step ST7. If it is NG, the process proceeds to step ST9, stops, the semiconductor memory device is discarded, and the process proceeds to step ST12 and ends. If OK, after the assembly process in step ST9, if the result of the final test in step ST10 is OK, the process proceeds to step ST12 and ends. If it is NG, the process proceeds to step ST11 and stops, the semiconductor memory device is discarded, and the process proceeds to step ST12 and ends. That is, after the assembly process in step ST9, if there is no problem in the final test in step ST10, the product is shipped as a non-defective product.

  The semiconductor memory device and the memory row relief circuit according to the first embodiment of the present invention are finally assembled and commercialized through the row redundancy relief process shown in the above series of flowcharts.

(Specific circuit configuration of semiconductor memory device and row relief circuit)
FIG. 7 shows a specific circuit configuration diagram of the semiconductor memory device according to the first embodiment of the present invention. In the overall block diagram of the semiconductor memory device according to the first embodiment shown in FIG. 1, a memory cell array 10, a redundancy memory cell array 26, a precharge circuit 12, a column select circuit 14, and a sense amplifier circuit 16 are provided. Each block is expressed as a specific circuit configuration.

The memory cell array 10 is expressed as a 4 × 4 matrix circuit. Each memory cell includes four word lines WL _i−1 , WL _i , WL _{i + 1} , WL _{i + 2} and four bit lines BL _j−1 , BL _j , BL _{j + 1} , BL _{j +.} It is arranged at the position where _two intersect. The memory cell is composed of a MOS transistor and a program element (PGV). One end of the program element is connected to the bit line BL, the other end is connected to the drain of the MOS transistor, connected to the source ground line (GND) of the MOS transistor, and the ROM data is transferred by the conduction / non-conduction of the program element (PGV). Remembered.

The redundancy memory cell array 26 has a 2 × 4 matrix circuit configuration composed of two spare word lines SP1 and SP0 and four bit lines BL _j−1 , BL _j , BL _{j + 1} and BL _{j + 2} . The spare word line SP1 is connected to the gates of MOS transistors N _{SP1, j-1} , N _{SP1, j} , N _{SP1, j + 1} , N _{SP1, j + 2} and the drain of each MOS transistor is connected to the bit line BL _j. Program elements (PGV) are connected between ₋₁ , BL _j , BL _{j + 1} , and BL _{j + 2} . In the example of FIG. 7, the programs are programmed so as to be open, open, short, and short in order from the left. Similarly, the spare word line SP0 is connected to the gates of MOS transistors N _{SP0, j−1} , N _{SP0, j} , N _{SP0, j + 1} , N _{SP0, j + 2} and the drain of each MOS transistor is a bit. line BL _j-1, BL _j, connecting program element (PGV) between the _{BL j + 1, BL j +} 2. In the example of FIG. 7, programming is performed so as to be short, short, open, and open from the left.

  A portion surrounded by a dotted line is a row relief circuit added in the first embodiment of the present invention. In the case of the circuit configuration of FIG. 7, since the memory cell array 10 has four word lines in the row direction and four bit lines in the column direction, the row address is 2 bits and 2 input / output (IO) ) Since D0 and D1 are included, the column address corresponds to the case of 1 bit.

The memory row repair circuit has a function of repairing a row (L) data read failure due to an unopened program via. The redundancy memory cell array 26 corresponds to a memory cell array 10 in which the circuit configuration similar to that of the memory cell array 10 is increased by the number of input / output (IO) bits in the row direction. That is, the semiconductor memory device according to the first embodiment of the present invention has the same number of relief rows (word lines) as the number of input / output (IO) bits in addition to the normal ROM circuit. Yes. Each input / output (IO) is programmed to have a memory cell driven by the same spare word line SP1, SP0. The portion of the added redundancy memory cell array 26 can be formed in exactly the same shape as the portion of the memory cell array 10. Therefore, it is the same as expansion of the memory cell array 10 and productivity is good. In the semiconductor memory device according to the first embodiment of the present invention, as shown in the block configuration diagram of FIG. 1 or the specific circuit diagram of FIG. By arranging 26, the array can be easily expanded. In the example shown in FIG. 7, the row address is 2 bits, and four word lines WL _i−1 , WL _i , WL _{i + 1} , WL _{i + 2} are targeted. Since the number of input / output (IO) is two (D0, D1), there are two relief rows, SP1 and SP0, and the column address is 1 bit.

The precharge circuit 12 shown in FIG. 1 includes precharge transistors arranged at positions where the precharge signal line PRECHL and the bit lines BL _j−1 , BL _j , BL _{j + 1} , and BL _{j + 2} intersect in FIG. 7. P _j−1 , P _j , P _{j + 1} , P _{j + 2} .

The column select circuit 14 shown in FIG. 1 includes the bit line select transistors N _BLj and N _{BLj + 2} and the column select signal line CSL0 arranged at the position where the column select signal line CSL1 and the bit lines BLj and BLj + 2 intersect in FIG. And bit line selection transistors N _BLj-1 and N _{BLj + 1} arranged at positions where the bit lines BL _j-1 and BL _{j + 1} intersect.

The sense amplifier circuit 16 shown in FIG. 1 is connected to the sense amplifier enable signal line SAEL in FIG. 7 and is driven by the sense amplifier enable signal SAE, and the tri-state inverter 40 is in antiparallel. It is shown by an inverter 42 connected to. Further, as apparent from FIG. 7, the bit line BL _j-1 and the bit line BL _j share the output D0, and the bit line BL _{j + 1} and the bit line BL _{j + 2} share the output D1. The number of output lines is reduced.

In FIG. 7, as described above, since there are two spare word lines SP0 and SP1, two column select signal lines CSL0 and CSL1 are arranged. At this time, in the MOS transistors constituting the memory row relief circuit, the MOS transistors N _{SP1, j−1} , N _{SP1, j} , N _{SP1, j + 1} , N _{SP1, j +} connected to the same spare word line SP1 ₂ and the MOS transistor N _{SP0, j−1} , N _{SP0, j} , N _{SP0, j + 1} , N _{SP0, j + 2} connected to the same spare word line SP0 have the same program via Those belonging to the output (IO) assign the same program state to the relief line corresponding to the output (IO) number.

If the spare word line SP0 in this relief row rescues D0 of the output (IO) _, the program vias of the MOS transistors N _{SP0, j-1} and N _{SP0, j} are programmed to a short-circuited state, and the MOS transistor N SP Program the program vias _{SP1, j-1} and _{NSP1, j} to the open state. Since the memory cell belonging to the spare word line SP1 saves D1 of the output (IO), the program vias of the MOS transistors N _{SP1, j + 1} and N _{SP1, j + 2} are programmed to the short-circuit state, and the MOS transistor The program vias N _{SP0, j + 1} and N _{SP0, j + 2} are programmed to the open (open) state.

  The program method for realizing the redundancy of the redundancy memory cell array 26 constituting the row relief circuit in the above description is irrelevant to the user data programmed in the memory cell array 10, and is determined only by the configuration of the output (IO). The

In FIG. 7, various circuits constituting the sense amplifier SA can be considered. It is not limited to this example. As an example, the tri-state inverter 40 constituting the sense amplifier circuit has a gate circuit configuration as shown in FIGS. That is, as shown in FIG. 8B, the tri-state inverter 40 in FIG. 8A inputs the signal φ to the intermediate point with respect to the series connection of the inverters 44 and 46 and outputs the inverted signal. It is equivalent to a gate circuit that obtains a φ bar. Further, the tri-state inverter circuit 40 can be expressed as a specific circuit configuration example, as shown in FIGS. FIG. 9A shows a CMOS inverter composed of a p-channel MOS transistor 48 and an n-channel MOS transistor 50 connected between the power supply voltage V _DD and the ground potential, and a p-channel MOS transistor 54 and an n-channel MOS transistor 52. 3 represents a tri-state inverter circuit configured by a series circuit with a CMOS semiconductor switch functioning as a transfer gate. On the other hand, FIG. 9B shows a tri-type of a switched CMOS or gated CMOS configuration which is connected between the power supply voltage V _DD and the ground potential and is composed of p-channel MOS transistors 56 and 58 and n-channel MOS transistors 60 and 62. It represents a state inverter circuit. Both the tri-state inverter circuits of FIGS. 9A and 9B apply the signals φ and φ bar to the gate of the CMOS semiconductor switch or gated CMOS when obtaining the output signal Vo with respect to the input signal Vi. It works with that. As another example, the circuit shown in FIG. 8C may be used for the sense amplifier SA. This is a circuit in which the input signal Vi is pulled up by a pMOS having a small driving force. This circuit is level driven.

(Normal ROM operation without redundancy operation)
First, the normal operation without the redundancy operation of the memory row relief circuit will be described, and then the redundancy operation will be described.

(A) In FIG. 7, the precharge signal line PRECHL is driven to make the precharge transistors P _j−1 , P _j , P _{j + 1} , P _{j + 2} conductive, and the bit lines BL _j−1 , BL _j , BL _{j + 1} , BL _{j + 2} are precharged.

(B) Open the word lines WL _i−1 , WL _i , WL _{i + 1} , WL _{i + 2} .

(C) Next, for example, the specific word line WL _i is driven to make the memory cell transistor conductive, and the bit lines BL _j−1 , BL _j , BL _{j + 1} , BL _{j + 2} by the memory cell transistor This discharge is performed.

(D) The column select signal lines CSL1 and CSL0 are selected, and the bit line selection transistors N _BLj−1 , N _BLj , N _{BLj + 1} and N _{BLj + 2} are selected.

(E) The sense amplifier enable signal SAE is driven to the sense amplifier enable signal line SAEL.

(E) Discharge states of the bit lines BL _j−1 , BL _j , BL _{j + 1} , BL _{j + 2} selected by the bit line selection transistors N _BLj−1 , N _BLj , N _{BLj + 1} , N _{BLj + 2} Is read out to the data input / output (D0, D1).

(Redundancy operation method of memory row relief circuit)
Redundancy of the semiconductor memory device according to the first embodiment of the present invention when the bit line BL does not become low (L) level, that is, when the program via becomes unopened and becomes low (L) level data read failure. The operation is as follows.

(A) In FIG. 7, as usual, the precharge signal PRECH to be applied to the precharge signal line PRECHL is asserted to a low level (L), and precharge transistors P _j−1 , P _j , which are constituted by p-channel MOS transistors. using _{P j + 1, P j +} 2, the bit lines BL _j-1, BL _j, the _{BL j + 1, BL j +} 2 to precharge. At this time, the sense amplifier enable signal line SAEL is negated (invalidated), and the latch of the sense amplifier SA is once released.

(B) When the word line WL determined by the read address is set to the high level (H), the non-defective bit is set to “0”, that is, the cell in which the bit line BL level is programmed to the low level (L) The bit line BL is discharged through the MOS transistor and becomes low level (L).

(C) At this time, a defective bit that does not become “0” cannot discharge the bit line BL, so that the bit line BL remains at the high level (H).

(D) At this time, the relief address comparison circuit 30 comprising the defective address holding circuit 31 and the address comparison circuit 33 compares the relief address with the input addresses ADDR0 and ADDR1, and if they match, the IO number is determined. One of the relief row drive signals SPWL0 and SPWL1 is asserted.

(E) The bit line BL including the defective bit is driven to the high level (H) by the repair row drive signals SPWL0 and SPWL1 determined by the IO number, and the bit line is forcibly set by the redundancy cell. The line BL can be set to a low level (L).

(F) Thereafter, the column select signal CSL determined by the read address in a normal sequence is set to a high level (H), and data is taken into the sense amplifier circuit (SA) by normal access (redundancy complete). At this time, the sense amplifier enable signal line SAEL is asserted, and the data is latched by the sense amplifier SA.

 In the redundancy operation method of the memory row relief circuit of the semiconductor memory device according to the first embodiment of the present invention, each relief row can operate independently. Alternatively, each relief line may be operated simultaneously. Furthermore, it is possible to relieve a defect of a plurality of bits at the same address.

 Various circuit systems can be considered as the system of the sense amplifier circuit 16. The circuit system shown in the first embodiment of the present invention is an example, and the present invention is not limited to this. It is also clear that the semiconductor memory device and the memory row relief circuit according to the first embodiment of the present invention are not restricted by the circuit system of the sense amplifier and can operate independently.

(Additional circuit part of row decoder)
The specific circuit configuration of the row decoder adding circuit 28 shown in FIG. 1 is configured as a circuit for driving the redundancy memory cell array 26, as shown by the dotted line portion in FIG. That is, in FIG. 10, the dotted frame corresponds to the driver circuit 100 and address input circuit 102 for the spare word lines SP1 and SP0. The other parts correspond to a driver circuit and an address input circuit for driving the word lines WL _i−1 , WL _i , WL _{i + 1} , WL _{i + 2} . A driver circuit for driving the word lines WL _i−1 , WL _i , WL _{i + 1} , WL _{i + 2} or the spare word lines SP0 and SP1 is composed of a NAND gate 90 and an inverter 92. The address input circuit includes a portion where inverters 94 and 96 are connected in series and a portion where inverters 94, 96 and 98 are connected in series. The circuit shown in FIG. 10 has a circuit form in which the row decoder 20 and the row decoder addition circuit 28 shown in FIG. 1 are combined. The basic configuration of each of the row decoder circuit 20 and the row decoder addition circuit 28 is substantially the same. Are identical. The circuit increase due to the provision of the row decoder addition circuit 28 is only the increase of the driver circuits of the spare word lines SP0 and SP1 with respect to the row decoder 20.

 In the operation of the circuit configuration shown in FIG. 10, it is possible to fix the terminals irrelevant to the operations of the spare word lines SP0 and SP1 by the word line boost signal WLUP. That is, the layout of the row decoder can be easily created.

(Relief address comparison circuit)
As shown in FIG. 11, the relief address comparison circuit 30 compares the defective address holding circuit 31 holding the address of the defective memory cell whose bit line cannot be set to the low level with the address inputs ADDR0 and ADDR1, and compares them. As a result, the address comparator 33 is configured to drive an input / output relief row.

  In FIG. 11, the defective address holding circuit 31 includes a fuse 116, resistors 118, 120 and 122, and three D-type flip-flops 114. The address comparison circuit 33 includes inverters 112 and 110 that receive address inputs ADDR 0 and ADDR 1, two exclusive NOR circuits 108, and an AND gate 104. Further, the relief address comparison circuit 30 includes two inverters 106 and two AND gates as shown in FIG.

 The relief address comparison operation in the relief address comparison circuit 30 is as follows.

(A) Latch the data of the fuse 116 when the power is turned on.

(B) Next, the held data is compared with the address inputs ADDR0 and ADDR1 by the exclusive NOR circuit 108.

(C) When the comparison results match, one of the spare signals SPWL0 and SPWL1 is asserted by the data of the fuse 116 holding the IO number, and the spare word lines SP0 and SP1 can be operated.

  The relief address comparison circuit 30 is characterized by always selecting one of the row addresses. A relief address comparison circuit 30 shown in FIG. 11 is an example of a circuit that stores a relief row in the defective address holding circuit 31 and compares the stored data with an input address in the address comparison circuit 33. The relief row must be stored and the number of the input / output (IO) to be rescued must also be stored.

  The semiconductor memory device according to the first embodiment of the present invention is characterized by a circuit system that realizes row redundancy of a mask ROM assuming a program by a program via. Each input / output (IO) has a transistor for extracting the charge precharged to the bit line BL. If the address is compared with the input address and the address can correspond to the bit whose low level (L) cannot be read from the bit line BL, the spare word lines SP0 and SP1 are driven to operate the redundancy memory cell array 26 as the extraction circuit. . The increase in area of the memory cell array is an increase in the number of rows equal to the number of input / output (IO), which is 1% or less. Spare cells are simply an extension of the number of rows, making layout easy. Unlike ECC, there is little penalty for operation timing because no operation is required in the data circuit. It is possible to relieve the defective opening of the program via. A defective opening (unnecessary via (VIA) being opened) cannot be remedied, but the ratio of the defective opening is high in an actual process. Therefore, a high rescue rate can be expected in an actual process. It is possible to relieve defects of the same address and multiple bits. When combined with a second embodiment, which will be described later, in which the program logic of the bit line BL is inverted and the number of vias (VIA) is reduced, the rescue rate can be increased. According to the semiconductor memory device of the first embodiment of the present invention, since the number of relief rows is the same as the number of input / outputs (IO), the occupancy rate of the relief circuit is extremely small compared to a method such as ECC, and The movement of the relief line is represented by a fixed program via irrespective of the user data, and therefore, data can be easily created as compared with ECC or the like. Furthermore, since no additional circuit is generated in the column system, the influence on the access time is extremely small.

  In addition, according to the semiconductor memory device of the first embodiment of the present invention, the circuits after the row decoder circuit in the row address portion can be operated at the same timing in both normal operation and relief operation. The operation can be executed without stopping the normal operation. Therefore, the circuit becomes simple and high-speed operation can be realized.

  In addition, according to the semiconductor memory device of the first embodiment of the present invention, it is possible to create spare cells by simple expansion of the ROM memory cell array, and it is possible to easily construct a layout, and to connect the word lines WL. Since the driver can have the same layout configuration as that of a normal row, the area increase due to the addition of the relief function is extremely small.

  On the other hand, “0” read failure in which the via (VIA) or the contact is not opened and the bit line BL is not discharged to low (L) is dominant in the actual LSI failure, but the first embodiment of the present invention. According to the semiconductor memory device according to the present invention, this type of defect can be relieved, and the majority of defects can be relieved. Here, ““ 0 ”read failure” refers to a failure in which “1” is read although the expected value is “0”.

  In addition, according to the semiconductor memory device of the first embodiment of the present invention, the enable bit (EnableBit) can be omitted by adopting the operation method of operating the relief circuit even for the non-defective product in the normal cell. Therefore, the number of relief fuses (FUSE) added can be reduced. In the first embodiment of the present invention, one of the spare signals SPWL0 or SPWL1 is operated, but both may be operated simultaneously.

(Second Embodiment)
FIG. 12 is a schematic circuit diagram of a semiconductor memory device according to the second embodiment of the present invention. By using the signal normal / invert selection output circuit 84 for normal / invert the bit line signal, it is possible to reduce the number of contacts for setting ROM data to logic “0”. 12, a sense amplifier circuit _{66 j-1, 66 j,} 66 j + 1 is connected to a separate bit line BL _j-1, BL _j, for each BL _{j + 1,} a sense amplifier circuit 66 _j-1, 66 Whether to invert the output of _j , 66 _{j + 1} is selected using the two program elements 76, 78. In FIG. 12, the memory cell array has a 3 × 3 matrix circuit component. That is, the memory cells are arranged at positions where the bit lines BL _j−1 , BL _j , BL _{j + 1} and the word lines WL _i−1 , WL _i , WL _{i + 1} intersect. The memory cell is composed of a series circuit of a memory cell transistor and a program element (PGV). In FIG. 12, a redundancy memory cell array 26, a precharge circuit 12, a column select circuit 14, a relief address comparison circuit 30, a row decoder additional circuit 28, and the like are arranged as in the semiconductor memory device according to the first embodiment. It is clear that it is also good.

In FIG. 12, _one sense amplifier circuit 66 _j−1 , 66 _j , 66 _{j + 1} is connected to each bit line BL _j−1 , BL _j , BL _{j + 1} , and these The outputs of the sense amplifier circuits 66 _j−1 , 66 _j , 66 _{j + 1} are connected to a signal normal / invert selection output circuit 84. As shown in FIG. 12, the signal normal / inverted selection output circuit 84 includes program elements 76 _j−1 , 76 _j , 76 _{j + 1} , 78 _j−1 , 78 _j , 78 _{j + 1} , 82 _{j−. 1} , 82 _j , 82 _{j + 1} , inverters 80 _j−1 , 80 _j , 80 _{j + 1} , buffer circuits 70 _j−1 , 70 _j , 70 _{j + 1} , and output terminals 72 _j−1 , 72 _j , 72 _{j + 1} . When the program via contact is conductive, the program element is represented by a contact hole display. When the program via contact is non-conductive, the program element is represented by an open program element display as shown in FIG. Has been. Further, as apparent from FIG. 12, one end of the open program element 76 _{j + 1} is connected to the MOS transistor 74 _{j + 1} . On the other hand, the short program elements 76 _j-1 and 76 _j are not connected to the MOS transistors 74 _j-1 and 74 _j .

  In the operation of the semiconductor memory device according to the second embodiment of the present invention, in the signal normal / inversion selection output circuit 84, the ROM code is set such that the number of contacts to be set to logic “0” in a certain bit line. If it is larger than half the number of rows, the ROM code reversely sets the presence or absence of program vias or contacts, and inverts the bit line output for output. If the number of contacts is ½ or less of the number of rows, the ROM code remains as it is and the bit line is output in the normal direction.

  In the semiconductor memory device according to the second embodiment of the present invention, the number of contacts for setting ROM data to logic “0” by using the signal normal / inversion selection output circuit 84 for inverting the signal of the bit line. Is reduced. For example, when the number of rows is 128, in the case of a ROM code that requires 127, 65, and 1 contact in the conventional example, 0 and 63 are provided in the semiconductor memory device according to the second embodiment of the present invention. One contact is used.

  Accordingly, in the semiconductor memory device according to the second embodiment of the present invention, the ROM code of the bit line that inverts and outputs the signal is set by reversing the high-level (H) and low-level (L) ROM codes. To do. If the number of contacts is one, the bit line signal is output in the normal direction and the ROM code is not reversed, and is set as it is.

  According to the semiconductor memory device of the second embodiment of the present invention, the ROM data is set to logic “0” using the signal normal / invert selection output circuit 84 for normal / invert the bit line signal. The number of programmed vias or contacts can be reduced.

 By combining the method according to the second embodiment of inverting the program logic of the bit line BL and reducing the number of program vias with the configuration of the semiconductor memory device according to the first embodiment, the relief rate is further increased. Can be made.

  Since the number of program vias or contacts for setting ROM data to logic “0” can be reduced, the off-leakage current flowing in the n-channel MOS transistors constituting the memory cells in the memory cell array 10 is suppressed (reduction of power consumption), Of course, the high (H) level can be read reliably, and further, by reducing the number of contacts, it becomes difficult to receive process failures caused by the contacts, so that the product yield is improved. Furthermore, in the embodiment of the present invention, defective products that can be remedied are determined by the number of RD fuses. Therefore, by reversing the data of the bit lines BL, the number of remedies can be reduced and the remedy rate can be improved. .

(Modification 1 of the second embodiment)
FIG. 13 is a schematic circuit configuration diagram of a semiconductor memory device according to Modification 1 of the second embodiment of the present invention. In FIG. 13, a plurality of bit lines BL _j−1 , BL _j , BL _{j + 1} are connected to a column multiplexer 64 and further share a sense amplifier circuit 66. The output of the sense amplifier circuit 66 is connected to the signal normal / inversion selection output circuit 124. The signal normal / inversion selection output circuit 124 includes an inverter 126, a multiplexer 128 including program elements 130 </ b> A and 130 </ b> B, a buffer circuit 70, and an output terminal 72. On the one hand, the output of the sense amplifier circuit 66 is inverted through the inverter 126 and transmitted to the multiplexer 128, and on the other hand, it is transmitted to the multiplexer 128 without being inverted. The column multiplexer 64 and the multiplexer 128 are simultaneously controlled by the bit line selection signal BLS. Furthermore, whether to invert the sense amplifier output is selected using the program elements 130A and 130B in the multiplexer 128.

  According to the semiconductor memory device according to the first modification of the second embodiment of the present invention, the inverting circuit and the ROM code are set in the signal normal / invert selection output circuit 124 for normal / invert the bit line signal. The same program vias and contacts are used. For this reason, the number of circuit elements and the number of program vias or contacts can be reduced. In the semiconductor memory device according to the first modification of the second embodiment of the present invention, the signal normal rotation / inversion selection output circuit 124 for normal / inversion of the signal of the bit line is used to make the ROM data logically “ The number of contacts set to “0” is reduced. For example, when the number of rows is 128, the ROM code that requires 127, 65, and 1 contact in the conventional example is 0 in the semiconductor memory device according to the first modification of the second embodiment of the present invention. 64, 1 contact is used.

  In FIG. 13, as in the semiconductor memory device according to the first embodiment, the redundancy memory cell array 26, the precharge circuit 12, the column select circuit 14, the relief address comparison circuit 30, the row decoder additional circuit 28, and the like are arranged. It is clear that it is also good.

(Modification 2 of the second embodiment)
FIG. 14 is a schematic circuit configuration diagram of a semiconductor memory device according to Modification 2 of the second embodiment of the present invention. In FIG. 14, sense amplifier circuits 66 _j−1 , 66 _j , 66 _{j + 1} are independently connected to the bit lines BL _j−1 , BL _j , BL _{j + 1} , respectively, and whether or not the sense amplifier output is inverted. These are selected by one program element 78 using exclusive NOR circuits 132 _j−1 , 132 _j , 132 _{j + 1} .

In FIG. 14, the outputs of the sense amplifier circuits 66 _j−1 , 66 _j , 66 _{j + 1} are connected to separate signal normal / inverted selection output circuits 134, respectively. The signal normal / inverted selection output circuit 134 includes exclusive NOR circuits 132 _j−1 , 132 _j , 132 _{j + 1} and program elements 76 _j−1 , 76 _j , 76 _{j + 1} , 78 _j−1 , 78. _j , 78 _{j + 1} , MOS transistors 74 _j−1 , 74 _j , 74 _{j + 1} , 136 _j−1 , 136 _j , 136 _{j + 1} , and buffer circuits 70 _j−1 , 70 _j , 70 _{j + 1} and output terminals 72 _j−1 , 72 _j , 72 _{j + 1} .

  According to the semiconductor memory device of the second modification of the second embodiment of the present invention, the ROM data is logically converted using the signal normal / invert selection output circuit 134 for normal / invert the bit line signal. The number of program vias or contacts set to 0 "can be reduced. For example, when the number of rows is 128, the ROM code that requires 127, 65, and one contact in the conventional example is 0 in the semiconductor memory device according to the second modification of the second embodiment of the present invention. 64, 1 contact is used.

  Since the number of program vias or contacts for setting ROM data to logic “0” can be reduced, the off-leakage current flowing in the n-channel MOS transistors constituting the memory cells in the memory cell array 10 is suppressed (reduction of power consumption), The high (H) level can be read reliably. Further, by reducing the number of contacts, it becomes difficult to receive process failures caused by the contacts, so that the yield of products is improved.

  In FIG. 14, the redundancy memory cell array 26, the precharge circuit 12, the column select circuit 14, the relief address comparison circuit 30, the row decoder additional circuit 28, and the like are arranged as in the semiconductor memory device according to the first embodiment. It is clear that it is also good.

(Modification 3 of the second embodiment)
FIG. 15 is a schematic circuit configuration diagram of a semiconductor memory device according to Modification 3 of the second embodiment of the present invention. 15 is characterized in that a plurality of bit lines BL _j−1 , BL _j , BL _{j + 1} are connected to a column multiplexer 64 and further share a sense amplifier circuit 66. The output of the sense amplifier circuit 66 is connected to a signal normal / inversion selection output circuit 138. The signal normal / invert selection output circuit 138 includes exclusive NOR gate circuits 132a and 132b, a multiplexer 128 including program elements 130A and 130B, a buffer circuit 70, an output terminal 72, program elements 76a and 76b, and a MOS. The transistors 74a, 74b, 136a, and 136b are configured. The output of the sense amplifier circuit 66 is forward / inverted through the exclusive NOR gate circuit 132a or 132b and transmitted to the multiplexer 128. The logic state determined by the conduction / non-conduction of the program elements 76a, 76b or 78a, 78b determines the logic state of the other input terminal of the exclusive NOR gate circuit 132a or 132b.

  The column multiplexer 64 and the multiplexer 128 are simultaneously controlled by the bit line selection signal BLS. Furthermore, whether to invert the sense amplifier output is selected using the program elements 130A and 130B in the multiplexer 128.

  According to the semiconductor memory device of Modification 3 of the second embodiment of the present invention, in the signal normal rotation / inversion selection output circuit 138 for normal / inverting the signal of the bit line, the exclusive NOR gate circuit 132 and The ROM code is set using the same program via and contact. For this reason, the number of circuit elements and the number of program vias or contacts can be reduced.

  In the semiconductor memory device according to the third modification of the second embodiment of the present invention, by using the signal normal rotation / inversion selection output circuit 138 for normal / inversion of the bit line signal, the ROM data is logically “ The number of contacts set to “0” is reduced. For example, when the number of rows is 128, in the case of a ROM code that requires 127 contacts, 65 contacts, and one contact in the conventional example, the number of rows is 0 in the semiconductor memory device according to the third modification of the second embodiment of the present invention. 64, 1 contact is used.

  In FIG. 15, as in the semiconductor memory device according to the first embodiment, the redundancy memory cell array 26, the precharge circuit 12, the column select circuit 14, the relief address comparison circuit 30, the row decoder additional circuit 28, and the like are arranged. It is clear that it is also good.

(Third embodiment)
A schematic block configuration of the one-chip microcomputer to which the semiconductor memory device according to the first embodiment or the second embodiment of the present invention described above is applied is shown in FIG. Internally, ROM 200, CPU 202, direct memory access controller (DMA) 204, data RAM 206, interrupt control circuit 208, timer circuit 210, data bus driver 212, stack RAM / work RAM 214, liquid crystal A display (LCD) drive circuit 216, a booster circuit 218, a battery voltage detection circuit 220, a buzzer circuit 222, an I / O port 224, a test circuit 226, a clock oscillation circuit 228, and a reset circuit 230 Is done.

  The role of the ROM 200 is to store a command to be given to the CPU 202 as program data, and to send the corresponding program data to the CPU 202 when a read command is issued from the CPU 202.

 As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, embodiments, and operational techniques will be apparent to those skilled in the art. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

 Furthermore, it is needless to say that the semiconductor memory devices disclosed by the embodiments of the present invention can be operated by being combined with each other.

1 is a schematic entire block configuration diagram of a semiconductor memory device according to a first embodiment of the present invention. FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a basic circuit diagram showing a concept of a unit memory cell of a semiconductor memory device according to a first embodiment of the present invention, where (a) a circuit configuration diagram including an open program element and a MOS transistor; The circuit block diagram which consists of a state program element and a MOS transistor. 1 is a 1 × 4 bit matrix circuit configuration diagram of a semiconductor memory device according to a first embodiment of the present invention; FIG. FIG. 3 is a plan pattern layout configuration diagram corresponding to the circuit configuration of FIG. 2 of the semiconductor memory device according to the first embodiment of the present invention. 2A and 2B are schematic cross-sectional structure diagrams of a unit memory cell of the semiconductor memory device according to the first embodiment of the present invention, where FIG. FIG. 3 is a schematic flowchart for explaining a row redundancy repair process in a product manufacturing process in the semiconductor memory device according to the first embodiment of the present invention. 1 is a schematic circuit configuration diagram of a semiconductor memory device according to a first embodiment of the present invention. (A) a symbol mark of a tri-state inverter applied to the sense amplifier circuit of the semiconductor memory device according to the first embodiment of the present invention, (b) an equivalent circuit representation by two stages of inverters, and (c) 4 is a circuit example of a level operation sense amplifier SA. (A) an equivalent circuit representation of a tri-state inverter applied to the sense amplifier circuit of the semiconductor memory device according to the first embodiment of the present invention, and (b) a switched circuit Equivalent circuit representation in CMOS. 1 is a schematic circuit configuration example of a row decoder and a row decoder additional circuit of a semiconductor memory device according to a first embodiment of the present invention. 1 is a schematic circuit configuration example of a relief address comparison circuit of a semiconductor memory device according to a first embodiment of the present invention. FIG. 6 is a schematic circuit configuration diagram of a semiconductor memory device according to a second embodiment of the present invention. FIG. 10 is a schematic circuit configuration diagram of a semiconductor memory device according to Modification 1 of the second embodiment of the present invention. FIG. 10 is a schematic circuit configuration diagram of a semiconductor memory device according to a second modification of the second embodiment of the present invention. FIG. 10 is a schematic circuit configuration diagram of a semiconductor memory device according to Modification 3 of the second embodiment of the present invention. FIG. 7 is an application circuit configuration diagram of a semiconductor memory device according to a third embodiment of the present invention.

Explanation of symbols

10 ... memory cell array 12 ... pre-charge circuit 14 ... column select circuits _{16,66,66 j-1, 66 j,} 66 j + 1 ... sense amplifier circuit 18 ... output buffer circuit 20 ... row decoder 22 ... address control circuit 24 ... Read control circuit 26 ... Redundancy memory cell array 28 ... Row decoder addition circuit 30 ... Relief address comparison circuit 31 ... Defective address holding circuit 32 ... Open program element (PGV)
33 ... Address comparison circuit 34 ... Program element (PGV) in a short state
36 ... bit line contact 38 ... word line contact 40 ... tri-state inverter _{42,44,46,80,80 j-1, 80 j,} 80 j + 1, 92,94,96,98,106,110, 112 ... Inverters 48, 52, 56, 58 ... p-channel MOS transistors 50, 54, 60, 62 ... n-channel MOS transistors 64 ... column multiplexers 70, 70 _{j -1} , 70 _j , 70 _{j + 1} ... buffer circuit 72, 72 _j−1 , 72 _j , 72 _{j + 1} ... Output terminals 74, 74 _j−1 , 74 _j , 74 _{j + 1} , 74a, 74b, 136 _j−1 , 136 _j , 136 _{j + 1} , 136a, 136b ... MOS transistors _{76,76 j-1, 76 j,} 76 j + 1, 76a, 76b, 78,78 j-1, 78 j, 78 j + 1, 78a, 78b, 82,82 j-1, 82 j , 82 _{j + 1} , 130A, 130B... Program elements 84, 124, 134, 138. Power circuit 90,104 ... NAND gate circuit 100 ... driver circuit 102 ... address input circuit 114 ... D-type flip-flop 116 ... fuse 118, 120, 122 ... resistor _{108,132,132 j-1, 132 j,} 132 j + 1 , 132a, 132b ... exclusive NOR circuit 200 ... ROM
202 ... CPU
204 ... DMA
206: Data RAM
208 ... Interrupt control circuit 210 ... Timer circuit 212 ... Data bus driver circuit 214 ... Stack RAM / Work RAM
216: LCD drive circuit 218 ... Boost circuit 220 ... Battery voltage detection circuit 222 ... Buzzer circuit 224 ... I / O port 226 ... Test circuit 228 ... Clock oscillation circuit 230 ... Reset circuit 240 ... LSI
300 ... Semiconductor substrate 302 ... Element isolation region 304 ... n ⁺ diffusion layer 310 ... Program via (VIA)
ST0～ST12 ... Step GND ... ground line _{WL i-1, WL i,} WL i + 1, WL i + 2 ... word line WLUP ... word line boosting signal _{P j-1, P j,} P j + 1, P j ₊₂ ... Precharge transistors BL _j−1 , BL _j , BL _{j + 1} , BL _{j + 2} ... Bit line BLS... Bit line selection signals N _ij−1 , N _ij , N _{ij + 1} , N _{ij + 2} , N _{i + 1j−1} , N _{i + 1j} , N _{i + 1j + 1} , N _{i + 1j + 2} ... MOS transistor SAE ... sense amplifier enable signal SAEL ... sense amplifier enable signal line PRECH ... precharge signal PRECHL ... precharge Signal lines SP0, SP1 ... Spare word lines _NBLj-1 , _NBLj , _{NBLj + 1} , _{NBLj + 2} ... Bit line selection transistors CSL0, CSL1 ... Column select signal line CLS ... Column select signal CS ... Source line contact CB ... Bit line contact

Claims (8)

A plurality of word lines extending in the row direction and a plurality of bit lines extending in the column direction are provided at positions where the plurality of word lines and the plurality of bit lines intersect from a series circuit of a switching element and a program element, respectively. A memory cell array in which memory cells are arranged;
A redundancy memory cell array in which the series circuits are respectively arranged at positions where the same number of spare word lines and bit lines as the data outputs extending in the row direction intersect;
A row decoder for driving a plurality of word lines of the memory cell array;
A row decoder additional circuit for driving the plurality of spare word lines;
A precharge circuit for precharging the plurality of bit lines;
A column select circuit connected to the precharge circuit and selecting the bit line;
A sense amplifier circuit connected to the column select circuit for detecting data stored in the memory cell ;
A semiconductor memory device , wherein the word line and the spare word line are simultaneously driven to relieve the low-level reading of the bit line .   2. The redundancy memory cell array according to claim 1, wherein gates of memory cells belonging to the same data output are connected to the same spare word line, and the bit line is discharged by activating the spare word line. The semiconductor memory device described.   2. The semiconductor memory device according to claim 1, wherein the row decoder and the row decoder additional circuit have substantially the same circuit configuration. A defective address holding circuit for holding an address of a defective memory cell which cannot make the bit line low level and its data output number;
3. The semiconductor memory device according to claim 2, further comprising: a comparison circuit that compares the held address with an address input and drives an output relief row based on the comparison result. 5. The semiconductor memory device according to claim 4 , wherein the relief address comparison circuit always selects one of the row addresses. 2. The semiconductor memory device according to claim 1, further comprising a signal normal rotation / inversion selection output circuit connected to the sense amplifier circuit and configured to normal / invert the signal of the bit line. 7. The semiconductor memory device according to claim 6, wherein the signal normal / inversion selection output circuit includes an inverter and a program element connected in parallel to the inverter and having the same configuration as the program element. 7. The semiconductor memory device according to claim 6, wherein the signal normal / inverted output circuit includes an exclusive NOR gate circuit and a program element having the same configuration as the program element.

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