JP4386277B2 - Image forming apparatus - Google Patents

Description

  The present invention relates to a beam scanning type image forming apparatus in a laser printer, a digital copying machine, a facsimile machine or the like, and in particular, when forming an image of a plurality of colors, the pulse width or the phase of a light beam can be adjusted, and the image The present invention relates to an image forming apparatus that forms a high-quality color image without color misregistration.

2. Description of the Related Art Conventionally, in an image forming apparatus such as a laser printer, a digital copying machine, and a facsimile machine, laser light is scanned in a main scanning direction on a surface to be scanned such as a photosensitive member by a scanning means such as a polygon mirror. A beam scanning type writing method is employed in which an image is written line by line on the photosensitive member by moving in the sub-scanning direction.
In such a beam scanning type writing system, the laser beam is deflected at a constant angular velocity by a polygon mirror, and an fθ lens and an fθ mirror are used in order to make the scanning velocity constant on the surface to be scanned. However, the laser light that passes through the fθ lens and the fθ mirror has a problem that the scanning speed on the surface to be scanned is not completely constant, and the image magnification on the image surface varies depending on the image height. The reason is that the shape and mounting position of optical elements such as glass, lenses, and mirrors that pass from when the laser beam is emitted from the laser diode to the image plane are different, and the thickness of the fθ lens is different depending on the image height. Etc.
Such fluctuations in image magnification due to image height (uneven scanning) affect the formed image as pixel dot misalignment. (The pixel dots are generated by controlling the light emission source according to the pixel clock. In particular, in a color image forming apparatus, since it appears as a conspicuous color shift, in the beam scanning type writing method, an adjustment for eliminating a variation in magnification due to an image height is performed.

The following Patent Documents 1 and 2 can be cited as conventional examples in which correction of this scanning unevenness is a problem to be solved. The pixel clock generation device described in Patent Document 1 includes means for setting a data area according to the number of pixel clocks and means for setting phase shift data for performing phase shift for each data area, and the phase of the pixel clock of each area data is set. By shifting according to the setting, it is possible to correct the positional deviation of the pixel dots due to uneven scanning.
The optical scanning device described in Patent Document 2 has the same purpose as Patent Document 1 (correction of pixel dot position deviation) in that it corrects the density of beam spots in the main scanning direction. The optical scanning device described in Patent Document 2 can correct the density of the beam spot in the main scanning direction by variably controlling the phase of the pixel clock in units of 1 / n (n = 2 or more) of one cycle of the pixel clock. It is said. Further, in this conventional example, a scanning region is divided, and a means for setting the number of insertions of a beam spot coarse / dense correction clock (external pulse train xpls that determines the timing for changing the phase of the pixel clock) for each divided area; A storage means for storing magnification correction information is provided. Each of these means reads out magnification correction information every time a set number of correction clocks are generated for each divided area, and reflects the obtained magnification correction information in the set value, thereby reducing the density of the beam spot depending on the image height. It is possible to make corrections and make adjustments to eliminate magnification fluctuations.
JP 2003-103830 A JP 2004-4510 A

The devices described in Patent Documents 1 and 2 both use a correction method that divides a scanning region and shifts the phase of a pixel clock according to a set value when a correction insertion clock is generated for each divided area. By adopting the correction method, the memory capacity required for storing the phase shift data can be reduced as compared with the case where the phase shift is performed for each pixel clock.
However, even in the apparatus described in Patent Document 2 in which the number of clock insertions can be set for each of the divided scanning regions, the correction insertion clock has a constant insertion interval (depending on the configuration of a gate array or the like having a write control function). Therefore, it is difficult to perform correction with higher accuracy by the devices described in Patent Documents 1 and 2 above.
The present invention has been made in view of the above-described problems of the related art with respect to the positional deviation of pixel dots caused by uneven scanning, which occurs in an image forming apparatus adopting a beam scanning type writing method. The object is to further improve the accuracy of pixel dot positional deviation correction by means for enabling the setting of the number of correction clock insertions for each scanning region.

The invention of claim 1 controls the lighting of the light emitting source, the light beam scanning means for projecting the light output from the light emitting source as a scanning beam to the image carrier, and the lighting of the light emitting source based on the image data. In this case, the image forming apparatus includes a lighting control unit that can adjust the lighting timing by changing the pixel clock according to the phase data indicating the shift amount from the reference lighting timing, and the lighting control unit adjusts the lighting timing. As means for enabling, a means for dividing a scanning area by a light beam into a plurality of areas, a means for setting a variable number of pixel clocks for each divided area, and a switching interval between variable pixel clocks in the divided areas are set. comprising a pixel clock switching interval setting means, and setting the pixel clock switching interval setting means, to place the switching intervals equally spaced over the divided areas throughout There are at least two types of patterns, a setting pattern in which switching is performed only in the right half or left half range of the divided area and the switching interval is arranged at equal intervals, and a setting pattern in which the switching interval is provided with a bias. The switching interval between the variable pixel clocks is set according to the instruction of one setting pattern selected from here .
According to a second aspect of the present invention, in the image forming apparatus according to the first aspect, the pixel clock switching interval setting means is configured to enable pixel clocks respectively set in a divided area to be set and divided areas around the divided area. A setting pattern determining unit that determines one setting pattern to be selected from a plurality of patterns based on a variable is provided.
According to a third aspect of the present invention, in the image forming apparatus according to the second aspect, the setting pattern determining unit is configured to set a variable number of pixel clocks respectively set in a divided area to be set and divided areas around the divided area. , “Pixel area setting value”> “Setting object division area setting value”> “Subdivision area setting value” on the condition that the pixel closer to the previous division area in the setting object division area A pattern in which a large number of variable clocks are arranged is determined as a setting pattern.
According to a fourth aspect of the present invention, in the image forming apparatus according to the second aspect, the setting pattern determining unit is configured to set a variable number of pixel clocks respectively set in a divided area to be set and divided areas around the divided area. The switching interval is arranged at equal intervals within the setting target divided area on condition that “the setting value of the previous dividing area” ≈ “the setting value of the setting target dividing area” ≈ “the setting value of the subsequent dividing area”. The pattern is determined as a setting pattern.
According to a fifth aspect of the present invention, in the image forming apparatus according to the second aspect, the setting pattern determining unit is configured to set a variable number of pixel clocks respectively set in a divided area to be set and a divided area around the divided area. , “Pixel area setting value” <“Setting object division area setting value” <“Subdivision area setting value”. A pattern in which a large number of variable clocks are arranged is determined as a setting pattern.

According to the present invention, the scanning area is divided into a plurality of areas, a variable number of pixel clocks can be set for each of the divided areas, and a switching interval of variable pixel clocks in the area can be set. It is possible to determine the correction insertion position and perform pixel clock correction (adjustment of lighting timing) according to fluctuations in the scanning speed, and to reduce both memory capacity and correction accuracy. remembering Do Ri, moreover pattern to place the switching intervals equally spaced over the divided areas throughout bias to the switching intervals only in the pattern and dividing the area to place the switching interval at equal intervals right half or the left half range of the divided area by that enables setting of a pattern selected from at least two kinds of patterns in the pattern of placing Te, can and that Do corresponding to various positional shift case.
Further, since one set pattern to be selected is determined based on the variable number of pixel clocks set in the divided area to be set and the divided areas around the divided area, a special pattern selection is performed. A pattern suitable for each case can be selected without requiring input (Claims 2 to 5 ), and smoother correction can be performed at the boundary between the front and rear areas which are surrounding divided areas. (Claims 3 to 5 ).

An image forming apparatus according to the present invention will be described based on the following embodiments. The following embodiment shows an example in which the present invention is applied to a color copying machine that performs LD (laser diode) optical writing in the main / sub scanning mode.
FIG. 1 shows a schematic configuration of the color copying machine of the present embodiment. 2 is a perspective view for explaining a schematic configuration around the exposure apparatus in FIG. 1. FIG. 3 shows an image on the photosensitive member while deflecting and scanning the light beam output from the LD (laser diode) in FIG. An explanatory view of an optical path until writing is shown.
As shown in FIG. 1, the color copying machine of this embodiment mainly includes a copying machine main body 100, a paper feed table 200, a scanner 300, and an automatic document feeder (ADF) 400.
An endless belt-like intermediate transfer member 10 is provided at the center of the copying machine main body 100. In this example, the intermediate transfer member 10 is wound around three support rollers 14, 15, and 16, and is rotated and conveyed clockwise as indicated by arrows in the drawing.
Among the three support rollers, four color components composed of black, cyan, magenta, and yellow are arranged on the intermediate transfer member 10 stretched between the first support roller 14 and the second support roller 15 along the conveyance direction. The so-called tandem-type image forming apparatus 20 is configured in which the image forming units 18 are arranged side by side and simultaneously enable image forming operations of four colors. Further, an exposure device 21 is provided above the tandem image forming apparatus 20.
Further, an intermediate transfer member cleaning device 17 for removing residual toner remaining on the intermediate transfer member 10 after image transfer is provided on the right side of the second support roller 15.

On the other hand, a secondary transfer device 22 is provided on the opposite side of the intermediate transfer member 10 from the tandem image forming device 20. The secondary transfer device 22 is configured such that a secondary transfer belt 24, which is an endless belt stretched between two rollers 23, is pressed against the third support roller 16 via the intermediate transfer body 10. The image on the intermediate transfer member 10 is transferred to a sheet supplied between the secondary transfer belt 24 and the intermediate transfer member 10.
A fixing device 25 for fixing the transfer image on the sheet by a thermocompression bonding method is provided on the downstream side of the secondary transfer device 22. The fixing device 25 is configured by pressing a pressure roller 27 against a fixing belt 26 that is an endless belt.
In this example, as the secondary transfer device 22, a device having a sheet conveyance function for conveying the image-transferred sheet to the fixing device 25 is used. Of course, a non-contact charger may be arranged as the secondary transfer device 22, but in this case, it is necessary to provide this sheet conveying function separately.
Further, in the embodiment shown in FIG. 1, under the secondary transfer device 22 and the fixing device 25, a sheet reversal that inverts the sheet in order to record images on both sides of the sheet in parallel with the tandem image forming apparatus 20 described above. A device 28 is provided.

When copying a document using the color copying machine shown in FIG. 1, the document is set on the document table 30 of the automatic document feeder 400 or the automatic document feeder 400 is opened and the document is placed on the contact glass 32 of the scanner 300. , And a start switch (not shown) is pressed while the automatic document feeder 400 is closed and pressed. When a document is set on the automatic document feeder 400, the document is transported and moved onto the contact glass 32 (sheet-through reading mode). When a document is set on the contact glass 32, the scanner 300 immediately Driven to cause the first traveling body 33 and the second traveling body 34 to travel (book reading mode).
In any of the above-described reading modes, when the document surface is illuminated by the light source of the first traveling body 33, the reflected light from the document surface is reflected by the mirrors of the first traveling body 33 and the second traveling body 34, and is connected. The image is input to the reading sensor 36 through the image lens 35, and the image on the document surface is read.
When a start switch (not shown) is pressed, one of the support rollers 14, 15 and 16 is driven to rotate by a drive motor (not shown), and the other two support rollers are driven to rotate. 10 is rotated and conveyed. At the same time, the photoconductors 40 of the four-color image forming unit 18 are individually rotated to form black, yellow, magenta, and cyan monochrome images on the photoconductors 40, respectively. Then, the intermediate transfer member 10 is conveyed, and the monochrome image on each photoconductor 40 is sequentially transferred to form a composite color image on the intermediate transfer member 10.
An image is formed on each photoconductor 40 by the exposure device 21 using an LD light beam writing method. The exposure device 21 controls the LD driving unit 62 based on the image data of the document read by the reading sensor 36 and the like and the pixel clock generated and corrected by the pixel clock generation circuit described later, and the light whose lighting is controlled. By scanning the surface of the photoconductor 40 in the main scanning direction while deflecting the beam with a polygon mirror, an electrostatic latent image is formed on the surface of the photoconductor. The exposure apparatus 21 will be described in detail later with reference to FIGS. 2 and 3.

On the other hand, when a start switch (not shown) is pressed, one of the paper feed rollers 42 of the paper feed table 200 is selectively rotated, and a desired paper feed cassette 44 provided in multiple stages in the paper bank 43 is selected. The sheet is fed out and fed one by one to the sheet feeding path 46 while being separated one by one by the separation roller 45, conveyed by the conveying roller 47, guided to the sheet feeding path 48 in the copying machine main body 100, and abutted against the registration roller 49 and stopped. Let In addition to the above paper feeding method, the paper feed roller 50 is rotated to feed out the sheets on the manual feed tray 51, and the paper is fed to the manual paper feed path 53 while being separated one by one by the separation roller 52. You may stop at 49.
After the sheet is stopped by the registration roller 49, the registration roller 49 is rotated in synchronization with the composite color image formed on the intermediate transfer body 10, and the sheet is placed between the intermediate transfer body 10 and the secondary transfer device 22. A color image is recorded on the sheet by feeding and transferring by the secondary transfer device 22.
The sheet after the image transfer is conveyed by the secondary transfer device 22 and sent to the fixing device 25, and heat and pressure are applied by the fixing device 25 to fix the transferred image, and then the sheet is switched by the switching claw 55 and discharged. The paper is discharged at 56 and stacked on the paper discharge tray 57. Alternatively, when the sheet is switched by the switching claw 55 and enters the sheet reversing device 28, the sheet is reversed and guided again to the transfer position, and an image is recorded on the back surface, and then discharged onto the discharge tray 57 by the discharge roller 56. The
On the other hand, the intermediate transfer member 10 after the image transfer is subjected to removal of residual toner remaining on the intermediate transfer member 10 after the image transfer by the intermediate transfer member cleaning device 17, so that the image forming device 20 by the tandem method can form an image again. Prepare.

Here, the configuration and operation of the exposure apparatus will be described in more detail with reference to FIGS.
As shown in FIG. 2, a synchronization sensor 61 is disposed on the scanning optical path of the beam from the LD 63 in order to detect the main scanning timing. The writing control unit 60 receives the phase synchronization signal from the synchronization sensor 61 and the image data of the original read by the scanner 300, and generates a pixel clock by a pixel clock generation circuit described later based on these signals and data. The Each pixel position in the scanning direction is determined by a pixel clock. Therefore, image writing is performed by controlling the driving of the LD driving unit 62 by the pixel clock and controlling the lighting of the LD 63.
The laser beam emitted from the LD 63 is shaped through the collimator lens 64 and the aperture 65, and after passing through the cylinder lens 66, the incident laser beam is deflected and scanned by the polygon mirror 67 for rotational deflection. As shown in FIG. 3, the polygon mirror 67 is rotationally driven by a polygon motor 73 at a predetermined rotational speed. The laser light reflected by the polygon mirror 67 passes through the fθ lens 68 and the double toroidal lens (WTL) 74, is reflected by the folding mirror 69, and further passes through the dust-proof glass 70 to be a photosensitive member as a recording medium. 40 is collected.
For example, a photosensitive drum is used as the photosensitive member 40. The photosensitive drum 40 is rotationally driven in a direction opposite to the sub-scanning direction by a rotation driving unit (not shown), and is uniformly charged by a charger (not shown), and then a laser. By repeatedly scanning in the main scanning direction with light, an image is written and an electrostatic latent image is formed.
The electrostatic latent image formed on the photosensitive drum 40 is developed by a developing device (not shown) to become a toner image, is transferred to a recording sheet such as transfer paper through the above-described transfer process, and is fixed by a fixing device 25. It is fixed on the recording sheet.
In this way, the laser light emitted from the LD 63 is deflected at a constant angular velocity by the polygon mirror 67, and in order to make the scanning speed on the scanned surface of the photoreceptor 40 constant, the polygon mirror 67, the fθ lens 68, or An optical element such as a folding mirror 69 is used.

However, as described in the section “Background Art” above, since these optical elements have variations and non-uniformities in their shapes and mounting positions, the scanning speed on the surface to be scanned of the photoconductor is completely high. It is not uniform and appears as color misregistration, particularly in the case of a color image in which an image is synthesized using a plurality of image forming units.
Therefore, in the present invention, it is an object to correct the positional deviation of the pixel dots, and as means for solving this problem, means according to a method of shifting the phase of the pixel clock is proposed. Here, the principle of the correction method based on the phase shift of the pixel clock which is the base of the present invention will be described first.
4 is a diagram showing an example of the distribution of the scanning speed of the light beam with respect to the image height (position in the main scanning direction) of the photoconductor 40 in FIGS. 2 and 3, and FIG. 5 is a scan with respect to the image height in FIG. It is the diagram which calculated | required the correction amount which becomes an inverse characteristic based on speed distribution. FIG. 6 is a block diagram illustrating a configuration example of a pixel clock generation circuit that generates a pixel clock based on phase data.
The laser light beam is deflected and scanned with the main scanning line directed to the photoreceptor 40 as shown in FIG. That is, if the center of the photoconductor 40 in the main scanning direction is set to the image height 0 in the range including the synchronization sensor 61 with the photoconductor 40 as the center, scanning is performed so that an effective writing area exists in the left-right direction.
In the diagram corresponding to the width of the photoreceptor 40 shown in FIG. 4B, the horizontal axis is drawn so that the position from the image height 0 to the image height ± 150 corresponds, and the vertical axis is the image height 0. When the scanning speed at that time is 100%, the scanning speed at each image height position is expressed as a percentage. As can be seen from this diagram, the fluctuation in the scanning speed of the main scanning due to the laser light tends to increase as it goes to the end of the photoreceptor 40. Of course, the fluctuation in the scanning speed of the main scanning is not limited to this, and other trends may be shown depending on the situation.
The fluctuation of the scanning speed is affected by using the method shown in FIG. 4B, in which the scanning speed at each image height position is corrected using the correction amount as an amount that cancels the tendency of the scanning speed distribution. Can be eliminated. That is, this is a method of correcting fluctuations in scanning speed at each image height position using the reciprocal of the tendency of the scanning speed distribution as a correction value.
FIG. 5 is a diagram in which the correction amount of the scanning speed at each image height position is obtained by taking the reciprocal. In this diagram, assuming that the image height is 0% and the scanning speed is corrected at each image height position, the surface to be scanned of the photosensitive member is always scanned uniformly at the same scanning speed as the image height 0 position. It shows what can be done. Of course, if the tendency of the scanning speed distribution shown in FIG. 4B changes, the correction amount distribution of FIG. 5 also changes accordingly.

Next, means for correcting the scanning speed according to the correction principle described above will be described.
In the present invention, the correction amount of the scanning speed given as described above is reflected in the phase of the pixel clock in pixel writing. That is, an effect equivalent to that obtained when the scanning speed is corrected by changing the writing speed corresponding to the positional deviation of the pixel dots, which is changed by correcting the scanning speed, is obtained. Since the writing speed can be changed by changing the phase of the pixel clock, the writing speed can be changed by replacing the scanning speed correction amount with the phase shift amount of the pixel clock.
A pixel clock generation circuit 80 shown in FIG. 6 is used as an example of means for realizing a phase shift of the pixel clock using the correction amount distribution of the scanning speed shown in FIG.
Since the pixel clock generation circuit 80 determines each pixel position in the image area based on the pixel clock, in order to correct the local variation in the scanning speed in the main scanning direction, the pixel clock frequency is locally set during the main scanning. This is because it can be realized by changing the phase (shifting the phase).
The pixel clock generation circuit 80 in FIG. 6 is a circuit that shifts the phase based on phase data that indicates the transition timing of the pixel clock and changes the cycle of the pixel clock. The high-frequency clock generation circuit 81, the counter 82, and the comparison The circuit 83, the pixel clock control circuit 84, and the like.

The high frequency clock generation circuit 81 generates a high frequency clock VCLK serving as a reference for the generated pixel clock PCLK.
The counter 82 operates here at the rising edge of the high frequency clock VCLK, counts the high frequency clock VCKL, and resets the count value when a reset signal is input from the comparison circuit 83 described later.
The comparison circuit 83 compares the count value from the counter 82, a preset value, and phase data given from the outside (data indicating the phase shift amount as the transition timing of the pixel clock), and the respective comparisons obtained. Based on the result, the control signal a and the control signal b are output. The phase data is data for instructing the shift amount of the phase of the pixel clock in order to correct the dot position deviation (for example, correction of scanning unevenness caused by the characteristics of the fθ lens 68, or dot due to rotational unevenness of the polygon mirror 67). Data for correcting misregistration or color shift caused by chromatic aberration of laser light) and can be given as a digital value of several bits.
The pixel clock control circuit 84 controls the transition timing of the generated pixel clock PCLK based on the control signal a and the control signal b input from the comparison circuit 83. The control signal a determines the falling edge of the pixel clock PCLK, and the control signal b determines the rising edge of the pixel clock PCLK.

Next, the operation of the pixel clock generation circuit 80 in FIG. 6 will be described with reference to the timing charts shown in FIGS. 7A is a timing chart for explaining an operation example when the phase data of the pixel clock generation circuit 80 of FIG. 6 is set to 7. FIG. 7B is a timing chart for explaining the operation of the pixel clock generation circuit of FIG. It is a timing chart explaining the operation example when the phase data of 80 is set to 8, (C) of the same figure is the operation example when the phase data is set to 6, and (D) of the same figure is the same. The operation example when the phase data is set to 9 and (E) in the figure are timing charts for explaining the operation example when the phase data is set to 5. FIG. 8 is a timing chart when the phase of the pixel clock to be generated is changed every clock.
The pixel clock PCLK generated in (A) of FIG. 7 is obtained by dividing the high frequency clock VCLK generated by the high frequency clock generation circuit 81 by 8 and the duty ratio is set to 50% as a standard. It is assumed that a value “7” is given as phase data input to the generation circuit 80, and a value “3” is set in the comparison circuit 13 in advance.
The counter 82 in FIG. 6 performs a count operation at the rising edge of the high frequency clock VCLK generated by the high frequency clock generation circuit 81. Since the value “3” is set in the comparison circuit 83 in advance, the control signal “a” is output when the counter value of the counter 82 becomes “3”. Upon receiving the “H” input of the control signal a, the pixel clock control circuit 84 changes the pixel clock PCLK from “H” to “L” at the clock timing (1) in FIG.
Subsequently, the comparison circuit 83 compares the given phase data with the counter value, and outputs a control signal b if they match. Since the value “7” is set as the phase data in the comparison circuit 83, the comparison circuit 83 outputs the control signal b when the counter value of the counter 82 becomes “7”. Upon receiving the “H” input of the control signal b, the pixel clock control circuit 84 changes the pixel clock PCLK from “L” to “H” at the clock timing (2) in FIG. At this time, the comparison circuit 83 sends a reset signal to the counter 82 at the same time to reset it so that it starts counting from 0 again. Thereby, as shown in FIG. 7A, it is possible to generate the pixel clock PCLK having a duty ratio of 50% corresponding to the frequency division of the high frequency clock VCLK by 8.

By changing the phase according to the instructed phase shift amount with reference to the pixel clock PCLK generated by the setting of FIG. 7A described above, a certain area (the area designation will be described in detail later). The pixel density inside is changed.
For example, in FIG. 7B, a pixel clock PCLK whose phase is delayed by 1/8 clock with respect to the reference pixel clock (a divided clock of the high-frequency clock VCLK in FIG. 7A) is generated. In C), a pixel clock PCLK having a phase advanced by 1/8 clock with respect to the reference pixel clock is generated.
In the case of FIG. 7B, the difference is that the phase data given to the comparison circuit 83 of FIG. In this case, the pixel clock PCLK is changed from “H” to “L” at the clock timing (1) because the set value of the control signal “a” remains “3”. )), But the phase data of the transition from “L” to “H” of the pixel clock PCLK is “8”, so that the phase is delayed by 1/8 clock from the reference pixel clock. The pixel clock PCLK can be generated. That is, in the pixel clock control circuit 84, when the counter value of the counter 82 reaches “8” as shown in the clock timing (2) in FIG. The pixel clock PCLK is changed from “L” to “H”. Accordingly, it is possible to generate the pixel clock PCLK whose phase is delayed by 1/8 clock with respect to the frequency-divided clock of the high-frequency clock VCLK serving as a reference.
In the case of FIG. 7C, the difference is that the phase data given to the comparison circuit 83 of FIG. Also in this case, the transition of the pixel clock PCLK from “H” to “L” at the clock timing (1) is the same as the operation of the reference pixel clock, but from “L” to “H” of the pixel clock PCLK. Since the phase data is “6”, the pixel clock PCLK whose phase is advanced by 1/8 clock from the reference pixel clock can be generated. That is, in the pixel clock control circuit 84, when the counter value of the counter 82 reaches “6” as shown in the clock timing (2) in FIG. The pixel clock PCLK is changed from “L” to “H”. Accordingly, it is possible to generate the pixel clock PCLK whose phase is advanced by 1/8 clock with respect to the frequency-divided clock of the high-frequency clock VCLK serving as a reference.

Further, in FIGS. 7D and 7E, the phase shift amount is made larger than the reference pixel clock (the high frequency clock VCLK divided by 8 in FIG. 7A). For example, in FIG. 7D, a pixel clock PCLK having a phase advanced by 2/8 clock with respect to the divided high-frequency clock VCLK by 8 is generated. In FIG. 7E, the high-frequency clock VCLK divided by 8 is generated. A pixel clock PCLK having a phase delayed by 2/8 clock with respect to the clock is generated.
In the case of FIG. 7D, the difference is that the phase data applied to the comparison circuit 83 of FIG. Also in this case, the transition of the pixel clock PCLK from “H” to “L” at the clock timing (1) is the same as the operation of the reference pixel clock because the set value of the control signal “a” remains “3”. However, since the phase data is “9” when the pixel clock PCLK transitions from “L” to “H”, the pixel clock PCLK whose phase is delayed by 2/8 clock from the reference pixel clock is generated. be able to. That is, in the pixel clock control circuit 84, when the counter value of the counter 82 becomes “9” as shown in the clock timing (2) in FIG. The pixel clock PCLK is changed from “L” to “H”. Accordingly, it is possible to generate the pixel clock PCLK having a phase delayed by 2/8 clock with respect to the frequency-divided clock of the high-frequency clock VCLK serving as a reference.
7E is different in that the phase data given to the comparison circuit 83 in FIG. 6 is set to “5”. Also in this case, the transition of the pixel clock PCLK from “H” to “L” at the clock timing (1) is the same as the operation of the reference pixel clock, but from “L” to “H” of the pixel clock PCLK. Since the phase data is “5”, the pixel clock PCLK whose phase is advanced by 2/8 clock from the reference pixel clock can be generated. That is, in the pixel clock control circuit 84, as indicated by the clock timing (2) in FIG. 7E, when the counter value of the counter 82 becomes “5”, the control signal b output from the comparison circuit 83 is used. The pixel clock PCLK is changed from “L” to “H”. Therefore, it is possible to generate the pixel clock PCLK having a phase advanced by 2/8 clock with respect to the frequency-divided clock of the high-frequency clock VCLK serving as a reference.

As described above, only by changing the phase data input to the pixel clock generation circuit 80, the phase of the generated pixel clock PCLK is freely advanced or delayed, and the pixel clock density (pixels that fall within a certain region). Number) can be changed.
In such an operation, as shown in FIG. 4, the scanning speed becomes slower toward the end of the photoconductor 40, and the pixel density on the end side becomes higher than the vicinity of the image height 0 in the center. Applies to correction for pixel density variation. That is, when generating a pixel clock that scans near the edge, the pixel on the main scanning surface of the photoreceptor 40 is increased by increasing the value of the phase data or increasing the ratio of generation with high phase data. It becomes possible to correct so that the density becomes uniform.
This correction is caused by the fact that the scanning speed on the main scanning surface of the photoconductor 40 is not uniform due to the optical system or the like, so that the pixel density is variably controlled in accordance with the situation where the scanning speed is not uniform. It is necessary to disperse the ratio to be performed unevenly during main scanning. That is, as shown in FIG. 5, the phase data corresponding to the correction amount corresponding to the image height is input to the pixel clock generation circuit 80 of FIG. 6, and the LD drive unit 62 is controlled using the pixel clock PCLK generated thereby. By driving, deflecting and scanning the laser beam emitted from the LD 63 and writing the pixels, the non-uniformity of the pixel density due to the non-uniform scanning speed is corrected, and the pixel density on the main scanning surface is made uniform. It becomes possible to do.

As described above, the pixel clock generation circuit 80 has a configuration capable of phase shifting in units of clocks.
Accordingly, in the pixel clock generation circuit 80, if the phase data for correcting the pixel position is provided in units of one clock in synchronization with the rising edge of the pixel clock PCLK, the phase shift amount of the pixel clock PCLK is set for each clock. It is also possible to change it.
FIG. 8 is a timing chart showing the generation operation of the pixel clock PCLK when the phase shift is performed in units of clocks. FIG. 8 shows an example in which one clock is generated using the phase data “6” and then the next one clock is generated using the phase data “8”.
In this way, the phase shift of the pixel clock PCLK is controlled in the ± direction in units of the clock width of the high-frequency clock VCLK with a simple configuration in which the phase data input to the pixel clock generation circuit 80 is changed. This can be performed for each clock PCLK. For this reason, not only the phase shift is performed at regular intervals in the scanning area, but also the phase shift points are dispersed non-uniformly, the pixel position is adjusted, and the non-uniform correction of the pixel density due to the fluctuation of the scanning speed is corrected. It becomes possible to carry out with high precision.

As described above, the pixel clock generation circuit 80 provides a basic circuit for controlling the phase shift of the pixel clock PCLK in units of clocks and enables high-accuracy correction. A considerable amount of memory is required to store data and setting values of the comparison circuit, which causes an increase in cost.
Therefore, by dividing the main scanning area as a correction area containing a predetermined number of pixel clocks and setting phase data for the correction area, the pixel clock can be varied in a configuration that can reduce the memory capacity, and the pixel density Correct.
When adopting a correction method that changes the pixel clock by area division, if you try to divide the area with a fixed number of pixel clocks and enable the reduction of memory capacity, the correction amount will correspond to the fluctuation of the local scanning speed On the other hand, since accurate approximation cannot be performed, the correction accuracy does not increase.
For this reason, in the present invention, a variable number of pixel clocks is set for each of a plurality of divided correction areas, and further, a variable pixel clock switching interval (hereinafter referred to as “correction insertion interval” or simply “clock interval” in the area). ”May also be settable. By making these settings possible, the correction insertion position for correcting the pixel clock is determined in accordance with fluctuations in the localized scanning speed, and both reduction in memory capacity and improvement in correction accuracy are achieved.

In the following, a first embodiment relating to a pixel clock generation circuit unit that can set the correction insertion interval in the correction area will be described.
FIG. 9 is a block diagram illustrating a configuration of a pixel clock generation circuit unit according to the first embodiment. FIG. 10 is a diagram for explaining a setting example of divided areas when the main scanning area is divided by the pixel clock generation circuit unit of FIG. FIG. 11 is a diagram illustrating a configuration example of the phase data signal generation circuit of FIG.
The configuration of the pixel clock generation circuit unit shown in FIG. 9 is to divide the main scanning region into a plurality of areas based on the input area division number setting value in addition to the pixel clock generation circuit 80 (FIG. 6) described above. Based on a correction area setting signal generation circuit 90 for generating a setting signal for the correction area, a correction area setting signal from the correction area setting signal generation circuit 90, and a variable clock number setting value for setting a variable number of pixel clocks for each correction area. The pixel clock generation circuit 80 determines the phase shift amount of the pixel clock, the phase data generated by the phase data signal generation circuit 91, and the phase synchronization signal input from the synchronization sensor 61. To generate a pixel clock PCLK.
FIG. 10 shows a divided area when the area of one main scanning line is set to be divided into eight. In this setting example, the entire main scanning region including the non-image region is divided into areas, and the divided regions 2 to 7 are used as the correction areas. However, only the image region may be the area division target. Since the area division is performed based on the area division number setting value, each divided area is equal.

The phase data signal generation circuit 91 shown in FIG. 11 is a circuit for instructing the pixel clock generation circuit 80 (FIG. 9) to generate a variable pixel clock by changing the phase data at the correction insertion interval, and setting the correction clock interval. A circuit 911, a counter 913, a comparison circuit 915, a phase data signal control circuit 917, and the like are included.
The correction clock interval setting circuit 911 receives a correction area setting signal, a variable insertion number for each area, and a variable clock number setting value for determining the correction insertion interval, and a clock interval corresponding to the correction area setting signal and the variable clock number setting value. Generate configuration data. Note that the clock interval setting data includes data indicating a correction amount (phase shift amount) at the set clock interval.
The counter 913 operates at the rising edge of the pixel clock PCLK and counts the pixel clock PCLK. When a reset signal is input from the comparison circuit 915, the count value is reset.
The comparison circuit 915 compares the count value from the counter 913 with the clock interval setting data supplied from the correction clock interval setting circuit 911, and outputs a control signal at the set clock interval. The control signal output from the comparison circuit 915 is data for determining the phase data timing for instructing the generation of the variable clock and for instructing the phase shift amount of the pixel clock in order to correct the positional deviation of the pixel dots. And given as a digital value of several bits.
The phase data signal control circuit 917 outputs phase data corresponding to the control signal from the comparison circuit 915.

The time chart shown in FIG. 12 shows an example where the clock interval set as the correction insertion interval in the correction area is set to an equal interval in the phase data signal generation circuit 91 described above. Here, the setting target area is [n area], the front side of the adjacent areas is [n-1 area], and the back side of the adjacent areas is [n + 1 area].
The image height handled here is defined as 0 at the center of the image area, minus on the scanning start side, and plus on the scanning end side. When the scanning speed is constant over the entire image area, the diagram showing the image height in FIG. 12 is a straight line rising to the right.
In this embodiment, since the slope of [n area] is different from the areas on both sides, the number of variable correction clocks of [n area] is set to 12, and the number of variable clocks of [n−1 area] and [n + 1 area] is set. 0 is set. By adjusting the inclination shape for each area, it is possible to perform approximate pixel displacement correction.

In the first embodiment described above (see FIGS. 9 and 11), the correction insertion number and the correction insertion interval of each correction area are required as the variable clock number setting value input to the correction clock interval setting circuit 911. An example is shown. These set values are values necessary for determining the insertion position of the variable clock, and in order to perform optimum correction, it is desirable to use a method of instructing the set value for each insertion position. However, the input operation is difficult.
Therefore, a setting pattern for determining the insertion position of the variable clock is prepared in advance, and a setting value necessary for determining the insertion position of the variable clock is derived by instructing the correction insertion number and the setting pattern of the correction area. Provide the function.
The second embodiment described below shows an example in which the insertion position of the variable clock can be set by instructing a setting pattern.
FIG. 13 is a diagram illustrating a configuration example of the phase data signal generation circuit of the present embodiment.
A phase data signal generation circuit 91 shown in FIG. 13 is configured to receive a right-justified left-justification setting signal in addition to the phase data signal generation circuit shown in FIG.
The correction clock interval setting circuit 911 receives a right-justified and left-justified setting signal in addition to a variable clock number setting value and a correction area setting signal that determine the correction insertion number of each area, and generates clock interval setting data according to these inputs. . At this time, each of the right-justified and left-justified setting signals selects a setting pattern for determining the insertion position of the variable clock. Note that the selectable setting pattern has a selectable basic pattern as shown in the example of FIG. 12 in which variable clock insertion positions are arranged at equal intervals, and there is no instruction for a right-justified left-justified setting signal. Alternatively, an equally spaced arrangement pattern may be selected.
The correction clock interval setting circuit 911 generates clock interval setting data based on the correction insertion number of the correction area and the selected setting pattern. The subsequent processing of the phase data signal generation circuit 91 that generates the phase data signal is the same as that in the first embodiment.

The time chart shown in FIG. 14 shows an example in which the phase data signal generation circuit 91 shown in FIG. 13 sets the variable clock interval in the area to the left.
Similar to the description of FIG. 12 in which the variable clock insertion position is set, the setting target area is [n area], the front side among the adjacent areas is [n-1 area], and the rear side among the adjacent areas. The side is [n + 1 area].
In this embodiment, the number of variable clock settings for [n area] is 12, and the number of variable clock settings for [n-1 area] and [n + 1 area] is 0. Since the left alignment pattern is set here, the variable clock insertion position is arranged in the left half of [n area]. In this case, the left and right sides have different inclinations from the center of [n area], and the left side is an area that requires correction. By selecting such a setting pattern, the same effect as that obtained by doubling the number of area divisions can be obtained.
In this way, in addition to the phase data signal generation circuit shown in FIG. 11, the clock interval setting pattern can be set to be right-justified or left-justified, so that it is possible to correct the displacement of the pixel with higher accuracy.

The third embodiment described below shows another example in which the insertion position of the variable clock can be set by designating a setting pattern.
FIG. 15 is a diagram illustrating a configuration example of the phase data signal generation circuit of the present embodiment.
A phase data signal generation circuit 91 shown in FIG. 15 is configured to receive a gravity center setting signal in addition to the phase data signal generation circuit shown in FIG.
The correction clock interval setting circuit 911 receives a center-of-gravity setting signal in addition to a variable clock number setting value and a correction area setting signal that determine the correction insertion number of each area, and generates clock interval setting data in response to these inputs. At this time, the center-of-gravity setting signal selects a setting pattern for determining the insertion position of the variable clock in which the correction clock interval is biased. The selectable setting pattern has a setting pattern in which variable clock insertion positions are arranged at equal intervals as shown in the example of FIG. 12 as a selectable basic pattern, and there is no instruction of the center of gravity setting signal. May select an equally spaced arrangement pattern.
The correction clock interval setting circuit 911 generates clock interval setting data based on the correction insertion number of the correction area and the selected setting pattern. The subsequent processing of the phase data signal generation circuit 91 that generates the phase data signal is the same as that in the first embodiment.

The time chart shown in FIG. 16 shows an example in which the phase data signal generation circuit 91 shown in FIG.
Similar to the description of FIG. 12 in which the variable clock insertion position is set, the setting target area is [n area], the front side among the adjacent areas is [n-1 area], and the rear side among the adjacent areas. The side is [n + 1 area].
In this embodiment, the number of variable clock settings for [n area] is 12, and the number of variable clock settings for [n-1 area] and [n + 1 area] is 0. Since the left center-of-gravity pattern is set, the number of variable clocks is arranged closer to [n-1 area] in [n area]. In this case, in [n area], the inclination is larger as it is closer to [n-1 area], and the inclination is smaller as it is closer to [n + 1 area]. By selecting such a setting pattern, an effect similar to that obtained by subdividing the number of divisions of the scanning area can be obtained.
In this way, in addition to the phase data signal generation circuit shown in FIG. 11, it is possible to set the correction clock interval with a bias, so that it is possible to correct the displacement of the pixel with higher accuracy.

The fourth embodiment described below shows an example in which the variable clock insertion position can be set by instructing the setting of a pattern selected from a plurality of types of correction patterns.
FIG. 17 is a block diagram illustrating a configuration of a pixel clock generation circuit unit according to the fourth embodiment. The phase data signal generation circuit 91 shown in FIG. 17 is a diagram showing a configuration in which a correction pattern setting signal input is added to the circuit shown in FIG.
FIG. 18 is a diagram illustrating a configuration example of the phase data signal generation circuit 91 of the present embodiment. The phase data signal generation circuit 91 shown in FIG. 18 has a configuration in which a correction pattern selection circuit 911s is added to the correction clock interval setting circuit 911 of the phase data signal generation circuit 91 shown in FIG.
The correction pattern selection circuit 911s prepares a plurality of types of correction patterns such as an equally spaced pattern, a left-justified pattern, a right-justified pattern, a left centroid pattern, and a right centroid pattern as shown in the first to third embodiments. One pattern can be selected from among the patterns according to the correction pattern setting signal. Furthermore, as the setting pattern, a pattern in which a large number of correction clocks are arranged at the center of the area or a pattern in which a large number of correction clocks are arranged outside the area may be selectable.
In this manner, by making it possible to select an adaptive pattern from a plurality of types of correction clock interval setting patterns, it is possible to correct pixel misalignment corresponding to various cases.

The fifth embodiment described below shows another example in which the insertion position of the variable clock can be set by selecting a pattern from a plurality of types of correction patterns.
In the present embodiment, a correction pattern is selected based on the variable clock number setting value input in the area before and after the area for which the correction pattern is set, and smooth characteristics can be obtained at the boundary of the area. .
FIG. 19 is a diagram illustrating a configuration example of the phase data signal generation circuit 91 according to the fifth embodiment. The phase data signal generation circuit 91 shown in FIG. 19 is a diagram showing a configuration in which the correction pattern setting signal of the same circuit shown in FIG.
The correction pattern selection circuit 911s has a correction pattern selection table in which a correction pattern suitable for the combination of the variable clock number setting value of the target area and the variable clock number setting value of the front and rear areas is stored in advance, and the input variable clock The correction pattern to be set is determined by referring to the pattern selection table according to the combination of the number setting values, and the equally spaced pattern, the left-justified pattern, the right-justified pattern, and the left centroid pattern as shown in the first to third embodiments. The determined pattern is selected from a plurality of types of correction patterns such as the right center of gravity pattern. Furthermore, as a correction pattern to be selected, a pattern in which many correction clocks are arranged at the center of the area or a pattern in which many correction clocks are arranged outside the area may be used.
As described above, by referring to the variable clock number setting values in the front and rear areas and making it possible to select an optimal correction clock interval setting pattern, it is possible to correct pixel misalignment corresponding to various cases.

In the time chart shown in FIG. 20, in the phase data signal generation circuit 91 shown in FIG. 19, the variable clock setting number of [n area] is 12, the variable clock setting number of [n−1 area] is 24, and [n + 1]. The correction pattern setting example when the variable clock setting number of [Area] is 0 is shown.
When the set number of variable clocks has a relationship of [n-1 area]> [n area]> [n + 1 area], the inclination of the image height is larger in [n-1 area] than in [n area]. In addition, the inclination of the image height tends to be smaller in [n + 1 area] than in [n area]. At this time, by setting the left center-of-gravity pattern as the correction pattern, the number of variable clock insertion positions is closer to [n-1 area] within [n area], so that [n area] It is possible to increase the inclination as the [n-1 area] is closer, and to decrease the inclination as the [n + 1 area] is closer.
In this way, when the set number of variable clocks has a relationship of [n-1 area]> [n area]> [n + 1 area], by setting the left center of gravity pattern, the front and rear of the area It is possible to perform smoother correction at the boundary.

The time chart shown in FIG. 20 shows the case where the number of variable clocks set to [n area], [n−1 area], and [n + 1 area] in the phase data signal generation circuit 91 shown in FIG. An example of correction pattern setting is shown.
When the set number of variable clocks has a relationship of [n-1 area] = [n area] = [n + 1 area], the inclination of the image height in each area becomes equal. At this time, by setting an equally spaced pattern as the correction pattern, the variable clock insertion positions are arranged at equal intervals in [n area], so that the slope is constant in [n area].
In this way, when the set number of variable clocks has a relationship of [n-1 area] = [n area] = [n + 1 area], by setting an equally spaced pattern, the boundary before and after the area Thus, smoother correction can be performed. Also, the variable clock setting value in each area is large, and the difference between the setting values in each area is small, and the number of set variable clocks is [n-1 area] ≈ [n area] ≈ [n + 1 area] ], An equally spaced pattern may be set.

In the time chart shown in FIG. 22, in the phase data signal generation circuit 91 shown in FIG. 19, the variable clock setting number of [n area] is set to 12, the variable clock setting number of [n−1 area] is set to 0, and [n + 1]. An example of correction pattern setting when the number of variable clock settings in [Area] is 24 is shown.
When the set number of variable clocks has a relationship of [n-1 area] <[n area] <[n + 1 area], the inclination of the image height is larger in [n-1 area] than in [n area]. In addition, the inclination of the image height tends to be larger in [n + 1 area] than in [n area]. At this time, by setting the right center-of-gravity pattern as the correction pattern, the number of variable clock insertion positions is closer to [n + 1 area] in [n area], so that more variable clocks are arranged in [n area]. The closer to [n + 1 area], the larger the slope, and the closer to [n-1 area], the smaller the slope.
In this way, when the set number of variable clocks has a relationship of [n−1 area] <[n area] <[n + 1 area], the boundary between the front and rear of the area is set by setting the right center of gravity pattern. Thus, smoother correction can be performed.
20 to 22 show setting examples in the case of referring only to adjacent areas, but not only [n-1 area] and [n + 1 area] but also reference to the front and rear 2 areas and the front and rear 3 areas. A corresponding correction pattern selection table may be prepared to determine a correction pattern.

1 shows a schematic configuration of a color copying machine according to an embodiment of the present invention. 2 shows a schematic configuration around an exposure apparatus included in the color copying machine of FIG. 3 shows a writing optical path to the photosensitive member by the light beam output from the LD of FIG. It is a diagram showing an example of the distribution of the scanning speed of the light beam with respect to the image height of the photoreceptor. FIG. 5 is a diagram in which a correction amount having reverse characteristics is obtained based on the scanning speed distribution with respect to the image height in FIG. 4. It is the block diagram which showed one structural example of the pixel clock generation circuit which produces | generates a pixel clock based on phase data. 6 is a timing chart for explaining the operation of the pixel clock generation circuit. 12 is a timing chart illustrating another operation of the pixel clock generation circuit. FIG. 2 is a block diagram illustrating a configuration of a pixel clock generation circuit unit according to the first embodiment. A divided area when the area of one main scanning line is set to be divided into eight is shown. 10 shows an internal configuration of the phase data signal generation circuit shown in FIG. The timing chart at the time of setting the correction | amendment insertion space | interval in a correction | amendment area at equal intervals is shown. The structure of the phase data signal generation circuit concerning 2nd Embodiment is shown. FIG. 14 is a timing chart when the correction insertion interval in the correction area is set to the left in the circuit of FIG. The structure of the phase data signal generation circuit concerning 3rd Embodiment is shown. FIG. 16 is a timing chart when the correction insertion interval in the correction area is set to the left center of gravity in the circuit of FIG. It is a block diagram which shows the structure of the pixel clock generation circuit part concerning 4th Embodiment. 18 shows an internal configuration of the phase data signal generation circuit shown in FIG. 10 shows a configuration of a phase data signal generation circuit according to a fifth embodiment. In the circuit of FIG. 19, a timing chart when the correction pattern of the left center of gravity is selected as the correction insertion interval in the correction area is shown. FIG. 20 shows a timing chart when a regular correction pattern is selected as the correction insertion interval in the correction area in the circuit of FIG. FIG. 20 shows a timing chart when the right center of gravity correction pattern is selected as the correction insertion interval in the correction area in the circuit of FIG.

Explanation of symbols

21 ... Exposure device 40 ... Photoconductor
60..Write controller 61..Synchronous sensor,
62 .. LD drive part, 63 .. LD (laser diode),
67 .. Polygon mirror, 80 .. Pixel clock generation circuit,
90 .. Correction area setting signal generation circuit,
91..Phase data signal generation circuit, 100.Copier body,
200 ... Paper feed table, 300 ... Scanner,
400. Automatic document feeder (ADF).

Claims (5)

A light source, light beam scanning means for projecting light output from the light source as a scanning beam to the image carrier, and lighting of the light source are controlled based on image data. An image forming apparatus having a lighting control means for adjusting a lighting timing by changing a pixel clock according to phase data indicating a shift amount, wherein the lighting control means is a light control means for adjusting a lighting timing. Means for dividing a scanning region by a beam into a plurality of areas, means for setting a variable number of pixel clocks for each divided area, and pixel clock switching interval setting means for setting a switching interval between variable pixel clocks in the divided area setting pattern includes, and the pixel clock switching interval setting means, to place the switching intervals equally spaced over the divided areas throughout divided et A) There are at least two types of patterns in the setting pattern in which switching is performed only in the range of the right half or the left half and the switching interval is arranged at equal intervals and the setting pattern in which the switching interval is biased. An image forming apparatus characterized in that a switching interval between variable pixel clocks is set in accordance with an instruction of one selected setting pattern . 2. The image forming apparatus according to claim 1, wherein the pixel clock switching interval setting means includes a plurality of patterns based on a variable number of pixel clocks respectively set in a divided area to be set and divided areas around the divided area. An image forming apparatus comprising setting pattern determining means for determining one setting pattern to be selected from the following . 3. The image forming apparatus according to claim 2 , wherein the setting pattern determining unit is configured to set “pre-divided area setting” for a variable number of pixel clocks respectively set in a setting target divided area and a divided area around the divided area. Many variable numbers of pixel clocks are arranged on the side closer to the previous division area within the division area to be set on the condition that “value”> “setting value of the setting division area”> “setting value of the subsequent division area”. An image forming apparatus that determines a pattern to be set as a setting pattern . 3. The image forming apparatus according to claim 2 , wherein the setting pattern determining unit is configured to set “pre-divided area setting” for a variable number of pixel clocks respectively set in a setting target divided area and a divided area around the divided area. As a setting pattern, a pattern that arranges switching intervals at equal intervals in the setting target divided area is set on condition that “value” ≈ “setting value of setting target divided area” ≈ “setting value of subsequent divided area”. An image forming apparatus. 3. The image forming apparatus according to claim 2 , wherein the setting pattern determining unit is configured to set “pre-divided area setting” for a variable number of pixel clocks respectively set in a setting target divided area and a divided area around the divided area. Many variable numbers of pixel clocks are placed on the side closer to the rear division area within the subdivision area to be set, provided that “value” <“setting value of the setting target division area” <“setting value of the rear division area”. An image forming apparatus that determines a pattern to be set as a setting pattern .

Images