JP4384948B2 - Power module - Google Patents

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JP4384948B2
JP4384948B2 JP2004217293A JP2004217293A JP4384948B2 JP 4384948 B2 JP4384948 B2 JP 4384948B2 JP 2004217293 A JP2004217293 A JP 2004217293A JP 2004217293 A JP2004217293 A JP 2004217293A JP 4384948 B2 JP4384948 B2 JP 4384948B2
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conductor pattern
semiconductor element
power semiconductor
terminal
positive
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JP2006041098A (en
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慶太 橋元
伸一 藤野
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Hitachi Ltd
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    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Description

本発明は、パワーモジュールに係り、特に実装面積を低減することのできるパワーモジュールの実装技術に関する。   The present invention relates to a power module, and more particularly to a power module mounting technique capable of reducing a mounting area.

近年、駆動負荷の出力の増大に伴い、パワーモジュールを構成するパワー半導体素子に流れる負荷電流が増大してきている。パワー半導体素子内で発熱として失われる損失は、負荷電流の二乗に比例するため、パワー半導体素子を複数の素子で構成すると共にこれらの素子を並列に配置することにより、各パワー半導体素子に流れる電流を減少させて、損失を抑える手法がとられている（特許文献１，特許文献２参照）。
特開２００２-３６８１９２号公報 特開平５-８３９４７号公報 In recent years, with an increase in the output of the driving load, the load current flowing through the power semiconductor element constituting the power module has increased. Since the loss lost as heat generation in the power semiconductor element is proportional to the square of the load current, the current flowing through each power semiconductor element can be obtained by configuring the power semiconductor element with a plurality of elements and arranging these elements in parallel. Is used to reduce the loss (see Patent Document 1 and Patent Document 2).
JP 2002-368192 A JP-A-5-83947

上記特許文献に示すように、パワー半導体素子を複数の素子で構成すると共にこれらの素子を並列に配置することにより、各パワー半導体素子に流れる電流を減少させて、損失を抑えることはできる。   As shown in the above-mentioned patent document, the power semiconductor element is constituted by a plurality of elements and these elements are arranged in parallel, whereby the current flowing through each power semiconductor element can be reduced and the loss can be suppressed.

しかし、パワー半導体素子を複数の素子で構成し、これらの素子を並列に配置する場合は、これらの並列配置されたパワー半導体素子に負荷電流を均等に分配するため、これらのパワー半導体素子を同一のタイミングで駆動しなければならない。このため、各半導体素子に対する信号配線が複雑化し、パワーモジュールの実装面積も増大することになる。 本発明は、これらの問題点に鑑みてなされたもので、実装面積を低減することのできるパワーモジュールの実装技術を提供するものである。   However, when a power semiconductor element is composed of a plurality of elements and these elements are arranged in parallel, the load currents are evenly distributed to the power semiconductor elements arranged in parallel. It must be driven at the timing. This complicates the signal wiring for each semiconductor element and increases the mounting area of the power module. The present invention has been made in view of these problems, and provides a power module mounting technique capable of reducing the mounting area.

本発明は上記課題を解決するため、次のような手段を採用した。   In order to solve the above problems, the present invention employs the following means.

正極側パワー半導体素子の一方の端子を接続した正極導電体パターンと、正極側パワー半導体素子の他方の端子および負極側パワー半導体素子の一方の端子を接続した中間電位導電体パターンと、負極側パワー半導体素子の他方の端子を接続した負極導電体パターンを備え、正極導電体パターンと負極導電体パターン間に電源電圧を印加し中間電位導電体パターンから変換出力を取り出す単位モジュールを並列接続したパワーモジュールにおいて、並列接続される単位モジュールにおける対応するパワー半導体素子に共通のゲート信号を中継し分配する中継基板を備え、前記各単位モジュールにおける対応するパワー半導体素子は前記中継基板の長手方向に対して対称となるように配置した。 A positive conductor pattern connecting one terminal of the positive power semiconductor element, an intermediate potential conductor pattern connecting the other terminal of the positive power semiconductor element and one terminal of the negative power semiconductor element, and a negative power A power module having a negative electrode conductor pattern connected to the other terminal of the semiconductor element, and having unit modules connected in parallel to apply a power supply voltage between the positive electrode conductor pattern and the negative electrode conductor pattern and extract a conversion output from the intermediate potential conductor pattern And a relay substrate for relaying and distributing a common gate signal to the corresponding power semiconductor elements in the unit modules connected in parallel, and the corresponding power semiconductor elements in each unit module are symmetrical with respect to the longitudinal direction of the relay substrate It arranged so that it might become .

本発明は、以上の構成を備えるため、パワー半導体素子を複数の素子で構成する大出力のパワーモジュールにおいても、その実装面積低減することができる。   Since the present invention has the above-described configuration, the mounting area can be reduced even in a high-output power module in which a power semiconductor element is configured by a plurality of elements.

以下、本発明の実施形態を図１ないし図３を用いて説明する。図１、図２、図３において、同じもの及び同じ機能を有するものは同じ符号を付した。図１は、本実施形態のパワーモジュールの上面図である。図１において、１はケース、２は絶縁基板、３は正極直流端子、４は負極直流端子、５，６，７は出力端子、１０ａ，１０ｂ，１０ｃ，１０ｄ，１０ｅ，１０ｆは信号用中継基板、２０ａ，２０ｂ，２０ｃ，２０ｄ，２０ｅ，２０ｆ，２０ｇ，２０ｈ，２０ｉ，２０ｊ，２０ｋ，２０ｍはパワー半導体素子を構成するＭＯＳＦＥＴである。ケース１はプラスチック製であり、正極直流端子３，負極直流端子４，出力端子５，６，７はそれぞれケース１にインサートすることにより保持されている。   Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3. In FIG. 1, FIG. 2, FIG. 3, the same thing and the thing which has the same function attached | subjected the same code | symbol. FIG. 1 is a top view of the power module of the present embodiment. In FIG. 1, 1 is a case, 2 is an insulating substrate, 3 is a positive DC terminal, 4 is a negative DC terminal, 5, 6 and 7 are output terminals, 10a, 10b, 10c, 10d, 10e, and 10f are signal relay boards. , 20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h, 20i, 20j, 20k, and 20m are MOSFETs constituting the power semiconductor element. The case 1 is made of plastic, and the positive DC terminal 3, the negative DC terminal 4, the output terminals 5, 6, and 7 are held by being inserted into the case 1, respectively.

信号用中継基板１０ａ，１０ｂ，１０ｃ，１０ｄ，１０ｅ，１０ｆは絶縁基板２に接着剤により接着されており、，ＭＯＳＦＥＴ２０ａ，２０ｃ（２０ｂ，２０ｄ，２０ｅ，２０ｆ，２０ｇ，２０ｈ，２０ｉ，２０ｊ，２０ｋ，２０ｍも同様）は、それぞれ中間電位導電体パターン５０あるいは正極導電体パターン４０にハンダを介して、信号用中継基板１０ａ（１０ｂ，１０ｃ，１０ｄ，１０ｅ，１０ｆに対しても同様）の長手方向に対して対称になるように固着されている。   The signal relay boards 10a, 10b, 10c, 10d, 10e, and 10f are bonded to the insulating board 2 with an adhesive, and MOSFETs 20a and 20c (20b, 20d, 20e, 20f, 20g, 20h, 20i, 20j, and 20k). , 20m is also the same as the longitudinal direction of the signal relay substrate 10a (same as 10b, 10c, 10d, 10e, 10f) via solder to the intermediate potential conductor pattern 50 or the positive electrode conductor pattern 40, respectively. It is fixed so as to be symmetrical with respect to.

このように、各ＭＯＳＦＥＴ（例えばＭＯＳＦＥＴ２０ａ、２０ｃ）を信号用中継基板１０ａに対して等距離になるように実装するため、これらの並列配置ＭＯＳＦＥＴ２０ａ、２０ｃを同時に駆動して、それらに流れる負荷電流を均等に分配することができる。また、制御信号を絶縁基板２上に配置した信号用中継基板１０ａ，１０ｂ，１０ｃ，１０ｄ，１０ｅ，１０ｆに集約することにより、信号配線パターンを絶縁基板２上に直接配置する必要がなくなる。絶縁基板２上に配線パターンを直接配置する場合には、通常エッチングによってパターンを形成するため、配線幅および配線間のピッチを小さくすることが困難である。これに対して、信号用中継基板１０ａ，１０ｂ，１０ｃ，１０ｄ，１０ｅ，１０ｆを設ける場合は印刷により配線パターンを作成することができる。このため、線幅およびピッチを小さくすることができ、多層化も可能である。   Thus, in order to mount each MOSFET (for example, MOSFET 20a, 20c) so that it may become equidistance with respect to the signal relay board | substrate 10a, these parallel arrangement | sequence MOSFETs 20a, 20c are driven simultaneously, and the load current which flows through them is changed. Can be distributed evenly. Further, by collecting the control signals on the signal relay boards 10a, 10b, 10c, 10d, 10e, and 10f arranged on the insulating substrate 2, it is not necessary to directly arrange the signal wiring pattern on the insulating substrate 2. When the wiring pattern is directly arranged on the insulating substrate 2, since the pattern is formed by normal etching, it is difficult to reduce the wiring width and the pitch between the wirings. On the other hand, when the signal relay boards 10a, 10b, 10c, 10d, 10e, and 10f are provided, the wiring pattern can be created by printing. For this reason, the line width and pitch can be reduced, and multilayering is also possible.

このため、従来、絶縁基板２上で行っていた信号の統合および分配を信号用中継基板１０ａ，１０ｂ，１０ｃ，１０ｄ，１０ｅ，１０ｆ上で行うことができ、実装面積を減少させ、ワイヤ経路も単純化することができ、結果として配線インピーダンスを低減することができる。また、ワイヤ経路を単純化することにより、ワイヤの長さを短くすることができる。これによりワイヤの固有振動数を増加することができ、ワイヤの振動に対する耐性を高めることができる。   Therefore, integration and distribution of signals conventionally performed on the insulating substrate 2 can be performed on the signal relay substrates 10a, 10b, 10c, 10d, 10e, and 10f, reducing the mounting area and the wire path. It can be simplified, and as a result, the wiring impedance can be reduced. Further, by simplifying the wire path, the length of the wire can be shortened. As a result, the natural frequency of the wire can be increased, and resistance to vibration of the wire can be increased.

図２は、図１に示すパワーモジュール信号用中継基板周辺の拡大図である。図２において、３０ａ，３０ｂ，３０ｃ，３０ｄは絶縁基板２表面に形成した負極銅パターン、４０は絶縁基板２表面に形成した正極銅パターン、５０は絶縁基板２表面に形成した中間電位導電体パターン、１０１ａ，１０１ｂ，１０２ａ，１０２ｂ，１０３ａ，１０３ｂ，１０４ａ，１０４ｂ，１０５ａ，１０５ｂ，１０６ａ，１０６ｂ，１０７ａ，１０７ｂはアルミワイヤ、１１０ａ，１１０ｂは信号用中継端子を表す。   FIG. 2 is an enlarged view around the power module signal relay board shown in FIG. In FIG. 2, 30a, 30b, 30c, 30d are negative copper patterns formed on the surface of the insulating substrate 2, 40 is a positive copper pattern formed on the surface of the insulating substrate 2, and 50 is an intermediate potential conductor pattern formed on the surface of the insulating substrate 2. , 101a, 101b, 102a, 102b, 103a, 103b, 104a, 104b, 105a, 105b, 106a, 106b, 107a, 107b are aluminum wires, and 110a, 110b are signal relay terminals.

信号用中継端子１１０ａ，１１０ｂはパワーモジュールと図示しない制御基板の間の信号配線であり、ケース１にインサートされている。正極直流端子３はアルミワイヤ１０１ａ，１０１ｂを介して、絶縁基板２の表面に形成した正極銅パターン４０と接続される。ＭＯＳＦＥＴ２０ｂ，２０ｄのドレインはハンダにより絶縁基板２に表面に形成した正極銅パターン４０と電気的に接合され、ソースは絶縁基板２表面の中間電位導電体パターン５０とアルミワイヤ１０２ａ，１０２ｂを介して接続される。また、この中間電位導電体パターン５０はアルミワイヤ１０４ａ，１０４ｂを介して、出力端子５に接続される。   The signal relay terminals 110 a and 110 b are signal wirings between the power module and a control board (not shown), and are inserted in the case 1. The positive DC terminal 3 is connected to a positive copper pattern 40 formed on the surface of the insulating substrate 2 via aluminum wires 101a and 101b. The drains of the MOSFETs 20b and 20d are electrically joined to the positive copper pattern 40 formed on the surface of the insulating substrate 2 by solder, and the sources are connected to the intermediate potential conductor pattern 50 on the surface of the insulating substrate 2 via the aluminum wires 102a and 102b. Is done. The intermediate potential conductor pattern 50 is connected to the output terminal 5 via aluminum wires 104a and 104b.

ＭＯＳＦＥＴ２０ａ，２０ｃのドレインは絶縁基板２表面に形成した中間電位導電体パターン５０とハンダにより電気的に接続され、ソースはアルミワイヤ１０３ａ，１０３ｂを介して、絶縁基板２表面に形成した負極銅パターン３０ｂ，３０ｃと接続される。ＭＯＳＦＥＴ２０ｂ，２０ｄのゲートはアルミワイヤ１０６ａ，１０６ｂを介して信号用中継基板１０ｂに接続され、ＭＯＳＦＥＴ２０ｂ，２０ｄのゲートはアルミワイヤ１０６ａ，１０６ｂを介して信号用中継基板１０ｂに接続される。   The drains of the MOSFETs 20a and 20c are electrically connected to the intermediate potential conductor pattern 50 formed on the surface of the insulating substrate 2 by solder, and the sources are negative copper patterns 30b formed on the surface of the insulating substrate 2 via the aluminum wires 103a and 103b. , 30c. The gates of the MOSFETs 20b and 20d are connected to the signal relay substrate 10b via the aluminum wires 106a and 106b, and the gates of the MOSFETs 20b and 20d are connected to the signal relay substrate 10b via the aluminum wires 106a and 106b.

このように、正極導電体パターン４０、ＭＯＳＦＥＴ２０ｂ、中間電位導電体パターン５０、ＭＯＳＦＥＴ２０ａ、負極導電体パターン３０ｂにより、正極導電体パターンと負極導電体パターン間に電源電圧を印加し中間電位導電体パターンから変換出力を取り出すことのできる単位モジュールが形成されることになる。同様に、正極導電体パターン４０、ＭＯＳＦＥＴ２０ｄ、中間電位導電体パターン５０、ＭＯＳＦＥＴ２０ｃ、負極導電体パターン３０ｃにより、正極導電体パターンと負極導電体パターン間に電源電圧を印加し中間電位導電体パターンから変換出力を取り出すことのできる他の単位モジュールが形成されることになる。そして、各単位モジュールの組み合わせにより一相分のパワーモジュールが構成される。   In this way, the positive electrode conductor pattern 40, the MOSFET 20b, the intermediate potential conductor pattern 50, the MOSFET 20a, and the negative electrode conductor pattern 30b are used to apply a power supply voltage between the positive electrode conductor pattern and the negative electrode conductor pattern, and from the intermediate potential conductor pattern. A unit module capable of taking out the conversion output is formed. Similarly, the positive electrode conductor pattern 40, the MOSFET 20d, the intermediate potential conductor pattern 50, the MOSFET 20c, and the negative electrode conductor pattern 30c are converted from the intermediate potential conductor pattern by applying a power supply voltage between the positive electrode conductor pattern and the negative electrode conductor pattern. Another unit module from which output can be extracted is formed. And the power module for one phase is comprised by the combination of each unit module.

また、ＭＯＳＦＥＴ２０ａ，２０ｃ，２０ｂ，２０ｄを信号用中継基板１０ａ，１０ｂに対してそれぞれ対称に配置することにより、信号配線用アルミワイヤ１０６ａと１０６ｂ，１０７ａと１０７ｂの長さをそれぞれ等しくすることができ、ＭＯＳＦＥＴ２０ａと２０ｃ、２０ｂと２０ｄの間における配線インピーダンスを等しくすることができる。   Further, by arranging the MOSFETs 20a, 20c, 20b, and 20d symmetrically with respect to the signal relay boards 10a and 10b, the lengths of the aluminum wires 106a and 106b, 107a and 107b for signal wiring can be made equal, respectively. The wiring impedances between the MOSFETs 20a and 20c and the MOSFETs 20b and 20d can be made equal.

図３は、信号用中継基板の詳細を説明する図である。図において、２００はセラミック基板である。２０１ａ，２０１ｂ，２０１ｃ，２０１ｄ，２０１ｅ，２０１ｆ，２０１ｇ，２０１ｈ，２０１ｉ，２０１ｊ，２０１ｋ，２０１ｍ，２０１ｎ，２０１ｐはパッド、２０２ａ，２０２ｂはゲート抵抗、２０３ａ，２０３ｂ，２０３ｃ，２０３ｄ，２０３ｅ，２０３ｆは信号配線、２０４は配線を固定するための絶縁ガラスを表す。   FIG. 3 is a diagram illustrating details of the signal relay board. In the figure, reference numeral 200 denotes a ceramic substrate. 201a, 201b, 201c, 201d, 201e, 201f, 201g, 201h, 201i, 201j, 201k, 201m, 201n, 201p are pads, 202a, 202b are gate resistors, 203a, 203b, 203c, 203d, 203e, 203f are signals A wiring 204 represents an insulating glass for fixing the wiring.

信号配線２０３ａ，２０３ｂ，２０３ｃ，２０３ｄ，２０３ｅ，２０３ｆはセラミック基板２００上に印刷により設けられ、ゲート抵抗２０２ａ，２０２ｂは印刷によりセラミック基板２００上に印刷した後、エッチングにより抵抗値が調整される。パッド２０１ａ，２０１ｂ，２０１ｃ，２０１ｄ，２０１ｅ，２０１ｆ，２０１ｇ，２０１ｈ，２０１ｉ，２０１ｊ，２０１ｋ，２０１ｍ，２０１ｎ，２０１ｐは信号配線２０３ａ，２０３ｂ，２０３ｃ，２０３ｄ，２０３ｅ，２０３ｆ上にハンダにより接続される。また、パッド２０１ａ，２０１ｂ，２０１ｃ，２０１ｄ，２０１ｅ，２０１ｆ，２０１ｇ，２０１ｈ，２０１ｉは、図２におけるＭＯＳＦＥＴ２０ａ，２０ｂ，２０ｃ，２０ｄのゲートとアルミワイヤ１０６ａ，１０６ｂ，１０７ａ，１０７ｂを介して接続される。   The signal wirings 203a, 203b, 203c, 203d, 203e, and 203f are provided on the ceramic substrate 200 by printing, and the gate resistors 202a and 202b are printed on the ceramic substrate 200 by printing, and then the resistance value is adjusted by etching. The pads 201a, 201b, 201c, 201d, 201e, 201f, 201g, 201h, 201i, 201j, 201k, 201m, 201n, and 201p are connected to the signal wirings 203a, 203b, 203c, 203d, 203e, and 203f by solder. The pads 201a, 201b, 201c, 201d, 201e, 201f, 201g, 201h, 201i are connected to the gates of the MOSFETs 20a, 20b, 20c, 20d in FIG. 2 through the aluminum wires 106a, 106b, 107a, 107b. .

また，信号配線のクロス部は絶縁ガラス２０４を配線間に配置することにより絶縁して固定することができる。この構成では、ゲート抵抗２０２ａ，２０２ｂをＭＯＳＦＥＴ近傍に配置することができ，信号配線のインダクタンスを減少することができる。   In addition, the cross portion of the signal wiring can be insulated and fixed by disposing the insulating glass 204 between the wirings. In this configuration, the gate resistors 202a and 202b can be disposed in the vicinity of the MOSFET, and the inductance of the signal wiring can be reduced.

なお、前記パワー半導体素子は、ＭＯＳＦＥＴ等の主半導体素子、温度測定用のダイオードおよび分流用のＭＯＳＦＥＴ等からなる補助半導体素子を備える複合素子で構成することができる。この場合、パッド２０１ｊは信号配線２０３ｂ、パッド２０１ｅを介して前記ダイオードのカソードに接続し、パッド２０１ｋは信号配線２０３ｃ、パッド２０１ｆを介して前記ダイオードのアノードに接続する。また、パッド２０１ｍは信号配線２０３ｅ、ゲート抵抗２０２ａ，２０２ｂ、パッド２０１ｃ，２０１ｇを介してそれぞれ主制御素子のゲートに接続する。また、パッド２０１ｎは信号配線２０３ｄ、パッド２０１ｈ，２０１ｂを介してそれぞれ主半導体素子のソースに接続する。また、パッド２０１ｐは信号配線２０３ｆ，２０３ａ、パッド２０１ｉ，２０１ｄを介してそれぞれ補助半導体素子のソース（分流電流の出力端）に接続する。   The power semiconductor element can be composed of a composite element including a main semiconductor element such as a MOSFET, a temperature measuring diode, a shunting MOSFET, and the like. In this case, the pad 201j is connected to the cathode of the diode through the signal wiring 203b and the pad 201e, and the pad 201k is connected to the anode of the diode through the signal wiring 203c and the pad 201f. The pad 201m is connected to the gate of the main control element through the signal wiring 203e, the gate resistors 202a and 202b, and the pads 201c and 201g. The pad 201n is connected to the source of the main semiconductor element through the signal wiring 203d and the pads 201h and 201b. The pad 201p is connected to the source of the auxiliary semiconductor element (the output terminal of the shunt current) through the signal wirings 203f and 203a and the pads 201i and 201d, respectively.

以上説明したように、本実施形態によれば、並列接続されたパワー半導体素子間に、信号配線を統合し分配する中継基板を前記絶縁基板とは別個に設けるため、パワーモジュールを配置した高耐圧の絶縁基板上に信号配線を直接形成する場合に比して、形成する信号配線の耐圧を低減して信号配線のサイズを小型化することができる。このため信号配線を簡略化することができ、また、各パワー半導体素子に信号を供給する信号配線の面積を減少させて、パワーモジュールの小型化を図ることができる。   As described above, according to the present embodiment, a relay substrate that integrates and distributes signal wiring between power semiconductor elements connected in parallel is provided separately from the insulating substrate. As compared with the case where the signal wiring is directly formed on the insulating substrate, the withstand voltage of the signal wiring to be formed can be reduced and the size of the signal wiring can be reduced. Therefore, the signal wiring can be simplified, and the area of the signal wiring for supplying a signal to each power semiconductor element can be reduced, and the power module can be downsized.

本実施形態のパワーモジュールの上面図である。It is a top view of the power module of this embodiment. 図１に示すパワーモジュール信号用中継基板周辺の拡大図である。FIG. 2 is an enlarged view around a power module signal relay board shown in FIG. 1. 信号用中継基板の詳細を説明する図である。It is a figure explaining the detail of the relay board for signals.

符号の説明Explanation of symbols

１ ケース
２ 絶縁基板
３ 正極直流端子
４ 負極直流端子
５，６，７ 出力端子
１０ａ，１０ｂ，１０ｃ，１０ｄ，１０ｅ，１０ｆ 信号用中継基板
２０ａ，２０ｂ，２０ｃ，２０ｄ，２０ｅ，２０ｆ，２０ｇ，２０ｈ，２０ｉ，２０ｊ， ２０ｋ，２０ｍ ＭＯＳＦＥＴ
３０ａ，３０ｂ，３０ｃ 負極銅パターン
４０ 正極銅パターン
５０ 中間電位導電体パターン，
１０１ａ，１０１ｂ，１０２ａ，１０２ｂ，１０３ａ，１０３ｂ，１０４ａ，１０４ｂ， １０５ａ，１０５ｂ，１０６ａ，１０６ｂ，１０７ａ，１０７ｂ アルミワイヤ
１１０ａ，１１０ｂ 信号用中継端子
２００ セラミック基板
２０１ａ，２０１ｂ，２０１ｃ，２０１ｄ，２０１ｅ，２０１ｆ，２０１ｇ，２０１ｈ，２０１ｉ，２０１ｊ，２０１ｋ，２０１ｍ，２０１ｎ，２０１ｐ パッド
２０２ａ，２０２ｂ ゲート抵抗
２０３ａ，２０３，ｂ，２０３ｃ，２０３ｄ，２０３ｅ，２０３ｆ 信号配線
２０４ 絶縁ガラス 1 Case 2 Insulating board 3 Positive DC terminal 4 Negative DC terminal 5, 6, 7 Output terminal 10a, 10b, 10c, 10d, 10e, 10f Signal relay board 20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h , 20i, 20j, 20k, 20m MOSFET
30a, 30b, 30c negative copper pattern 40 positive copper pattern 50 intermediate potential conductor pattern,
101a, 101b, 102a, 102b, 103a, 103b, 104a, 104b, 105a, 105b, 106a, 106b, 107a, 107b Aluminum wire 110a, 110b Signal relay terminal 200 Ceramic substrate 201a, 201b, 201c, 201d, 201e, 201f , 201g, 201h, 201i, 201j, 201k, 201m, 201n, 201p Pad 202a, 202b Gate resistance 203a, 203, b, 203c, 203d, 203e, 203f Signal wiring 204 Insulating glass

Claims (1)

正極側パワー半導体素子の一方の端子を接続した正極導電体パターンと、
正極側パワー半導体素子の他方の端子および負極側パワー半導体素子の一方の端子を接続した中間電位導電体パターンと、
負極側パワー半導体素子の他方の端子を接続した負極導電体パターンを備え、
正極導電体パターンと負極導電体パターン間に電源電圧を印加し中間電位導電体パターンから変換出力を取り出す単位モジュールを並列接続したパワーモジュールにおいて、
並列接続される単位モジュールにおける対応するパワー半導体素子に共通のゲート信号を中継し分配する中継基板を備え、
前記各単位モジュールにおける対応するパワー半導体素子は前記中継基板の長手方向に対して対称となるように配置したことを特徴とするパワーモジュール。 A positive electrode conductor pattern connected to one terminal of the positive power semiconductor element;
An intermediate potential conductor pattern connecting the other terminal of the positive power semiconductor element and one terminal of the negative power semiconductor element;
A negative electrode conductor pattern connected to the other terminal of the negative power semiconductor element,
In a power module in which unit modules that apply a power supply voltage between a positive electrode conductor pattern and a negative electrode conductor pattern and extract a conversion output from the intermediate potential conductor pattern are connected in parallel
A relay board that relays and distributes a common gate signal to the corresponding power semiconductor elements in the unit modules connected in parallel;
The power module corresponding to each unit module is arranged so as to be symmetric with respect to the longitudinal direction of the relay substrate .
JP2004217293A 2004-07-26 2004-07-26 Power module Expired - Fee Related JP4384948B2 (en)

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