JP4375373B2 - Frequency detection circuit, optical receiver using the same, and optical transmission system - Google Patents

Description

  The present invention relates to a frequency detection circuit, an optical receiver using the same, and an optical transmission system, and in particular, detects the frequency of a regenerated information electrical signal or a clock signal regenerated in synchronization with the information electrical signal in an optical receiver in an optical transmission system. The present invention relates to a frequency detection circuit.

  In recent years, along with the increase in speed and ultra-long distance of long-distance optical communication, an optical signal (Optical Signal) that has been modulated by an information electrical signal (Infomation Data Signal) in an optical transmitter (0ptical Transmitter), In order to compensate the attenuation of the optical signal intensity due to the transmission loss of the transmission line fiber when it is transmitted through the transmission line fiber, the optical direct amplification repeater system that performs optical direct amplification by the optical amplification repeater (Optical Amplified Repeater) is used. Has been.

  In an optical transmission system using such an optical direct amplifier, the output light of the optical direct amplifier includes amplified signal light and amplified spontaneous emission (ASE) noise that is noise generated from the amplifier. Is included. The ratio of the ASE noise to the output light of the amplifier increases as the number of relay stages in the multi-relay transmission increases, and as the input signal power to the optical direct amplifier decreases and the amplifier operates at a high gain.

  When reproducing the information signal from this output light, the optical signal is received by an optical receiver and converted from an optical signal to an electrical signal by an optical to electrical converter. , Fluctuations in the amplitude direction due to ASE noise and electrical noise, and chromatic dispersion (polarization mode dispersion) of the transmission line fiber, or polarization mode dispersion (polarization mode dispersion), or fluctuations in the phase direction caused by the optical / electrical amplifier (jitter) For this reason, the probability of erroneous logic determination of the information signal increases. For this reason, it is common to regenerate the waveform of the electrical signal output from the optical / electrical converter using a D-type flip-flop (DFF).

  In this case, as a clock signal synchronized with the electrical signal necessary for retiming the electrical signal by the DFF, conventionally, a clock frequency component is extracted from the information electrical signal by a narrow band electrical band pass filter and amplified by an electrical limiter amplifier or the like. The clock recovery method is generally used.

  However, with the increase in communication speed, problems such as difficulty in manufacturing due to insufficient operation speed of the electric limiter amplifier have become apparent. Instead of the above method, a variable voltage oscillator (self-oscillating in the signal frequency band ( By synchronizing the frequency and phase of the output signal of the Voltage Controlled Oscillator (VCO) with the information electrical signal, a phase locked loop (PLL) system using the VCO output signal as a reproduction clock signal has come to be used. It was.

  FIG. 7 is a schematic block diagram of the high-speed optical transmitter / receiver (Hi-speed Optical Transmitter / Receiver) having the above-described configuration, particularly on the receiving side. In the figure, an optical signal transmitted through a transmission line is directly amplified by an optical amplifier 14 and then transmits only the signal light wavelength, and an optical bandpass filter for removing ASE noise light generated by the optical amplifier 14. 15 and input to the O (light) / E (electric) converter 16 to be an electric signal. This electric signal is branched into two by a branching unit 17, one of which is supplied to a DFF 23 for waveform reproduction (retiming, reshaping, and regenerating), and the other is a PLL circuit that reproduces a retiming clock signal for the DFF 23. 18 is input.

  The PLL circuit 18 has a well-known configuration, and the phase comparison of the divided output by the divider 22 of the VCO 21 that self-oscillates in the frequency band of the information electrical signal and the branch output is performed by the phase comparator 19, and this comparison output Is set as the control voltage of the VCO 21 via the loop filter or the low-pass filter 20. The output of the VCO 21 is a regenerated clock signal and a clock signal for retiming of the DFF 23.

  The information electrical signal reproduced by the DFF 23 is serial / parallel converted by a demultiplexer (DMUX) 24, and is separated into low-speed reproduction data and a reproduction clock signal and output.

  As described above, in the system using the PLL circuit for clock recovery, the output clock signal of the VCO 21 is synchronized with the information electrical signal in order to match the frequency of the retiming clock signal with the frequency of the information electrical signal. It is important to monitor the frequency of the information electrical signal by detecting the frequency of the VCO output clock signal with high accuracy.

  Therefore, as shown in FIG. 7, the low-speed recovered clock output from the demultiplexer 24 is input to the frequency detection circuit 12, and the frequency of the clock is monitored. Note that the output of the VCO 21 may be branched and the frequency of this branch output may be monitored. As shown in FIG. 8, this frequency detection circuit 12 uses a narrow band electric bandpass filter 101 and a peak detection circuit 102 that pass only the information electric signal frequency, and this peak detection output is compared with a reference value Vref0 and a comparator. There is a method of detecting the frequency change of the clock signal as a voltage change by comparing in 103.

In this method, the frequency detection accuracy largely depends on the passband characteristic of the narrowband electric bandpass filter 101 to be used. Ideally, as shown in FIG. If the frequency characteristic is the same as that of the signal frequency (denoted by f0) and the frequency characteristics before and after it are symmetrically attenuated, the output of the peak detection circuit 102 is set to a certain threshold value (Vth: in the configuration of FIG. 8, the comparator 103). by determining in the reference value Vref0), it is possible to detect the frequency deviation of more than ± delta f from f0.

In addition, there exists a thing of patent document 1 as a related technique.
Japanese Patent Laid-Open No. 11-239099

However, in practice, it is very difficult to manufacture the filter with the center frequency of f0 accurately matched, and the slope of the slope around the center frequency f0 is not symmetric but asymmetrical and therefore different from the peak detection circuit. output voltage of 102 frequency is below the threshold value Vth, f0 - Δ f1 or less, or f0 + delta frequency shift of f2 more (Δ f1 ≠ Δ f2) only will not be able to detect the value of the further delta f1 and delta f2 Cannot be set freely.

  In particular, an optical transmission / reception apparatus of a SONET (Synchronous Optical Network) system which is one of communication systems uses a CDR (Clock and Data Recovery) circuit using a PLL circuit for data and clock recovery described above. In order to meet the jitter specification (standard) in the SONET system, the output frequency of the VCO of the PLL circuit which is the clock extraction circuit of the CDR circuit is required to exactly match the received data.

  Assuming that this CDR circuit is used in an optical transmission system, the transmission speed of the most common SONET system is about 10 Gbps. In order to accurately detect the frequency of such a high-speed clock signal. It is extremely difficult to accurately obtain the symmetry of the center frequency f0 of the narrow-band filter 101 shown in FIG.

The present invention has been made in view of the problems of the conventional techniques as described above, and the object of the present invention is to easily and accurately use a device used for an optical transceiver without using a special device. f0 ± delta f over frequency shift can be detected, and to provide an inexpensive and high-performance frequency detection circuit and the light receiving device and an optical transmission system using the same.

The frequency detection circuit according to the present invention is a frequency detection circuit that detects a frequency shift of ± Δf or more with respect to the original frequency f0 of the monitored signal, and receives the monitored signal as an input, a first bandpass filter transmission center frequency f1 has a transmission characteristic shifted by Δf1 to the high frequency side, the inputs the monitored signal, to the frequency f0, the transmission center frequency f2 and Δf1 to the low frequency side And a second band-pass filter having transmission characteristics shifted by different Δf 2 and detection means for detecting a frequency shift of the monitored signal based on the outputs of the first and second filters. To do.

  An optical receiver according to the present invention includes a PLL circuit that generates a clock signal synchronized with a received information electrical signal, means for performing retiming reproduction of the received information electrical signal at least by the generated clock signal by the PLL circuit, and the generation An optical receiver including a frequency detection circuit configured to detect a frequency of a clock signal, wherein the frequency detection circuit includes the frequency detection circuit, and the generated clock signal is used as the monitored signal in the frequency detection circuit. It is characterized by doing. An optical transmission system according to the present invention is characterized by using the above optical receiver.

  The operation of the present invention will be described. When a clock component is extracted and reproduced from an information electric signal obtained by converting an optical reception signal into an electric signal using a PLL circuit, and the frequency of this reproduction clock is monitored, the transmission center frequency is set higher than the center frequency of the electric signal. A low frequency side frequency detection circuit having a BPF shifted to a low frequency side and a high frequency side frequency detection circuit having a BPF shifted to a low frequency side are provided in parallel. By using each one-side slope of each transmission characteristic of the BPF, the detection frequency can be set freely and accurately.

  According to the present invention, the frequency of the clock signal synchronized with the information electrical signal can be detected with high accuracy in the retiming / waveform reproduction of the information electrical signal in the optical transmitter / receiver, particularly in the receiver. This is advantageous in that it is possible to detect an abnormality of the optical receiver or an abnormal operation of the optical receiver early and reliably.

  Even if the frequency of the information electrical signal is an ultra-high-speed signal of about GHz, the clock signal obtained by dividing the ultra-high-speed information electrical signal and reducing the frequency is used as the frequency detection circuit. Since it can also be used as an input clock signal, there is also an effect that it can be realized even if the electrical components used in the detection circuit are not compatible with ultra-high speed.

  Furthermore, there is an effect that it is possible to cope with various optical transmission / reception apparatuses regardless of whether the data modulation method is direct modulation with respect to the light source, external modulation, wavelength or transmission speed.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration example of a frequency detection circuit 12 showing an embodiment of the present invention. In FIG. 1, a clock signal subject to frequency monitoring input to the signal input terminal 1 (normal frequency is assumed to be f 0) is branched into two by a branching device 2. Each branch output is input to narrow band electrical band pass filters (# 1, # 2) 4, 8 having transmission center frequencies of f1 and f2, respectively.

  The frequency components transmitted through these filters 4 and 8 are converted into DC voltage corresponding to the AC amplitude value by peak detectors 5 and 9, and a threshold corresponding to the DC voltage corresponding to the frequency to be detected. (Vref1, Vref2) and comparators 6 and 10 are respectively compared, and as a result of the comparison, a logic signal having a binary level of high / low is output. The outputs of these comparators 6 and 10 are ORed by an OR circuit 11 and derived as a frequency detection output.

  In FIG. 1, the filter 4, the peak detection circuit 5 and the comparator 6 constitute a low frequency side frequency detection circuit 3, and the filter 8, the peak detection circuit 9 and the comparator 10 constitute a high frequency side frequency detection circuit 7. It is assumed that

Here, referring again to FIG. 8, as already described, this circuit has a configuration of a commonly used frequency detection circuit, and the filter used here has the frequency transmission performance shown in FIG. It is desirable that As shown in FIG. 9, it is ideal that the center frequency of the transmission band characteristic of the narrowband electric bandpass filter to be used coincides with the signal frequency f0 and the shape of the transmission band is symmetrical with respect to the center frequency f0. If a filter, even if the signal frequency is shifted over delta f in either the high-frequency side and the low frequency side from f0, it is possible to determine at the same threshold voltage Vth. Furthermore, the more narrow the filter transmission bandwidth, it is possible to set small delta f, it becomes possible to detect a slight frequency shift from f0.

However, as described above, in practice, it is very difficult to manufacture the narrow band electric bandpass filter with the center frequency strictly matching f0. Further, for example, as shown in FIG. band shape, because the slope is different from the situation on both sides of the center frequency, the frequency shift from f0 which can be determined by a threshold voltage Vth is less in the low frequency side delta f, in the high frequency side delta f3 Thus, the frequency detection range is different between the high frequency side and the low frequency side.

  Therefore, in the conventional frequency detection circuit 12 as shown in FIG. 8, the value of the detection frequency greatly depends on the manufacturing accuracy of the filter to be used, and the detection frequency varies depending on the high frequency side and the low frequency side. Will end up with.

Therefore, in the present invention, in order to set the detection frequency shift amount on the high frequency side and the detection frequency shift amount on the low frequency side to the same value, two types of narrow bands having different center frequencies as shown in FIGS. Electric bandpass filters 4 and 8 are used. The center frequencies f1 and f2 of these two types of narrow-band electrical bandpass filters are respectively
f1 = f0 + Δ f1
f2 = f0 - Δ f2
The clock signal frequency f0 is intentionally shifted from the high frequency side to the low frequency side.

In this way, two types of frequency detection circuits 3 and 7 are configured in parallel by using two types of filters whose transmission center frequencies are shifted to the high frequency side and the low frequency side with respect to the clock signal frequency fo. ing. The filter 4 of the transmission center frequencies f1, f0 - detecting a frequency shift of the delta f or lower frequency side, also, the filter 8 of the transmission center frequency f2, to detect the high-frequency side frequency shift of more than f0 + delta f Are set to threshold values Vth1 and Vth2, respectively. Then, by taking the logical sum of the outputs S1, S2 of which such two detection circuits 3 and 7 in the OR circuit 11, resulting in exactly f0 - delta f or less, or f0 + delta f over frequency shift detection It becomes possible to do.

<Example>
An embodiment of the present invention will be described in detail with reference to FIG. In Figure 1, the frequency detection circuit 12 includes a clock signal input terminal 1 for receiving the monitored clock signal (a center frequency f0), a transmission center frequency f1 = f0 + Δ f1 surface acoustic wave filters ( A narrow-band electrical bandpass filter (FIL # 1) 4 comprising a surface acoustic wave filter (SAW), a peak detector 5 for detecting a peak value of an amplitude value of a frequency component transmitted through the filter and converting the peak value into a DC voltage component, and a peak It has a low frequency side frequency shift detection circuit 3 comprising a comparator 6 for comparing the output voltage of the detector 5 with a determination threshold voltage Vth1 corresponding to the frequency shift.

The branches a monitored clock signal by splitter 2, the transmission center frequency f2 = f0 - and delta f2 at which the narrow band electrical band-pass filter (FIL # 2) 8, the amplitude value of the frequency component passing through the filter A high frequency side frequency shift detection circuit 7 comprising a peak detector 9 that detects a peak and converts it into a DC voltage component, and a comparator 10 that compares the output voltage of the peak detector with a determination threshold voltage Vth2 corresponding to the frequency shift. Have Then, it comprises an OR circuit 11 that takes the logical sum of the outputs of the low frequency side frequency detection circuit 3 and the high frequency side frequency detection circuit 7.

  It is obvious that the high-accuracy frequency detection circuit 12 shown in FIG. 1 is applied to the frequency detection circuit 12 in the high-speed optical transceiver shown in FIG.

  Next, the operation of the high precision frequency detection circuit 12 of FIG. 1 will be described. In FIG. 1, a clock signal input to a signal input terminal 1 is branched into two by a branching device 2 and input to narrowband electric bandpass filters 4 and 8 having transmission center frequencies f1 and f2. The clock signal that has passed through the filter 4 is converted into a DC voltage corresponding to the AC amplitude value of the clock signal that has passed through the filter 4 by the peak detector 5, and the threshold value is determined by the comparator 6 according to the voltage value corresponding to the frequency to be detected. Determined.

Here, the transmission band characteristic of the narrow band electrical band-pass filter 4, as shown in FIG. 2, the center frequency f1 is the signal frequency f0 without there is shifted by delta f1 to the high frequency side and f1 = f0 + delta f1 . As a result, the frequency lower than f0 and f0 always corresponds to the upward slope of the filter. Therefore, as shown in FIG. 2, when the detection threshold voltage of the filter 4 is set to Vth1, Vref1 is set so that the output voltage value of the peak detection circuit 5 is equal to or lower than Vth1 and the output of the comparator 6 becomes high level, the filter 4 frequency of the input clock signal has f0 to - delta f in the following cases, or in the case of f0 + Δ f3 (f1 ') or more, it is possible the output of the comparator 6 goes high, detects the frequency deviation. Here, Δ f3 is always greater than the Δ f.

Similarly, as shown in FIG. 3, the transmission band characteristic of the narrow-band electrical bandpass filter 8 is such that the center frequency f2 is not the signal frequency f0 but is shifted by f2 = f0- [ Delta] f2 to the low frequency side by [ Delta] f2. is there. As a result, the frequency lower than f0 and the frequency higher than f0 always correspond to the right-down slope of the filter.

Therefore, as shown in FIG. 3, when the detection threshold voltage of the filter 8 is set to Vth2, Vref2 is set so that the output voltage value of the peak detection circuit 9 is equal to or lower than Vth2 and the output of the comparator 10 becomes high level, the filter 8 If the frequency of the input clock signal has a higher f0 + delta f, or f0 + Δ f4 (f2 ') in the following cases in the can output of the comparator 10 becomes high level, to detect the frequency deviation. Here, Δ f4 is always greater than the Δ f.

Therefore, both outputs S1 and S2 of the comparator 6 and the comparator 10 are as shown in FIG. 4. By taking the logical sum of these outputs S1 and S2 in the OR circuit 11, the detection indicated by OUT in FIG. A waveform is obtained. That is, in the low-frequency side than f0, f0 - delta logical sum output below f is always at a high level, the high-frequency side of f0, the logical sum output by f0 + delta f above is necessarily high. Only when the clock frequency f0 is within the range of f0- [ Delta] f <f0 <f0 + [ Delta] f, the logical sum output is at a low level, enabling highly accurate frequency detection.

  In addition to the configuration shown in FIG. 1 described above, several modifications are conceivable. For example, a surface acoustic wave filter (SAW filter) is used as a narrow-band electrical bandpass filter, but other acoustic wave filters such as a mechanical filter, a crystal filter, a ceramic filter, and a monolithic crystal filter may be used, or a dielectric resonator type A filter other than an elastic wave filter such as a filter may be used.

  If the comparator 6 and 10 has a comparison output having a logic opposite to that of the above-described example, an AND circuit that performs a logical product operation can be used instead of the OR circuit 11. It is. FIG. 5 is a diagram showing the configuration of another embodiment of the present invention. FIG. 5 is a block diagram when an AND circuit 13 is used instead of the OR circuit 11 in FIG. It shows with. When the AND circuit 13 is used, the relationship between the outputs S1 and S2 of the comparators 6 and 10 and the output OUT of the AND circuit 13 is as shown in FIG. Other than that, the configuration is the same as that of FIG. 1, and a description thereof will be omitted.

  Further, as the peak detection circuit, a voltage doubler rectifier circuit using a diode and a capacitor can be used, and a full wave or half wave rectifier circuit using a transistor or a transformer may be used. In the present invention, any peak detection circuit may be used as long as it can detect a signal corresponding to the energy of the signal passing through the narrowband filters 4 and 8. In addition to the above configuration, a signal power detection and amplitude detection are possible. Any configuration may be used as long as it does. In these cases, the threshold value, which is the comparison reference level of the comparator, is determined according to the signal power and amplitude value output corresponding to the transmission characteristics f0 ± Δf of the filters 4 and 8. Of course.

  Of course, the electric branching device and various electric circuits may be of any structure and type as long as they have the performance.

  Furthermore, the frequency detection circuit 12 may be configured to monitor the frequency of the clock signal output from the demultiplexer 24 (see FIG. 7) in the high-speed optical transceiver, but the output clock of the VCO 21 configuring the PLL circuit 18 may be used. The frequency of the signal may be monitored, and the output of the frequency divider 22 in the PLL circuit 18 may be monitored for the frequency of the clock signal.

  In the demultiplexer 24 in this high-speed optical transmission / reception apparatus, for example, a 10 GHz serial information electrical signal is parallelized (S / P conversion) and reduced to a 1 / N speed, and the same frequency is used. The clock signal having the frequency divided by 10 GHz / N is output. Therefore, the frequency detection circuit should monitor the clock signal divided by 1 / N. Since the frequency of the oscillation clock signal of the VCO 21 in the PLL circuit 18 is monitored as it is, it is not necessary to use ultra-high-speed electronic components constituting the circuit. The design is easy and the design is easy.

  Furthermore, this frequency detection circuit 12 can be used for an optical transmission / reception device in a terminal device of the SONET communication system in the optical communication system described above, and of course, detects the signal frequency in other communication systems of other communication systems. Obviously, it can be used widely for general frequency detection.

It is a figure which shows the structure of the frequency detection circuit by embodiment of this invention. It is a figure which shows the filter transmission characteristic of the low frequency side frequency detection circuit. It is a figure which shows the filter transmission characteristic of a high frequency side frequency detection circuit. FIG. 2 is a diagram showing a relationship between outputs of comparators 6 and 10 and an output of an OR circuit 11 in FIG. 1. It is a figure which shows the structure of the frequency detection circuit by other embodiment of this invention. FIG. 6 is a diagram showing the relationship between the outputs of the comparators 6 and 10 and the output of the AND circuit 13 in FIG. 5. It is a figure which shows a part of optical transmission / reception apparatus with which the frequency detection circuit of FIG. 1 is applied. It is a figure which shows the example of the conventional frequency detection circuit. It is a figure which shows the transmission characteristic of the filter for general frequency detection.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Branch device 3 Low frequency side frequency detection circuit 4,8 Filter 5,9 Peak detection circuit 6,10 Comparison circuit 7 High frequency side frequency detection circuit 11 OR circuit 12 Frequency detection circuit 13 AND circuit

Claims (10)

A frequency detection circuit for detecting a frequency deviation of ± Δf or more with respect to the original frequency f0 of the monitored signal,
A first bandpass filter having a transmission characteristic in which the monitored signal is input and the transmission center frequency f1 is shifted by Δf1 to the high frequency side with respect to the frequency f0;
A second bandpass filter having a transmission characteristic in which the monitored signal is input and the transmission center frequency f2 is shifted by a Δf2 different from Δf1 on the low frequency side with respect to the frequency f0;
And a detecting means for detecting a frequency shift of the monitored signal based on the outputs of the first and second filters.   The detection means uses the characteristic of the slope part rising to the right of the transmission characteristics of the first filter, and detects the frequency using the characteristic of the slope part of the right slope among the transmission characteristics of the second filter. The frequency detection circuit according to claim 1, wherein: The detection means includes
A first comparator for comparing the output of the first filter with a threshold corresponding to the output of the first filter shifted by -Δf from the f0;
A second comparator for comparing the output of the second filter with a threshold corresponding to the output of the second filter shifted from the f0 by the + Δf;
3. The frequency detection circuit according to claim 2, wherein a frequency shift greater than ± Δf is detected in accordance with the output of the comparator.   The detection means further includes a logical operation unit that performs a logical operation of outputs of the first and second comparators, and the frequency shift is detected by the logical operation output. 2. The frequency detection circuit according to 2.   5. The frequency detection circuit according to claim 4, wherein the logical operation unit is a logical sum circuit.   The frequency detection circuit according to claim 4, wherein the logical operation unit is a logical product circuit.   The detection means has first and second peak detectors for detecting peak values of output amplitudes of the first and second filters, respectively. 7. The frequency detection circuit according to claim 4, wherein an output is input to the first and second comparators.   The detection means includes first and second power detectors for detecting output powers of the first and second filters, respectively, and outputs of the first and second power detectors are described above. 7. The frequency detection circuit according to claim 4, wherein the frequency detection circuit is input to the first and second comparators. A PLL circuit that generates a clock signal synchronized with the received information electrical signal, a means for retiming reproduction of the received information electrical signal by the generated clock signal by the PLL circuit, and a frequency for detecting the frequency of the generated clock signal An optical receiver including a detection circuit,
9. The optical receiver according to claim 1, wherein the frequency detection circuit comprises the frequency detection circuit according to any one of claims 1 to 8, wherein the generated clock signal is used as the monitored signal in the frequency detection circuit.   An optical transmission system using the optical receiver according to claim 9.

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