JP4373119B2

JP4373119B2 - Wide viewing angle fast response liquid crystal display

Info

Publication number: JP4373119B2
Application number: JP2003110895A
Authority: JP
Inventors: 直人広田
Original assignee: 大林精工株式会社
Priority date: 2003-02-26
Filing date: 2003-02-26
Publication date: 2009-11-25
Anticipated expiration: 2023-02-26
Also published as: JP2004258598A

Description

【０００１】
【産業上の利用分野】
本発明は、低コストで広視野角、高輝度・高速応答の大画面アクティブマトリックス型液晶ＴＶ表示装置に関する。
【０００２】
【従来の技術】
図１にあるように従来の垂直配向方式液晶表示装置は、カラーフィルター側基板の透明共通電極の上に、液晶分子の運動方向を制御するバンプを形成し、かつアクティブマトリックス基板の透明画素電極に、液晶分子の運動方向を制御するスリットをもうけ、これらのバンプとスリットが１組になって液晶分子の運動方向を決定する方式を採用している。カラーフィルター側基板にバンプのかわりに液晶分子の運動方向を制御するスリットを透明共通電極に形成する方法もある。
これらの両方の方式ともに量産され実用化されている。
【０００３】
【発明が解決しようとする課題】
従来のマルチドメイン垂直配向方式液晶表示装置ではカラーフィルター基板に、バンプかスリットを透明共通電極に形成しなければならず、ホトマスク工程を、１回ふやさなければならなかった。そのためにコストアップをさけることができなかった。
【０００４】
さらに図１にあるようなカラーフィルター側にバンプを形成する垂直配向方式液晶表示装置では、バンプの幅、高さ、傾斜面の角度を精密にコントロールしないと、液晶分子のたおれかたにバラツキが生じてしまい、中間調領域でムラが発生しやすかった。
バンプの材質がポジ型ホトレジストであるために、有機溶剤を完全にとりのぞく必要があり、２００度以上の高温で焼きかためなければならず工程の短縮化が難かしかった。ポジ型ホトレジストのバンプから液晶中に汚染物が溶出した場合、残像の現象が発生し信頼性の点でも問題となる。
【０００５】
従来のバンプを用いたカラーフィルター基板では、バンプの材料としてポジ型ホトレジストを用いるために、垂直配向膜の塗布工程で不良が発生した場合、リワークする時に、酸素プラズマを用いたダライアッシング方法を用いることができない。そのためにランニングコストの高い有機溶剤を用いたウェットリムーブ方法を用いなければならずリワークコストが非常に高くなるという欠点があった。
【０００６】
従来のバンプやスリットを用いる垂直配向方式液晶表示装置では黒表示から中間調表示または白表示から中間調表示に移る時の液晶の応答速度が遅いという欠点があった。
【０００７】
本発明は、上記の問題点を解決するものであり、その目的とする所は、大型の垂直配向方式液晶表示装置の信頼性を向上し、安価に短時間で製造できしかも明るく応答速度のはやい液晶表示を実現することにある。
【０００８】
【課題を解決するための手段】
前記課題を解決し、上記目的を達成するために、本発明では下記の手段を用いる。
【０００９】
〔手段１〕アクティブマトリックス基板とカラーフィルター基板に垂直配向された負の誘電率異方性液晶分子に電圧を印加し、異なる２方向または４方向に液晶分子をたおれさせるために下記の２種類の電極構造と構造配置をアクティブマトリックス基板の１画素内に形成した。
ｉ）カラーフィルター基板側には透明なベタ電極を用い、これに対向するアクティブマトリックス基板側の透明画素電極には、細長いスリット状のパターン（スリット部には、透明電極はない。）を形成する。
ｉｉ）カラーフィルター基板側には透明なベタ電極を用い、これに対向するアクティブマトリックス基板側の透明画素電極には、細長いスリット状のパターンを形成し、このスリットの下層に絶縁膜をかいしてスリットの形状とほぼ同じ形状でスリットよりもオーバーサイズになっている液晶配向方向制御電極を形成する。
ｉｉｉ）ｎ行ｍ列の画素において、（ｎ−１）行の走査線と（ｍ＋１）列の映像信号配線がまじわる位置に薄膜トランジスタ素子を形成し、（ｍ＋１）列の映像信号配線と、ｎ行ｍ列の画素に用いる液晶配向方向制御電極とが、この薄膜トランジスタをかいして連結されており、かつｎ行の走査線とｍ列の映像信号配線がまじわる位置に薄膜トランジスタ素子を形成し、ｍ列の映像信号配線と、ｎ行ｍ列の画素に用いる透明画素電極とが、この薄膜トランジスタ素子をかいして連結されている。
【００１０】
〔手段２〕アクティブマトリックス基板とカラーフィルター基板に垂直配向された負の誘電率異方性液晶分子に電圧を印加し、異なる２方向または４方向に液晶分子をたおれさせるために下記の２種類の電極構造と構造配置をアクティブマトリックス基板の１画素内に形成した。
ｉ）カラーフィルター基板側には透明なベタ電極を用い、これに対向するアクティブマトリックス基板側の透明画素電極には、細長いスリット状のパターン（スリット部には透明電極はない。）を形成する。
ｉｉ）カラーフィルター基板側には、透明なベタ電極を用い、これに対向するアクティブマトリックス基板側の透明画素電極には、細長いスリット状のパターンを形成し、このスリットの下層に絶縁膜をかいしてスリットの形状とほぼ同じ形状でスリットよりもオーバーサイズになっている液晶配向方向制御電極を形成する。
ｉｉｉ）ｎ行ｍ列の画素において、（ｎ−１）行の走査線上に、薄膜トランジスタ素子を形成し、ｎ行の共通電極と、ｎ行ｍ列の画素に用いる液晶配向方向制御電極とが、この薄膜トランジスタ素子をかいして連結されており、かつｎ行の走査線とｍ列の映像信号配線とがまじわる位置に薄膜トランジスタ素子を形成し、ｍ列の映像信号配線とｎ行ｍ列の画素に用いる透明画素電極とが、この薄膜トランジスタをかいして連結されている。
【００１１】
〔手段３〕アクティブマトリックス基板とカラーフィルター基板に垂直配向された負の誘電率異方性液晶分子に電圧を印加し多方向に液晶分子をたおれさせるために下記の２種類の電極構造と構造配置をアクティブマトリックス基板の１画素内に形成した。
ｉ）カラーフィルター基板側には透明なベタ電極を用い、これに対向するアクティブマトリックス基板側の透明画素電極には、円形または多角形の穴（穴の部分には透明電極はない。）
ｉｉ）カラーフィルター基板側には透明なベタ電極を用い、これに対向するアクティブマトリックス基板側の透明画素電極には、細長いスリット状のパターンを形成し、このスリットの下層に絶縁膜をかいして、スリットの形状とほぼ同じ形状でスリットよりもオーバーサイズになっている液晶配向方向制御電極を形成する。
ｉｉｉ）ｎ行ｍ列の画素において、（ｎ−１）行の走査線と（ｍ＋１）列の映像信号配線がまじわる位置に薄膜トランジスタ素子を形成し、（ｍ＋１）列の映像信号配線とｎ行ｍ列の画素に用いる液晶配向方向制御電極とが、この薄膜トランジスタ素子をかいして連結されており、かつ、ｎ行の走査線とｍ列の映像信号配線がまじわる位置に薄膜トランジスタ素子を形成し、ｍ列の映像信号配線とｎ行ｍ列の画素に用いる透明画素電極とが、この薄膜トランジスタ素子をかいして連結されている。
【００１２】
〔手段４〕アクティブマトリックス基板とカラーフィルター基板に垂直配向された負の誘電率異方性液晶分子に電圧を印加し、多方向に液晶分子をたおれさせるために下記の２種類の電極構造と構造配置をアクティブマトリックス基板の１画素内に形成した。
ｉ）カラーフィルター基板側には透明なベタ電極を用い、これに対向するアクティブマトリックス基板側の透明画素電極には、円形または多角形の穴（穴の部分には透明電極はない。）を多数形成する。
ｉｉ）カラーフィルター基板側には透明なベタ電極を用い、これに対向するアクティブマトリックス基板側の透明画素電極には、細長いスリット状のパターンを形成し、このスリットの下層に絶縁膜をかいしてスリットの形状とほぼ同じ形状でスリットよりもオーバーサイズになっている液晶配向方向制御電極を形成する。
ｉｉｉ）ｎ行ｍ列の画素において、（ｎ−１）行の走査線上に、薄膜トランジスタ素子を形成し、ｎ行の共通電極と、ｎ行ｍ列の画素に用いる液晶配向方向制御電極とが、この薄膜トランジスタ素子をかいして連結されており、かつｎ行の走査線とｍ列の映像信号配線とがまじわる位置に薄膜トランジスタを形成し、ｍ列の映像信号配線とｎ行ｍ列の画素に用いる透明画素電極とが、この薄膜トランジスタ素子をかいして連結されている。
【００１３】
〔手段５〕手段１，２，３，４において、走査線のアドレス信号波形の時間幅が水平周期の２倍以上あり、（ｎ−１）番めの走査線アドレス信号波形とｎ番めの走査線のアドレス信号波形とが水平周期の１倍以上かさなりあっており、かつｍ列の映像信号配線の映像信号電圧と、（ｍ＋１）列の映像信号配線の映像信号電圧の極性は、お互に異なっておりかつ水平周期ごとに互いに極性がいれかわり、かつ垂直周期ごとに互いに極性がいれかわるようにした。
【００１４】
〔手段６〕手段１，３において、ｎ行の走査線とｍ列の映像信号配線がまじわる位置に形成され、透明画素電極に連結されている薄膜トランジスタ素子のチャネル長（Ｌ_１）よりも、（ｎ−１）行の走査線と（ｍ＋１）列の映像信号配線がまじわる位置に形成され液晶配向方向制御電極に連結されている薄膜トランジスタ素子のチャネル長（Ｌ_２）の方が大きく（Ｌ_１＜Ｌ_２）なるようにした。
【００１５】
〔手段７〕手段２，４において、ｎ行の走査線とｍ列の映信号配線がまじわる位置に形成され、透明画素電極に連結されている薄膜トランジスタ素子のチャネル長（Ｌ_１）よりも、（ｎ−１）行の走査線上に形成され、液晶配向方向制御電極に連結されている薄膜トランジスタ素子のチャネル長（Ｌ_２）の方が大きく（Ｌ_１＜Ｌ_２）なるようにした。
【００１６】
〔手段８〕手段１，２，３，４において、液晶配向方向制御電極に連結されている薄膜トランジスタ素子に、ダブルトランジスタ素子構造またはオフセットチャネル素子構造を用いた。
【００１７】
〔手段９〕手段１，２において、アクティブマトリックス基板側の透明画素電極に形成されている細長くのびたスリットと、液晶配向方向制御電極と組みになったスリットとが、走査線ののびている方向に対してほぼ±４５度の角度の方向に、お互いにほぼ平行な関係をたもちながら、交互に配置されており、液晶セルの外部に設置する２枚の偏光板の偏光軸は、走査線方向と映像信号配線方向にそろえ、互いに直交する配置とした。
【００１８】
〔手段１０〕手段１，２において、アクティブマトリックス基板側の透明画素電極に形成されている細長くのびたスリットが、走査線ののびている方向に対して、ほぼ平行な方向と、直交する方向に配置されかつ液晶配向方向制御電極と組みになっているスリットが、走査信号配線方向に対してほぼ±４５度の角度の方向になるように配置し、液晶セルの外部に設置する２枚の偏光板の偏光軸は、走査線方向と映像信号配線方向にそろえ、互いに直交する配置とした。
【００１９】
〔手段１１〕手段１，２において、アクティブマトリックス基板側の透明画素電極に形成されている細長くのびたスリットが、走査線ののびている方向に対してほぼ±４５度の角度に配置されており、かつ液晶配向方向制御電極と組みになっているスリットが、走査線ののびている方向に対してほぼ平行な方向と、直交する方向とに配置され、かつ画素電極の外周部を液晶配向方向制御電極が、絶縁膜をかいして透明画素電極とかさなりあいながらとり囲んでいる構造とし、液晶セルの外部に設置する２枚の偏光板の偏光軸は、走査線方向と映像信号配線方向にそろえ、互いに直交する配置とした。
【００２０】
〔手段１２〕手段３，４において、アクティブマトリックス基板側の透明画素電極に形成されている複数の円形または多角形の穴をとり囲むように液晶配向方向制御電極と組になったスリットが、走査線ののびた方向に対して平行な方向と直交する方向に配置されており、かつ透明画素電極の外周部を液晶配向方向制御電極が、透明画素電極と絶縁膜をかいしてかさなりながらとり囲んでいる構造とし、液晶セルの外部に設置する２枚の偏光板の偏光軸は、走査線方向と、映像信号配線方向にそろえ、互いに直交する配置とした。
【００２１】
〔手段１３〕手段１，２，３，４において透明画素電極のスリットの下層に絶縁物をかいして形成された液晶配向方向制御電極が走査線形成時に同時に同じ層に形成されるようにした。
【００２２】
〔手段１４〕手段１，２において、透明画素電極のスリットの下層に絶縁物をかいして形成された液晶配向方向制御電極が映像信号配線形成時に同時に同じ層に形成されるようにした。
【００２３】
〔手段１５〕手段１において１画素を駆動するために１画素中に２個の薄膜トランジスタ素子を必要とし、かつｎ行の走査線とｍ列の映像信号配線がまじわる位置に形成された薄膜トランジスタ素子のドレイン電極と透明画素電極とを電気的に接続するためのコンタクトホールが１個だけ存在するようにした。
【００２４】
〔手段１６〕手段１，３において、１画素を駆動するために１画素中に２個の薄膜トランジスタ素子を必要とし、かつ（ｎ−１）行の走査線と（ｍ＋１）列の映像信号配線がまじわる位置に形成された薄膜トランジスタ素子のドレイン電極と、液晶配向方向制御電極とを電気的に接続するためのコンタクトホールが２個存在し、かつｎ行の走査線とｍ列の映像信号配線がまじわる位置に形成された薄膜トランジスタ素子のドレイン電極と透明画素電極とを電気的に接続するためのコンタクトホールが１個だけ存在するようにした。
【００２５】
〔手段１７〕手段１，２，３，４において、１画素を駆動するために１画素中に２個の薄膜トランジスタ素子を必要とし、かつ１個の薄膜トランジスタは、透明画素電極に接続されており、残りの１個の薄膜トランジスタは、液晶配向方向制御電極に接続し、透明画素電極と液晶配向方向制御電極とを絶縁膜をかいしてオーバーラップさせて容量を形成した。
【００２６】
〔手段１８〕手段１，２，３，４において液晶配向方向制御電極と連結されているダブルトランジスタ構造を有する薄膜トランジスタ素子の中間電極と透明画素電極とが絶縁膜をかいしてかさなりあって容量を形成するようにした。
【００２７】
〔手段１９〕手段１，３においてｎ行ｍ列の透明画素電極と（ｎ−１）行の走査線とが、絶縁膜をかいしてかさなりあって保持容量を形成できるようにした。
【００２８】
〔手段２０〕手段２，４においてｎ行ｍ列の透明画素電極とｎ行の共通電極とが、絶縁膜をかいしてかさなりあって保持容量を形成できるようにした。
【００２９】
【作用】
手段１，２，３，４，５を用いることで、従来図１にあるような液晶分子の運動方向制御用バンプをＣＦ（カラーフィルター）基板に形成する必要がなくなった。図２，図１０，図１５，図１６にあるように簡単なカラーフィルター構造となり低価格を実現できる。
さらに従来問題となっていたバンプからの汚染物の液晶中への拡散問題は完全になくなり、パンプの形状の不均一性から発生していた中間調領域でのムラの問題も完全になくなった。
これによりいちじるしい歩留りの向上と信頼性の向上を同時に実現できる。
【００３０】
さらにバンプがないので、配向膜塗布が失敗しても、ドライアッシャーによる酸素プラズマで簡単に短時間で再成することができる。配向膜塗布前の表面処理にドライアッシャーを用いた酸素とアルゴンのプラズマ処理を用いることができるので、配向膜塗布工程でのはじきやピンホールの発生をいちじるしく低減できる。
【００３１】
手段１，２，３，４，５，６，７，８，１８を用いることで、液晶配向方向制御電極を駆動するための特別な駆動ＩＣや、接続端子部が必要なくなり製品の低価格を実現できる。さらにダブルトランジスタ構造やオフセットトランジスタ構造を用いることでリーク電流を低減できる。トランジスタのソースとドレイン電極間に大きな電圧が印加されても電界の集中を分散して防止できるので薄膜トランジスタのスレーショールド電圧（Ｖｔｈ）のシフトを低減でき、信頼性の高い液晶パネルを実現できる。液晶配向方向制御電極に接続されている薄膜トランジスタのチャネル長（Ｌ_２）を大きくすることでリーク電流を低減できる。
【００３２】
手段１，２，３，４，５，９，１０，１１，１２を用いることで、偏光板の有効利用効率を従来のＴＮモードの液晶パネルとくらべて、大幅に向上することができ、超大型液晶表示装置で用いる偏光板のコストを低減できる。さらにバックライトで使用する２種類の材料の多層積層体（商品名スリーエムのＤ−ＢＥＦ）からなる反射性偏光子の有効利用効率も同様に大幅に向上することができるので、超大型液晶表示装置用のバックライトのコストも大幅に低減できる。
【００３３】
手段１，２，３，４，１３，１４を用いることで従来のＴＮモードのアクティブマトリックス基板の製造工程とカラーフィルターの製造工程をほとんど変更することなく同じプロセスで本発明のアクティブマトリックス液晶パネルを製造することができるので、歩留りと低コスト化の点で優位に立てる。
【００３４】
手段１，２，３，４，５，１５，１６，１７を用いることで最も単純な構造の垂直配向方式液晶表示装置を実現できる。１画素内でよぶんな、不必要な薄膜トランジスタがないので最も開口率を大きくできるので明るい表示を実現できる。
【００３５】
手段１，２，３，４，５，６，７，８，１８を用いることで、透明画素電極と液晶配向方向制御電極との間に大きな電圧を印加できるので垂直配向された液晶分子を駆動させるための電界の歪みを非常に大きくできる。これにより液晶分子の反応速度を大きくすることができ、動画表示をしても画像の流れや残像現象はほとんど発生しない。
【００３６】
手段１，２，３，４，１９，２０を用いることで、ｎ行の走査線がＯＦＦするときに透明画素電極の電位変動が小さくなりフリッカーを低減することができる。
【００３７】
手段１，２，３，４，５を用いることで黒表示の時に垂直配向された液晶分子は、全領域ほぼ垂直に配向しているので、光ぬけが従来のバンプを用いるものよりもはるかに少なくなり暗室でも完全に均一な黒表示を実現できる。
【００３８】
【実施例】
〔実施例１〕図２，図５，図８，は、本発明の第１の実施例の断面図，モデル図，平面図である。図１９，図２０が本発明の第１の実施例のＴＦＴアレイ基板の製造プロセスフローである。図３１，図３２はＴＦＴアレイ基板の拡大断面図である。
カラーフィルター基板には、ベタ透明共通電極があり、この基板に対向してアクティブマトリックス基板が平行に配置されている。従来の垂直配向モードの液晶パネルには図１にあるように液晶の運動方向を制御するためのバンプが透明共通電極上に形成されていたが、本発明の垂直配向モードの液晶パネルには、このようなバンプは必要ない。
アクティブマトリックス基板は、まずはじめに走査線を形成した後絶縁膜とアモルファスシリコン層（ノンドープ層）とオーミックコンタクト用のｎ^＋アモルファスシリコン層を堆積する。薄膜トランジスタ素子部を形成した後、映像信号配線とドレイン電極と液晶配向方向制御電極とを同時に同層に形成する。日本の公開特許特開２０００−０６６２４０に開示されているハーフトーン露光技術を用いることで、薄膜トランジスタ素子部と映像信号配線とドレイン電極と液晶配向方向制御電極を同時に同層に作ることも可能である。図３２，がハーフトーン露光を用いた本発明の実施例１の薄膜トランジスタとアクティブマトリックス基板の断面図である。
【００３９】
図８にあるように本発明の実施例１では１画素中に必要な薄膜トランジスタ素子は２個だけで十分である。ｎ行ｍ列の透明画素電極は、ｎ行の走査線とｍ列の映像信号配線のまじわる位置に形成された薄膜トランジスタ素子に連結されており、液晶配向方向制御電極は、（ｎ−１）行の走査線と（ｍ＋１）列の映像信号配線のまじわる位置に形成された薄膜トランジスタ素子に連結されている。透明画素電極には、２種類のスリットが形成されており、そのスリットの断面拡大図が図３，図４である。
図３のタイプのスリットでは電圧を印加された時に垂直配向された液晶分子は、図３にしめされた方向にたおれる。図４のタイプのスリットでは、スリットの下層に絶縁膜をかいして液晶配向方向制御電極が配置されている。図４のタイプのスリットでは、電圧を印加した時に垂直配向された液晶分子は、図４にしめされた方向にたおれる。図３，図４の変形したものが図１１，図１２である。図４では透明画素電極のスリットよりも液晶配向方向制御電極のほうがサイズが大きくなっており、お互いに絶縁膜をかいしてかさなりあっている。本発明の重要な点は、透明画素電極と液晶配向方向制御電極とが絶縁膜をかいしてかさなりあい、容量を形成している点である。図６１のような電極構造配置でも図４と同様な方向に負の誘電率異方性液晶分子を運動させることはできるが、図６２のような平面構造では透明画素電極と液晶配向方向制御電極とがかさなりあっていないため透明画素電極と液晶配向方向制御電極とで形成される容量が小さいために本発明の駆動方式を用いる場合問題である。
図６３，や図６４のように透明画素電極と液晶配向方向制御電極とが、すこしでも絶縁膜をかいしてかさなりあっていることが、本発明の駆動方式では特に重要となります。
【００４０】
〔実施例２〕図１０，図１３は、本発明の第２の実施例の断面図，平面図である。図２１，図２２が本発明の第２の実施例のＴＦＴアレイ基板の製造プロセスフローである。図２９，図３０は、ＴＦＴアレイ基板の拡大断面図である。
カラーフィルター基板にはベタ透明共通電極があり、実施例１と同様にバンプは無い。
アクティブマトリックス基板は、まずはじめに走査線と液晶配向方向制御電極を同時に同層に形成した後絶縁膜とアモルファスシリコン層（ノンドープ層）とオーミックコンタクト用のｎ^＋アモルファスシリコン層を堆積する。薄膜トランジスタ素子部を形成した後、映像信号配線とドレイン電極とを同時に形成する。
日本の公開特許特開２０００−０６６２４０に開示されているハーフトーン露光技術を用いることで、薄膜トランジスタ素子部と映像信号配線とドレイン電極とを同時に同層に作ることも可能である。図３０がハーフトーン露光を用いた本発明の実施例２の薄膜トランジスタとアクティブマトリックス基板の断面図である。
【００４１】
図１３にあるように本発明の実施例２では１画素中に必要な薄膜トランジスタ素子は２個だけで十分である。ｎ行ｍ列の透明画素電極は、ｎ行の走査線とｍ列の映像信号配線のまじわる位置に形成された薄膜トランジスタ素子に連結されており、液晶配向方向制御電極は、（ｎ−１）行の走査線と（ｍ＋１）列の映像信号配線のまじわる位置に形成された薄膜トランジスタ素子に連結されている。実施例１の場合この薄膜トランジスタ素子のドレイン電極と液晶配向方向制御電極とが同時に同層に形成されるため自動的に連結されるが、実施例２の場合、この薄膜トランジスタ素子のドレイン電極と液晶配向方向制御電極は同層に形成されていないためこれら２つの電極を電気的に連結するために２つのコンタクトホールをあけなければならない。実施例１では２つの薄膜トランジスタ素子と、１個のコンタクトホールで十分であったが、実施例２では図１３にあるように２つの薄膜トランジスタ素子と、３個のコンタクトホールが必要となります。
【００４２】
〔実施例３〕図２，図６，図９は本発明の第３の実施例の断面図，モデル図，平面図である。図２３，図２４が本発明の第３の実施例のＴＦＴアレイ基板の製造プロセスフローである。
図３５，図３６はＴＦＴアレイ基板の拡大断面図である。
カラーフィルター基板にはベタ透明共通電極があり、実施例１と同様にバンプは無い。
アクティブマトリックス基板は、まずはじめに走査線と共通電極を同時に同層に形成した後絶縁膜とアモルファスシリコン層（ノンドープ層）とオーミックコンタクト用のｎ^＋アモルファスシリコン層を堆積する。
薄膜トランジスタ素子部を形成した後、映像信号配線とドレイン電極と液晶配向方向制御電極とを同時に同層に形成する。
日本の公開特許特開２０００−０６６２４０に開示されているハーフトーン露光技術を用いることで、薄膜トランジスタ素子部と映像信号配線とドレイン電極と液晶配向方向制御電極とを同時に同層に作ることも可能である。図３６がハーフトーン露光を用いた本発明の実施例３の薄膜トランジスタとアクティブマトリックス基板の断面図である。
【００４３】
図９にあるように本発明の実施例３では、１画素中に必要な薄膜トランジスタ素子は２個だけで十分である。ｎ行ｍ列の透明画素電極は、ｎ行の走査線とｍ列の映像信号配線のまじわる位置に形成された薄膜トランジスタ素子に連結されており、液晶配向方向制御電極は、（ｎ−１）行の捜査線上に形成された薄膜トランジスタに連結されている。画素電極の構造としては実施例１，実施例２のような形状も可能であるが、図９では透明画素電極にあけられたスリットは走査線ののびている方向に対して水平配置と垂直配置されており、液晶配向方向制電極と組みになっているスリットは走査線ののびている方向に対して±４５度の角度に配置されている。実施例３の場合（ｎ−１）行の走査線上に形成された薄膜トランジスタ素子のソース電極とｎ行の共通電極とは同層に形成されていないため、これらの２つの電極を電気的に連結するために２つのコンタクトホールをあけなければならない。そのため実施例３では実施例２と同様に図９にあるように２個の薄膜トランジスタ素子と、３個のコンタクトホールが必要となります。
【００４４】
〔実施例４〕図１０，図６５は、本発明の第４の実施例の断面図と平面図である。図２５，図２６が本発明の第４の実施例のＴＦＴアレイ基板の製造プロセスフローである。図３３，図３４はＴＦＴアレイ基板の拡大断面図である。
カラーフィルター基板には、ベタ透明共通電極があり、実施例１と同様にバンプは無い。
アクティブマトリックス基板はまずはじめに走査線と共通電極と液晶配向制御電極とを同時に同層に形成した後絶縁膜とアモルファスシリコン層（ノンドープ層）とオーミックコンタクト用のｎ^＋アモルファスシリコン層を堆積する。薄膜トランジスタ素子部を形成した後、映像信号配線とドレイン電極とを同時に形成する。
日本の公開特許特開２０００−０６６２４０に開示されているハーフトーン露光技術を用いることで薄膜トランジスタ素子部と映像信号配線とドレイン電極とを同時に同層に作ることも可能である。図３４が、ハーフトーン露光を用いた本発明の実施例４の薄膜トランジスタとアクティブマトリックス基板の断面図である。
図６５にあるように本発明の実施例４では、１画素中に必要な薄膜トランジスタ素子は２個だけで十分である。ｎ行ｍ列の透明画素電極は、ｎ行の走査線とｍ列の映像信号配線のまじわる位置に形成された薄膜トランジスタ素子に連結されており、液晶配向方向制御電極は、（ｎ−１）行の走査線上に形成された薄膜トランジスタに連結されている。実施例４の場合（ｎ−１）行の走査線上に形成された薄膜トランジスタ素子のソース電極とドレイン電極とをそれぞれ共通電極と液晶配向方向制御電極とに電気的に連結させるために、それぞれ２個づつのコンタクトホールをあけなければならない。
そのため、実施例４では、図６５にあるように２個の薄膜トランジスタ素子と５個のコンタクトホールが必要となります。
【００４５】
〔実施例５〕図７が本発明の第５番目の実施例である駆動波形に関するタイミングチャートである。実施例１，２３，４で記述した垂直配向方式液晶表示装置を駆動するための駆動波形である。ここで重要なことは（ｎ−１）行の走査線とｎ行の走査線の信号波形（アドレス信号幅）がすくなくとも水平周期の２倍以上の時間幅をもっており、かつ互いに１水平周期以上の時間幅でかさなりあっており、かつ、ｍ列の映像信号配線の映像信号電圧極性と、（ｍ＋１）列の映像信号配線の映像信号電圧極性は、お互いに異なっており、かつ水平周期ごとに互いに極性が反転していることである。本発明の駆動方式を用いれば、図１７，図１８にあるように回路モデル図の容量Ｃ２（容量Ｃ２は透明画素電極と液晶配向方向制御電極とが絶縁膜をかいしてかさなりあうことで形成された容量である。）に（ｎ−１）行の走査線の信号波形とｎ行の走査線の信号波形がかさなりあっている時に充電することが可能となります。
【００４６】
図１７では、液晶配向方向制御電極は（ｎ−１）行の走査線と（ｍ＋１）列の映像信号配線がまじわる位置に形成された薄膜トランジスタ素子に連結され、透明画素電極はｎ行の走査線とｍ列の映像信号配線がまじわる位置に形成された薄膜トランジスタ素子に連結されている。ｍ列の映像信号配線が＋７Ｖ、（ｍ＋１）列の映像信号配線が−７Ｖの時に、（ｎ−１）行とｎ行の走査線が両方ともにアドレスされていると、上記２つの薄膜トランジスタは動作し容量Ｃ２は充電されＡ，Ｂの電位はそれぞれ＋７，−７Ｖになる。（ｎ−１）行の走査線がとじてからｍ列の映像信号配線の電圧が＋７Ｖから−７Ｖに極性を変化させ、（ｍ＋１）列の映像信号配線の電圧が−７Ｖから＋７Ｖに極性を変化させると、容量Ｃ２のＡの電位はｎ行の薄膜トランジスタが動作しているため＋７Ｖから−７Ｖに変化する。この時（ｎ−１）行の薄膜トランジスタは動作していないため容量Ｃ２のＢ電位は−７Ｖから−２１Ｖに変化する。次にｎ行走査線がとじるとｎ行ｍ列の画素容量Ｃ２の電位はＡが−７Ｖ，Ｂが−２１Ｖに固定される。
１垂直周期後同じ動作がおこなわれるがｍ列の映像信号配線の信号電圧と、（ｍ＋１）列の映像信号配線の信号電圧の極性が反転するため、１垂直周期後の容量Ｃ２の電位はＡが＋７Ｖ，Ｂは＋２１Ｖに固定される。このような電位関係が発生することで図４にあるような等電位線の分布となり液晶分子の運動方向が決定される。透明画素電極と液晶配向方向制御電極との間には、大きな電界が発生するため液晶分子の運動速度を大きくすることができるようになる。
【００４７】
図１８では、液晶配向方向制御電極は、（ｎ−１）行の走査線上に形成された薄膜トランジスタ素子に連結されており、この薄膜トランジスタ素子のソース電極はｎ行の共通電極に連結されている。透明画素電極はｎ行の走査線とｍ列の映像信号配線がまじわる位置に形成された薄膜トランジスタ素子に連結されている。
ｍ列の映像信号配線が＋７Ｖ、（ｍ＋１）列の映像信号配線が−７Ｖの時に、（ｎ−１）行とｎ行の走査線が両方ともにアドレスされていると、上記２つの薄膜トランジスタは動作し、容量Ｃ２は充電されＡ，Ｂの電位はそれぞれ＋７Ｖ，ＯＶになる。（ｎ−１）行の走査線がとじてからｍ列の映像信号配線の電圧が＋７Ｖから−７Ｖに極性を変化させ、（ｍ＋１）列の映像信号配線の電圧が−７Ｖから＋７Ｖに極性を変化させると、容量Ｃ２のＡの電位は、ｎ行の薄膜トランジスタが動作しているため＋７Ｖから−７Ｖに変化する。この時（ｎ−１）行の薄膜トランジスタは動作していないため、容量Ｃ２のＢ電位はＯＶから−１４Ｖに変化する。次にｎ行走査線がとじると、ｎ行ｍ列の画素容量Ｃ２の電位はＡが−７Ｖ，Ｂが−１４Ｖに固定される。１垂直周期後同じ動作がおこなわれるが、ｍ列の映像信号配線の信号電圧と、（ｍ＋１）列の映像信号配線の信号電圧の極性が反転するため、１垂直周期後の容量Ｃ２の電位はＡが＋７Ｖ，Ｂは＋１４Ｖに固定される。このような電位関係が発生することで、図４にあるような等電位線の分布となり、液晶分子の運動方向が決定される。
【００４８】
〔実施例６〕図１４，図２７，図２８，図１５，図１６は、本発明の第６の実施例の平面図と断面図である。図２１，図２２が本発明の第６の実施例のＴＦＴアレイ基板の製造プロセスフローである。
図２９，図３０は、ＴＦＴアレイ基板の拡大断面図である。
カラーフィルター基板には、ベタ共通電極があり、実施例１と同様にバンプは無い。液晶配向方向制御電極と薄膜トランジスタの連結方法は実施例２とまったく同じである。
実施例６では、透明画素電極に形成されたスリット形状が実施例２とは異なり、図１４，図２７，図２８にあるような走査線方向に±４５度で配置されているものと、水平または、垂直に配置されているもの、または、円形や多角形のもので構成されている。液晶配向方向制御電極は、図１４，図２７，図２８にあるように透明画素電極の外周をぐるりととり囲んでおり、スリットと組みになっている液晶配向方向制御電極は走査線の方向に対して水平または、垂直に配置されている。
【００４９】
〔実施例７〕図３７，図３８，図３９，図４０，図４１，図４２と図４５，図４６，図４７，図４８，図５１，図５２，図５３，図５４，図５９図６０は、本発明の第７の実施例の回路モデル図と、薄膜トランジスタの平面図と断面図である。本発明の実施例５にすでにのべたように本発明の駆動方式を用いた場合、（ｎ−１）行の走査線上に形成された薄膜トランジスタに連結されている（ｍ＋１）列の映像信号配線と液晶配向方向制御電極との電極間に印加される電圧は最大で２８Ｖ程度にもなるのでこの２つの電極間のリーク電流が増大するという問題が発生する。そこで本発明の実施例７では、（ｎ−１）行の走査線上に形状され、液晶配向方向制御電極と連結されている薄膜トランジスタ素子の構造にダブルトランジスタ構造を採用した。ダブルトランジスタ構造は図５９，図６０にあてるように通常のシングルトランジスタよりもチャネル長が長くなっておりソース電極とドレイン電極間に高電圧が印加されてもリーク電流の増加をおさえることが可能である。ダブルトランジスタ構造を用いない場合トランジスタのチャネル長を長くすることもリーク電流の低減のためには有効である。図２９や図３３にあるように透明画素電極に連結されている薄膜トランジスタのチャネル長（Ｌ_１）よりも液晶配向方向制御電極に連結されている薄膜トランジスタのチャネル長（Ｌ_２）の方を大きくすることでリーク電流を低減できる。
【００５０】
ソース電極とドレイン電極のリーク電流を低減する方法として図５６，図５７，図５８のようなオフセット・トランジスタ構造も考えられる。この場合図５５のような平面構造の薄膜トランジスタ構造となります。
【００５１】
〔実施例８〕図１１，図１２，図６３，図６４は、本発明の第８の実施例の平面図である。実施例１，２，３，４，６に用いられる透明画素電極と液晶配向方向制御電極の形状に関するものである。負の誘電率異方性液晶分子は電圧を印加した時に透明電極のくさびの長くのびた方向に液晶分子の長軸方向をそろえる性質があり、本発明の実施例８の形状を採用することでディスクリネーションの発生をおさえることができる。
ディスクリネーションが発生すると液晶パネルの透過率が低下してしまい、応答速度もおそくなる傾向にある。本発明の形状を採用することで応答速度と透過率を向上することができる。
【００５２】
【発明の効果】
本発明を用いることで従来のマルチドメイン垂直配向方式液晶表示装置に用いられていたバンプまたはスリット付きのカラーフィルター基板を用いる必要がなくなりコストを低減することが可能となる。
バンプやスリット加工にともなうバラツキが原因の表示ムラも同時になくなるので歩留りが非常に高くなる。
さらにバンプやスリットのすきまからカラーフィルターの顔料中の不純物やバンプ中の不純物が液晶中に拡散しムラや残像（画像焼き付き）の問題をひきおこすことがなくなるので非常に信頼性の高い垂直配向方式液晶表示装置を実現できる。
【００５３】
ポリイミド配向膜塗布工程で不良が発生しても、簡単に酸素プラズマ処理によりリワーク可能となるので、リワークコストを低減できる。
【００５４】
本発明の電極構造と構造配置ならびに駆動方法を用いることで、開口率の大きなアクティブマトリックス基板を作れるので明るい表示装置を実現できる。さらに液晶分子の応答速度を向上することができるので動画対応の超大型液晶ＴＶを実現できる。
【００５５】
バンプを用いた従来の垂直配向方式液晶表示装置よりも暗室で光ぬけの少ないより黒い表示を均一に実現できる。
【図面の簡単な説明】
【図１】従来のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図２】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図３】平面電極とスリット電極が形成する電界による、垂直配向された負の誘電率異方性液晶分子の運動方向
【図４】平面電極とスリット電極と配向方向制御電極が形成する電界による垂直配向された負の誘電率異方性液晶分子の運動方向
【図５】本発明のマルチドメイン垂直配向方式液晶パネルの平面構造図
【図６】本発明のマルチドメイン垂直配向方式液晶パネルの平面構造図
【図７】本発明のマルチドメイン垂直配向方式液晶パネルの駆動電圧波形
【図８】本発明のマルチドメイン垂直配向方式液晶パネルの平面構造図
【図９】本発明のマルチドメイン垂直配向方式液晶パネルの平面構造図
【図１０】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図１１】本発明の液晶配向方向制御電極と透明画素電極に形成されたスリットの平面構造図
【図１２】本発明の液晶配向方向制御電極と透明画素電極に形成されたスリットの平面構造図
【図１３】本発明のマルチドメイン垂直配向方式液晶パネルの平面構造図
【図１４】本発明のマルチドメイン垂直配向方式液晶パネルの平面構造図
【図１５】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図１６】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図１７】本発明のマルチドメイン垂直配向方式液晶パネルの回路モデル図
【図１８】本発明のマルチドメイン垂直配向方式液晶パネルの回路モデル図
【図１９】本発明のマルチドメイン垂直配向方式液晶パネル製造のための５ホトマスク工程フロー説明
【図２０】本発明のマルチドメイン垂直配向方式液晶パネル製造のための４ホトマスク工程フロー説明
【図２１】本発明のマルチドメイン垂直配向方式液晶パネル製造のための５ホトマスク工程フロー説明
【図２２】本発明のマルチドメイン垂直配向方式液晶パネル製造のための４ホトマスク工程フロー説明
【図２３】本発明のマルチドメイン垂直配向方式液晶パネル製造のための５ホトマスク工程フロー説明
【図２４】本発明のマルチドメイン垂直配向方式液晶パネル製造のための４ホトマスク工程フロー説明
【図２５】本発明のマルチドメイン垂直配向方式液晶パネル製造のための５ホトマスク工程フロー説明
【図２６】本発明のマルチドメイン垂直配向方式液晶パネル製造のための４ホトマスク工程フロー説明
【図２７】本発明のマルチドメイン垂直配向方式液晶パネルの平面構造図
【図２８】本発明のマルチドメイン垂直配向方式液晶パネルの平面構造図
【図２９】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図３０】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図３１】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図３２】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図３３】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図３４】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図３５】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図３６】本発明のマルチドメイン垂直配向方式液晶パネルの断面構造図
【図３７】本発明のマルチドメイン垂直配向方式液晶パネルの回路モデル図
【図３８】本発明のマルチドメイン垂直配向方式液晶パネルの回路モデル図
【図３９】本発明のマルチドメイン垂直配向方式液晶パネルの回路モデル図
【図４０】本発明のマルチドメイン垂直配向方式液晶パネルの回路モデル図
【図４１】本発明のマルチドメイン垂直配向方式液晶パネルの回路モデル図
【図４２】本発明のマルチドメイン垂直配向方式液晶パネルの回路モデル図
【図４３】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図４４】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図４５】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図４６】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図４７】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図４８】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図４９】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図５０】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図５１】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図５２】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図５３】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図５４】本発明のマルチドメイン垂直配向方式液晶パネルの部分平面図
【図５５】本発明のマルチドメイン垂直配向方式液晶パネル用オフセット薄膜トランジスター素子の平面図
【図５６】本発明のマルチドメイン垂直配向方式液晶パネル用オフセット薄膜トランジスター素子の断面図
【図５７】本発明のマルチドメイン垂直配向方式液晶パネル用オフセット薄膜トランジスター素子の断面図
【図５８】本発明のマルチドメイン垂直配向方式液晶パネル用オフセット薄膜トランジスター素子の断面図
【図５９】本発明のマルチドメイン垂直配向方式液晶パネル用ダブルゲート薄膜トランジスター素子の断面図
【図６０】本発明のマルチドメイン垂直配向方式液晶パネル用のダブルゲート薄膜トランジスター素子の断面図
【図６１】平面電極とスリット電極と液晶配向方向制御電極が形成する電界による垂直配向された負の誘電率異方性液晶分子の運動
【図６２】本発明の液晶配向方向制御電極と透明画素電極に形成されたスリットの平面構造図
【図６３】本発明の液晶配向方向制御電極と透明画素電極に形成されたスリットの平面構造図
【図６４】本発明の液晶配向方向制御電極と透明画素電極に形成されたスリットの平面構造図
【図６５】本発明のマルチドメイン垂直配向方式液晶パネルの平面構造図
【符合の説明】
１−−−−カラーフィルター側ガラス基板
２−−−−ブラックマスク（遮光膜）
３−−−−カラーフィルター層
４−−−−カラーフィルター側透明導電膜（透明共通電極）
５−−−−垂直配向液晶分子の方向制御用バンプ
６−−−−カラーフィルター側垂直配向膜
７−−−−アクティブマトリックス基板側垂直配向膜
８−−−−透明画素電極
９−−−−画素電極側に形成されたスリット開口部
１０−−−−パッシベーション膜
１１−−−−映像信号配線
１２−−−−ゲート絶縁膜
１３−−−−アクティブマトリックス素子側ガラス基板
１４−−−−負の誘電率異方性液晶
１５−−−−液晶配向制御電極
１６−−−−透明画素電極に接続されている薄膜トランジスタ素子
１７−−−−走査線
１８−−−−アクティブマトリックス基板側の共通電極
１９−−−−液晶配向制御電極に接続されている薄膜トランジスタ素子
２０−−−−共通電極と液晶配向制御電極に接続されている薄膜トランジスタ素子
２１−−−−共通電極電位
２２−−−−（ｎ−１）行走査線信号波形
２３−−−−ｍ列映像信号配線信号波形
２４−−−−（ｍ＋１）列映像信号配線波形
２５−−−−ｎ行走査線信号波形
２６−−−−透明画素電極とトランジスタのドレイン電極を連結するためのコンタクトホール
２７−−−−共通電極とトランジスタのソース電極とを連結するためのコンタクトホール
２８−−−−共通電極とトランジスタのソース電極とを連結するためのコンタクトホール
２９−−−−液晶配向制御電極上の透明画素電極に形成された開口部
３０−−−−薄膜トランジスタ素子のドレイン電極
３１−−−−液晶配向制御電極とトランジスタのドレイン電極を連結するためのコンタクトホール
３２−−−−液晶配向制御電極とトランジスタのドレイン電極を連結するためのコンタクトホール
３３−−−−透明画素電極に形成された四角形型開口部
３４−−−−走査線端子部
３５−−−−ノンドープ薄膜半導体層
３６−−−−ｎ^＋ａ−ｓｉ層（オーミックコンタクト層）
Ｃ１−−−−透明画素電極とＣＦ（カラーフィルター）基板側の共通電極が形成する容量
Ｃ２−−−−透明画素電極と液晶配向方向制御電極が形成する容量
Ｃ３−−−−透明画素電極と走査線が形成する容量
Ｃ４−−−−ダブル薄膜トランジスタの中間電極と透明画素電極が形成する容量Ｃ５−−−−透明画素電極と共通電極が形成する容量
３７−−−−ダブル薄膜トランジスタの中間電極
３８−−−−エッチングストッパー層
Ｆ−−−−オフセット薄膜トランジスタ素子のオフセット量
３９−−−−ソース電極（共通電極に連結）
４０−−−−ドレイン電極（液晶配向方向制御電極に連結）
４１−−−−液晶配向制御電極とトランジスタのドレイン電極とを連結するためのコンタクトホール
４２−−−−液晶配向制御電極とトランジスタのドレイン電極とを連結するためのコンタクトホール[0001]
[Industrial application fields]
The present invention relates to a large-screen active matrix liquid crystal TV display device having a wide viewing angle, high brightness and high speed response at low cost.
[0002]
[Prior art]
As shown in FIG. 1, in the conventional vertical alignment type liquid crystal display device, bumps for controlling the movement direction of liquid crystal molecules are formed on the transparent common electrode of the color filter side substrate, and the transparent pixel electrode of the active matrix substrate is formed. A method is adopted in which a slit for controlling the movement direction of the liquid crystal molecules is provided, and the bump and slit form a set to determine the movement direction of the liquid crystal molecules. There is also a method in which slits for controlling the direction of movement of liquid crystal molecules are formed in the transparent common electrode instead of bumps on the color filter side substrate.
Both of these methods are mass-produced and put into practical use.
[0003]
[Problems to be solved by the invention]
In the conventional multi-domain vertical alignment type liquid crystal display device, bumps or slits must be formed on the transparent common electrode on the color filter substrate, and the photomask process has to be performed once. Therefore, it was not possible to avoid an increase in cost.
[0004]
Further, in the vertical alignment type liquid crystal display device in which the bumps are formed on the color filter side as shown in FIG. 1, if the bump width, height and angle of the inclined surface are not precisely controlled, variations in the liquid crystal molecules will vary. It occurred and unevenness was likely to occur in the halftone area.
Since the material of the bump is a positive photoresist, it is necessary to completely remove the organic solvent, and it is necessary to bake at a high temperature of 200 ° C. or more, making it difficult to shorten the process. When contaminants elute into the liquid crystal from the positive photoresist bumps, an afterimage phenomenon occurs, which is also a problem in terms of reliability.
[0005]
In a conventional color filter substrate using bumps, a positive photoresist is used as a bump material. Therefore, when a defect occurs in the vertical alignment film coating process, a dull ashing method using oxygen plasma is used when reworking. I can't. Therefore, a wet removal method using an organic solvent having a high running cost has to be used, resulting in a very high rework cost.
[0006]
The conventional vertical alignment type liquid crystal display device using bumps and slits has a drawback that the response speed of the liquid crystal is slow when shifting from black display to halftone display or from white display to halftone display.
[0007]
The present invention solves the above-mentioned problems, and its object is to improve the reliability of a large-sized vertical alignment type liquid crystal display device, which can be manufactured at low cost in a short time, and is bright and quick in response speed. It is to realize a liquid crystal display.
[0008]
[Means for Solving the Problems]
In order to solve the above problems and achieve the above object, the present invention uses the following means.
[0009]
[Means 1] In order to apply a voltage to the negative dielectric anisotropy liquid crystal molecules vertically aligned on the active matrix substrate and the color filter substrate, and to cause the liquid crystal molecules to be tilted in two different directions or four directions, the following two types are used. The electrode structure and structure arrangement were formed in one pixel of the active matrix substrate.
i) A transparent solid electrode is used on the color filter substrate side, and an elongated slit-like pattern (there is no transparent electrode in the slit portion) is formed on the transparent pixel electrode on the active matrix substrate side facing this. .
ii) A transparent solid electrode is used on the color filter substrate side, an elongated slit-like pattern is formed on the transparent pixel electrode on the opposite side of the active matrix substrate, and an insulating film is placed under the slit. A liquid crystal alignment direction control electrode is formed which is substantially the same shape as the slit and is larger in size than the slit.
iii) In a pixel of n rows and m columns, a thin film transistor element is formed at a position where a scanning line of (n−1) rows and a video signal wiring of (m + 1) columns are mixed, and a video signal wiring of (m + 1) columns and n rows A liquid crystal alignment direction control electrode used for m columns of pixels is connected through this thin film transistor, and a thin film transistor element is formed at a position where n rows of scanning lines and m columns of video signal wirings are mixed. Are connected to each other through the thin film transistor element.
[0010]
[Means 2] In order to apply a voltage to the negative dielectric anisotropy liquid crystal molecules vertically aligned on the active matrix substrate and the color filter substrate, and to cause the liquid crystal molecules to be tilted in two different directions or four directions, the following two types are used. The electrode structure and structure arrangement were formed in one pixel of the active matrix substrate.
i) A transparent solid electrode is used on the color filter substrate side, and an elongated slit-like pattern (there is no transparent electrode in the slit portion) is formed on the transparent pixel electrode on the active matrix substrate side facing this.
ii) A transparent solid electrode is used on the color filter substrate side, an elongated slit-like pattern is formed on the transparent pixel electrode on the side of the active matrix substrate, and an insulating film is placed under the slit. Then, a liquid crystal alignment direction control electrode is formed which is substantially the same shape as the slit and is larger in size than the slit.
iii) In a pixel of n rows and m columns, a thin film transistor element is formed on a scanning line of (n−1) rows, and n rows of common electrodes and liquid crystal alignment direction control electrodes used for the pixels of n rows and m columns are A thin film transistor element is formed at a position where the n rows of scanning lines and the m columns of video signal wirings are connected to each other through the thin film transistor elements, and the m rows of video signal wirings and the n rows and m columns of pixels are formed. A transparent pixel electrode to be used is connected through the thin film transistor.
[0011]
[Means 3] The following two types of electrode structures and arrangements for applying a voltage to negative dielectric anisotropy liquid crystal molecules vertically aligned on the active matrix substrate and the color filter substrate to cause the liquid crystal molecules to be tilted in multiple directions Was formed in one pixel of the active matrix substrate.
i) A transparent solid electrode is used on the color filter substrate side, and a transparent pixel electrode on the side of the active matrix substrate opposite to this is a circular or polygonal hole (there is no transparent electrode in the hole portion).
ii) A transparent solid electrode is used on the color filter substrate side, an elongated slit-like pattern is formed on the transparent pixel electrode on the opposite side of the active matrix substrate, and an insulating film is placed under the slit. Then, a liquid crystal alignment direction control electrode is formed which is substantially the same shape as the slit and is larger in size than the slit.
iii) In a pixel of n rows and m columns, a thin film transistor element is formed at a position where a scanning line of (n-1) rows and a video signal wiring of (m + 1) columns are mixed, and a video signal wiring of (m + 1) columns and n rows m A liquid crystal alignment direction control electrode used for a column pixel is connected through the thin film transistor element, and a thin film transistor element is formed at a position where an n-row scanning line and an m-column video signal wiring are mixed. The video signal lines in the columns and the transparent pixel electrodes used for the pixels in the n rows and m columns are connected through the thin film transistor elements.
[0012]
[Means 4] The following two types of electrode structures and structures for applying a voltage to the negative dielectric anisotropy liquid crystal molecules vertically aligned on the active matrix substrate and the color filter substrate to cause the liquid crystal molecules to be tilted in multiple directions. The arrangement was formed within one pixel of the active matrix substrate.
i) A transparent solid electrode is used on the side of the color filter substrate, and a transparent pixel electrode on the side of the active matrix substrate opposite to this has many circular or polygonal holes (there is no transparent electrode in the hole portion). Form.
ii) A transparent solid electrode is used on the color filter substrate side, an elongated slit-like pattern is formed on the transparent pixel electrode on the opposite side of the active matrix substrate, and an insulating film is placed under the slit. A liquid crystal alignment direction control electrode is formed which is substantially the same shape as the slit and is larger in size than the slit.
iii) In a pixel of n rows and m columns, a thin film transistor element is formed on a scanning line of (n−1) rows, and n rows of common electrodes and liquid crystal alignment direction control electrodes used for the pixels of n rows and m columns are A thin film transistor is formed at a position where the n rows of scanning lines and the m columns of video signal wirings are connected through the thin film transistor elements, and is used for the m columns of video signal wirings and the n rows and m columns of pixels. A transparent pixel electrode is connected through the thin film transistor element.
[0013]
[Means 5] In means 1, 2, 3 and 4, the time width of the address signal waveform of the scanning line is at least twice the horizontal period, and the (n-1) th scanning line address signal waveform and the nth The address signal waveform of the scanning line is more than 1 times the horizontal period, and the polarity of the video signal voltage of the video signal wiring of m columns and the polarity of the video signal voltage of the video signal wiring of (m + 1) columns are mutually different. The polarities are different for each horizontal period, and the polarities are changed for each vertical period.
[0014]
[Means 6] In the means 1 and 3, the channel length (L) of the thin film transistor element formed at the position where the n rows of scanning lines and the m columns of video signal wirings are connected and connected to the transparent pixel electrode. ₁ ) Than the channel length (L) of the thin film transistor element formed at the position where the (n−1) row scanning lines and the (m + 1) column video signal wirings are connected to the liquid crystal alignment direction control electrode. ₂ ) Is larger (L ₁ <L ₂ ).
[0015]
[Means 7] In the means 2 and 4, the channel length (L) of the thin film transistor element formed at the position where the n rows of scanning lines and the m columns of video signal wirings are connected and connected to the transparent pixel electrode. ₁ ) Than the channel length (L) of the thin film transistor element formed on the (n−1) rows of scanning lines and connected to the liquid crystal alignment direction control electrode. ₂ ) Is larger (L ₁ <L ₂ ).
[0016]
[Means 8] In the means 1, 2, 3 and 4, the double transistor element structure or the offset channel element structure is used for the thin film transistor element connected to the liquid crystal alignment direction control electrode.
[0017]
[Means 9] In the means 1 and 2, the elongated slit formed in the transparent pixel electrode on the active matrix substrate side and the slit combined with the liquid crystal alignment direction control electrode are in the direction in which the scanning line extends. In the direction of the angle of approximately ± 45 degrees, they are alternately arranged while having a substantially parallel relationship with each other, and the polarization axes of the two polarizing plates installed outside the liquid crystal cell are the same as the scanning line direction and the image. Aligned in the signal wiring direction, they are arranged perpendicular to each other.
[0018]
[Means 10] In the means 1 and 2, the elongated slits formed in the transparent pixel electrode on the active matrix substrate side are arranged in a direction substantially parallel to and perpendicular to the direction in which the scanning line extends. In addition, the slits combined with the liquid crystal alignment direction control electrode are arranged so that the direction of the angle is approximately ± 45 degrees with respect to the scanning signal wiring direction, and the two polarizing plates installed outside the liquid crystal cell The polarization axes are aligned in the scanning line direction and the video signal wiring direction, and are orthogonal to each other.
[0019]
[Means 11] In the means 1 and 2, the elongated slit formed in the transparent pixel electrode on the active matrix substrate side is disposed at an angle of approximately ± 45 degrees with respect to the direction in which the scanning line extends, and The slits paired with the liquid crystal alignment direction control electrode are arranged in a direction substantially parallel to and perpendicular to the direction in which the scanning line extends, and the liquid crystal alignment direction control electrode is disposed on the outer periphery of the pixel electrode. The insulating film is surrounded by the transparent pixel electrode, and the polarizing axes of the two polarizing plates installed outside the liquid crystal cell are aligned in the scanning line direction and the video signal wiring direction, An orthogonal arrangement was adopted.
[0020]
[Means 12] In means 3 and 4, the slit paired with the liquid crystal alignment direction control electrode so as to surround a plurality of circular or polygonal holes formed in the transparent pixel electrode on the active matrix substrate side is scanned. The transparent pixel electrode is arranged in a direction perpendicular to the direction parallel to the line extending direction, and the liquid crystal alignment direction control electrode surrounds the transparent pixel electrode and the insulating film so as to surround the transparent pixel electrode. The polarization axes of the two polarizing plates installed outside the liquid crystal cell are aligned with the scanning line direction and the video signal wiring direction, and are arranged perpendicular to each other.
[0021]
[Means 13] The liquid crystal alignment direction control electrodes formed by applying an insulator below the slits of the transparent pixel electrodes in the means 1, 2, 3 and 4 are simultaneously formed in the same layer when forming the scanning lines. .
[0022]
[Means 14] In the means 1 and 2, the liquid crystal alignment direction control electrode formed by covering the lower layer of the slit of the transparent pixel electrode is formed in the same layer at the same time when the video signal wiring is formed.
[0023]
[Means 15] In order to drive one pixel in means 1, two thin film transistor elements are required in one pixel, and a thin film transistor element formed at a position where n rows of scanning lines and m columns of video signal wirings are arranged. There was only one contact hole for electrically connecting the drain electrode and the transparent pixel electrode.
[0024]
[Means 16] In the means 1 and 3, two thin film transistor elements are required in one pixel to drive one pixel, and (n-1) rows of scanning lines and (m + 1) columns of video signal wirings are provided. There are two contact holes for electrically connecting the drain electrode of the thin film transistor element formed in the surrounding position and the liquid crystal alignment direction control electrode, and n rows of scanning lines and m columns of video signal wirings are mixed. There was only one contact hole for electrically connecting the drain electrode of the thin film transistor element formed at the position and the transparent pixel electrode.
[0025]
[Means 17] In the means 1, 2, 3 and 4, two thin film transistor elements are required in one pixel to drive one pixel, and one thin film transistor is connected to the transparent pixel electrode. The remaining one thin film transistor was connected to the liquid crystal alignment direction control electrode, and the transparent pixel electrode and the liquid crystal alignment direction control electrode were overlapped with an insulating film to form a capacitor.
[0026]
[Means 18] An intermediate electrode and a transparent pixel electrode of a thin film transistor element having a double transistor structure connected to a liquid crystal alignment direction control electrode in the means 1, 2, 3, 4 and the transparent pixel electrode overlap each other through an insulating film to increase capacitance. It was made to form.
[0027]
[Means 19] In the means 1 and 3, the transparent pixel electrodes of n rows and m columns and the scanning lines of (n-1) rows are formed by interposing an insulating film so that a storage capacitor can be formed.
[0028]
[Means 20] In the means 2 and 4, the transparent pixel electrode of n rows and m columns and the common electrode of n rows are in contact with each other through an insulating film so that a storage capacitor can be formed.
[0029]
[Action]
By using the means 1, 2, 3, 4 and 5, it is not necessary to form bumps for controlling the movement direction of liquid crystal molecules as shown in FIG. 1 on a CF (color filter) substrate. As shown in FIG. 2, FIG. 10, FIG. 15, and FIG.
Furthermore, the problem of diffusion of contaminants from bumps into the liquid crystal, which has been a problem in the past, is completely eliminated, and the problem of unevenness in the halftone region, which has occurred due to the non-uniformity of the shape of the pump, is completely eliminated.
As a result, it is possible to improve the yield and reliability at the same time.
[0030]
Further, since there is no bump, even if alignment film application fails, it can be easily regenerated in a short time with oxygen plasma by a dry asher. Oxygen and argon plasma treatment using a dry asher can be used for the surface treatment before the alignment film application, so that the occurrence of repelling and pinholes in the alignment film application process can be greatly reduced.
[0031]
By using the means 1, 2, 3, 4, 5, 6, 7, 8, and 18, a special drive IC for driving the liquid crystal alignment direction control electrode and the connection terminal portion are not necessary, and the product is inexpensive. realizable. Furthermore, leakage current can be reduced by using a double transistor structure or an offset transistor structure. Even if a large voltage is applied between the source and drain electrodes of the transistor, the concentration of the electric field can be dispersed and prevented, so that the shift of the threshold voltage (Vth) of the thin film transistor can be reduced, and a highly reliable liquid crystal panel can be realized. The channel length (L of the thin film transistor connected to the liquid crystal alignment direction control electrode ₂ ) Can be increased to reduce the leakage current.
[0032]
By using the means 1, 2, 3, 4, 5, 9, 10, 11, 12, the effective use efficiency of the polarizing plate can be greatly improved as compared with the conventional TN mode liquid crystal panel. The cost of a polarizing plate used in a large liquid crystal display device can be reduced. Furthermore, since the effective utilization efficiency of the reflective polarizer made of a multilayer laminate (trade name 3M D-BEF) of two kinds of materials used in the backlight can be greatly improved, an ultra-large liquid crystal display device can be used. The cost of the backlight can be greatly reduced.
[0033]
By using the means 1, 2, 3, 4, 13, and 14, the active matrix liquid crystal panel of the present invention can be manufactured in the same process without substantially changing the manufacturing process of the conventional TN mode active matrix substrate and the manufacturing process of the color filter. Since it can be manufactured, it is advantageous in terms of yield and cost reduction.
[0034]
By using the means 1, 2, 3, 4, 5, 15, 16, 17, a vertical alignment type liquid crystal display device having the simplest structure can be realized. Since there is no unnecessary thin film transistor in one pixel, the aperture ratio can be maximized, so that a bright display can be realized.
[0035]
By using means 1, 2, 3, 4, 5, 6, 7, 8, and 18, a large voltage can be applied between the transparent pixel electrode and the liquid crystal alignment direction control electrode, so that vertically aligned liquid crystal molecules are driven. The distortion of the electric field for making it possible can be made very large. As a result, the reaction speed of the liquid crystal molecules can be increased, and even when moving images are displayed, there is almost no image flow or afterimage phenomenon.
[0036]
By using the means 1, 2, 3, 4, 19, and 20, when the n scanning lines are turned off, the potential fluctuation of the transparent pixel electrode is reduced, and flicker can be reduced.
[0037]
By using means 1, 2, 3, 4 and 5, the liquid crystal molecules that are vertically aligned during black display are aligned almost vertically, so that the light exposure is much higher than that using conventional bumps. It is possible to realize a completely uniform black display even in a dark room.
[0038]
【Example】
[Embodiment 1] FIGS. 2, 5, and 8 are a sectional view, a model view, and a plan view of a first embodiment of the present invention. 19 and 20 show a process flow for manufacturing the TFT array substrate according to the first embodiment of the present invention. 31 and 32 are enlarged sectional views of the TFT array substrate.
The color filter substrate has a solid transparent common electrode, and an active matrix substrate is arranged in parallel to face the substrate. In the conventional vertical alignment mode liquid crystal panel, bumps for controlling the movement direction of the liquid crystal are formed on the transparent common electrode as shown in FIG. 1, but in the vertical alignment mode liquid crystal panel of the present invention, Such bumps are not necessary.
An active matrix substrate is formed by first forming a scanning line, an insulating film, an amorphous silicon layer (non-doped layer), and an n for an ohmic contact. ⁺ Deposit an amorphous silicon layer. After the thin film transistor element is formed, the video signal wiring, the drain electrode, and the liquid crystal alignment direction control electrode are simultaneously formed in the same layer. By using the halftone exposure technique disclosed in Japanese Published Patent Application No. 2000-0666240, the thin film transistor element portion, the video signal wiring, the drain electrode, and the liquid crystal alignment direction control electrode can be simultaneously formed in the same layer. . FIG. 32 is a cross-sectional view of the thin film transistor and the active matrix substrate of Example 1 of the present invention using halftone exposure.
[0039]
As shown in FIG. 8, in the first embodiment of the present invention, only two thin film transistor elements are required in one pixel. The transparent pixel electrodes of n rows and m columns are connected to thin film transistor elements formed at positions where n rows of scanning lines and m columns of video signal wirings are mixed, and the liquid crystal alignment direction control electrodes are (n−1) rows. Are connected to the thin film transistor element formed at the position where the scanning signal line and the video signal wiring in the (m + 1) th column are mixed. Two types of slits are formed in the transparent pixel electrode, and FIGS. 3 and 4 are enlarged sectional views of the slits.
In the slit of the type shown in FIG. 3, the vertically aligned liquid crystal molecules are placed in the direction shown in FIG. 3 when a voltage is applied. In the slit of the type shown in FIG. 4, a liquid crystal alignment direction control electrode is disposed with an insulating film interposed below the slit. In the slit of the type shown in FIG. 4, the vertically aligned liquid crystal molecules are placed in the direction shown in FIG. 4 when a voltage is applied. FIG. 11 and FIG. 12 are modifications of FIG. 3 and FIG. In FIG. 4, the size of the liquid crystal alignment direction control electrode is larger than that of the slit of the transparent pixel electrode, and the insulating films are overlapped with each other. The important point of the present invention is that the transparent pixel electrode and the liquid crystal alignment direction control electrode overlap each other through an insulating film to form a capacitor. 61, the negative dielectric constant anisotropic liquid crystal molecules can be moved in the same direction as in FIG. 4, but in the planar structure as shown in FIG. 62, the transparent pixel electrode and the liquid crystal alignment direction control electrode can be moved. This is a problem when the driving method of the present invention is used because the capacitance formed by the transparent pixel electrode and the liquid crystal alignment direction control electrode is small.
As shown in FIGS. 63 and 64, it is particularly important in the driving method of the present invention that the transparent pixel electrode and the liquid crystal alignment direction control electrode slightly overlap each other through the insulating film.
[0040]
[Embodiment 2] FIGS. 10 and 13 are a sectional view and a plan view of a second embodiment of the present invention. 21 and 22 show a process flow for manufacturing a TFT array substrate according to the second embodiment of the present invention. 29 and 30 are enlarged sectional views of the TFT array substrate.
The color filter substrate has a solid transparent common electrode, and there is no bump as in the first embodiment.
In an active matrix substrate, first, a scanning line and a liquid crystal alignment direction control electrode are simultaneously formed in the same layer, and then an insulating film, an amorphous silicon layer (non-doped layer), and an n-type for ohmic contact are formed. ⁺ Deposit an amorphous silicon layer. After the thin film transistor element portion is formed, the video signal wiring and the drain electrode are formed simultaneously.
By using the halftone exposure technique disclosed in Japanese Published Patent Application No. 2000-0666240, the thin film transistor element portion, the video signal wiring and the drain electrode can be simultaneously formed in the same layer. FIG. 30 is a cross-sectional view of a thin film transistor and an active matrix substrate of Example 2 of the present invention using halftone exposure.
[0041]
As shown in FIG. 13, in the second embodiment of the present invention, only two thin film transistor elements are required for one pixel. The transparent pixel electrodes of n rows and m columns are connected to thin film transistor elements formed at positions where n rows of scanning lines and m columns of video signal wirings are mixed, and the liquid crystal alignment direction control electrodes are (n−1) rows. Are connected to the thin film transistor element formed at the position where the scanning signal line and the video signal wiring in the (m + 1) th column are mixed. In the case of Example 1, since the drain electrode of this thin film transistor element and the liquid crystal alignment direction control electrode are simultaneously formed in the same layer, they are automatically connected. In the case of Example 2, the drain electrode of this thin film transistor element and the liquid crystal alignment Since the direction control electrode is not formed in the same layer, two contact holes must be opened in order to electrically connect these two electrodes. In Example 1, two thin film transistor elements and one contact hole were sufficient, but in Example 2, two thin film transistor elements and three contact holes are required as shown in FIG.
[0042]
[Embodiment 3] FIGS. 2, 6, and 9 are a sectional view, a model view, and a plan view of a third embodiment of the present invention. 23 and 24 show the manufacturing process flow of the TFT array substrate according to the third embodiment of the present invention.
35 and 36 are enlarged sectional views of the TFT array substrate.
The color filter substrate has a solid transparent common electrode, and there is no bump as in the first embodiment.
In an active matrix substrate, first, a scanning line and a common electrode are formed in the same layer at the same time, and then an insulating film, an amorphous silicon layer (non-doped layer), and an ohmic contact n are formed. ⁺ Deposit an amorphous silicon layer.
After the thin film transistor element is formed, the video signal wiring, the drain electrode, and the liquid crystal alignment direction control electrode are simultaneously formed in the same layer.
By using the halftone exposure technique disclosed in Japanese Published Patent Application JP 2000-0666240, the thin film transistor element portion, the video signal wiring, the drain electrode, and the liquid crystal alignment direction control electrode can be simultaneously formed in the same layer. is there. FIG. 36 is a cross-sectional view of a thin film transistor and an active matrix substrate of Example 3 of the present invention using halftone exposure.
[0043]
As shown in FIG. 9, in the third embodiment of the present invention, only two thin film transistor elements are required in one pixel. The transparent pixel electrodes of n rows and m columns are connected to thin film transistor elements formed at positions where n rows of scanning lines and m columns of video signal wirings are mixed, and the liquid crystal alignment direction control electrodes are (n−1) rows. Are connected to a thin film transistor formed on the investigation line. As the structure of the pixel electrode, the shapes as in the first and second embodiments are possible, but in FIG. 9, the slits formed in the transparent pixel electrode are arranged horizontally and vertically with respect to the direction in which the scanning line extends. The slits combined with the liquid crystal alignment direction control electrodes are arranged at an angle of ± 45 degrees with respect to the direction in which the scanning lines extend. In the case of Example 3, since the source electrode of the thin film transistor element formed on the (n-1) row scanning line and the common electrode of the n row are not formed in the same layer, these two electrodes are electrically connected. In order to do this, two contact holes must be drilled. Therefore, in Example 3, as in Example 2, two thin film transistor elements and three contact holes are required as shown in FIG.
[0044]
[Embodiment 4] FIGS. 10 and 65 are a sectional view and a plan view of a fourth embodiment of the present invention. 25 and 26 show a process flow for manufacturing a TFT array substrate according to the fourth embodiment of the present invention. 33 and 34 are enlarged sectional views of the TFT array substrate.
The color filter substrate has a solid transparent common electrode, and there is no bump as in the first embodiment.
In the active matrix substrate, first, a scanning line, a common electrode, and a liquid crystal alignment control electrode are simultaneously formed in the same layer, and then an insulating film, an amorphous silicon layer (non-doped layer), and n for ohmic contact are formed. ⁺ Deposit an amorphous silicon layer. After the thin film transistor element portion is formed, the video signal wiring and the drain electrode are formed simultaneously.
By using the halftone exposure technique disclosed in Japanese Laid-Open Patent Publication No. 2000-0666240, the thin film transistor element portion, the video signal wiring, and the drain electrode can be simultaneously formed in the same layer. FIG. 34 is a cross-sectional view of the thin film transistor and the active matrix substrate of Example 4 of the present invention using halftone exposure.
As shown in FIG. 65, in the fourth embodiment of the present invention, only two thin film transistor elements are required in one pixel. The transparent pixel electrodes of n rows and m columns are connected to thin film transistor elements formed at positions where n rows of scanning lines and m columns of video signal wirings are mixed, and the liquid crystal alignment direction control electrodes are (n−1) rows. Are connected to the thin film transistor formed on the scanning line. In the case of Example 4, in order to electrically connect the source electrode and the drain electrode of the thin film transistor element formed on the scanning line of (n-1) rows to the common electrode and the liquid crystal alignment direction control electrode, respectively, two each Each contact hole must be opened.
Therefore, in Example 4, two thin film transistor elements and five contact holes are required as shown in FIG.
[0045]
[Embodiment 5] FIG. 7 is a timing chart relating to a drive waveform according to a fifth embodiment of the present invention. 4 is a driving waveform for driving the vertical alignment type liquid crystal display device described in Examples 1, 2, and 4. What is important here is that the signal waveform (address signal width) of the (n-1) -th scanning line and the n-th scanning line has a time width of at least twice the horizontal period, and more than one horizontal period. The video signal voltage polarities of the video signal wirings in the m columns and the video signal voltage polarities of the video signal wirings in the (m + 1) columns are different from each other and are different for each horizontal period. The polarity is reversed. If the driving method of the present invention is used, as shown in FIGS. 17 and 18, the capacitor C2 in the circuit model diagram (capacitor C2 is formed by the transparent pixel electrode and the liquid crystal alignment direction control electrode interposing an insulating film between each other). It is possible to charge when the signal waveform of the (n-1) -th scan line and the signal waveform of the n-th scan line overlap each other.
[0046]
In FIG. 17, the liquid crystal alignment direction control electrode is connected to a thin film transistor element formed at a position where (n−1) rows of scanning lines and (m + 1) columns of video signal wirings are mixed, and the transparent pixel electrode is n rows of scanning lines. Are connected to thin film transistor elements formed at positions where video signal wirings in m columns are mixed. When the video signal wiring in the m column is + 7V and the video signal wiring in the (m + 1) column is -7V, the two thin film transistors operate when both the (n-1) row and the n row scanning lines are addressed. The capacitor C2 is charged and the potentials of A and B become +7 and -7V, respectively. (N-1) The voltage of the video signal wiring in the m column changes from + 7V to -7V after the scanning line of the row is closed, and the polarity of the video signal wiring in the (m + 1) column changes from -7V to + 7V. When changed, the potential of A in the capacitor C2 changes from + 7V to -7V because the thin film transistors in the n rows are operating. At this time, since the thin film transistors in the (n-1) th row are not operating, the B potential of the capacitor C2 changes from -7V to -21V. Next, when the n-row scanning line is closed, the potential of the pixel capacitor C2 in the n-row and m-column is fixed to -7V for A and -21V for B.
The same operation is performed after one vertical cycle, but the polarity of the signal voltage of the m-th column video signal wiring and the signal voltage of the (m + 1) -th column video signal wiring is inverted, so that the potential of the capacitor C2 after one vertical cycle is A Is fixed at + 7V and B is fixed at + 21V. When such a potential relationship is generated, an equipotential line distribution as shown in FIG. 4 is obtained, and the movement direction of the liquid crystal molecules is determined. Since a large electric field is generated between the transparent pixel electrode and the liquid crystal alignment direction control electrode, the movement speed of the liquid crystal molecules can be increased.
[0047]
In FIG. 18, the liquid crystal alignment direction control electrode is connected to a thin film transistor element formed on (n-1) rows of scanning lines, and the source electrode of this thin film transistor element is connected to n rows of common electrodes. The transparent pixel electrode is connected to a thin film transistor element formed at a position where n rows of scanning lines and m columns of video signal wirings are mixed.
When the video signal wiring in the m column is + 7V and the video signal wiring in the (m + 1) column is -7V, the two thin film transistors operate when both the (n-1) row and the n row scanning lines are addressed. The capacitor C2 is charged and the potentials of A and B become + 7V and OV, respectively. (N-1) The voltage of the video signal wiring in the m column changes from + 7V to -7V after the scanning line of the row is closed, and the polarity of the video signal wiring in the (m + 1) column changes from -7V to + 7V. When changed, the potential of A of the capacitor C2 changes from + 7V to -7V because the n rows of thin film transistors are operating. At this time, since the thin film transistors in the (n−1) th row are not operating, the B potential of the capacitor C2 changes from OV to −14V. Next, when the n-row scanning line is closed, the potential of the pixel capacitor C2 in the n-row and m-column is fixed at -7V for A and -14V for B. The same operation is performed after one vertical cycle. However, since the polarity of the signal voltage of the video signal wiring in the m columns and the signal voltage of the video signal wiring in the (m + 1) columns are reversed, the potential of the capacitor C2 after one vertical cycle is A is fixed at + 7V and B is fixed at + 14V. By generating such a potential relationship, the distribution of equipotential lines as shown in FIG. 4 is obtained, and the movement direction of the liquid crystal molecules is determined.
[0048]
[Embodiment 6] FIGS. 14, 27, 28, 15 and 16 are a plan view and a sectional view of a sixth embodiment of the present invention. 21 and 22 show the process flow for manufacturing a TFT array substrate according to the sixth embodiment of the present invention.
29 and 30 are enlarged sectional views of the TFT array substrate.
The color filter substrate has a solid common electrode, and there is no bump as in the first embodiment. The connection method of the liquid crystal alignment direction control electrode and the thin film transistor is exactly the same as in the second embodiment.
In the sixth embodiment, the slit shape formed in the transparent pixel electrode is different from that in the second embodiment, and is arranged at ± 45 degrees in the scanning line direction as shown in FIGS. 14, 27, and 28. Or it is comprised by what is arrange | positioned perpendicularly | vertically, or circular or polygonal. As shown in FIGS. 14, 27, and 28, the liquid crystal alignment direction control electrode surrounds the outer periphery of the transparent pixel electrode, and the liquid crystal alignment direction control electrode paired with the slit is in the direction of the scanning line. They are arranged horizontally or vertically.
[0049]
[Embodiment 7] FIGS. 37, 38, 39, 40, 41, 42 and 45, 46, 47, 48, 51, 52, 53, 54, 59 60 is a circuit model diagram of the seventh embodiment of the present invention, and a plan view and a sectional view of a thin film transistor. When the driving method of the present invention is used as already described in the fifth embodiment of the present invention, (m + 1) columns of video signal wirings connected to the thin film transistors formed on the (n-1) rows of scanning lines; Since the voltage applied between the liquid crystal alignment direction control electrodes is about 28 V at the maximum, there arises a problem that the leakage current between the two electrodes increases. Therefore, in Example 7 of the present invention, a double transistor structure is adopted as the structure of the thin film transistor element which is formed on the (n-1) rows of scanning lines and connected to the liquid crystal alignment direction control electrode. As shown in FIGS. 59 and 60, the double transistor structure has a longer channel length than a normal single transistor, and can suppress an increase in leakage current even when a high voltage is applied between the source electrode and the drain electrode. is there. When the double transistor structure is not used, increasing the channel length of the transistor is also effective for reducing leakage current. As shown in FIGS. 29 and 33, the channel length of the thin film transistor connected to the transparent pixel electrode (L ₁ ) Than the channel length of the thin film transistor connected to the liquid crystal alignment direction control electrode (L ₂ The leakage current can be reduced by increasing the value of ().
[0050]
As a method of reducing the leakage current of the source electrode and the drain electrode, an offset transistor structure as shown in FIGS. 56, 57, and 58 can be considered. In this case, a thin film transistor structure with a planar structure as shown in Fig. 55 is obtained.
[0051]
[Embodiment 8] FIGS. 11, 12, 63 and 64 are plan views of an eighth embodiment of the present invention. This relates to the shapes of the transparent pixel electrode and the liquid crystal alignment direction control electrode used in Examples 1, 2, 3, 4, and 6. The negative dielectric anisotropy liquid crystal molecules have the property of aligning the long axis direction of the liquid crystal molecules in the direction of the longer wedge of the transparent electrode when a voltage is applied, and adopting the shape of Example 8 of the present invention allows the disc It is possible to suppress the occurrence of a combination.
When disclination occurs, the transmittance of the liquid crystal panel decreases, and the response speed tends to be slow. By adopting the shape of the present invention, response speed and transmittance can be improved.
[0052]
【The invention's effect】
By using the present invention, it is not necessary to use a color filter substrate with bumps or slits, which has been used in a conventional multi-domain vertical alignment type liquid crystal display device, and the cost can be reduced.
Since the display unevenness due to the variation caused by the bump or slit processing is eliminated at the same time, the yield becomes very high.
In addition, the impurities in the color filter pigment and the bumps diffuse from the gaps in the bumps and slits into the liquid crystal and cause no problems of unevenness and afterimage (image burn-in). A display device can be realized.
[0053]
Even if a defect occurs in the polyimide alignment film coating process, rework can be easily performed by oxygen plasma treatment, so that the rework cost can be reduced.
[0054]
By using the electrode structure, the structure arrangement, and the driving method of the present invention, an active matrix substrate having a large aperture ratio can be made, so that a bright display device can be realized. Furthermore, since the response speed of liquid crystal molecules can be improved, an ultra-large liquid crystal TV compatible with moving images can be realized.
[0055]
As compared with the conventional vertical alignment type liquid crystal display device using bumps, a darker display with less light exposure in a dark room can be realized uniformly.
[Brief description of the drawings]
FIG. 1 is a sectional view of a conventional multi-domain vertical alignment type liquid crystal panel.
FIG. 2 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 3 shows the direction of movement of vertically aligned negative dielectric anisotropy liquid crystal molecules due to the electric field formed by a plane electrode and a slit electrode.
FIG. 4 shows the direction of motion of negatively-polarized anisotropic liquid crystal molecules vertically aligned by an electric field formed by a planar electrode, a slit electrode, and an alignment direction control electrode.
FIG. 5 is a plan structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 6 is a plan view of a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 7 shows driving voltage waveforms of the multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 8 is a plan view of a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 9 is a plan structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 10 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 11 is a plan structural view of slits formed in the liquid crystal alignment direction control electrode and the transparent pixel electrode of the present invention.
FIG. 12 is a plan structural view of slits formed in the liquid crystal alignment direction control electrode and the transparent pixel electrode of the present invention.
FIG. 13 is a plan view of a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 14 is a plan view of a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 15 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 16 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 17 is a circuit model diagram of the multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 18 is a circuit model diagram of the multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 19 is a flow chart of a 5-photomask process for manufacturing a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 20 is a flow chart of a 4-photomask process for manufacturing a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 21 is a flow chart of a 5-photomask process for manufacturing a multi-domain vertical alignment liquid crystal panel according to the present invention.
FIG. 22 is a flow chart of a 4-photomask process for manufacturing a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 23 illustrates a 5-photomask process flow for manufacturing a multi-domain vertical alignment liquid crystal panel of the present invention.
FIG. 24 is a flow chart illustrating a 4-photomask process for manufacturing a multi-domain vertical alignment liquid crystal panel according to the present invention.
FIG. 25 illustrates a 5-photomask process flow for manufacturing a multi-domain vertical alignment liquid crystal panel of the present invention.
FIG. 26 illustrates a 4-photomask process flow for manufacturing a multi-domain vertical alignment liquid crystal panel of the present invention.
FIG. 27 is a plan structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 28 is a plan structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 29 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 30 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 31 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 32 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 33 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 34 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 35 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 36 is a sectional structural view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 37 is a circuit model diagram of the multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 38 is a circuit model diagram of the multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 39 is a circuit model diagram of the multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 40 is a circuit model diagram of the multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 41 is a circuit model diagram of the multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 42 is a circuit model diagram of the multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 43 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 44 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 45 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 46 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 47 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 48 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 49 is a partial plan view of a multi-domain vertical alignment mode liquid crystal panel of the present invention.
FIG. 50 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 51 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 52 is a partial plan view of a multi-domain vertical alignment mode liquid crystal panel of the present invention.
FIG. 53 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 54 is a partial plan view of a multi-domain vertical alignment type liquid crystal panel of the present invention.
FIG. 55 is a plan view of an offset thin film transistor element for a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 56 is a sectional view of an offset thin film transistor element for a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 57 is a cross-sectional view of an offset thin film transistor element for a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 58 is a sectional view of an offset thin film transistor element for a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 59 is a sectional view of a double-gate thin film transistor element for a multi-domain vertical alignment type liquid crystal panel according to the present invention.
FIG. 60 is a sectional view of a double gate thin film transistor element for a multi-domain vertical alignment type liquid crystal panel according to the present invention.
61 shows the motion of vertically aligned negative dielectric anisotropy liquid crystal molecules by an electric field formed by a plane electrode, a slit electrode, and a liquid crystal alignment direction control electrode.
62 is a plan structural view of slits formed in the liquid crystal alignment direction control electrode and the transparent pixel electrode of the present invention. FIG.
FIG. 63 is a plan structural view of slits formed in the liquid crystal alignment direction control electrode and the transparent pixel electrode of the present invention.
FIG. 64 is a plan structural view of slits formed in the liquid crystal alignment direction control electrode and the transparent pixel electrode of the present invention.
FIG. 65 is a plan view of a multi-domain vertical alignment type liquid crystal panel according to the present invention.
[Explanation of sign]
1 ---- Color filter side glass substrate
2 ---- Black mask (light shielding film)
3 ---- Color filter layer
4 ---- Color filter side transparent conductive film (transparent common electrode)
5 ---- Bump for controlling direction of vertically aligned liquid crystal molecules
6 ---- Color filter side vertical alignment film
7 ---- Active matrix substrate side vertical alignment film
8 ---- Transparent pixel electrode
9 ---- Slit opening formed on the pixel electrode side
10 ---- Passivation film
11 ---- Video signal wiring
12 ---- Gate insulation film
13 ---- Active matrix element side glass substrate
14 ---- Negative dielectric anisotropy liquid crystal
15 ---- Liquid crystal alignment control electrode
16 ---- Thin Film Transistor Device Connected to Transparent Pixel Electrode
17 ---- Scanning line
18 ---- Common electrode on the active matrix substrate side
19 ---- Thin film transistor element connected to liquid crystal alignment control electrode
20 ---- Thin film transistor element connected to common electrode and liquid crystal alignment control electrode
21 ---- Common electrode potential
22 ---- (n-1) Row Scan Line Signal Waveform
23 ---- m-line video signal wiring signal waveform
24 ---- (m + 1) column video signal wiring waveform
25 ---- n-row scanning line signal waveform
26 ---- Contact hole for connecting the transparent pixel electrode and the drain electrode of the transistor
27 ---- Contact hole for connecting the common electrode to the source electrode of the transistor
28 ---- Contact hole for connecting the common electrode and the source electrode of the transistor
29 ---- Opening formed in transparent pixel electrode on liquid crystal alignment control electrode
30 ---- Drain electrode of thin film transistor element
31 ---- a contact hole for connecting the liquid crystal alignment control electrode and the drain electrode of the transistor
32 ---- Contact hole for connecting the liquid crystal alignment control electrode and the drain electrode of the transistor
33 ---- Rectangular opening formed in transparent pixel electrode
34 ---- Scanning line terminal
35 ---- Non-doped thin film semiconductor layer
36 ---- n ⁺ a-si layer (ohmic contact layer)
C1 ---- Capacitance formed by a transparent pixel electrode and a common electrode on the CF (color filter) substrate side
C2 ---- Capacitance formed by the transparent pixel electrode and the liquid crystal alignment direction control electrode
C3 ---- Capacitance formed by the transparent pixel electrode and the scanning line
C4 ---- capacitance formed by the intermediate electrode and the transparent pixel electrode of the double thin film transistor C5 ---- capacitance formed by the transparent pixel electrode and the common electrode
37 ---- Intermediate electrode of double thin film transistor
38 ---- Etching stopper layer
F ---- Offset amount of offset thin film transistor element
39 ---- Source electrode (connected to common electrode)
40 ---- Drain electrode (connected to liquid crystal alignment direction control electrode)
41 ---- a contact hole for connecting the liquid crystal alignment control electrode and the drain electrode of the transistor
42 ---- Contact hole for connecting the liquid crystal alignment control electrode and the drain electrode of the transistor

Claims

On a substrate, run査線and the video signal lines, a thin film transistor element formed at each intersection of the scanning lines and the video signal wiring, connected to the thin film transistor element, the plurality of slits are formed An active matrix substrate having a transparent pixel electrode, a liquid crystal alignment direction control electrode formed by covering an insulating material under a slit of the transparent pixel electrode, a color filter substrate facing the active matrix substrate, and the active matrix substrate and the terms color active matrix type vertically aligned mode liquid crystal display device having a negative dielectric anisotropy liquid crystal layer interposed color filter substrate, a liquid crystal which is vertical alignment between the active matrix substrate and the color filter substrate Apply a voltage to the molecule in two different directions or four different directions To make fallen a crystal molecules, liquid crystal, characterized i below), to form the both two kinds of electrode structures in one pixel of the active matrix substrate of ii), that has a structural arrangement of the following iii) Display device.
i) a color filter substrate side of a transparent solid electrode on opposing the active matrix substrate side of the transparent pixel electrode in the narrow long slit-like pattern (the slit portion transparent electrode is not.) is formed in the lower layer of the slit portion The liquid crystal alignment direction control electrode is not formed.
ii) the color filter substrate side of the transparent fine long slit-like pattern in the transparent pixel electrode of the active matrix substrate side facing the solid electrode is formed, substantially the same as the shape of the slit through the lower layer insulating film of the slit A liquid crystal alignment direction control electrode having a shape that is larger than the slit is formed.
iii) In pixels of n rows and m columns, a thin film transistor element is formed at a position where a scanning line of (n-1) rows and a video signal wiring of (m + 1) columns are mixed, and a video signal wiring of (m + 1) columns, n A liquid crystal alignment direction control electrode used for pixels in rows and m columns is connected through the thin film transistor element, and the thin film transistor element is formed at a position where the scanning line of n rows and the video signal wiring of m columns are mixed, The video signal wiring of m columns and the transparent pixel electrode used for the pixel of n rows and m columns are connected through this thin film transistor element.

On a substrate, run査線and the video signal lines, the thin film transistor element formed at each intersection of the scanning lines and the video signal lines, transparent plurality of slits that are connected to the thin film transistor element is formed An active matrix substrate having a pixel electrode, a liquid crystal alignment direction control electrode formed by covering an insulating material under a slit of the transparent pixel electrode, a color filter substrate facing the active matrix substrate, and the active matrix substrate When the front Symbol respect color active matrix type vertically aligned mode liquid crystal display device having a negative dielectric anisotropy liquid crystal layer interposed color filter substrate, liquid crystal molecules are vertical aligned between the active matrix substrate and the color filter substrate A voltage is applied to the liquid crystal in two different directions or four different directions. To make fallen child, a liquid crystal display which i below), with both of the two electrode structures ii) forming in one pixel of the active matrix substrate, characterized by having a structure arranged below iii) apparatus.
i) a color filter substrate side of the transparent solid electrodes on opposing the active matrix substrate side of the transparent pixel electrode in the narrow long slit-like pattern (the slit portion transparent electrode is not.) is formed, the lower layer of the slit portion The liquid crystal alignment direction control electrode is not formed.
ii) color filter substrate side of the transparent active matrix substrate side of the transparent pixel electrode in the narrow long slit-like patterns facing the solid electrodes are formed, substantially the shape of the slit through the lower layer insulating film of the slit A liquid crystal alignment direction control electrode having the same shape and being larger than the slit is formed.
iii) In a pixel of n rows and m columns, a thin film transistor element is formed on a scanning line of (n−1) rows, and n rows of common electrodes and liquid crystal alignment direction control electrodes used for the pixels of n rows and m columns are A thin film transistor element is formed at a position where the n rows of scanning lines and the m columns of video signal wirings are connected to each other through the thin film transistor elements, and the m rows of video signal wirings and the n rows and m columns of pixels are formed. A transparent pixel electrode to be used is connected through the thin film transistor.

On a substrate, run査線and the video signal lines, a thin film transistor element formed at each intersection of the scanning lines and the video signal wiring, a circular or a plurality of holes of polygonal connected to the thin film transistor element, An active matrix substrate having a transparent pixel electrode formed with a plurality of elongated slits, a liquid crystal alignment direction control electrode formed by interposing an insulating film under the slit of the transparent pixel electrode, and facing the active matrix substrate a color filter substrate and the active matrix substrate and the color filter color substrate ing from a negative dielectric anisotropy liquid crystal layer interposed active matrix type vertically aligned mode liquid crystal display device, active matrix substrate and a color filter which a voltage to the liquid crystal molecules are vertical aligned between the substrates is applied, multiway To make fallen liquid crystal molecules, i below), both of the two electrode structures and forming in one pixel of the active matrix substrate of ii), characterized by having a structural arrangement described below iii) Liquid crystal display device.
i) a color filter substrate circle shaped transparent pixel electrode of the active matrix substrate side facing the transparent solid electrode side or polygonal holes (non transparent electrodes in a portion of the hole) is formed, in the lower layer of the hole The liquid crystal alignment direction control electrode is not formed.
ii) narrow long slit-like pattern in the transparent pixel electrode of the active matrix substrate side facing the color filter substrate side of the transparent solid electrodes are formed, the lower layer of the slit via an insulating film, and the shape of the slit A liquid crystal alignment direction control electrode having substantially the same shape and an oversize than the slit is formed .
iii) In pixels of n rows and m columns, a thin film transistor element is formed at a position where a scanning line of (n-1) rows and a video signal wiring of (m + 1) columns are mixed, and a video signal wiring of (m + 1) columns, n A liquid crystal alignment direction control electrode used for pixels in rows and m columns is connected through the thin film transistor element, and the thin film transistor element is formed at a position where the scanning line of n rows and the video signal wiring of m columns are mixed, The video signal wiring of m columns and the transparent pixel electrode used for the pixel of n rows and m columns are connected through this thin film transistor element.

On a substrate, running査線and the video signal lines, a thin film transistor element formed at each intersection of the scanning lines and the video signal wiring, connected to said thin film transistor element, a plurality of holes of circular or polygonal and the transparent pixel electrode thin long slits are formed, an active matrix substrate having a liquid crystal alignment direction control electrode in a lower layer of the slit of the transparent pixel electrode is formed via an insulating film, the active matrix substrate A color active matrix vertical alignment type liquid crystal display device comprising an opposing color filter substrate, the active matrix substrate and a negative dielectric constant anisotropic liquid crystal layer sandwiched between the active matrix substrate and the color filter substrate. a voltage to the liquid crystal molecules are vertical aligned between the substrates is applied, multiway To make fallen liquid crystal molecules, i below), both of the two electrode structures and forming in one pixel of the active matrix substrate of ii), characterized by having a structural arrangement described below iii) Liquid crystal display device.
i) color filter on the substrate side a transparent solid electrodes opposing the active matrix substrate side circular or polygonal holes (hole portions in the transparent pixel electrode to the non transparent electrode) is a number form, of the hole The liquid crystal alignment direction control electrode is not formed in the lower layer.
ii) the color filter substrate side of the transparent active matrix substrate side of the transparent pixel electrode in the narrow long slit-like patterns facing the solid electrodes are formed, substantially the shape of the slit through the lower layer insulating film of the slit A liquid crystal alignment direction control electrode having the same shape and being larger than the slit is formed .
iii) In a pixel of n rows and m columns, a thin film transistor element is formed on a scanning line of (n−1) rows, and n rows of common electrodes and liquid crystal alignment direction control electrodes used for the pixels of n rows and m columns are A thin film transistor is formed at a position where the n rows of scanning lines and the m columns of video signal wirings are connected through the thin film transistor elements, and is used for the m columns of video signal wirings and the n rows and m columns of pixels. A transparent pixel electrode is connected through the thin film transistor element.

5. The scanning line address signal waveform according to claim 1 , wherein the time width of the scanning line address signal waveform is at least twice the horizontal period, and the (n-1) th scanning line address signal waveform, The polarity of the address signal waveform of the first scanning line is more than 1 times the horizontal period, and the polarity of the video signal voltage of the m-th column video signal wiring and the video signal wiring of the (m + 1) -th column video signal wiring is They are different from each other, and a liquid crystal display device using the driving dynamic way to characterized in that the interchange is polarity for each horizontal period, and each of the polarities every vertical period is inverted.

According to claim 1 or 3, a video signal wiring of scan lines and m columns of n rows are formed in intersecting position than the channel length of the thin film transistor element connected to the transparent pixel electrode (L1), (n-1 ) The channel length (L2) of the thin film transistor element formed at the position where the scanning line in the row and the video signal wiring in the (m + 1) column are mixed and connected to the liquid crystal alignment direction control electrode is larger (L1 <L2). A liquid crystal display device.

According to claim 2 or 4, the video signal wiring of scan lines and m columns of n rows are formed in intersecting position than the channel length of the thin film transistor element connected to the transparent pixel electrode (L1), (n-1 ) A liquid crystal display device characterized in that a channel length (L2) of a thin film transistor element formed on a scanning line in a row and connected to a liquid crystal alignment direction control electrode is larger (L1 <L2).

Characterized in any one of claims 1, 2, 3, 4, the liquid crystal alignment direction control electrode coupled to have a thin film transistor element in a double transistor element structure, or may that using the offset channel element structure A liquid crystal display device.

3. The slit according to claim 1 or 2, which is formed on a transparent pixel electrode on the active matrix substrate side and has no liquid crystal alignment direction control electrode in a lower layer, and a slit paired with a liquid crystal alignment direction control electrode formed in a lower layer. A liquid crystal display device, wherein the liquid crystal display devices are alternately arranged in a direction of an angle of about ± 45 degrees with respect to the direction in which the scanning lines extend while maintaining a substantially parallel relationship with each other.

According to claim 1 or 2, the active matrix substrate side is formed on the transparent pixel electrode elongated extended slit no liquid crystal alignment direction control electrode in a lower layer is, the direction substantially parallel to Biteiru direction of the scanning lines, a direction orthogonal disposed, or one lower layer has a liquid crystal alignment direction control electrode and the set formed slits, and wherein the structure is arranged in the direction of the angle of approximately ± 45 degrees with respect to the scanning signal line direction Liquid crystal display device.

According to claim 1 or 2, the active matrix substrate side is formed on the transparent pixel electrode slits extending elongated no liquid crystal alignment direction control electrode in a lower layer is positioned at an angle of approximately ± 45 degrees with respect to a direction extending scan line And slits that are paired with the liquid crystal alignment direction control electrode formed in the lower layer are arranged in a direction substantially parallel to the direction in which the scanning line extends and in a direction orthogonal thereto, and A liquid crystal display device characterized in that a liquid crystal alignment direction control electrode surrounds an outer peripheral portion through an insulating film while being surrounded by a transparent pixel electrode.

5. The scanning line according to claim 3 or 4, wherein the slit paired with the liquid crystal alignment direction control electrode so as to surround a plurality of circular or polygonal holes formed in the transparent pixel electrode on the active matrix substrate side extends the scanning line. The liquid crystal alignment direction control electrode is disposed in a direction perpendicular to the direction parallel to the direction and the liquid crystal alignment direction control electrode surrounds the transparent pixel electrode and the insulating film while surrounding the transparent pixel electrode. A characteristic liquid crystal display device .

According to any one of claims 1, 2, 3, 4, it is lower in the liquid crystal alignment direction control electrode formed via an insulator slit of transparency pixel electrodes are formed in the same layer at the same time as the scanning lines formed A liquid crystal display device .

The liquid crystal display according to claim 1 or 2, the lower liquid crystal alignment direction control electrode formed via an insulator slit of the transparent pixel electrode is characterized in that it is formed in the same layer at the same time as the video signal lines formed Equipment .

2. The drain electrode of a thin film transistor element according to claim 1, wherein two thin film transistor elements are required in one pixel in order to drive one pixel, and n rows of scanning lines and m columns of video signal wirings are formed. A liquid crystal display device having only one contact hole for electrically connecting the transparent pixel electrode and the transparent pixel electrode .

Te claim 1 or 3 smell, and requires two thin film transistor elements in one pixel in order to drive the one pixel, and (n-1) row scanning line and (m + 1) video signal wiring of column intersect position There are two contact holes for electrically connecting the drain electrode of the thin film transistor element and the liquid crystal alignment direction control electrode, and n rows of scanning lines and m columns of video signal wirings are located at positions. A liquid crystal display device comprising a single contact hole for electrically connecting a drain electrode of a thin film transistor element and a transparent pixel electrode .

5. The method according to claim 1, wherein two thin film transistor elements are required in one pixel to drive one pixel, and one thin film transistor is connected to the transparent pixel electrode. , the remaining one of the thin film transistor is connected to the liquid crystal alignment direction control electrode, and said and said transparent pixel electrode liquid crystal alignment direction control electrode are overlapped by writing the insulating film, and characterized in that the formation of the capacitor Liquid crystal display device .

5. The intermediate electrode of the thin film transistor element having a double transistor structure connected to the liquid crystal alignment direction control electrode and the transparent pixel electrode in any one of claims 1, 2 , 3 , and 4 with an insulating film interposed therebetween. A liquid crystal display device characterized in that a capacitor is formed .

According to claim 1 or 3, a liquid crystal display, characterized in that the transparent pixel electrode of n rows and m columns and (n-1) row scanning line forms a storage capacitor overlap with an insulating film Equipment .

According to claim 2 or 4, the liquid crystal display device, characterized in that the common electrode of the transparent pixel electrode and the n lines of n rows and m columns form a storage capacitor overlap with an insulating film.

Any one smell of claims 1, 2, 3, 4 Te, characterized by being formed in the same layer a thin film transistor element part and the video signal wiring and the liquid crystal alignment direction control electrodes at the same time using the Halftone exposure technique Liquid crystal display device .