JP4372694B2 - mixer - Google Patents

Description

  The present invention relates to a charge sub-sampling mixer, and more particularly to a charge sub-sampling mixer that realizes a filtering characteristic for attenuating folded interference waves.

  In a conventional charge sampling circuit, it is possible to realize bandpass FIR filter characteristics by controlling whether or not to integrate a current proportional to an input signal (see, for example, Non-Patent Document 1). The charge sampling circuit introduced in Non-Patent Document 1 converts an input voltage into a current, accumulates the generated current as a charge in an integrator composed of a capacitor and an amplifier, and controls the accumulation period with a switch. . Filtering processing can be performed according to the switching pattern. If the signal is sampled as it is at a frequency lower than the Nyquist low frequency, the noise returns to the baseband and the S / N ratio deteriorates. However, in Non-Patent Document 1, the input signal is sampled at a frequency higher than the Nyquist frequency, and the bandpass After performing the filtering process, a low frequency output is generated by downsampling (decimation). In this case, the frequency of the signal for controlling the input switch is set to four times the frequency of the input signal. The output signal has a low frequency.

  Non-Patent Document 1 introduces a Nyquist sampling method for a signal down-converted to a frequency (IF) lower than an RF frequency (carrier frequency). Before this circuit, in order to down-convert from RF to IF, a conventional Gilbert mixer is required.

  According to the method of Non-Patent Document 1, the attenuation amount of the interference wave turned back by downsampling is 18 dB. If the tuner is to be used, a steep band pass filter (BPF) is required at the input in order to drop the interference wave.

  However, since the charge sampling circuit of Non-Patent Document 1 has a sampling frequency that is four times the carrier frequency, it is difficult to apply to the latest communication standard with a high carrier frequency. As a solution to the above problem, a sub-sampling circuit already exists. In subsampling, sampling is performed at a frequency smaller than twice the carrier frequency. However, the sampling frequency should be higher than twice the maximum frequency of the baseband signal that is modulating the carrier.

  An example of a conventional charge subsampling mixer is shown in FIG. 21 (see, for example, Non-Patent Document 2). The charge subsampling mixer 100 in FIG. 21 has a transconductance stage as a current source that generates a current proportional to a voltage value of an input signal of a radio frequency (RF: Radio Frequency, hereinafter referred to as RF) input to an input terminal IN. (Hereinafter referred to as “gm stage”) 101, an input switch 102, two paths path_a and path_b for performing signal processing, and an output capacitor 111. The path path_a includes a switch 103 that activates the path, an integration capacitor 107, a reset switch 105 that deletes charges accumulated in the integration capacitor 107, and a voltage proportional to the charges accumulated in the integration capacitor 107 at the output terminal OUT. And an output switch 109 to be applied. The path path_b includes a switch 104 that activates the path, an integration capacitor 108, a reset switch 106 that deletes the charge accumulated in the integration capacitor 108, and a voltage proportional to the charge accumulated in the integration capacitor 108 at the output terminal OUT. And an output switch 109 to be applied.

  FIG. 22 shows waveforms of signals from a control circuit (not shown) that controls each switch of the charge sub-sampling mixer 100. When the waveform level shown in this figure is 1, the controlled switch is turned on, and when the waveform level is 0, the controlled switch is turned off. The signal LO for controlling the input switch 102 is a pulse wave having the same frequency as the carrier frequency of the RF input signal and a duty of 50%. This frequency is set as the basic sampling frequency Fs of this system. The fundamental period for this frequency is called Ts and is given by the following equation.

  The signal enable_a that controls the switch 103 that activates the path path_a and the signal enable_b that controls the switch 104 that activates the path path_b are each a rectangular wave having a frequency Fs / N (N is an integer greater than 1) that becomes 1 in a certain period. In addition, since the phase difference between the signal enable_a and the signal enable_b is set to 180 °, the signal enable_b is turned off when the signal enable_a is on. The signal out_a (out_b) for controlling the output switch 109 becomes 1 when the signal enable_a (enable_b) of the path path_a (path_b) becomes 0, and the period for securing the state is N / 2 × Ts (= 0.5). × N / Fs). The signal reset_a for controlling the reset switch 105 becomes 1 when the signal out_a (out_b) of the path path_a becomes 0, and the period for securing the state is N / 2 × Ts (= 0.5 × N / Fs). To do. The signal out_b for controlling the output switch 110 becomes 1 when the signal enable_b of the path path_b becomes 0, and the period for securing the state is N / 2 × Ts (= 0.5 × N / Fs). The signal reset_b for controlling the reset switch 106 becomes 1 when the signal out_b of the path path_b becomes 0, and the period for securing the state is N / 2 × Ts (= 0.5 × N / Fs).

  The principle of operation of the charge subsampling mixer 100 will be described with reference to FIG. When the signal enable_a is 1, when the signal LO becomes 1, a current flows from the gm stage 101 to the integration capacitor 107, and the charge Qi of the integration capacitor 107 changes. The charge accumulated in the integrating capacitor 107 between time k × Ts and time (k + 1/2) × Ts is expressed by the following equation.

Here, i (t) represents the output current of the gm stage 101, and γ (t) is the basic waveform of the signal LO as shown in FIG.

  The above equation is the correlation between i (t) and γ (t) and is given by the following equation.

When the above equation is Fourier transformed, the following equation is obtained.

Here, Ic (f) and Γ (f) are Fourier transforms of i (t) and γ (t), respectively. In this equation, z is given by the following equation.

  Note that Γ (f) is expressed by the following equation.

  Hereinafter, a sinus cardinal (hereinafter referred to as sinc) function is defined by the following equation.

  Using the sinc function, Γ (f) is given by

  From the above equation, the Fourier transform of the electric charge accumulated while LO becomes level 1 once can be calculated from the following equation.

  When the signal enable_a is 1, the charge of the integration capacitor 107 is accumulated N times. When the signal out_a becomes 1, the total charge stored in the integration capacitor 107 is output. Further, when the signal enable_b is 1, the charge of the integration capacitor 108 is accumulated N times, and when the signal out_b becomes 1, the total charge stored in the integration capacitor 108 is output. In the example of the waveform shown in FIG. 22 (or FIG. 23), N = 5 is set. Note that the accumulated charge is deleted by setting the reset signals reset_a · reset_b to 1 after the voltage is output from the integrating capacitors 107 and 108. By resetting, integration is started from 0 each time, and the electric charge accumulated in the capacitors 107 and 108 is expressed by the following equation.

This is illustrated in FIG. From the above equation, the Fourier transform of the output charge can be written as:

It can be seen that the above equation shows the characteristics (transfer function) of an FIR (Finite Impulse Response) filter. That is, FIR = (1 + z ⁻¹ + z ⁻² + z ⁻³ + z ⁻⁴ ). As described above, the FIR filter is realized by the integration processing of the charges forming the current output from the gm stage 1010, and unnecessary signals can be removed by the FIR filter.

When the capacitance of the integrating capacitor is written as Ci, the output voltage V _out (f) is

The relationship between the current Ic and the input voltage V _in (f) is expressed by the following equation.

Here, gm is the transconductance of the gm stage 101.

Further, when the charge accumulated in the integrating capacitors 107 and 108 is transmitted to the output capacitor 111, charge sharing occurs, and therefore the output voltage V _o (f) of the output capacitor 111 is expressed by the following equation.

Here, Co is the capacitance of the output capacitor 111. The transfer function as described above is a characteristic of an IIR (Infinite Impulse Response) filter.

  From the above equation, the frequency characteristic of the output voltage Vo (f) is expressed by the following equation.

  Gain is

Because it is not influenced by the factor However, the phase is affected.

Since the frequency of the zero point of the FIR filter is the same as the frequency of folding, the folding noise can be reduced. The effect will be described with reference to FIG. The horizontal axis of all graphs shown in FIG. 25 indicates frequency, and the vertical axis other than that in FIG. 25C indicates signal power. The vertical axis of FIG. 25C shows the FIR gain normalized by the maximum FIR gain. FIG. 25A shows a signal spectrum at the input terminal of the gm stage 101. In the signal spectrum, a desired signal having a carrier frequency Fs and noise are shown. By integrating the charges in the capacitors 107 and 108 and sampling at the sampling frequency Fs, as shown in FIG. 25B, a discrete time signal is generated in a band N times lower than the sampling frequency Fs, and the desired signal is turned back to DC. At the same time, all noises are folded back to a band of 0 to Fs. FIG. 25C shows the characteristics of the FIR filter realized by charge integration and resetting by the capacitors 107 and 108. FIG. 25 (d) shows a spectrum after the signal spectrum represented in FIG. 25 (b) is subjected to the filtering process by the FIR filter. Noise is attenuated at frequencies such as Fs / N and 2Fs / N. FIG. 25E shows an output spectrum after the signal spectrum shown in FIG. 25D is downsampled (signal spectrum at the output terminal OUT of the charge sampling mixer 100). The noise is folded back in the 0 to Fs / N band, but not in the signal band. The baseband signal can be demodulated from FIG.
A 50-MHz CMOS Quadrature Charge Sampling Circuit With 66-dB SFDR, S. Karvonen et al., IEEE International Symposium Circuits and Systems 2004, May 2004, Paper 11.5 A Discrete-Time Bluetooth Receiver in a 0.13μm Digital CMOS Process, K. Muhammad et al., 2004 IEEE International Solid-State Circuits Conference, February 2004, Paper 15.1

  However, the above description is for the case where the desired signal is a narrow band and there is no interfering signal. If the desired signal is a wide-band signal (regardless of analog broadcast or digital broadcast) like a television reception wave, the noise attenuation amount becomes small at the edge of the band, and the noise is folded back to the desired signal band. In addition, the interference signal turns back and becomes higher than the desired signal. The effect will be described with reference to FIG.

  26A to 26E correspond to FIGS. 25A to 25E. However, FIG. 26A assumes the presence of a disturbing signal in addition to the desired signal. In FIG. 26 (b), the interference signal is folded back in the same manner as the noise in FIG. 25, and in FIG. 26 (d), the interference signal folded back by the FIR filter is attenuated. However, when the band of the desired signal is wide, the attenuation of the interference signal at the edge of the folded signal band becomes insufficient, and the folded interference signal still has high power as shown in FIG. Therefore, it is difficult to obtain only the baseband signal from FIG. In order to further reduce interference signal aliasing, a steep filter is required at the input of the sub-sampling mixer.

  If the order of FIR is increased, there is a possibility that the interference signal can be attenuated. However, in order to increase the order of FIR, it is necessary to increase the downsampling factor N. Then, the output band Fs / N is narrowed. Since the bandwidth needs to be twice as wide as the bandwidth of the desired signal, there is a limit to increasing N. Further, when N is increased, the order of IIR due to charge distribution increases, and the gain differs within the band.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a charge sub-sampling circuit that can easily obtain a baseband signal from a wideband signal without being affected by noise and interference signals. It is to realize a mixer provided with.

In order to solve the above problems, the mixer of the present invention is a mixer that demodulates the baseband signal from the input signal using a signal obtained by modulating a carrier with a baseband signal, and demodulating the baseband signal. a current source for generating a current proportional to the voltage, a charge Sabusanpu-ring circuit which receives the current generated by said current source, a control for generating a signal for controlling the sampling of the current by the charge Sabusanpu-ring circuit The charge sub-sampling circuit generates a discrete-time signal in a band lower than N times the carrier frequency (N is an integer greater than 1) from the input signal under the control of the sampling by the control circuit. Along with the generation of the discrete-time signal, the FIR filter realized by the integration process of the charge forming the current In a mixer performing Taringu process, the charge Sabusanpu-ring circuit, under control of said control circuit, and a circuit for performing the sampling at a sampling frequency equal to the frequency of the carrier, of the integration process of accumulating the charge A circuit for outputting the accumulated charge to the outside of the charge sub-sampling circuit, and a reset process for removing the charge accumulated in the charge sub-sampling circuit In the integration process, each term of the transfer function of the FIR filter is weighted by a weight selected from a plurality of weights. The selection of the weight is a signal that controls the integration process. It is characterized in that it selects a pattern of series of 0 and 0 .

  According to the invention described above, by weighting each term of the transfer function of the FIR filter, the gain characteristic of the FIR filter can be greatly attenuated by the entire disturbing signal.

  As a result, it is possible to realize a mixer including a charge sub-sampling circuit that can easily obtain a baseband signal from a wideband signal without being affected by noise and interference signals.

  In addition, since the FIR filter can greatly attenuate the entire folded interference signal, the amount of attenuation to be secured by the bandpass filter before input to the charge sub-sampling mixer can be suppressed. By using a pass filter, the power consumption and the circuit area can be reduced.

  In the mixer of the present invention, in order to solve the above-described problem, the current source has outputs of the current corresponding to the number of the charge sub-sampling circuits with respect to one input signal, and each of the outputs is different from each other. The charge sub-sampling circuit is connected to the input.

  According to the above invention, the current source can input an appropriate current corresponding to the input signal to each charge sub-sampling circuit regardless of the number of charge sub-sampling circuits. Play.

  In order to solve the above problems, the mixer according to the present invention is characterized in that the current source generates the current by a transconductance stage provided for each output.

  According to the above invention, each transconductance stage only needs to input a current to one charge sub-sampling circuit, so that the output capacitance can be reduced.

  In order to solve the above problems, the mixer according to the present invention is characterized in that the current source generates the current by one transconductance stage provided in common to the outputs.

  According to the above invention, since only one transconductance stage is used, the circuit scale can be reduced and the path matching can be improved.

In order to solve the above problem, the mixer according to the present invention includes a positive output path and a negative output path, which are connected to the output of the current source. Are connected in series from the input side to the output side in sequence from the A1 switch, the A2 switch, the A4 switch, between the A2 switch and the A4 switch, and the location of the first reference voltage. A5 switch, A6 switch, and A8 switch connected in series from the input side to the output side in order from the input side to the output side And an A7 switch and a second capacitor connected between the A6 switch and the A8 switch and between the second reference voltage and the carrier frequency = the support. The pulling frequency = Fs, the number of the charge sub-sampling circuits is m, and the A1 switch is ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the A5 switch is in phase with the first rectangular signal. ON / OFF is controlled by a second rectangular signal different by 180 °, the A2 switch and the A6 switch are ON / OFF controlled by a first A1 digital signal having a cycle of N × m / Fs, and the A4 switch and The A8 switch is ON / OFF controlled by an A2 digital signal having a cycle of N × m / Fs, and the A3 switch and the A7 switch are ON / OFF by an A3 digital signal having a cycle of N × m / Fs. OFF is controlled, and periods T1, T2, and T3 in which the total is the period are provided in order during one period of the A1 to A3 digital signals, and the period T While the A1 digital signal is a series of 1 and 0 during 1, the A2 digital signal and the A3 digital signal are 0, and during the period T2, the A2 digital signal is 1 while the, the first A1 digital signal and the first A3 digital signal becomes zero, during the period T3, while the first A3 digital signal is 1, the first A1 digital signal and the second a 2 digital signal It is characterized by zero.

  According to the above-described invention, there is an effect that it is possible to easily realize a charge sub-sampling mixer having FIR filter characteristics that greatly attenuates the entire disturbing interference signal.

  In the mixer of the present invention, in order to solve the above-mentioned problem, the charge sub-sampling circuit includes a B1 switch, and is connected to the output of the current source via the B1 switch. And a -side path connected to the output of the current source via the B2 switch, and the + side path is a + output terminal of the B1 switch and the differential output A first + side path and a second + side path provided in parallel with each other, and the-side path is provided in parallel between the B2 switch and the-output terminal of the differential output. A first-side path and a second-side path, wherein the first + side path includes a B3 switch, a B5 switch, and a B3 switch connected in series in order from the input side to the output side. Between the B5 switch and the first reference A B4 switch and a first capacitor connected to each other between the pressure points, and the second + side path is connected in series from the input side to the output side in order from the B6 switch and the B8th switch. A switch, a B7 switch and a second capacitor connected between the B6 switch and the B8 switch and between the second reference voltage and the first-side path, The B9 switch and the B11 switch connected in series from the input side to the output side, the connection between the B9 switch and the B11 switch, and the location of the third reference voltage, respectively. The second side path includes a B12 switch and a B14 switch connected in series from the input side to the output side, and the B1 switch. A B13 switch and a fourth capacitor connected between the switch and the B14 switch and a fourth reference voltage, respectively, the carrier frequency = the sampling frequency = Fs, and the charge The number of sub-sampling circuits is m, and the B1 switch is ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the B2 switch is a second rectangular signal that is 180 ° out of phase with the first rectangular signal. ON / OFF is controlled, and the B3 switch and the B9 switch are ON / OFF controlled by a B1 digital signal having a cycle of N × m / Fs, and the B6 switch and the B12 switch have a cycle. ON / OFF is controlled by the B2 digital signal of N × m / Fs, the B5 switch, the B8 switch, the B11 switch, and the front The B14 switch is ON / OFF controlled by a B3 digital signal having a cycle of N × m / Fs, and the B4 switch, the B7 switch, the B10 switch, and the B13 switch have a cycle of N × m / F. ON / OFF is controlled by the B4 digital signal of Fs, and periods T1, T2, and T3 in which the total is the period are sequentially provided during one period of the B1 to B4 digital signals. In the meantime, the B1 digital signal and the B2 digital signal are in a series of 1 and 0, and the B1 digital signal and the B2 digital signal are not 1 at the same time, while the B3 digital signal and the B2 digital signal are The B4 digital signal becomes 0 and the B3 digital signal becomes 1 during the period T2, while the B1 digital signal and the B2 digital signal And the B4 digital signal becomes 0 and the B4 digital signal becomes 1 during the period T3, while the B1 digital signal, the B2 digital signal, and the B3 digital signal become 0. It is characterized by becoming.

  According to the above-described invention, there is an effect that it is possible to easily realize a charge sub-sampling mixer having FIR filter characteristics that greatly attenuates the entire disturbing interference signal.

  Further, since the number of capacitors that perform integration processing, such as the B1 to B4 capacitors, increases, the size of the weight that can be realized by the FIR filter, that is, the value of the coefficient of each term in the transfer function can be increased. The effect that it is.

In the mixer of the present invention, in order to solve the above-described problem, the charge sub-sampling circuit includes a C1 switch, a C2 switch, and a first + side path connected to the output of the current source through the C1 switch. And a second side path, a first side path and a second side path connected to the output of the current source via the second C2 switch, and the first side path includes the first C1 switch and the second side path. between the + output terminal of the differential output, which is connected in series in this order toward the input side to the output side, and a second C3 switch and the C5 switch, between the first C5 switch and the second C3 switch And a first reference voltage, and a first capacitor is connected between the first reference voltage and the first reference voltage, and the first-side path includes the C2 switch and a negative output terminal of the differential output. Between the input side A C6 switch and a C8 switch are connected in series in order toward the output side, and are connected between the C6 switch and the C8 switch and between the second reference voltage and the second reference voltage, respectively. The second + side path includes a C7 switch and a second capacitor, and the second + side path is connected in series in order from the input side to the output side between the C2 switch and the + output terminal. A C10 switch and a C5 switch; and a C4 switch and a first capacitor. The second side path is between the C1 switch and the -output terminal from the input side. The C9 switch and the C8 switch connected in series in order toward the output side, the C7 switch and the second capacitor, and the carrier frequency = The sampling frequency is Fs, the number of the charge sub-sampling circuits is m, and the C1 switch is ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the C2 switch is in phase with the first rectangular signal. ON / OFF is controlled by a second rectangular signal with a difference of 180 °, and the C3 switch and the C6 switch are ON / OFF controlled by a C1 digital signal having a cycle of N × m / Fs, and the C9 switch The C10 switch is ON / OFF controlled by a C2 digital signal having a cycle of N × m / Fs, and the C5 switch and the C8 switch are ON / OFF by a C3 digital signal having a cycle of N × m / Fs. OFF is controlled, and the C4 and C7 switches are ON / OFF controlled by a C4 digital signal having a cycle of N × m / Fs. A period T1, T2, and T3 in which the total is the period are provided in order during one period of the C4th digital signal, and the C1 digital signal and the C2 digital signal are 1 during the period T1. The C1 digital signal and the C2 digital signal are not simultaneously 1 and the C3 digital signal and the C4 digital signal are 0 at the same time, and during the period T2, the C1 digital signal and the C2 digital signal are not simultaneously 1. While the C3 digital signal becomes 1, the C1 digital signal, the C2 digital signal, and the C4 digital signal become 0, and the C4 digital signal becomes 1 during the period T3, The C1 digital signal, the C2 digital signal, and the C3 digital signal are 0.

  According to the above-described invention, there is an effect that it is possible to easily realize a charge sub-sampling mixer having FIR filter characteristics that greatly attenuates the entire disturbing interference signal.

  Further, since the weight of the FIR filter can be made ternary, the number of types of coefficients in each term in the transfer function of the FIR filter is increased, and it is easy to realize an appropriate FIR filter for an application.

  In order to solve the above problem, the mixer according to the present invention includes a positive output path and a negative output path, which are connected to the output of the current source. Are connected in series in order from the input side to the output side, the D1 switch, the D2 switch, the D4 switch, between the D2 switch and the D4 switch, and the location of the first reference voltage A D3 switch, a D6 switch, and a D8 switch, each having a D3 switch and a first capacitor connected in series, wherein the -side path is connected in series from the input side to the output side. And a D7 switch and a second capacitor connected respectively between the D6 switch and the D8 switch and a second reference voltage location, wherein the carrier frequency = the support. The pulling frequency = Fs, the number of the charge sub-sampling circuits is m, and the D1 switch is ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the D5 switch is in phase with the first rectangular signal. ON / OFF is controlled by a second rectangular signal different by 180 °, the D2 switch is ON / OFF controlled by a D1 digital signal having a cycle of N × m / Fs, and the D6 switch has a cycle of N × m. ON / OFF is controlled by the D2 digital signal of / Fs, and the D4 switch and D8 switch are ON / OFF controlled by the D3 digital signal having a cycle of N × m / Fs. The D7 switch is ON / OFF controlled by a D4 digital signal having a cycle of N × m / Fs, and a total of one cycle of the D1 to D4 digital signals is the cycle. Periods T1, T2, and T3 are sequentially provided, and during the period T1, the D1 digital signal and the D2 digital signal are in a series of 1 and 0, while the D3 digital signal and the The D4 digital signal becomes 0, and the D3 digital signal becomes 1 during the period T2, while the D1 digital signal, the D2 digital signal, and the D4 digital signal become 0, and the period T3 During this period, the D4 digital signal becomes 1, while the D1 digital signal, the D2 digital signal, and the D3 digital signal become 0.

  According to the above-described invention, there is an effect that it is possible to easily realize a charge sub-sampling mixer having FIR filter characteristics that greatly attenuates the entire disturbing interference signal.

  In addition, by increasing the minimum period of the D1 digital signal and the D2 digital signal, the ratio between the minimum period of the signal and the rising period and falling period of the signal is increased, so that the D1 capacitor and the D2 capacitor, There is an effect that the charge error to the capacitor for performing the integration process is reduced, and the charge sub-sampling circuit can be easily realized.

  In order to solve the above problem, the mixer according to the present invention includes a positive output path and a negative output path, which are connected to the output of the current source. Are respectively connected in series from the input side to the output side, between the E1 switch and the E3 switch, between the E1 switch and the E3 switch, and between the first reference voltage and the first reference voltage. The -side path includes an E4 switch, an E6 switch, and an E4 switch connected in series in order from the input side to the output side. An E5 switch and a second capacitor respectively connected between the E6 switch and the second reference voltage; the carrier frequency = the sampling frequency = Fs, and the charge The number of bus sampling circuits is m, and the E1 switch is ON / OFF controlled by an E1 digital signal with a cycle of N × m / Fs, and the E4 switch is an E2 digital with a cycle of N × m / Fs. ON / OFF is controlled by a signal, the E3 switch and the E6 switch are ON / OFF controlled by an E3 digital signal with a cycle of N × m / Fs, and the E2 switch and the E5 switch have a cycle of N The ON / OFF is controlled by the E4 digital signal of xm / Fs, and the periods T1, T2, and T3 in which the total is the cycle are sequentially provided during one cycle of the E1 to E4 digital signals, During the period T1, the E1 digital signal and the E2 digital signal become a series of 1 and 0, and the E1 digital signal and the E2 digital signal are simultaneously 1 On the other hand, the E3 digital signal and the E4 digital signal are 0, and the E3 digital signal is 1 during the period T2, while the E1 digital signal, the E2 digital signal, and The E4 digital signal is 0, and the E4 digital signal is 1 during the period T3, while the E1 digital signal, the E2 digital signal, and the E3 digital signal are 0. It is characterized by.

  According to the above-described invention, there is an effect that it is possible to easily realize a charge sub-sampling mixer having FIR filter characteristics that greatly attenuates the entire disturbing interference signal.

  Further, since the switches connecting the charge sub-sampling circuit to the output of the current source are only the E1 switch and the E4 switch, the number of switches is reduced, the parasitic capacitance and resistance of the switch are reduced, and the circuit area is reduced. There is an effect that can be done.

  In order to solve the above problems, the mixer of the present invention is characterized in that T1 = N × (m−1) / Fs, T2 = 0.5 × N / Fs, and T3 = 0.5 × N / Fs. It is said.

  According to the above invention, the control circuit can be easily realized at the above timing. Further, at the above timing, the period for transmitting the accumulated charge to the output and the period for deleting the accumulated charge are sufficiently long, and it is possible to reduce the output switch and the reset switch. .

  In order to solve the above problems, the mixer of the present invention is characterized in that the first capacitor and the second capacitor have the same capacitance. If the capacitances of the first capacitor and the second capacitor are the same, the characteristics of each path of the charge sub-sampling circuit are the same, and there is an effect that mismatch is reduced when realized.

  In the mixer of the present invention, the first capacitor and the third capacitor have the same capacitance, the second capacitor and the fourth capacitor have the same capacitance, and the first capacitor The third capacitor and the second capacitor and the fourth capacitor have different capacities.

According to the above invention, since the weight of the FIR filter can be made ternary, the types of coefficients of the terms in the transfer function of the FIR filter are increased, and it is easy to realize an appropriate FIR filter for the application. Play. According to another aspect of the mixer of the present invention, the charge sub-sampling circuit includes the F1 switch, the F2 switch, the F9 switch, the F10 switch, and the current source via the F1 switch. A differential output first plus side path connected to the first output of the first current output; a differential output first side path connected to the second output of the current source via the F2 switch; and the F9th. A differential output second side path connected to the first output of the current source via a switch and a differential output connected to the second output of the current source via the F10 switch. And the first + side path includes the F1 switch, the F3 switch, and the F5 switch connected in series in order from the input side to the output side, and the F3 switch F5th switch And a first capacitor, and the first-side path is serially connected in order from the input side to the output side. The F2 switch, the F6 switch, and the F8 switch connected to each other, and connected between the F6 switch and the F8 switch, and the second reference voltage, respectively. An F7 switch and a second capacitor are provided, and the 2+ side path includes the F10 switch, the F3 switch, and the F5 switch connected in series in order from the input side to the output side. And the F4 switch and the first capacitor, and the second side path is connected in series from the input side to the output side in order, the F9 switch and the F6 switch, The F7 switch, the second capacitor, the frequency of the carrier = the sampling frequency = Fs, and the number of the charge sub-sampling circuits is m. The second F switch is ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the F9 switch and the 10F switch are second rectangular signals that are 180 ° out of phase with the first rectangular signal. The F3 switch and the F6 switch are ON / OFF controlled by the F1 digital signal having a cycle of N × m / Fs, and the F5 switch and the F8 switch have a cycle of N × m / Fs. ON / OFF is controlled by the second F2 digital signal, and the F4 and F7 switches have a cycle of N × m / Fs. ON / OFF is controlled by three digital signals, and periods T1, T2, and T3 in which the total is the period are sequentially provided during one period of the F1 to F3 digital signals, and during the period T1, The F1 digital signal is a series of 1 and 0, the F2 digital signal and the F3 digital signal are 0, and the F2 digital signal is 1 during the period T2, while the first F2 digital signal is 1 and 0. The F1 digital signal and the F3 digital signal become 0, and the F3 digital signal becomes 1 during the period T3, while the F1 digital signal and the F2 digital signal become 0, and the current The first output and the second output of the source are differential outputs.

Mixers of the present invention, as described above, the charge Sabusanpu-ring circuit performs the sampling at a sampling frequency equal to the frequency of the carrier, in the integration process, each term of the transfer function of the FIR filter, a plurality Waiting with a weight selected from the weights.

  Therefore, there is an effect that it is possible to realize a mixer including a charge sub-sampling circuit that can easily obtain a baseband signal from a wideband signal without being affected by noise and interference signals.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Hereinafter, the following symbols are used.

  Fs: a basic sampling frequency of the charge sub-sampling circuit. Set to the same frequency as the carrier frequency of the RF input signal.

  Ts: the basic sampling period of the charge sub-sampling circuit. Ts = 1 / Fs.

  N: Downsampling factor, an integer greater than 1. The frequency of the output signal becomes Fs / N by downsampling.

  M: The order of the FIR filter realized by the integration capacitor and the switch control pattern.

  m: Number of charge sub-sampling circuits connected in parallel.

  gm: gm-stage transconductance.

  Ci: capacitance of the integrating capacitor.

Co: The capacity of the output capacitor.
[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.

  FIG. 2A is a block diagram showing a configuration of a charge sub-sampling mixer (mixer) 1 according to the present embodiment. The charge subsampling mixer 1 includes a timing generation block (control circuit) 11, three charge subsampling circuits 12 to 14, and a current generation circuit (current source) 15. In FIG. 2A, the output capacitor connected to the output terminal OUT is not shown.

  The current generation circuit 15 converts the RF signal input from the input terminal IN into a current corresponding to the voltage and outputs the current. As will be described later, the current generation circuit 15 includes gm stages corresponding to the charge sub-sampling circuits 12, 13, and 14, respectively. The timing generation block 11 generates signals of two signal groups. The first signal group 16 is a signal group made up of signals input in common to all charge sub-sampling circuits, and is a signal LO / nLO in FIGS. 3, 5, and 6 to be described later. The second signal group 17 is a signal group composed of three signals for controlling each charge sub-sampling circuit, and is a signal other than the signals LO and nLO. The three signal patterns of the second signal group are the same, but the phases are shifted from each other and are input to each charge sub-sampling circuit. Although the number of charge sub-sampling circuits is generally m (m ≧ 1), the operation in the case of m = 3 will be described as an example in the present embodiment.

  The operation of the charge sub-sampling circuits 12 to 14 can be divided into an integration state, an output state, and a reset state in order, as shown in FIG. The integration state is a state (period T1) called an integration period Integrate, and the charge sub-sampling circuits 12 to 14 sample charges. The output state, which is the next state after the integration state, is a state (period T2) called an output period Out, and the accumulated charge is transmitted to the output terminal OUT. The reset state, which is the next state after the output state, is a state (period T3) called a reset period Reset, and charges accumulated in the charge sub-sampling circuits 12 to 14 are removed. In FIG. 2A, the charge sub-sampling circuits 12 to 14 are sequentially denoted with a, b, and c after Integrate, Out, and Reset.

  By providing each period so that any one of the charge sub-sampling circuits is in the Out state once every N × Ts time, the frequency of the output signal becomes Fs / N, so the signal is reduced N times Sampling is possible. After the output state, the reset state is entered, and then the integration state is restored. When one charge sub-sampling circuit is in the output state and reset state, the phase of each signal of the second signal group 17 is adjusted so that the remaining charge sub-sampling circuits are in the integration state. When the integration period Integrate, the output period Out, and the reset period Reset are combined, it becomes m × N / Fs or m × N × Ts (here, 3 × N / Fs or 3 × N × Ts). It coincides with the timing pattern period of each signal of the second signal group 17.

  FIG. 3 is a circuit diagram showing a configuration example of the charge sub-sampling circuits 12-14. Since any sub-sampling circuit has the same configuration, only the charge sub-sampling circuit 12 is shown here. The charge sub-sampling circuit 12 is connected to the subsequent stage of the gm stage 1201 that generates a current proportional to the RF input voltage provided in the current generation circuit 15, and includes a + side path and a − side path that are in parallel with each other. It has.

  The + side path includes an input switch (A1 switch) 1202, an integration control switch (A2 switch) 1204, a reset switch (A3 switch) 1206, and an integration capacitor (first switch) in order from the input side to the output side. 1 capacitor) 1208 and an output switch (A4 switch) 1210. However, the input switch 1202, the integration control switch 1204, and the output switch 1210 are connected in series on the + side path, and the reset switch 1206 and the integration capacitor 1208 are respectively connected to the integration control switch 1204 and the output switch 1210. And GND (first reference voltage: that is, the voltage is arbitrary. The same applies to the following reference voltages). Note that the positions of the reset switch 1206 and the integrating capacitor 1208 may be interchanged.

  The negative side path includes an input switch (A5th switch) 1203, an integration control switch (A6th switch) 1205, a reset switch (A7th switch) 1207, and an integration capacitor (first) in order from the input side to the output side. 2 capacitors) 1209 and an output switch (A8 switch) 1211. However, the input switch 1203, the integration control switch 1205, and the output switch 1211 are connected in series on the negative side path, and the reset switch 1207 and the integration capacitor 1209 are respectively connected to the integration control switch 1205 and the output switch 1211. And GND (second reference voltage). Note that the positions of the reset switch 1207 and the integrating capacitor 1209 may be interchanged.

  Further, the capacitance of the integrating capacitors 1208 and 1209 is assumed to be Ci.

  The control signal input to each switch will be described later.

  When the output switch 1210 is turned on in the + side path, the integration capacitor 1208 is connected to the + output terminal 1212. Similarly, in the negative side path, when the output switch 1211 is turned on, the integration capacitor 1209 is connected to the negative output terminal 1213. The + side path and the + output terminal 1212 constitute the + side of the charge subsampling circuit 12, and the − side path and the − output terminal 1213 constitute the − side of the charge subsampling circuit 12. The output signal is output as a voltage difference (differential signal) between the + output terminal 1212 and the − output terminal 1213.

  FIG. 4 is a circuit diagram showing a configuration example of the gm stage 1201 of FIG. The gm stage 1201 includes a current source Ibias, P-channel type MOS transistors P1 and P2 having a current mirror configuration, an N-channel type MOS transistor M1, an input capacitor C, and a bias resistor R. The capacitor C and the resistor R apply a signal in which the input signal (RF) is superimposed on the bias voltage Vbias to the gate terminal of the MOS transistor M1. The drain terminal of the MOS transistor P1 is connected to the current source Ibias, and the gate terminal of the MOS transistor P1 and the gate terminal of the MOS transistor P2 are connected to each other. The drain terminal of the MOS transistor P2 and the drain terminal of the MOS transistor M1 are connected to each other, and the common connection point is the output of the gm stage.

  FIG. 5 is a circuit diagram showing a configuration of the charge sub-sampling mixer 1 in a state where the three charge sub-sampling circuits 12 to 14 are used and the output capacitors 101 and 102 are connected to the output terminal OUT. However, in this figure, the timing generation block 11 is not shown. The charge subsampling circuits 12, 13 and 14 have the same configuration as the charge subsampling circuit 12 described above. The RF input signal is input to each of the charge subsampling circuits 12 to 14, the + output terminals and the − output terminals of the charge subsampling circuits 12 to 14 are connected to each other, and the common connection point of the + output terminals is The charge sub-sampling mixer 1 becomes the Out + output, and the common connection point of the − output terminal becomes the Out-output of the charge sub-sampling mixer 1. The output capacitor 101 is connected to Out +, and the output capacitor 102 is connected to Out− output. A voltage difference (differential signal) between the Out + output and the Out− output becomes an output signal of the charge sub-sampling circuit 1. Note that the capacitance of the output capacitors 101 and 102 is Co.

  Next, FIG. 6 shows an example of a control signal generated by the timing generation block 11 and input to each of the switches shown in FIGS.

  When the level of the signal shown in this figure becomes 1, the switch controlled by the signal is turned on. Conversely, when the level of the signal becomes 0, the switch controlled by the signal is turned off.

  In the present embodiment, the following signal LO is a first rectangular signal, signal nLO is a second rectangular signal, signal enable is an A1 digital signal, signal out is an A2 digital signal, and signal reset is an A3 digital signal. To do.

  The frequency of the signal LO · nLO is set to Fs, and the signal LO and the signal nLO are 180 ° out of phase. The signal LO controls all the + side input switches 1202, 1302, and 1402 of the charge sub-sampling circuits 12 to 14, and the signal nLO controls all the − side input switches 1203, 1303, and 1403 of the charge sub-sampling circuits 12 to 14. To control.

  The signal enable_a controls the integration control switches 1204 and 1205 of the charge sub-sampling circuit 12, the signal enable_b controls the integration control switches 1304 and 1305 of the charge sub-sampling circuit 13, and the signal enable_c is the integration control switch of the charge sub-sampling circuit 14. 1404 and 1405 are controlled.

  The signal out_a controls the output switches 1210 and 1211 of the charge sub-sampling circuit 12, the signal out_b controls the output switches 1310 and 1311 of the charge sub-sampling circuit 13, and the signal out_c is the output switches 1410 and 1411 of the charge sub-sampling circuit 14. To control.

  The signal reset_a controls the reset switches 1206 and 1207 of the charge subsampling circuit 12, the signal reset_b controls the reset switches 1306 and 1307 of the charge subsampling circuit 13, and reset_c controls the reset switches 1406 and 1407 of the charge subsampling circuit 14. Control.

  During the integration period Integrate, the signal enable is a series of 1 and 0, while the signal reset and the signal out are 0. During the output period Out, the signal out becomes 1 while the signal enable and the signal reset become 0. During the reset period Reset, the signal reset is 1 while the signal enable and the signal out are 0.

  In this example, since three charge subsampling circuits (that is, m = 3) are used, the period of each signal is set to 3 × N × Ts. In this example, N = 5. In order to reliably transfer the charge accumulated in each integration capacitor to the output capacitors 101 and 102, the output period Out is made as long as possible, and the charge remaining in each integration capacitor after the output period Out is reliably removed. In addition, it is preferable to make the reset period Reset as long as possible. In the present embodiment, the output period Out and the reset period Reset are each set to N / 2 × Ts (= 0.5 × N / Fs), and the integration period Integrate is set to 2 × N × Ts. In general, the integration period Integrate is (m−1) × N × Ts.

  In order to match the above period, the signal reset_a · reset_b · reset_c and the signal out_a · out_b · out_c are signals that become 1 during N / 2 × Ts (= 0.5 × N / Fs), respectively. . In addition, the signals enable_a, enable_b, and enable_c are alternately set to 1 and 0 in a predetermined sequence during 2 × N × Ts, and become 0 during the remaining N × Ts. The basic patterns of the signal enable, the signal reset, and the signal out are the same, and the signal enable_b, the signal reset_b, and the signal out_b delay the signal enable_a, the signal reset_a, and the signal out_a by N × Ts, respectively. The signal enable_c, the signal reset_c, and the signal out_c are obtained by delaying the signal enable_b, the signal reset_b, and the signal out_b by N × Ts, respectively.

  The characteristic of the FIR filter is determined with respect to the pattern of 1 and 0 of the signal enable in the integration period Integrate. The effect will be described below.

  According to the same analysis as in the prior art, the charge accumulated during the sampling period Ts is:

here,

Was ignored. In the above formula, z is defined by the following formula.

A _k written by the expression of Q _out (f) becomes 0 or 1 with respect to the value of the signal enable. M is the order of the FIR filter. In the example of FIG. 6, {a _{0 to} a ₁₉ } = {0,0,1,0,0,0,1,1,1,0,1,1,0,1,1,1,0,0, 0,1}. During N × Ts, the + side and − side of the charge sub-sampling circuit are sampled N times, so that the output signal of the gm stage is sampled 2 × N times. Note that, as described above, since the integration period Integrate is (m−1) × N × Ts, the order of the FIR filter can be calculated by the following equation.

In this embodiment, M = 20. That is, it means that the number of patterns 0 and 1 of each signal enable in the timing chart of FIG. 6 is 20 in the integration period Integrate.

  From the above, the output is expressed by the following equation.

here,

The interference wave can be attenuated by the value of the coefficient _ak of the FIR filter as shown in FIG. Determining whether the signal enable is set to 1 or 0 is determining whether each coefficient _ak of the FIR filter is set to 1 or 0. In the filtering process by the FIR filter, the FIR filter This corresponds to weighting each term of the transfer function with a weight selected from a plurality of weights of 1 or 0. FIGS. 7A and 7B are the same as FIGS. 26A and 26B described above, and FIG. 7C shows the gain characteristics of the FIR filter according to the present embodiment. FIG. 7D shows a state where the interference signal is attenuated by the FIR filter. Compared to the conventional case, it can be seen that in this embodiment, the entire band of the interference signal (band turned back to the desired signal band) is greatly attenuated. FIG. 7E shows how a baseband signal is extracted from the differential output signal of FIG.

  Thus, according to the present embodiment, a baseband signal can be easily obtained from a wideband signal without being affected by noise and interference signals.

The weighting of the filtering process by the FIR filter, that is, the method of setting the filter coefficient is not limited to the above example, and the following pattern may be used.
{a _{0 to} a ₁₉ } = {1,0,1,0,1,1,1,1,1,1,0,1,0,1,0,0,0,0,0,0}
{a _{0 to} a ₁₉ } = {1,0,0,1,1,0,1,1,1,1,0,1,1,0,0,1,0,0,0,0}
It is possible to use a computer program to determine the pattern. For example, by calculating the attenuation amount of the interference wave for all the patterns of the FIR coefficient by a program, a pattern having a large attenuation amount can be searched.

Further, in the above two patterns, a plurality of zeros continue on the right side. Therefore, the same characteristics (different input / output delay amounts) can be obtained even in the following pattern in which the above two patterns are shifted to the right.
{a _{0 to} a ₁₉ } = {0,1,0,1,0,1,1,1,1,1,1,0,1,0,1,0,0,0,0,0}
{a _{0 to} a ₁₉ } = {0,0,0,1,0,1,0,1,1,1,1,1,1,0,1,0,1,0,0,0}
Next, FIG. 8A shows a calculation value of the gain characteristic of the charge sub-sampling mixer 1 shown in FIG. 2 by a theoretical formula (the above formula) and a circuit simulation result using an ideal element. The horizontal axis of the graph indicates the output frequency of the charge sub-sampling mixer 1 displayed in hertz (Hz), and the vertical axis indicates the gain of the sub-sampling mixer displayed in dB. The simulation parameters were set as follows.

gm = 1mS
Ci = Co = 500 pF
N = 5
M = 20
{a _{0 to} a ₁₉ } = {0,0,1,0,0,0,1,1,1,0,1,1,0,1,1,1,0,0,0,1} ( (The pattern shown in FIG. 6 was used)
Fs = 506MHz
Signal bandwidth = 8 MHz (Fc +/- 4 MHz)
The above frequency parameters were determined from the specifications used in TV tuners. With the above parameters, for a desired signal in the range of 502 to 510 MHz, the carrier frequency of the first jamming signal is Fs + Fs / N, and the first jamming signal is in the range of 603.2 to 611.2 MHz. When a signal with the above frequency is input to the sub-sampling mixer, the output is in the range of +/− 4 MHz.

  In FIG. 7A, which is the simulation result of the present embodiment, the upper line and the point are gains for the desired signal, and the lower line and the point are gains of the disturbing signal. The gain indicated by the line is the gain calculated from the above formula, and the point is the gain obtained as a result of the simulation. Vertical lines at +4 MHz and −4 MHz indicate the edge of the signal band. The minimum gain difference between the desired signal and the disturbing signal is about 60 dB, and this value is the rejection ratio (Unknown Rejection Ratio, hereinafter referred to as URR) of the disturbing signal.

  For comparison, FIG. 7B shows a simulation result of a conventional charge sub-sampling mixer using the same parameters. In this case, URR is about 30 dB.

  Considering an example of the application, URR required for the receiver as a whole is 75 dB from the receiver specification for DVB-H. It is necessary to attenuate the signal separated by 100 MHz from the signal by 45 dB. On the other hand, according to the charge sub-sampling mixer of the present embodiment, it is only necessary to attenuate a signal 100 MHz away from the desired signal by 15 dB by the input filter, and it is conventionally possible to realize a filter arranged in a stage preceding the charge sub-sampling mixer. There is an effect that it becomes easy.

  In the above description, the specific example is shown for the case where there are three charge sub-sampling circuits. However, as can be understood from the above description, the number of charge sub-sampling circuits (= m) may be arbitrary. FIG. 1A shows a configuration of the charge sub-sampling mixer 5 in which m = 1. The charge subsampling mixer 5 includes a timing generation block (control circuit) 6, a charge subsampling circuit 7, and a current generation circuit (current source) 8. In FIG. 1A, the output capacitor connected to the output terminal OUT is not shown.

  The current generation circuit 8 converts an RF signal input from the input terminal IN into a current corresponding to the voltage and outputs the current, and has a configuration in which one gm stage 1201 of FIG. 2 is provided. . The timing generation block 6 generates signals of two signal groups. The first signal group 9 is the same signal as the first signal group 16 in FIG. 2A, and the second signal group is one of the second signal groups 17 in FIG. The signal is similar to the signal supplied to one charge sub-sampling circuit. FIG. 1B shows a sequence followed by the second signal group 10. The meaning and sequence of the symbols are the same as those in FIG.

  In the present embodiment, the input signal (RF) and the output signal of the gm stage are described as a configuration that handles single-ended signals, but these signals may be differential signals. FIG. 9 shows a part of the charge sub-sampling mixer having such a configuration. In FIG. 9, the input signal is a differential signal, and the gm stage 151 is a differential input in accordance with this, and the gm stage 151 is a differential output. When the LO is 1, the charge sub-sampling circuit 152 connects the positive side of the differential output to the enable switch on the positive side and connects the negative side of the differential output to the enable switch on the negative side. The configuration is such that the + side of the differential output of the stage is connected to the enable switch on the − side and the − side of this differential output is connected to the enable switch on the + side. When an input signal is input as a differential signal, it is possible to reduce the influence of secondary distortion and common mode noise.

  Further, according to the present embodiment, current sources such as the current generation circuits 8 and 15 have current outputs corresponding to the number of charge sub-sampling circuits for one input signal (RF), and each output is separately provided. Connected to the input of the charge sub-sampling circuit. According to this, the current source can input an appropriate current according to the input signal to each charge sub-sampling circuit regardless of the number of charge sub-sampling circuits.

Further, according to the present embodiment, the current source such as the current generation circuits 8 and 15 generates a current by the gm stage provided for each current output. Accordingly, each gm stage only needs to input a current to one charge sub-sampling circuit, so that the output capacity can be small.
[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. In addition, the same code | symbol is attached | subjected to the component which has the same function as the said Embodiment 1, and the description is abbreviate | omitted.

  FIG. 10A shows the configuration of the charge sub-sampling mixer 2 according to the present embodiment. The charge sub-sampling mixer 2 includes a timing generation block (control circuit) 21, three charge sub-sampling circuits 22 to 24, and a current generation circuit (current source) 25. In FIG. 10A, the output capacitor connected to the output terminal OUT is not shown.

  The timing generation block 21 is the same as the timing generation block 11 of FIG. 2 and generates the first signal group 16 and the second signal group 17. FIG. 10B shows a sequence followed by the second signal group 17. The meaning and sequence of the symbols are the same as in FIG. The charge subsampling circuits 22 to 24 are the same as the charge subsampling circuits 12 to 14 in FIG. The current generation circuit 25 includes only one gm stage 2501. The three charge sub-sampling circuits 22 to 24 are connected in parallel, and the output of the gm stage 2501 is input in common.

  FIG. 11 is a circuit diagram illustrating a detailed configuration example of the charge sub-sampling mixer 2. As shown in FIG. 11, each charge subsampling circuit 22-24 is controlled by an input switch controlled by signals LO and nLO, an integration control switch controlled by signal enable, and a signal reset, as in FIG. A reset switch, an integration capacitor, and an output switch controlled by a signal out.

  The signal LO controls all the + side input switches 2202, 2302, and 2402 of the charge subsampling circuits 22 to 24, and the signal nLO controls all the − side input switches 2203, 2303, and 2403 of the charge subsampling circuits 22 to 24. To control.

  The signal enable_a controls the integration control switches 2204 and 2205 of the charge sub-sampling circuit 22, the signal enable_b controls the integration control switches 2304 and 2305 of the charge sub-sampling circuit 23, and the signal enable_c is the integration control switch of the charge sub-sampling circuit 24. 2404 and 2405 are controlled.

  The signal out_a controls the output switches 2210 and 2211 of the charge sub-sampling circuit 22, the signal out_b controls the output switches 2310 and 2311 of the charge sub-sampling circuit 23, and the signal out_c is the output switches 2410 and 2411 of the charge sub-sampling circuit 14. To control.

  The signal reset_a controls the reset switches 2206 and 2207 of the charge sub-sampling circuit 22, the signal reset_b controls the reset switches 2306 and 2307 of the charge sub-sampling circuit 23, and reset_c controls the reset switches 2406 and 2407 of the charge sub-sampling circuit 24. Control.

  The output capacitor 201 is connected to the Out + output terminal, and the output capacitor 202 is connected to the Out− output terminal. The output signal is output as a voltage difference (differential signal) between the Out + output terminal and the Out− output terminal.

When the switching timing in the present embodiment is the same as the pattern shown in FIG. 6, the same effect as in the first embodiment can be obtained. In addition, since only one gm stage is used in the present embodiment, the circuit scale can be reduced, and the path matching is higher than in the first embodiment. When making a circuit, each path is slightly different because it may be different from the designed size. For example, if two gm stages are used, each transconductance is different and the effect is a path mismatch.
[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIGS. In addition, the same code | symbol is attached | subjected to the component which has the same function as the said Embodiment 1 and 2, and the description is abbreviate | omitted.

  FIG. 12 shows a part of the configuration of the charge sub-sampling mixer according to the present embodiment. This charge subsampling mixer includes three gm stages 3201 and a charge subsampling circuit 32 connected in parallel as shown in FIG. 5 of the first embodiment. The three gm stages 3201 constitute a current generation circuit (current source). In addition, a timing generation block (control circuit) similar to the timing generation block 11 of FIG. 2 is provided.

  The gm stage 3201 generates a current proportional to the voltage of the input signal (RF). The charge sub-sampling circuit 32 includes an input switch (B1 switch) 3202, a + side path connected to the output of the gm stage 3201 via the input switch 3202, and an input switch (second B2 switch) 3203. A negative-side path connected to the output of the gm stage 3201 via the input switch. Further, the + side path includes a first + side path and a second + side path provided in parallel between the input switch 3202 and the + output terminal 3220, and the − side path includes the input switch 3203 and the − output. A first side path and a second side path provided in parallel with the terminal 3221 are provided.

  The first + side path includes, in order from the input side to the output side, a first integration control switch (B3 switch) 3205, a first reset switch (B4 switch) 3209, and a first integration capacitor (first capacitor). 3213 and a first output switch (B5 switch) 3217. However, the first integration control switch 3205 and the first output switch 3217 are connected in series on the first + side path, and the first reset switch 3209 and the first integration capacitor 3213 are respectively the first integration control switch 3205. And the first output switch 3217 and the GND (first reference voltage). Note that the positions of the first reset switch 3209 and the first integrating capacitor 3213 may be interchanged.

  The second + side path includes, in order from the input side to the output side, a second integration control switch (B6 switch) 3204, a second reset switch (B7 switch) 3208, and a second integration capacitor (second capacitor). 3212 and a second output switch (B8 switch) 3216. However, the second integration control switch 3204 and the second output switch 3216 are connected in series on the 2+ side path, and the second reset switch 3208 and the second integration capacitor 3212 are respectively connected to the second integration control switch 3204. And the second output switch 3216 and between GND (second reference voltage). Note that the positions of the second reset switch 3208 and the second integration capacitor 3212 may be interchanged.

  The first-side path includes, in order from the input side to the output side, a first integration control switch (B9 switch) 3206, a first reset switch (B10 switch) 3210, and a first integration capacitor (third capacitor). ) 3214 and a first output switch (B11 switch) 3218. However, the first integration control switch 3206 and the first output switch 3218 are connected in series on the first-side path, and the first reset switch 3210 and the first integration capacitor 3214 are each a first integration control switch. It is connected between 3206 and the first output switch 3218 and between GND (third reference voltage). Note that the positions of the first reset switch 3210 and the first integration capacitor 3214 may be interchanged.

  The second side path includes, in order from the input side to the output side, a second integration control switch (B12 switch) 3207, a second reset switch (B13 switch) 3211, and a second integration capacitor (fourth capacitor). ) 3215 and a second output switch (B14th switch) 3219. However, the second integration control switch 3207 and the second output switch 3219 are connected in series on the second-side path, and the second reset switch 3211 and the second integration capacitor 3215 are each a second integration control switch. It is connected between 3207 and the second output switch 3219 and between GND (fourth reference voltage). Note that the positions of the second reset switch 3219 and the second integration capacitor 3215 may be interchanged.

  When the first output switch 3217 and the second output switch 3216 are turned on, the first integration capacitor 3213 and the second integration capacitor 3216 are connected to the + output terminal 3220. Similarly, when the first output switch 3218 and the second output switch 3219 are turned on, the first integration capacitor 3214 and the second integration capacitor 3215 are connected to the − output terminal 3221. The output signal is output as a voltage difference (differential signal) between the + output terminal 3220 and the − output terminal 3221.

  FIG. 13 shows an example of a timing diagram of the control signal of this embodiment.

  In this embodiment, the following signal LO is a first rectangular signal, signal nLO is a second rectangular signal, signal enable1 is a B1 digital signal, signal enable2 is a B2 digital signal, signal out is a B3 digital signal, Let signal reset be the B4th digital signal.

  The difference from the first embodiment is that there are two signals enable1 and enable2 in one charge sub-sampling circuit. The signal LO controls the input switch 3202, and the signal nLO controls the input switch 3203. The signal enable1 controls the first integration control switches 3205 and 3206, and the signal enable2 controls the second integration control switches 3204 and 3207. If the signal enable1 and the signal enable2 are not simultaneously set to 1 and the first integration capacitors 3213 and 3214 and the second integration capacitors 3212 and 3215 are set to different values, the FIR coefficient can be switched to three values. When the capacitance of the first integration capacitors 3213 and 3214 is set to Ci and the capacitance of the second integration capacitors 3212 and 3215 is set to Ci / k, the FIR coefficient can be selected from 0, 1, and k. In this case, in the filtering process by the FIR filter, each term is weighted by a weight selected from a plurality of weights of 1 or 0 or k.

  In addition, the signal reset controls the first reset switches 3209 and 3210 and the second reset switches 3208 and 3211, and the signal out controls the first output switches 3217 and 3218 and the second output switches 3216 and 3219. The above signals are provided for each of the three charge sub-sampling circuits, and are distinguished by a, b, and c.

  According to the present embodiment, since the coefficients of usable FIR filters increase, it is easy to realize an appropriate FIR filter for an application.

  Further, by increasing the number of integrating capacitors, it is possible to increase the value of the coefficient that can be realized.

Further, only one gm stage can be used as in the second embodiment.
[Embodiment 4]
The following will describe still another embodiment of the present invention with reference to FIGS. In addition, the same code | symbol is attached | subjected to the component which has the same function as the said Embodiment 1 thru | or 3, and the description is abbreviate | omitted.

  FIG. 14 shows a part of the configuration of the charge sub-sampling mixer according to the present embodiment. This charge subsampling mixer includes three gm stages 4201 and a charge subsampling circuit 42 connected in parallel as in the configuration of FIG. 5 of the first embodiment. The three gm stages 4201 constitute a current generation circuit (current source). In addition, a timing generation block (control circuit) similar to the timing generation block 11 of FIG. 2 is provided.

  The gm stage 4201 generates a current proportional to the voltage of the input signal (RF). The charge sub-sampling circuit 42 includes an input switch (first C1 switch) 4202 and an input switch (second C2 switch) 4203, and a first + side path and a second side connected to the output of the gm stage 4201 through the input switch 4202. And a first side path and a second side path connected to the output of the gm stage 4201 through the input switch 4203.

  The first + side path includes a first integration control switch (C3 switch) 4204 and a reset switch (C4 switch) 4206 between the input switch 4202 and the + output terminal 4212 in order from the input side to the output side. And an integration capacitor (first capacitor) 4208 and an output switch (C5th switch) 4210. However, the first integration control switch 4204 and the output switch 4210 are connected in series on the first + side path, and the reset switch 4206 and the integration capacitor 4208 are respectively between the first integration control switch 4202 and the output switch 4210. And GND (first reference voltage). Note that the positions of the reset switch 4206 and the integrating capacitor 4208 may be interchanged.

  In the first-side path, a first integration control switch (C6th switch) 4205 and a reset switch (C7th switch) are arranged in order from the input side to the output side between the input switch 4203 and the -output terminal 4213. 4207, an integration capacitor (second capacitor) 4209, and an output switch (C8 switch) 4211. However, the first integration control switch 4205 and the output switch 4211 are connected in series on the first-side path, and the reset switch 4207 and the integration capacitor 4209 are respectively connected to the first integration control switch 4205 and the output switch 4211. And GND (second reference voltage). Note that the positions of the reset switch 4207 and the integrating capacitor 4209 may be interchanged.

  In the second + side path, a second integration control switch (C10 switch) 4215, a reset switch 4206, and an integration capacitor 4208 are arranged between the input switch 4203 and the + output terminal 4212 in order from the input side to the output side. And an output switch 4210. The reset switch 4206, the integrating capacitor 4208, and the output switch 4210 are shared with the first + side path. The second integration control switch 4215 and the output switch 4210 are connected in series on the 2+ side path.

  In the second-side path, a second integration control switch (C9 switch) 4214, a reset switch 4207, and an integration capacitor are arranged between the input switch 4202 and the -output terminal 4212 in order from the input side to the output side. 4209 and an output switch 4211 are provided. The second integration control switch 4214, the reset switch 4207, the integration capacitor 4209, and the output switch 4211 are shared with the first-side path. The second integration control switch 4214 and the output switch 4211 are connected in series on the second side path.

  Note that the capacitance of the integrating capacitors 4208 and 4209 is Ci.

  When the output switch 4210 is turned on, the integration capacitor 4208 is connected to the + output terminal 4212. Similarly, when the output switch 4211 is turned on, the integration capacitor 4209 is connected to the negative output terminal 4213. The output signal is output as a voltage difference (differential signal) between the + output terminal 4212 and the − output terminal 4213.

  FIG. 15 is an example of a timing diagram of a control signal in this embodiment.

  In this embodiment, the following signal LO is the first rectangular signal, signal nLO is the second rectangular signal, signal enable + is the C1 digital signal, signal enable− is the C2 digital signal, and signal out is the C3 digital signal. , Signal reset is the C4th digital signal.

  The difference from the first embodiment is that there are two signals enable + and enable− in one charge sub-sampling circuit. The signal enable + and the signal enable− are not set to 1 simultaneously. When the signal enable + is set to 1, the first integration control switches 4204 and 4205 are turned on, and the coefficient of the FIR filter becomes +1. Conversely, when the signal enable- is set to 1, the second integration control switches 4214 and 4215 are turned on, and the coefficient of the FIR filter becomes -1. If both are set to 0, the coefficients of the FIR filter become 0, and a total of 3 FIR filter coefficients can be created.

  According to the present embodiment, since the coefficients of usable FIR filters increase, an appropriate FIR filter for an application can be realized.

  Further, only one gm stage can be used as in the second embodiment.

It is also possible to combine Embodiment 3 with this embodiment.
[Embodiment 5]
The following will describe still another embodiment of the present invention with reference to FIGS. In addition, the same code | symbol is attached | subjected to the component which has the same function as the said Embodiment 1 thru | or 4, and the description is abbreviate | omitted.

  FIG. 16 shows a part of the configuration of the charge sub-sampling mixer according to the present embodiment. This charge sub-sampling mixer includes three gm stages 5201 and charge sub-sampling circuits 52 connected in parallel as shown in FIG. 5 of the first embodiment. The three gm stages 5201 constitute a current generation circuit (current source). In addition, a timing generation block (control circuit) similar to the timing generation block 11 of FIG. 2 is provided.

  The gm stage 5201 generates a current proportional to the voltage of the input signal (RF). The charge sub-sampling circuit 52 includes a + side path and a − side path.

  In the + side path, in order from the input side to the output side, an input switch (D1 switch) 5202, an integration control switch (D2 switch) 5204, a reset switch (D3 switch) 5206, and an integration capacitor (first switch). 1 capacitor) 5208 and an output switch (D4 switch) 5210. However, the input switch 5202, the integration control switch 5204, and the output switch 5210 are connected in series on the + side path, and the reset switch 5206 and the integration capacitor 5208 are respectively connected between the integration control switch 5204 and the output switch 5210. And GND (first reference voltage). Note that the positions of the reset switch 5206 and the integrating capacitor 5208 may be interchanged.

  The negative side path includes, in order from the input side to the output side, an input switch (D5 switch) 5203, an integration control switch (D6 switch) 5205, a reset switch (D7 switch) 5207, and an integration capacitor (first switch). 2 capacitor) 5209 and an output switch (D8 switch) 5211. However, the input switch 5203, the integration control switch 5205, and the output switch 5211 are connected in series on the negative side path, and the reset switch 5207 and the integration capacitor 5209 are respectively connected between the integration control switch 5205 and the output switch 5211. And GND (second reference voltage). Note that the positions of the reset switch 5207 and the integrating capacitor 5209 may be interchanged.

  Note that the capacitance of the integrating capacitors 5208 and 5209 is Ci.

  When the output switch 5210 is turned on, the integration capacitor 5208 is connected to the + output terminal 5212. Similarly, when the output switch 5211 is turned on, the integrating capacitor 5209 is connected to the negative output terminal 5213. The output signal is output as a voltage difference (differential signal) between the + output terminal 5212 and the − output terminal 5213.

  The charge sub-sampling circuit 52 has the same configuration as that of the charge sub-sampling circuit 12 shown in FIG. 2, and is different in that the control signals for the integration control switch 5204 and the integration control switch 5205 are separated. This will be described below.

  An example of a timing diagram of the control signal of this embodiment is shown in FIG.

  In this embodiment, the following signal LO is the first rectangular signal, signal nLO is the second rectangular signal, signal enable1 is the first D1 digital signal, signal enable2 is the second D2 digital signal, signal out is the D3 digital signal, Let signal reset be the D4th digital signal.

The difference from the first embodiment is that there are two signals enable1 and enable2 in one charge sub-sampling circuit. A minimum one period of each signal enable is set as Ts. The odd coefficient (a ₁ , a ₃ etc.) of the FIR filter is determined from the value of the signal enable 1 when the signal LO is 1. The even coefficient (a ₀ , a ₂ etc.) of the FIR filter is determined from the value of the signal enable2 when the signal nLO is 1.

  According to the present embodiment, the same FIR filter as in the first embodiment can be realized. Further, since the minimum period of the signals enable1 and enable2 is set to be twice as long as the first to fourth embodiments (= 2 × Ts / 2), the minimum period of the signal and the rising (falling) period of the signal are reduced. Since the ratio increases, the charging error to the integrating capacitor is reduced, and the charge subsampling circuit can be easily realized.

Further, only one gm stage can be used as in the second embodiment.
[Embodiment 6]
The following will describe still another embodiment of the present invention with reference to FIGS. In addition, the same code | symbol is attached | subjected to the component which has the same function as the said Embodiment 1 thru | or 5, and the description is abbreviate | omitted.

  FIG. 18 shows a part of the configuration of the charge sub-sampling mixer according to the present embodiment. This charge sub-sampling mixer includes three gm stages 6201 and charge sub-sampling circuits 62 connected in parallel as shown in FIG. 5 of the first embodiment. The three gm stages 6201 constitute a current generation circuit (current source). In addition, a timing generation block (control circuit) similar to the timing generation block 11 of FIG. 2 is provided.

  The gm stage 6201 generates a current proportional to the voltage of the input signal (RF). The charge sub-sampling circuit 62 includes a + side path and a − side path.

  The + side path includes, in order from the input side to the output side, an integration control switch (E1 switch) 6204, a reset switch (E2 switch) 6206, an integration capacitor (first capacitor) 6208, and an output switch (first switch). E3 switch) 6210. However, the integration control switch 6204 and the output switch 6210 are connected in series on the + side path, and the reset switch 6206 and the integration capacitor 6208 are respectively connected between the integration control switch 6204 and the output switch 6210, and GND (first 1 reference voltage). Note that the positions of the reset switch 6206 and the integrating capacitor 6208 may be interchanged.

  The negative side path includes, in order from the input side to the output side, an integration control switch (E4 switch) 6205, a reset switch (E5 switch) 6207, an integration capacitor (second capacitor) 6209, and an output switch (second switch). E6 switch) 6211. However, the integration control switch 6205 and the output switch 6211 are connected in series on the negative side path, and the reset switch 6207 and the integration capacitor 6209 are respectively connected between the integration control switch 6205 and the output switch 6211 and the GND (first 2 reference voltage). Note that the positions of the reset switch 6207 and the integrating capacitor 6209 may be interchanged.

  Note that the capacitance of the integrating capacitors 6208 and 6209 is Ci.

  When the output switch 6210 is turned on, the integration capacitor 6208 is connected to the + output terminal 6212. Similarly, when the output switch 6211 is turned on, the integrating capacitor 6209 is connected to the negative output terminal 6213. The output signal is output as a voltage difference (differential signal) between the + output terminal 6212 and the − output terminal 6213.

  FIG. 19 shows an example of a timing diagram of control signals in this embodiment.

  In the present embodiment, the following signal enable1 is an E1 digital signal, signal enable2 is an E2 digital signal, signal out is an E3 digital signal, and signal reset is an E4 digital signal.

  The difference from the first embodiment is that there is no signal LO / nLO (that is, the timing generation block does not generate the first signal group), and there are two signals enable1 and enable2 in one charge sub-sampling circuit. That is.

When the same FIR filter is realized in the first embodiment and the present embodiment, there is the following relationship.
enable1 = LO AND enable
enable2 = nLO AND enable
In this equation, the left is the signal of the present embodiment, and the right is the signal of the first embodiment. That is, in this embodiment, the input switch 1202 and the integration control switch 1204 of Embodiment 1 are combined, and the input switch 1203 and the integration control switch 1205 are combined. By combining the switches, the integration control switches 6204 and 6205 are the only switches that connect the charge sub-sampling circuit 62 to the output of the gm stage 6201. Therefore, the number of switches is reduced, the parasitic capacitance and resistance of the switches are reduced, and the circuit area can be reduced.
[Embodiment 7]
The following will describe still another embodiment of the present invention with reference to FIG.

  FIG. 20 is a block diagram of a configuration example of a television tuner manufactured using the charge sub-sampling mixer described in the first to sixth embodiments. 20 includes an antenna 71, an LNA 72 (Low Noise Amplifier) that amplifies a signal received from the antenna 71 in the RF front end 77, and an RF bandpass filter that attenuates an interference signal in the RF front end 77. 73, a charge subsampling mixer (for example, charge subsampling mixer 1) according to the present invention, a low pass filter 74 in the analog baseband signal processing unit 78, and an analog signal in the analog baseband signal processing unit 78 as a digital signal. It comprises an ADC 75 for converting to a digital signal, and a DSP (Digital Signal Processor) or microprocessor 76 for processing a digital signal. Further, by feeding back the output from the DSP or the microprocessor 76 to the charge sub-sampling mixer 1, the frequency, timing pattern, etc. of the charge sub-sampling mixer 1 can be controlled with respect to the received signal.

  The present invention can be suitably used for a device that receives a broadband signal, such as a television tuner.

(A) is a block diagram which shows the structure of the 1st mixer which concerns on the 1st Embodiment of this invention, (b) is a figure explaining the period of the signal which the timing generation block of this mixer generates. (A) is a block diagram which shows the structure of the 2nd mixer which concerns on the 1st Embodiment of this invention, (b) is a figure explaining the period of the signal which the timing generation block of this mixer generates. It is a circuit diagram which shows the structure of the electric charge subsampling circuit with which the mixer of Fig.1 (a) and Fig.2 (a) is provided. It is a circuit diagram which shows the structure of the gm stage with which the mixer of Fig.1 (a) and Fig.2 (a) is equipped. FIG. 3 is a circuit block diagram showing the mixer of FIG. 2A using a detailed configuration diagram of a charge subsampling circuit. It is a timing chart which shows the timing of each signal of the mixer of Fig.2 (a). (A) thru | or (e) are the spectrum figure explaining the state which attenuate | damps an interference signal with the mixer of Fig.2 (a), and the gain characteristic figure of a FIR filter. (A) is a figure which shows the gain characteristic of the signal obtained by the mixer of Fig.2 (a), (b) is a figure which shows the gain characteristic of the signal obtained by the conventional mixer. It is a circuit block diagram which shows a part of structure of a mixer in case an input signal is a differential signal. (A) is a block diagram which shows the structure of the mixer which concerns on the 2nd Embodiment of this invention, (b) is a figure explaining the period of the signal which the timing generation block of this mixer generates. FIG. 11 is a circuit block diagram illustrating the mixer of FIG. 10 using a detailed configuration diagram of a charge subsampling circuit. It is a circuit block diagram which shows the structure of the electric charge subsampling circuit with which the mixer which concerns on the 3rd Embodiment of this invention is provided. It is a timing chart which shows the timing of each signal of the mixer of FIG. It is a circuit block diagram which shows the structure of the electric charge subsampling circuit with which the mixer which concerns on the 3rd Embodiment of this invention is provided. It is a timing chart which shows the timing of each signal of the mixer of FIG. It is a circuit block diagram which shows the structure of the electric charge subsampling circuit with which the mixer which concerns on the 4th Embodiment of this invention is provided. It is a timing chart which shows the timing of each signal of the mixer of FIG. It is a circuit block diagram which shows the structure of the electric charge subsampling circuit with which the mixer which concerns on the 5th Embodiment of this invention is provided. It is a timing chart which shows the timing of each signal of the mixer of FIG. It is a block diagram which shows the structure of the tuner provided with the mixer of 1st-5th embodiment. It is a circuit block diagram which shows a prior art and shows the structure of a mixer. It is a timing chart explaining the timing of each signal of the mixer of FIG. It is a timing chart explaining the mode of electric charge accumulation of the mixer of FIG. It is a wave form diagram explaining the basic waveform of signal LO of FIG. (A) thru | or (e) are the spectrum figure explaining the state which attenuates the noise with the mixer of FIG. 21, and the gain characteristic figure of a FIR filter. (A) thru | or (e) are the spectrum figure explaining the state which cannot fully attenuate an interference signal with the mixer of FIG. 21, and the gain characteristic figure of a FIR filter.

Explanation of symbols

1, 5 Mixer 8, 15, 25
Current generation circuit (current source)
7, 12, 13, 14, 22, 23, 24, 32, 42, 52, 62, 152
Charge sub-sampling circuit 151, 1201, 1301, 1401, 2501, 3201, 4201, 5201, 6201
Transconductance stage

Claims (13)

A mixer that demodulates the baseband signal from the input signal using a signal obtained by modulating a carrier with a baseband signal as an input signal,
A current source for generating a current proportional to the voltage of the input signal, a charge Sabusanpu-ring circuit which receives the current generated by said current source, a signal for controlling the sampling of the current by the charge Sabusanpu-ring circuit And a control circuit for generating
The charge sub-sampling circuit generates a discrete-time signal in a band lower than N times (N is an integer greater than 1) the frequency of the carrier from the input signal under the control of the sampling by the control circuit, and the discrete-time signal In the mixer that performs the filtering process by the FIR filter realized by the integration process of the charges forming the current,
The charge Sabusanpu-ring circuit,
Based on control by the control circuit, a circuit for performing the sampling at a sampling frequency equal to the frequency of the carrier, a circuit for integration processing for accumulating the charge, and the accumulated charge in the charge sub-sampling A circuit for output processing to be output to the outside of the circuit, and a circuit for reset processing for removing the charge accumulated in the charge sub-sampling circuit,
In the integration process, each term of the transfer function of the FIR filter is weighted by a weight selected from a plurality of weights ,
The mixer is characterized in that the selection of the weight selects a pattern of a sequence of 1s and 0s of a signal for controlling the integration process.   The current source has outputs of the current corresponding to the number of the charge sub-sampling circuits for one input signal, and each of the outputs is connected to an input of a separate charge sub-sampling circuit. The mixer according to claim 1.   The mixer according to claim 2, wherein the current source generates the current by a transconductance stage provided for each of the outputs.   The mixer according to claim 2, wherein the current source generates the current by one transconductance stage provided in common to the outputs. The charge sub-sampling circuit includes a + -side path and a −-side path of differential outputs connected to the output of the current source,
The + side path includes a first reference, an A2 switch, an A4 switch, an A2 switch, an A4 switch, and a first reference connected in series from the input side to the output side. A first A3 switch and a first capacitor respectively connected between the voltage points;
The − side path includes a second reference, an A5 switch, an A6 switch, an A8 switch, a connection between the A6 switch and the A8 switch, which are connected in series from the input side to the output side. An A7th switch and a second capacitor respectively connected between the voltage points;
The frequency of the carrier = the sampling frequency = Fs, and the number of the charge sub-sampling circuits is m.
The first A1 switch is ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the A5 switch is ON / OFF controlled by a second rectangular signal that is 180 ° out of phase with the first rectangular signal.
The A2 switch and the A6 switch are ON / OFF controlled by an A1 digital signal having a cycle of N × m / Fs,
The A4 switch and the A8 switch are ON / OFF controlled by an A2 digital signal having a cycle of N × m / Fs,
The A3 switch and the A7 switch are ON / OFF controlled by an A3 digital signal having a cycle of N × m / Fs,
Periods T1, T2, and T3 in which the total is the period are provided in order during one period of the A1 to A3 digital signals,
During the period T1, the A1 digital signal is a series of 1 and 0, while the A2 digital signal and the A3 digital signal are 0,
During the period T2, the A2 digital signal becomes 1, while the A1 digital signal and the A3 digital signal become 0,
2. The mixer according to claim 1, wherein the A3 digital signal becomes 1 and the A1 digital signal and the A2 digital signal become 0 during the period T < b > 3. The charge sub-sampling circuit includes a B1 switch, includes a + side path of a differential output connected to the output of the current source via the B1 switch, a B2 switch, and passes through the B2 switch. A -side path connected to the output of the current source
The + side path includes a first + side path and a second + side path provided in parallel between the B1 switch and the + output terminal of the differential output,
The − side path includes a first side path and a second side path provided in parallel between the B2 switch and the − output terminal of the differential output,
The first + side path includes a B3 switch and a B5 switch connected in series from the input side to the output side, between the B3 switch and the B5 switch, and a location of the first reference voltage. A first B4 switch and a first capacitor connected to each other,
The second + side path includes a second reference voltage position between the B6 switch and the B8 switch, the B6 switch, and the B8 switch connected in series in order from the input side to the output side. And a second B7 switch and a second capacitor respectively connected between
The first-side path includes a third reference voltage between a B9 switch and a B11 switch connected in series from the input side to the output side, between the B9 switch and the B11 switch, and A third B10 switch and a third capacitor connected to each other,
The second side path includes a B12 switch and a B14 switch connected in series in order from the input side to the output side, between the B12 switch and the B14 switch, and a fourth reference voltage. Each having a B13 switch and a fourth capacitor connected to each other,
The frequency of the carrier = the sampling frequency = Fs, and the number of the charge sub-sampling circuits is m.
The first B1 switch is ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the second B2 switch is ON / OFF controlled by a second rectangular signal that is 180 ° out of phase with the first rectangular signal.
The B3 switch and the B9 switch are ON / OFF controlled by a B1 digital signal having a cycle of N × m / Fs.
The B6 switch and the B12 switch are ON / OFF controlled by a B2 digital signal having a cycle of N × m / Fs,
The B5 switch, B8 switch, B11 switch, and B14 switch are ON / OFF controlled by a B3 digital signal having a cycle of N × m / Fs,
The B4 switch, the B7 switch, the B10 switch, and the B13 switch are ON / OFF controlled by a B4 digital signal having a cycle of N × m / Fs.
Periods T1, T2, and T3 in which the total is the period are provided in order during one period of the B1 to B4 digital signals,
During the period T1, the B1 digital signal and the B2 digital signal are in a series of 1 and 0, and the B1 digital signal and the B2 digital signal are not 1 at the same time, while the B3 The digital signal and the B4th digital signal are 0,
During the period T2, the B3 digital signal becomes 1, while the B1 digital signal, the B2 digital signal, and the B4 digital signal become 0,
The B4 digital signal becomes 1 during the period T3, while the B1 digital signal, the B2 digital signal, and the B3 digital signal become 0 during the period T3. Mixer. The charge sub-sampling circuit includes a C1 switch and a C2 switch, a first + side path and a second side path connected to the output of the current source via the C1 switch, and the C2 switch. A first side path and a second side path connected to the output of the current source,
Wherein the 1+ path is provided between the first C1 switches and differential output of the + output terminal, which is connected in series in this order toward the input side to the output side, and a second C3 switch and the C5 switch, A C4 switch and a first capacitor connected between the C3 switch and the C5 switch and between the first reference voltage and the first capacitor, respectively.
The first-side path includes a C6 switch and a C8 switch connected in series from the input side to the output side between the C2 switch and the negative output terminal of the differential output. A C7 switch and a second capacitor connected between the C6 switch and the C8 switch and between the second reference voltage and the second capacitor, respectively.
The second + side path includes a C10 switch and a C5 switch connected in series from the input side to the output side between the C2 switch and the + output terminal, and A C4 switch and the first capacitor;
The second side path includes a C9 switch and a C8 switch connected in series from the input side to the output side between the C1 switch and the -output terminal. The C7 switch and the second capacitor;
The frequency of the carrier = the sampling frequency = Fs, and the number of the charge sub-sampling circuits is m.
The first C1 switch is ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the second C2 switch is ON / OFF controlled by a second rectangular signal that is 180 ° out of phase with the first rectangular signal.
The C3 switch and the C6 switch are ON / OFF controlled by a C1 digital signal having a cycle of N × m / Fs,
The C9 switch and the C10 switch are ON / OFF controlled by a C2 digital signal having a cycle of N × m / Fs,
The C5 and C8 switches are ON / OFF controlled by a C3 digital signal having a cycle of N × m / Fs,
The C4 switch and the C7 switch are ON / OFF controlled by a C4 digital signal having a cycle of N × m / Fs,
Periods T1, T2, and T3 in which the total is the period are provided in order during one period of the C1 to C4 digital signals,
During the period T1, the C1 digital signal and the C2 digital signal are in a series of 1 and 0, and the C1 digital signal and the C2 digital signal are not 1 at the same time, while the C3 The digital signal and the C4th digital signal are 0,
During the period T2, the C3 digital signal becomes 1, while the C1 digital signal, the C2 digital signal, and the C4 digital signal become 0,
2. The C4 digital signal becomes 1 during the period T3, while the C1 digital signal, the C2 digital signal, and the C3 digital signal become 0. Mixer. The charge sub-sampling circuit includes a + -side path and a −-side path of differential outputs connected to the output of the current source,
The + side path includes a first reference, a D2 switch, a D4 switch, a D2 switch, a D4 switch, and a first reference connected in series from the input side to the output side. A third D3 switch and a first capacitor, each connected between the voltage points;
The − side path includes a second reference, a D5 switch, a D6 switch, a D8 switch, a D6 switch, a D8 switch, and a second reference connected in series from the input side to the output side. A D7th switch and a second capacitor respectively connected between the voltage points;
The frequency of the carrier = the sampling frequency = Fs, and the number of the charge sub-sampling circuits is m.
The first D1 switch is ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the D5 switch is ON / OFF controlled by a second rectangular signal that is 180 degrees out of phase with the first rectangular signal.
The D2 switch is ON / OFF controlled by a D1 digital signal having a cycle of N × m / Fs.
The D6 switch is ON / OFF controlled by a D2 digital signal having a cycle of N × m / Fs,
The D4 switch and the D8 switch are ON / OFF controlled by a D3 digital signal having a cycle of N × m / Fs,
The D3 switch and the D7 switch are ON / OFF controlled by a D4 digital signal having a cycle of N × m / Fs,
Periods T1, T2, and T3 in which the total is the period are provided in order during one period of the D1 to D4 digital signals,
During the period T1, the D1 digital signal and the D2 digital signal are in a series of 1 and 0, while the D3 digital signal and the D4 digital signal are 0,
During the period T2, the D3 digital signal becomes 1, while the D1 digital signal, the D2 digital signal, and the D4 digital signal become 0,
The D4 digital signal becomes 1 during the period T3, while the D1 digital signal, the D2 digital signal, and the D3 digital signal become 0 during the period T3. Mixer. The charge sub-sampling circuit includes a + -side path and a −-side path of differential outputs connected to the output of the current source,
The + side path includes an E1 switch and an E3 switch connected in series from the input side to the output side, between the E1 switch and the E3 switch, and a location of the first reference voltage. Each having a second E2 switch and a first capacitor,
The negative side path includes an E4 switch and an E6 switch connected in series in order from the input side to the output side, between the E4 switch and the E6 switch, and a location of the second reference voltage. Each having an E5th switch and a second capacitor connected between
The frequency of the carrier = the sampling frequency = Fs, and the number of the charge sub-sampling circuits is m.
The E1 switch is ON / OFF controlled by an E1 digital signal having a cycle of N × m / Fs.
The E4 switch is ON / OFF controlled by an E2 digital signal having a cycle of N × m / Fs,
The E3 switch and the E6 switch are ON / OFF controlled by an E3 digital signal having a cycle of N × m / Fs,
The E2 switch and the E5 switch are ON / OFF controlled by an E4 digital signal having a cycle of N × m / Fs,
Periods T1, T2, and T3 in which the total is the period are provided in order during one period of the E1 to E4 digital signals,
During the period T1, the E1 digital signal and the E2 digital signal are in a series of 1s and 0s, and the E1 digital signal and the E2 digital signal do not become 1 simultaneously, while the E3 digital signal The digital signal and the E4th digital signal are 0,
During the period T2, the E3 digital signal becomes 1, while the E1 digital signal, the E2 digital signal, and the E4 digital signal become 0,
2. The E4 digital signal becomes 1 during the period T3, while the E1 digital signal, the E2 digital signal, and the E3 digital signal become 0. Mixer.   10. The mixer according to claim 5, wherein T1 = N * (m-1) / Fs, T2 = 0.5 * N / Fs, and T3 = 0.5 * N / Fs. .   The mixer according to any one of claims 5, 7, 8, and 9, wherein the first capacitor and the second capacitor have the same capacitance. The capacitances of the first capacitor and the third capacitor are equal to each other,
The capacitances of the second capacitor and the fourth capacitor are equal to each other,
The mixer according to claim 6, wherein the first capacitor and the third capacitor, and the second capacitor and the fourth capacitor have different capacities. The charge sub-sampling circuit includes a first output side of a differential output connected to the first output of the current source through the F1 switch, the F2 switch, the F9 switch, the F10 switch, and the F1 switch. And a first-side path of a differential output connected to the second output of the current source via the F2 switch, and the first output of the current source connected to the first output of the current source via the F9 switch. A differential output second side path and a differential output second side path connected to the second output of the current source via the F10 switch;
The first + side path includes the F1 switch, the F3 switch, and the F5 switch connected in series in order from the input side to the output side, and between the F3 switch and the F5 switch. A first F4 switch and a first capacitor respectively connected between the first reference voltage and the first reference voltage;
  The first-side path includes the F2 switch, the F6 switch, and the F8 switch connected in series in order from the input side to the output side, and includes the F6 switch and the F8 switch. And a second capacitor connected to each other between the second reference voltage and the second reference voltage,
  The 2+ side path includes the F10 switch, the F3 switch, and the F5 switch connected in series in order from the input side to the output side, and includes the F4 switch and the first capacitor. And
  The second-side path includes the F9 switch, the F6 switch, and the F8 switch connected in series in order from the input side to the output side, and includes the F7 switch and the second switch. With a capacitor,
  The frequency of the carrier = the sampling frequency = Fs, and the number of the charge sub-sampling circuits is m.
  The F1 switch and the F2 switch are ON / OFF controlled by a first rectangular signal having a frequency of Fs, and the F9 switch and the F10 switch have a second rectangular shape that is 180 degrees out of phase with the first rectangular signal. ON / OFF is controlled by signal,
  The F3 switch and the F6 switch are ON / OFF controlled by a F1 digital signal having a cycle of N × m / Fs,
  The F5 switch and the F8 switch are ON / OFF controlled by a F2 digital signal having a cycle of N × m / Fs,
  The F4 and F7 switches are ON / OFF controlled by a F3 digital signal having a cycle of N × m / Fs.
  Periods T1, T2, and T3 in which the total is the period are provided in order during one period of the F1 to F3 digital signals,
  During the period T1, the F1 digital signal is a series of 1 and 0, and the F2 digital signal and the F3 digital signal are 0,
  During the period T2, the F2 digital signal becomes 1, while the F1 digital signal and the F3 digital signal become 0,
  During the period T3, the F3 digital signal becomes 1, while the F1 digital signal and the F2 digital signal become 0.
  The mixer according to claim 1, wherein the first output and the second output of the current source are differential outputs.

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