JP4361666B2 - Display device and drive circuit thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device having a plurality of display pixels and a drive circuit thereof, and more particularly to a display device that performs gradation display of display pixels and a drive circuit thereof.
[0002]
[Prior art]
One of display devices having a plurality of display pixels is a fluorescent display tube. A fluorescent display tube is an electron tube that displays a desired pattern by causing electrons emitted from a cathode to collide with phosphors applied on a plurality of anodes in a vacuum vessel (envelope) that is transparent on one side. . FIG. 6 is a block diagram showing the configuration of a conventional general fluorescent display tube and its driving circuit. In FIG. 1, a fluorescent display tube 1 includes a plurality of anodes 4 in which a phosphor 3 is applied in an envelope 2 that has been evacuated, a cathode 5 that is spaced apart from the anode 4, and an anode 4 and a cathode. 5 and a grid 6 for controlling electrons emitted from the cathode 5.
[0003]
Here, the cathode 5 is a filament coated with an electron emission material, and is connected to an AC power source 8 through a transformer 7 with a center tap, and is connected to the ground and the negative side of the DC power source 9 through the center tap of the transformer 7. It is connected. The grid 6 has a mesh shape and is connected to the positive side of the DC power supply 9. Each anode 4 is connected to a driver circuit 62 of the drive circuit 60.
[0004]
The conventional drive circuit 60 is configured to turn on / off a positive voltage applied to each anode 4 based on the memory unit 61 that holds the input display data for a predetermined display period and the display data output from the memory unit 61. And a driver circuit 62 that is turned off. The serial signal line 20 is connected to the data input terminal of the memory unit 61, and the display data serially input to the data input terminal is converted into parallel data and held in the memory 61, and data is displayed according to a read signal (not shown). Output as parallel data from the output terminal. The driver circuit 62 drives the anode 4 of the pixel to be displayed based on the parallel data output from the memory unit 61 and causes the phosphor 3 on the anode 4 to emit light.
[0005]
[Problems to be solved by the invention]
In the conventional display device configured as described above, in order to change the luminance of the pixel, the apparent luminance is changed by changing the ratio of the light emission time and the extinction time of the pixel within the time when an afterimage occurs in the human eye. The method to be used was used. As long as it is limited to the fluorescent display tube, there is a method of changing the voltage applied to the grid 6 or the anode 4, but these methods all change the luminance of the entire screen and display individual pixels in gradation. It wasn't.
An object of the present invention is to provide a display device capable of gradation display of individual pixels.
[0006]
[Means for Solving the Problems]
To solve the problems described above, the driving circuit used in the display device of the present invention, a memory for receiving and storing pixel information represented by two bits for each display pixel, at most 2 ^two pulses of different pulse widths and a pulse generating circuit for outputting a signal, and inputs the most two ^two pulse signals are outputted from the pixel information and the pulse generation circuit which is stored in the memory, each display pixel of one pulse signal based on the pixel information A pulse signal selection circuit that selects and outputs the signal, and a driver circuit that drives each display pixel for a period corresponding to the pulse width of the pulse signal output from the pulse signal selection circuit in a predetermined display period, and a pulse generation circuit The pulse width of the pulse signal output from the pulse width setting signal input from the outside to the pulse generation circuit and the display mode of the display pixel are set to the gradation display mode and the pixel information. It characterized by being set by a combination of the display mode signal to switch to the screen synthesis mode for displaying the calculation result of the screen made of 2 bit of the data of the screen and the pixel information to make the data of the bit.
[0008]
One configuration example of the display device according to the present invention includes a plurality of anodes coated with phosphors, a grid provided above the anodes, and a space above the grids. And a driving circuit for lighting and driving a plurality of display pixels composed of a plurality of anodes coated with a phosphor, and the driving circuit described above is used as the driving circuit. Yes. An example of the display device according to the present invention includes a plurality of anodes coated with phosphors, a grid provided above the anodes, and a space above the grids. And a driving circuit for lighting and driving a plurality of display pixels composed of a plurality of anodes coated with phosphors, and the driving circuit is 2 ² for each display pixel. A screen for displaying pixel information represented by bits and a display mode of a display pixel by a gradation display mode and a screen created by the first bit data of the pixel information and a result of calculating a screen created by the second bit data of the pixel information and a display mode signal for switching to the synthesis mode is entered, by a combination of the display mode signal and the pixel information from the most 2 ^two pulse widths indicating the different lighting periods during a given display period Duration of the selected pulse width Te, is configured to display each display pixel in the synthesis of 2 ² gradations or two screens by lighting the display pixel.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, a reference example that is the first stage of the embodiment of the present invention will be described.
FIG. 1 is a block diagram showing a reference example of the present invention. The same reference numerals are given to the same parts as those in FIG. The driving circuit 10 of this reference example is different from the driving circuit 60 of FIG. 6 described above in that the memory unit 11 is a pixel that indicates the luminance of each pixel represented by n bits (n is an integer of 2 or more) for each display pixel. The information can be stored, the pulse generation circuit 13 that outputs at most 2n pulse signals having different pulse widths, and the pixel information stored in the memory unit 11 and the 2n pieces at most output from the pulse generation circuit 13 A pulse signal selection circuit 14 is provided which receives a pulse signal as input and selects and outputs one of the pulse signals for each display pixel based on pixel information.
[0010]
The drive circuit 10 includes a memory unit 11, a pulse generation circuit 13, a pulse signal selection circuit 14, and a driver circuit 15. The number of bits n of pixel information for each display pixel is 2 bits, and the drive output The score is 144 points. In this case, the memory unit 11 includes a memory A11a and a memory B11b each storing 144-bit information, and each of these memories 11a and 11b includes one data input terminal and 144 data output terminals. ing.
[0011]
Here, the signal line 21 for serially inputting the first bit data (pixel information 1) of the pixel information is connected to the data input terminal of the memory A11a, and the second bit (pixel information) of the pixel information is connected to the data input terminal of the memory B11b. A signal line 22 for serially inputting pixel information 2) data is connected. In these memories 11a and 11b, 144-bit serial data input to the data input terminal is converted into parallel data and held, and output as 144-bit parallel data from the data output terminal in response to a read signal (not shown). It is configured as follows. Such memories 11a and 11b can be easily realized by a known technique using a shift register and a latch, for example.
[0012]
The pulse generation circuit 13 includes two input terminals and four output terminals. A signal line 23 for inputting a pulse width setting signal is connected to one input terminal, and a display cycle signal is input to the other input terminal. A signal line 24 is connected. Here, the pulse width setting signal is a signal in which two pulses are output during the display cycle as shown in FIG. 2A, and the first pulse has a time t1 from the start of the display cycle. The second pulse is output immediately before t2 so that it falls when the time from the start of the display cycle reaches t2. The display cycle signal is a signal in which a pulse is output at the start of the display cycle T as shown in FIG.
[0013]
The pulse generation circuit 13 generates four types of pulse signals shown in (c) to (f) of FIG. 2 for determining the lighting time of the pixels during the display cycle, and outputs them from the four output terminals. Here, (c) is a signal (hereinafter referred to as gradation signal 1) whose output is at least “L” during which the pixel remains off during the display cycle, and (f) is a pixel during the display cycle. Is an “H” output signal (hereinafter referred to as gradation signal 4) at least during the display cycle. Further, (d) and (e) are signals whose pulse width is set by the pulse width setting signal and the display cycle signal.
[0014]
In this case, as shown in (e), the pulse generation circuit 13 captures the rise of the pulse of the display cycle signal and changes the output from “H” to “L”, and the fall of the first pulse of the pulse width setting signal. , And the output from “L” to “H” (hereinafter referred to as gradation signal 3), and the rising edge of the display period signal as shown in FIG. “L” is generated, a signal (hereinafter referred to as gradation signal 2) is generated from “L” to “H” by detecting the falling edge of the second pulse of the pulse width setting signal, and the gradation is generated. Output together with signals 1 and 4.
[0015]
The pulse signal selection circuit 14 receives four pulse signals output from the pulse generation circuit 13 and pixel information of each display pixel output from the memory A 11a and the memory B 11b, and outputs a pulse signal for each display pixel based on the pixel information. Is selected and output. In this case, as shown in FIG. 3, the relationship between the pixel information input from the memory A11a and the memory B11b and the output signal of the pulse signal selection circuit 14 is such that the gradation signal 1 is when both the memory A11a and the memory B11b are 0. When the memory A11a is 1 and the memory B11b is 0, the gradation signal 2 is obtained. When the memory A11a is 0 and the memory B11b is 1, the gradation signal 3 is obtained. When both the memory A11a and the memory B11b are 1, the gradation signal 2 is obtained. Each of the signals 4 is configured to be output.
[0016]
Such a pulse signal selecting circuit 14, for example, can be easily realized by placing 1 44 known multiplexers. In this case, the four pulse signals output from the pulse generation circuit 13 are distributed to 144 multiplexers having four inputs, and the 144-bit parallel data output from the memory A11a and the memory B11b are allocated one bit at a time. What is necessary is just to make it input into two selection signal inputs of each multiplexer. In this way, 144 pulse signals selected based on the pixel information are output.
[0017]
The driver circuit 15 is configured to drive the anode 4 of the fluorescent display tube 1 for a period corresponding to the pulse width of the pulse signal output from the pulse signal selection circuit 14. In this case, the driver circuit 15 has 144 points of input and 144 points of output corresponding to these inputs on a one-to-one basis. The 144 points of input are paired with the 144 points of output of the pulse signal selection circuit 14. 1 is connected. Further, 144 outputs are connected to the anode 4 of the fluorescent display tube 1 on a one-to-one basis. Here, the fluorescent display tube 1 is the same as that described with reference to FIG. Further, the connection of the AC power supply 8 to the cathode 5 and the connection of the DC power supply 9 to the grid 6 are the same as in FIG.
[0018]
Next, the operation of the drive circuit according to this reference example will be described.
In FIG. 1, 144 bits of 2-bit pixel information is input and held in the memory unit 11 from the outside. In this case, the first bit of pixel information is input to the memory A11a, and the second bit of pixel information is input to the memory B11b. The pixel information for 144 pixels held in the memory unit 11 is simultaneously output for 144 pixels by a read signal (not shown) and is input to the pulse signal selection circuit 14.
[0019]
On the other hand, when a pulse width setting signal and a display cycle signal are input to the pulse generation circuit 13 from the outside, gradation signals 1 to 4 are generated and input to the pulse signal selection circuit 14. The gradation signals 1 to 4 input to the pulse signal selection circuit 14 are selected for each pixel based on the previously input pixel information, are simultaneously output for 144 pixels, and are input to the driver circuit 15. The driver circuit 15 drives the corresponding anodes 4 independently for a period corresponding to the pulse width of each gradation signal in accordance with the input gradation signal for 144 pixels.
[0020]
According to this reference example , the driving time of the anode 4 corresponding to the display pixel of the fluorescent display tube 1 can be selected from four by inputting pixel information of 2 bits for each display pixel. Since the luminance of the fluorescent display tube is proportional to the lighting time during the display cycle when the voltage applied to the grid and the anode is constant, this drive circuit can display the luminance in four gradations for each display pixel. For example, if the pulses of the pulse width setting signal are equally spaced, the luminance can be 0%, 33%, 67%, and 100%.
[0021]
Thus, since the pulse width of the gradation signal is determined by the pulse width setting signal, any gradation can be realized using t1 and t2 in the pulse width setting signal as parameters. That is, among the four gradation signals, the two signals excluding the signal indicating the maximum luminance and the luminance 0 can set the lighting time during the display cycle by the pulse width setting signal input from the outside. As a result, it is possible not only to make the luminance change equal intervals, but also to increase the luminance resolution of a high luminance region or a low luminance region. For example, the luminance can be set to 0%, 10%, 20%, and 100% in order to increase the luminance resolution in a low region. Further, since the gradation signal for setting the lighting time is identified by counting the number of pulses of the pulse width setting signal, the number of signal lines for the pulse width setting signal may be minimized.
[0022]
In this reference example, the number of drive output points has been described as 144, but the present invention is not limited to this.
[0023]
Next, an embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing an embodiment of the present invention. The same reference numerals are given to the same parts as those in FIG. The driving circuit 40 of this embodiment is different from the driving circuit 10 of FIG. 1 described above in that it is possible to switch between gradation display and screen composition. In this case, the screen composition is such that the first bit and the second bit of the pixel information are each one screen, a screen created from the first bit data (hereinafter referred to as screen 1) and a screen created from the second bit data (hereinafter referred to as “screen 1”). The result of calculating (screen 2) is displayed. As the composite screen, only screen 1, only screen 2, logical sum of screen 1 and screen 2, logical product of screen 1 and screen 2, and exclusive logical sum of screen 1 and screen 2 can be displayed.
[0024]
1 except that the pulse generation circuit 43 is different from the pulse generation circuit 13 of FIG. 1 and that the signal line 25 for inputting the display mode signal from the outside to the pulse generation circuit 43 is connected. This is the same as the drive circuit 10. Here, the pulse generation circuit 43 is configured to switch the gradation signals output to the four output terminals according to the display mode signal. FIG. 5 shows the relationship between the display mode signal in the pulse generation circuit 43 and the gradation signals output to the four output terminals. The pulse generation circuit 43 uses the pixel information “00” (memory) in the pulse signal selection circuit 14. Gradation display for the output terminal connected to the input terminal selected when A = 0, memory B = 0), Screen 1 only, Screen 2 only, Screen 1 and Screen 2 OR (hereinafter referred to as OR) ), Gradation signal 1 is output in all cases of logical product of screen 1 and screen 2 (hereinafter referred to as AND) and exclusive OR of screen 1 and screen 2 (hereinafter referred to as EXOR).
[0025]
In addition, for the output terminal connected to the input terminal selected when the pixel information is “01” (memory A = 1, memory B = 0), the gradation signal 2 is ORed with only the screen 1 for gradation display. And the gradation signal 4 is output when only the screen 2 is ANDed. For the output terminal connected to the input terminal selected when the pixel information is “10” (memory A = 0, memory B = 1), the gradation signal 3 is ORed with only the screen 1 for gradation display. A gradation signal 4 is output when the gradation signal 1 is AND and EXOR only with the screen 2. With respect to the output terminal connected to the input terminal selected when the pixel information is “11” (memory A = 1, memory B = 1), the gradation display, screen 1 only, screen 2 only, and OR and AND The gradation signal 1 is output when the adjustment signal 4 is EXOR.
[0026]
According to this embodiment, the gradation display of the fluorescent display tube and the screen composition can be switched, so that the expressive power of the fluorescent display tube can be greatly improved. In addition, since the screen composition is performed by the drive circuit, there is no need to perform screen composition calculation externally, and the processing is simplified.
[0027]
In the embodiment of the present invention, the case where the drive output of the driver circuit 15 and the anode 4 are connected on a one-to-one basis has been described. However, the present invention is not limited to this. Can be used for dynamic driving in which the number of display pixels can be increased by switching the output data of the driver circuit 15 in response to scanning of a plurality of grids. In this case, the pulse width setting signal and the display cycle signal may be matched with the grid scan cycle.
[0028]
Further, the drive circuit may be constituted by one semiconductor integrated circuit, and the semiconductor chip on which the semiconductor integrated circuit is formed may be disposed inside the fluorescent display tube. In this case, there is no need to provide an external drive circuit, so that an effect of simplifying and downsizing the display device can be obtained. The display device to which the drive circuit of the present invention can be applied is not limited to the fluorescent display tube, and the light emission time and the quenching time within the time when the afterimage occurs using the afterimage phenomenon of the human eye. Any display device that changes the luminance by changing the ratio may be used.
[0029]
【The invention's effect】
As described above, the display device of the present invention, a memory and a pulse generating circuit for outputting different most 2 ^two pulse signals having a pulse width of receiving and storing pixel information represented by two bits for each display pixel When, and most two ^two pulse signals are outputted from the pixel information and the pulse generation circuit which is stored in the memory as an input, and outputs the selected for each display pixel of one of the pulse signal based on the pixel information pulses and a signal selection circuit, the period corresponding to the pulse width of the pulse signal outputted from the pulse signal selecting circuit in a predetermined display period, and a driver circuit for driving the display pixels, the pulse signal output from the pulse generating circuit The pulse width is a pulse width setting signal input to the pulse generation circuit from the outside and a display mode of the display pixel which is created by the gradation display mode and the first bit data of the pixel information. And so it was assumed to be set by a combination of the display mode signal to switch to the screen synthesis mode for displaying the calculation result of the screen made of 2 bit data of pixel information, the luminance of 2 ² gradations individual pixels In addition to being able to display, it is possible to switch between gradation display and screen composition, and the expressive power of the display device can be greatly improved. In addition, since the screen composition is performed by the drive circuit, there is no need to perform screen composition calculation externally, and the processing is simplified.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a reference example of the present invention.
2 is a waveform diagram of input / output signals in the pulse generation circuit of FIG. 1. FIG.
3 is a table showing the relationship between pixel information and output signals in the pulse signal selection circuit of FIG. 1. FIG.
FIG. 4 is a block diagram showing an embodiment of the present invention.
5 is a table showing a relationship between a display mode and an output signal in the pulse generation circuit of FIG.
FIG. 6 is a block diagram showing the configuration of a conventional general fluorescent display tube and its drive circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Fluorescent display tube, 2 ... Envelope, 3 ... Phosphor, 4 ... Anode, 5 ... Cathode, 6 ... Grid, 7 ... Transformer, 8 ... AC power supply, 9 ... DC power supply, 10, 40, 60 ... Drive Circuit 11, memory unit 11 a, 11 b, 61 memory, 13, 43 pulse generation circuit 14 pulse signal selection circuit 15, 62 driver circuit 20, 21, 22, 23, 24, 25 signal line.

Claims (3)

A drive circuit for a display device having a plurality of display pixels,
A memory for receiving and storing pixel information represented by 2 bits for each display pixel;
A pulse generating circuit for outputting different most 2 ^two pulse signals having the pulse width,
As input and at most 2 ^two of the pulse signal outputted from the pulse generating circuit and the pixel information stored in said memory, select one of the pulse signal for each of the display pixel based on the pixel information And a pulse signal selection circuit to output,
A driver circuit that drives each display pixel for a period corresponding to a pulse width of the pulse signal output from the pulse signal selection circuit in a predetermined display period ;
The pulse width of the pulse signal output from the pulse generation circuit includes a pulse width setting signal input to the pulse generation circuit from the outside, a display mode of the display pixel, a gradation display mode, and a first bit of the pixel information. And a display mode signal for switching to a screen composition mode for displaying a result obtained by calculating a screen generated from the second bit data of the pixel information and a screen generated from the pixel information. . A fluorescent display tube having a plurality of anodes coated with phosphors in the envelope, a grid spaced apart above the anodes, and a cathode spaced apart above the grids; ,
In a display device comprising a drive circuit for driving and lighting a plurality of display pixels composed of a plurality of anodes coated with the phosphor,
The display device according to claim 1, wherein the drive circuit is the drive circuit according to claim 1. A fluorescent display tube having a plurality of anodes coated with phosphors in the envelope, a grid spaced apart above the anodes, and a cathode spaced apart above the grids; ,
A display device comprising a drive circuit for lighting and driving a plurality of display pixels composed of a plurality of anodes coated with the phosphor,
2 for each display pixel ² The pixel information represented by bits and the display mode of the display pixel are calculated as a result of calculating a gradation display mode, a screen created by the first bit data of the pixel information, and a screen created by the second bit data of the pixel information. A display mode signal for switching to the screen composition mode to be displayed is input, and at most 2 indicating different lighting periods in a predetermined display cycle. ² Each display pixel is turned on by turning on the display pixel for a period of a pulse width selected from the combination of the pixel information and the display mode signal among the pulse widths. ² A display device comprising a driving circuit for displaying by gradation or two-screen composition.

Images