JP4359280B2 - PLL circuit - Google Patents

Description

The present invention, PLL (Phase Locked Loop) circuits relates to.

  Conventionally, a PLL circuit that synchronizes the phase of an output signal with reference to an input signal and multiplies the frequency of the input signal and outputs it from a voltage controlled oscillator (VCO) has been used in various fields. (For example, refer to Patent Documents 1 to 3.)

  FIG. 11 is a diagram showing a configuration of a conventional general PLL circuit. FIG. 11 shows a PLL circuit 101A configured such that the loop filter 104A uses the power supply potential Vdd as a potential reference.

  The phase comparator 102 compares the phases of the reference signal (clock signal) REF and the feedback signal FB from the frequency divider 106 to detect the phase difference between them. Specifically, the phase comparator 102 detects the phase difference of the feedback signal FB with respect to the reference signal REF, and outputs an up / down signal corresponding to the detected phase difference to the charge pump 103.

  The charge pump 103 charges or discharges the loop filter 104A (more specifically, a capacitor (not shown) in the loop filter 104A) according to the up / down signal. Loop filter 104A is connected between voltage-controlled oscillator (VCO) 105A and power supply potential Vdd. The VCO 105A oscillates the output signal FVCO at an oscillation frequency corresponding to the input voltage, using the voltage VCTL of the node NA determined based on the amount of charge accumulated in the loop filter 104A as an input voltage.

  When the down signal is input, the charge pump 103 injects electric charge into the loop filter 104A and raises the voltage VCTL. On the contrary, when the up signal is input, the charge pump 103 extracts the charge from the loop filter 104A and lowers the voltage VCTL. The oscillation frequency of the VCO 105A changes according to the input voltage, and the oscillation frequency increases as the input voltage decreases. Therefore, in the case of a down signal, the voltage VCTL as the input voltage of the VCO 105A increases, and the oscillation frequency of the output signal FVCO decreases. In the case of an up signal, the voltage VCTL decreases and the oscillation frequency of the output signal FVCO increases.

  The frequency divider 106 divides the oscillation output signal FVCO of the VCO 105 </ b> A and outputs a feedback signal FB to the phase comparator 102. In this way, a series of feedback operations are repeated until the phases of the reference signal REF and the feedback signal FB coincide with each other, and finally the phases of both coincide. This state is called a locked state.

  FIG. 12 is a diagram showing another configuration of a conventional general PLL circuit, and shows a PLL circuit 101B configured such that the loop filter 104B uses a reference potential (eg, ground potential) as a potential reference. . 12, blocks having the same functions as those shown in FIG. 11 are denoted by the same reference numerals, and redundant description is omitted.

  The loop filter 104B is connected between a voltage controlled oscillator (VCO) 105B and a reference potential. The VCO 105B oscillates the output signal FVCO at an oscillation frequency corresponding to the input voltage using the voltage VCTL of the node NB determined based on the amount of charge accumulated in the loop filter 104B as an input voltage. In the VCO 105B, the oscillation frequency of the output signal FVCO increases as the input voltage increases.

  In the PLL circuit 101B, when the down signal is input, the charge pump 103 extracts the charge from the loop filter 104B and decreases the voltage VCTL. Conversely, when the up signal is input, the charge pump 103 injects electric charge into the loop filter 104B and raises the voltage VCTL. Therefore, in the case of a down signal, the voltage VCTL decreases and the oscillation frequency of the output signal FVCO decreases. In the case of an up signal, the voltage VCTL increases and the oscillation frequency of the output signal FVCO increases. Other operations are the same as those of the PLL circuit 101A shown in FIG.

Japanese Patent Laid-Open No. 11-112333 JP-A-2-244822 JP-A-10-56379

  Here, in the conventional PLL circuit as shown in FIGS. 11 and 12, the VCO 105A (105B) has a higher frequency than the desired oscillation frequency in the process in which the output signal FVCO reaches the desired oscillation frequency immediately after the power is turned on. May output the output signal FVCO. If the VCO 105A (105B) oscillates the output signal FVCO having a frequency higher than the operable frequency of the frequency divider, the feedback signal FB output from the frequency divider 106 is fixed to a certain signal level. . As a result, the phase comparator 102 determines that the phase of the feedback signal FB is delayed with respect to the reference signal REF, and is controlled to increase the oscillation frequency of the output signal FVCO.

  That is, as shown in FIG. 13, in the convergence process of the output frequency in the PLL circuit, when the VCO oscillates an output signal having a frequency higher than the operable frequency (frequency that can be divided) FMAX after the power is turned on. The output signal FVCO does not converge to the desired frequency PLL Target but enters a divergence state (region DIV shown in FIG. 13). Finally, the output signal from the PLL circuit is fixed at the oscillation limit frequency of the VCO (the frequency at which the input voltage is 0 V for the VCO 105A and the frequency at which the input voltage is the power supply voltage Vdd for the VCO 105B). Will be.

  In order to prevent such a malfunction of the PLL circuit, conventionally, the operable frequency of the frequency divider is designed to be wider than the oscillation frequency of the VCO so that the output signal FVCO of the VCO converges to a desired frequency. It was.

  However, the frequency divider is generally composed of a logic circuit, and its operable frequency is limited. On the other hand, the VCO can be configured to output a very high frequency with a small amplitude by using an analog element such as a differential circuit or an inductance. Therefore, when a PLL circuit is configured by combining these circuits, it is considered that the operable frequency of the frequency divider is lower than the oscillation frequency of the VCO. In order to prevent malfunction of the PLL circuit, Care must be taken in the design of the loop filter and charge pump so that the oscillation frequency does not exceed the operable frequency of the frequency divider. Further, when it is desired to widen the lock range in the PLL circuit, a circuit that makes the gains of the loop filter and the charge pump variable must be added. Therefore, the design man-hour and the circuit area increase.

  The present invention reliably prevents malfunction in the process of convergence of the oscillation frequency after power-on in the PLL circuit, and enables the output signal to oscillate at a desired oscillation frequency.

A PLL circuit according to the present invention detects a phase difference between a reference signal and a feedback signal and outputs an up / down signal according to the phase difference, and a charge pump circuit that outputs a voltage signal according to the up / down signal A loop filter that has a resistor element and a capacitor element provided between the output terminal of the charge pump circuit and the power supply line, and charges or discharges the capacitor element based on a voltage signal, and a loop filter A voltage-controlled oscillator that oscillates an output signal at an oscillation frequency corresponding to an input voltage based on the amount of accumulated charge. Furthermore, one of the source and the drain is connected to the connection point between the resistance element and the capacitor, the other of the source and the drain is connected to the power supply line , the gate of the transistor, and the input to the voltage controlled oscillator. And a control circuit that turns on the transistor when the input voltage is outside a predetermined range.

  According to the present invention, when the input voltage input to the voltage controlled oscillator becomes a voltage corresponding to the oscillation frequency exceeding the operable frequency of the divider, the oscillation frequency is within the operable frequency of the divider. Thus, the input voltage is controlled so that the voltage controlled oscillator can be controlled so as not to oscillate the output signal at an oscillation frequency equal to or higher than the operable frequency of the frequency divider.

  According to the present invention, when the input voltage input to the voltage controlled oscillator is outside the predetermined range, the charge amount accumulated by charging or discharging the loop filter is controlled, and the input voltage is within the predetermined range. The voltage is controlled to be As a result, the voltage controlled oscillator can be controlled so as not to oscillate the output signal at an oscillation frequency equal to or higher than a predetermined frequency, and the malfunction in the convergence process of the oscillation frequency of the PLL circuit is surely prevented, and the desired oscillation frequency And the output signal can be oscillated.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram illustrating a configuration example of a PLL circuit according to an embodiment of the present invention.
The PLL circuit 10 in this embodiment includes a phase comparator 20, a loop filter 30, a limiter circuit 40, a voltage controlled oscillator (VCO) 50, and a frequency divider 60.

  The phase comparator 20 receives a reference signal (clock signal) REF from the outside and a feedback signal FB from the frequency divider 106 and compares the phases thereof to detect a phase difference. The phase comparator 20 outputs the detected phase difference between the reference signal REF and the feedback signal FB to the loop filter 30. The loop filter 30 outputs a voltage corresponding to the output of the phase comparator 20 to the limiter circuit 40. Specifically, the loop filter 30 is charged or discharged according to the phase difference between the reference signal REF detected by the phase comparator 20 and the feedback signal FB, and outputs a voltage based on the accumulated charge amount.

  The limiter circuit 40 is connected between the loop filter 30 and the input terminal of the VCO 50 and performs control so that the voltage output from the loop filter 30 becomes a voltage within a predetermined range. When the output voltage of the loop filter 30 is not within a predetermined range, the limiter circuit 40 increases or decreases the output voltage by charging or discharging the loop filter 30 to a voltage within the predetermined range.

  The VCO 50 uses the output voltage of the loop filter 30 supplied via the limiter circuit 40 as an input voltage, and oscillates the output signal FVCO at an oscillation frequency corresponding to the input voltage. The output signal FVCO is output to the outside of the PLL circuit 10 and is output to the frequency divider 60 inside the PLL circuit 10. The frequency divider 60 divides the oscillation output signal FVCO of the VCO 50 and outputs a feedback signal FB to the phase comparator 20.

  In the PLL circuit 10, the loop filter 30 is charged or discharged according to the phase difference between the reference signal REF and the feedback signal FB obtained by the phase comparator 20. The voltage based on the amount of charge accumulated in the loop filter 30 is a voltage within a predetermined range, specifically, a voltage at which the oscillation frequency of the VCO 50 becomes the operable frequency of the frequency divider 60 (frequency that can be divided). In this case, it is supplied as it is to the VCO 50 as an input voltage.

  On the other hand, when the voltage based on the amount of charge accumulated in the loop filter 30 is a voltage outside a predetermined range, specifically, a voltage corresponding to an oscillation frequency exceeding the operable frequency of the frequency divider 60, the limiter circuit The electric charge is charged or discharged in the loop filter 30 by 40, and voltage control is performed so that the oscillation frequency of the VCO 50 becomes the operable frequency of the frequency divider 60. The controlled voltage is supplied to the VCO 50 as an input voltage.

  An output signal FVCO oscillated from the VCO 50 at an oscillation frequency corresponding to an input voltage that is changed based on the phase difference between the reference signal REF and the feedback signal FB is output to the outside and is also frequency-divided by the frequency divider 60 and fed back. The signal FB is output to the phase comparator 20. In this way, a series of feedback operations are repeated until the phases of the reference signal REF and the feedback signal FB coincide with each other, and finally the phases of both coincide. This state is called a locked state.

  FIG. 2A is a diagram illustrating a configuration example of the PLL circuit according to the present embodiment. FIG. 2A shows a PLL circuit 10A configured such that the loop filter 30A uses the power supply potential Vdd as a potential reference. In FIG. 2A, blocks having the same functions as the blocks shown in FIG.

  The phase comparator 20 compares the phases of the reference signal REF and the feedback signal FB from the frequency divider 60 to detect the phase difference between them. Specifically, the phase comparator 20 detects the phase difference of the feedback signal FB with respect to the reference signal REF, and outputs an up / down signal corresponding to the detected phase difference to the charge pump 11.

The charge pump 11 charges or discharges the loop filter 30A (more specifically, a capacitor (not shown) in the loop filter 30A) according to the up / down signal. The charge pump 11 includes a CMOS configuration including a current source 12, a P-type MOSFET (metal oxide semiconductor field effect transistor) 13 and an N-type MOSFET 14 between a power supply potential Vdd and a reference potential (for example, a ground potential), and a current. A source 15 is connected in series. Hereinafter, the P-type MOSFET is simply referred to as “PMOS”, and the N-type MOSFET is simply referred to as “NMOS”.
Loop filter 30A is connected between VCO 50A and power supply potential Vdd.

  The limiter circuit 40A can control the voltage VCTL of the node NA determined based on the amount of charge accumulated in the loop filter 30A by charging the loop filter 30A. The limiter circuit 40A has one comparator 41A and one PMOS 42A.

  The comparator 41A is for detecting whether or not the voltage VCTL at the node NA is equal to or lower than the reference voltage VREFA. The reference voltage VREFA and the voltage VCTL are supplied to one set of input terminals, and the comparison result is obtained. The corresponding voltage VOA is output from the output terminal. Here, the reference voltage VREFA is a voltage at which the oscillation frequency of the VCO 50A becomes the maximum operable frequency of the frequency divider 60, that is, the voltage corresponding to the operation limit of the frequency divider 60, as will be described later. The PMOS 42A has a source connected to the power supply potential Vdd and a drain connected to the node NA. Further, the output voltage VOA of the comparator 41A is supplied to the gate of the PMOS 42A.

  The VCO 50A oscillates the output signal FVCO at an oscillation frequency corresponding to the input voltage using the voltage VCTL of the node NA as an input voltage. The frequency divider 60 divides the oscillation output signal FVCO of the VCO 50 </ b> A and outputs a feedback signal FB to the phase comparator 20.

  Here, when the down signal is input, the charge pump 11 injects electric charge into the loop filter 30A and raises the voltage VCTL. Conversely, when the up signal is input, the charge pump 11 pulls out the charge from the loop filter 30A and lowers the voltage VCTL. Further, when the voltage VCTL is lower than the reference voltage VREFA, the limiter circuit 40A injects electric charge into the loop filter 30A to increase the voltage VCTL.

  In the VCO 50A, as shown in FIG. 2B, the oscillation frequency of the output signal FVCO changes according to the voltage VCTL as the input voltage, and the oscillation frequency increases as the voltage VCTL decreases. Therefore, when a down signal is input to the charge pump 11, the voltage VCTL increases and the oscillation frequency of the output signal FVCO decreases. When the up signal is input, the voltage VCTL decreases and the oscillation frequency of the output signal FVCO increases. In this way, a series of feedback operations are repeated until the phases of the reference signal REF and the feedback signal FB coincide with each other, and finally the phases of both coincide.

  However, even if the up signal is input to the charge pump 11, if the voltage VCTL becomes lower than the reference voltage VREFA corresponding to the operable maximum frequency FLA of the frequency divider 60, the limiter circuit 40A causes the voltage VCTL to become the reference voltage VREFA. To be controlled. Specifically, when the voltage VCTL becomes lower than the reference voltage VREFA, the PMOS 42A is turned on according to the output voltage VOA of the comparator 41A, and charges the loop filter 30A to increase the voltage VCTL. Therefore, in the PLL circuit 10A, the output signal FVCO is not oscillated from the VCO 50A at an oscillation frequency higher than the maximum operable frequency FLA of the frequency divider 60.

  FIG. 3A is a diagram showing another configuration example of the PLL circuit according to the present embodiment. FIG. 3A shows a PLL circuit 10B configured such that the loop filter 30B uses a reference potential (for example, a ground potential) as a potential reference. In FIG. 3A, blocks having the same functions as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description is omitted.

The loop filter 30B is connected between the VCO 50B and the reference potential.
The limiter circuit 40B can control the voltage VCTL of the node NB determined based on the amount of charge accumulated in the loop filter 30B by extracting (discharging) the charge from the loop filter 30B. The limiter circuit 40B has one comparator 41B and one NMOS 42B.

  The comparator 41B is for detecting whether or not the voltage VCTL at the node NB is equal to or higher than the reference voltage VREFB. The reference voltage VREFB and the voltage VCTL are supplied to one set of input terminals, and the comparison result is obtained. The corresponding voltage VOB is output from the output terminal. Here, the reference voltage VREFB is a voltage corresponding to the operation limit of the frequency divider 60, that is, the oscillation frequency of the VCO 50B becomes the maximum operable frequency of the frequency divider 60, as will be described later. The NMOS 42B has a source connected to the reference potential and a drain connected to the node NB. The output voltage VOB of the comparator 41B is supplied to the gate of the NMOS 42B.

  The VCO 50B uses the voltage VCTL of the node NB as an input voltage and oscillates the output signal FVCO at an oscillation frequency corresponding to the input voltage. In the VCO 50B, as shown in FIG. 3B, the oscillation frequency of the output signal FVCO changes according to the voltage VCTL as the input voltage, and the oscillation frequency of the output signal FVCO increases as the voltage VCTL increases.

  In the PLL circuit 10B, when a down signal is input, the charge pump 11 extracts charges from the loop filter 30B and lowers the voltage VCTL. Conversely, when the up signal is input, the charge pump 11 injects electric charge into the loop filter 30B and raises the voltage VCTL. Therefore, in the case of a down signal, the voltage VCTL decreases and the oscillation frequency of the output signal FVCO decreases. In the case of an up signal, the voltage VCTL increases and the oscillation frequency of the output signal FVCO increases.

Here, when the voltage VCTL is higher than the reference voltage VREFB, the limiter circuit 40B extracts the charge from the loop filter 30B and lowers the voltage VCTL. Therefore, even when the up signal is input to the charge pump 11, if the voltage VCTL becomes higher than the reference voltage VREFB corresponding to the maximum operable frequency FLB of the frequency divider 60, the limiter circuit 40B causes the voltage VCTL to become the reference voltage VREFB. To be controlled. Specifically, when the voltage VCTL becomes higher than the reference voltage VREFB, the NMOS 42B is turned on according to the output voltage VOB of the comparator 41B, and the charge is discharged from the loop filter 30B to the reference potential, thereby lowering the voltage VCTL. Therefore, in the PLL circuit 10B, the output signal FVCO is not oscillated from the VCO 50B at an oscillation frequency higher than the maximum operable frequency FLB of the frequency divider 60.
Other operations are the same as those of the PLL circuit 10A shown in FIG.

  4A and 4B are diagrams illustrating convergence characteristics of the oscillation frequency of the PLL circuit according to the present embodiment. As described above, the PLL circuit according to the present embodiment is a voltage corresponding to an oscillation frequency such that the voltage VCTL supplied to the VCO 50 (50A, 50B) as the input voltage exceeds the maximum operable frequency of the frequency divider 60. In this case, the voltage VCTL is controlled so that the oscillation frequency of the VCO 50 (50A, 50B) does not exceed the maximum operable frequency of the frequency divider 60 by operating the limiter circuit 40 (40A, 40B).

  For example, as shown in FIG. 4A, the limiter circuit 40 operates even when the oscillation frequency of the output signal FVCO from the VCO 50 immediately after power-on has already exceeded the maximum operable frequency FL of the frequency divider 60. As a result, the voltage VCTL is controlled and the oscillation frequency of the VCO 50 becomes lower than the maximum operable frequency FL of the frequency divider 60. Therefore, it operates normally as a PLL circuit, and the oscillation frequency of the VCO 50 converges to a desired frequency PLL Target.

  Further, for example, even when the initial state of the VCO 50 is different and the oscillation frequency of the output signal FVCO increases as time elapses immediately after the power is turned on as shown in FIG. When the maximum operable frequency FL is reached (the voltage VCTL becomes the reference voltages VREFA and VREFB), the limiter circuit 40 operates. As a result, the voltage VCTL is controlled, and the oscillation frequency of the VCO 50 becomes lower than the maximum operable frequency FL of the frequency divider 60. Therefore, it operates normally as a PLL circuit, and the oscillation frequency of the VCO 50 converges to a desired frequency PLL Target.

  As described above, according to the present embodiment, as described above, the voltage VCTL input as the input voltage to the VCO 50 (50A, 50B) is a voltage corresponding to an oscillation frequency that exceeds the maximum operable frequency of the frequency divider 60. In this case, the limiter circuit 40 (40A, 40B) operates to control the voltage VCTL so that the oscillation frequency of the VCO is within the operable frequency of the frequency divider. As a result, it is possible to control the oscillation frequency of the VCO so as not to exceed the maximum operable frequency of the frequency divider, and it is possible to reliably prevent malfunction in the process of convergence of the oscillation frequency of the PLL circuit, and to prevent the output signal FVCO from The oscillation frequency can be converged to a desired frequency. Therefore, it is possible to prevent a malfunction from occurring in the PLL circuit and oscillate a stable output signal.

Next, a specific configuration example of the PLL circuit according to the present embodiment will be described. In the following, the basic operation of the PLL circuit according to the present embodiment shown in FIGS. 5 to 10 is the same as that of the PLL circuit described with reference to FIGS. Omitted.
(Specific configuration example 1)
5 and 6 are diagrams showing a specific configuration example of the PLL circuit according to the present embodiment. 5 and 6, the blocks having the same functions as the blocks shown in FIGS. 1, 2 (A), and 3 (A) are denoted by the same reference numerals, and redundant description is omitted. .

  FIG. 5 shows a PLL circuit 10C configured such that the loop filter 30A is connected to the power supply potential Vdd, and the power supply potential Vdd is used as a potential reference. The loop filter 30A is configured by a lag lead filter including a resistor 31A and a capacitor 32A, and the resistor 31A and the capacitor 32A are connected in series between the node NA and the power supply potential Vdd in this order. Specifically, one end of the resistor 31A is connected to the node NA, and the other end is connected to one electrode of the capacitor 32A. The other electrode of the capacitor 32A is connected to the power supply potential Vdd.

  In the PLL circuit 10C shown in FIG. 5, when the voltage VCTL of the node NA becomes lower than the reference voltage VREFA corresponding to the operation limit of the frequency divider 60, the output VOA of the comparator 41A becomes low level (“L”) and the PMOS 42A Is turned on. As a result, charge is charged in the capacitor 32A of the loop filter 30A, the voltage VCTL is increased, and the oscillation frequency of the VCO 50A is decreased. When the voltage VCTL at the node NA is higher than the reference voltage VREFA, the output VOA of the comparator 41A becomes high level (“H”) and the PMOS 42A is turned off.

  FIG. 6 shows a PLL circuit 10D configured such that the loop filter 30B is connected to a reference potential (for example, a ground potential) and the reference potential is used as a reference for the potential. The loop filter 30B is configured by a lag lead filter including a resistor 31B and a capacitor 32B, and the resistor 31B and the capacitor 32B are connected in series in this order between the node NB and the reference potential. Specifically, one end of the resistor 31B is connected to the node NB, and the other end is connected to one electrode of the capacitor 32B. The other electrode of the capacitor 32B is connected to the reference potential.

  In the PLL circuit 10D shown in FIG. 6, when the voltage VCTL of the node NB becomes higher than the reference voltage VREFB corresponding to the operation limit of the frequency divider 60, the output VOB of the comparator 41B becomes “H” and the NMOS 42B is turned on. become. As a result, charge is discharged from the capacitor 32B of the loop filter 30B to the reference potential, the voltage VCTL is lowered, and the oscillation frequency of the VCO 50B is lowered. When the voltage VCTL at the node NB is lower than the reference voltage VREFB, the output VOB of the comparator 41B becomes “L” and the NMOS 42B is turned off.

  According to the PLL circuit according to the present embodiment shown in FIGS. 5 and 6, the voltage VCTL is reduced by the limiter circuits 40A and 40B so that the oscillation frequency of the VCOs 50A and 50B does not always exceed the maximum operable frequency of the frequency divider 60. Therefore, it is possible to reliably prevent the malfunction in the process of converging the oscillation frequency of the PLL circuit, to converge the oscillation frequency, and to oscillate the output signal FVCO having a desired oscillation frequency.

(Specific configuration example 2)
7 and 8 are diagrams showing other specific configuration examples of the PLL circuit according to the present embodiment. 7 and 8, blocks having the same functions as those shown in FIGS. 1, 2 (A), 3 (A), 5 and 6 are denoted by the same reference numerals, and duplicated. The description to be omitted is omitted.

  The PLL circuit 10E shown in FIG. 7 differs from the PLL circuit 10C shown in FIG. 5 only in that the drain of the PMOS 42A in the limiter circuit 40A is connected to the interconnection point of the resistor 31A and the capacitor 32A in the loop filter 30A. Different. Similarly, the PLL circuit 10F shown in FIG. 8 is the PLL shown in FIG. 6 only in that the drain of the NMOS 42B in the limiter circuit 40B is connected to the interconnection point of the resistor 31B and the capacitor 32B in the loop filter 30B. Different from the circuit 10D.

  Also in the PLL circuit according to the present embodiment shown in FIGS. 7 and 8, the voltage VCTL is controlled by the limiter circuits 40A and 40B so that the oscillation frequency of the VCOs 50A and 50B does not always exceed the maximum operable frequency of the frequency divider 60. Therefore, it is possible to reliably prevent malfunction in the convergence process of the oscillation frequency of the PLL circuit, to converge the oscillation frequency, and to oscillate the output signal FVCO having a desired oscillation frequency. Further, in the PLL circuit 10E, the drain of the PMOS 42A of the limiter circuit 40A is connected to the interconnection point of the resistor 31A and the capacitor 32A that constitute the loop filter 30A. In the PLL circuit 10F, the resistor 31B and the capacitor 32B that constitute the loop filter 30B. By connecting the drain of the NMOS 42B of the limiter circuit 40B to this interconnection point, the time constant relating to charge control can be made smaller than controlling the charge charging or discharging of the capacitors 32A, 32B via the resistors 31A, 31B. And charge control can be performed quickly.

(Specific configuration example 3)
9 and 10 are diagrams showing other specific configuration examples of the PLL circuit according to the present embodiment. 9 and 10, blocks having the same functions as the blocks shown in FIGS. 1, 2 (A), 3 (A), 5 and 6 are denoted by the same reference numerals, and duplicated. The description to be omitted is omitted.

  In the PLL circuit 10G shown in FIG. 9, the limiter circuit 40C can control the voltage VCTL of the node NA by charging the loop filter 30A with electric charges. The limiter circuit 40C includes one comparator 41C, one PMOS 42C, and one variable resistor 43C. The comparator 41C is for detecting whether or not the voltage VCTL at the node NA is equal to or lower than the reference voltage VREFA. The reference voltage VREFA and the voltage VCTL are supplied to one set of input terminals, and the comparison result is obtained. The corresponding voltage VOC is output from the output terminal. The PMOS 42C has a source connected to the power supply potential Vdd via the variable resistor 43C and a drain connected to the node NA. The output voltage VOC of the comparator 41C is supplied to the gate of the PMOS 42C.

  In the PLL circuit 10G shown in FIG. 9, when the voltage VCTL of the node NA becomes lower than the reference voltage VREFA corresponding to the operation limit of the frequency divider 60, the output VOC of the comparator 41C becomes “L” and the PMOS 42C is turned on. It becomes. As a result, charge is charged in the capacitor 32A of the loop filter 30A, the voltage VCTL is increased, and the oscillation frequency of the VCO 50A is decreased. When the voltage VCTL at the node NA is higher than the reference voltage VREFA, the output VOC of the comparator 41C becomes high level “H” and the PMOS 42C is turned off.

  In the PLL circuit 10H shown in FIG. 10, the limiter circuit 40D can control the voltage VCTL of the node NB by discharging the charge from the loop filter 30B to the reference potential. The limiter circuit 40D has one comparator 41D, one NMOS 42D, and one variable resistor 43D. The comparator 41D is for detecting whether or not the voltage VCTL at the node NB is equal to or lower than the reference voltage VREFB. The reference voltage VREFB and the voltage VCTL are supplied to one set of input terminals, and the comparison result is obtained. The corresponding voltage VOD is output from the output terminal. The NMOS 42D has a source connected to the reference potential via the variable resistor 43D and a drain connected to the node NB. Further, the output voltage VOD of the comparator 41D is supplied to the gate of the NMOS 42D.

  In the PLL circuit 10H shown in FIG. 10, when the voltage VCTL of the node NB becomes higher than the reference voltage VREFB corresponding to the operation limit of the frequency divider 60, the output VOD of the comparator 41D becomes “H” and the NMOS 42D is in the on state. become. As a result, charge is discharged from the capacitor 32D of the loop filter 30D to the reference potential, the voltage VCTL is lowered, and the oscillation frequency of the VCO 50B is lowered. When the voltage VCTL at the node NB is lower than the reference voltage VREFB, the output VOD of the comparator 41D becomes “L” and the NMOS 42D is turned off.

  Also in the PLL circuit according to the present embodiment shown in FIGS. 9 and 10, the voltage VCTL is controlled by the limiter circuits 40C and 40D so that the oscillation frequency of the VCOs 50A and 50B does not always exceed the maximum operable frequency of the frequency divider 60. Therefore, it is possible to reliably prevent malfunction in the convergence process of the oscillation frequency of the PLL circuit, to converge the oscillation frequency, and to oscillate the output signal FVCO having a desired oscillation frequency.

  Further, in the PLL circuit 10G, the drain of the PMOS 42C of the limiter circuit 40C is connected to the interconnection point of the resistor 31A and the capacitor 32A constituting the loop filter 30A, and the source of the PMOS 42C is connected to the power supply potential Vdd via the variable resistor 43C. To do. In the PLL circuit 10H, the drain of the NMOS 42D of the limiter circuit 40D is connected to the interconnection point of the resistor 31B and the capacitor 32B constituting the loop filter 30B, and the source of the NMOS 42D is connected to the reference potential via the variable resistor 43D. . As a result, similar to the PLL circuits 10E and 10F shown in FIGS. 7 and 8, the time constants related to the charge control of the loop filters 30A and 30B can be reduced, the charge can be controlled quickly, and the variable resistor 43C can be controlled. , 43D can be used to adjust the time constant related to charge control.

  In the above-described specific configuration example in the present embodiment, a case where a lag lead filter is used as the loop filter is shown as an example, but the present invention is not limited to this.

In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Appendix 1) A phase comparator that detects the phase difference by comparing the phases of the reference signal and the feedback signal;
A loop filter in which charges are charged or discharged according to the phase difference between the reference signal and the feedback signal;
A voltage controlled oscillator that oscillates an output signal at an oscillation frequency corresponding to an input voltage based on an amount of charge accumulated in the loop filter;
A PLL circuit comprising: a control circuit that charges or discharges the loop filter to change the input voltage to a voltage within a predetermined range when the input voltage is different from a voltage within a predetermined range.
(Supplementary note 2) A frequency divider that further divides the output signal oscillated by the voltage controlled oscillator and outputs the feedback signal is further provided.
2. The PLL circuit according to claim 1, wherein the voltage within the predetermined range is a voltage at which an output signal is oscillated from the voltage controlled oscillator at an oscillation frequency that can be divided by the frequency divider.
(Supplementary Note 3) The control circuit includes a voltage detection circuit that detects whether or not the input voltage is a voltage within a predetermined range;
The PLL circuit according to appendix 1 or 2, further comprising: a voltage control circuit capable of switching whether to charge or discharge the loop filter according to a detection result of the voltage detection circuit.
(Supplementary Note 4) The control circuit includes a comparator that compares the input voltage with a reference voltage that defines the predetermined range;
The PLL circuit according to appendix 1 or 2, further comprising: a transistor having an output of the comparator connected to a control terminal.
(Appendix 5) The loop filter is connected to a power supply potential,
The control circuit charges the loop filter with charge when the input voltage is a voltage at which the oscillation frequency of the output signal is equal to or higher than a predetermined frequency. The PLL circuit described.
(Appendix 6) The loop filter is connected to a reference potential,
The control circuit discharges the electric charge accumulated in the loop filter when the input voltage is a voltage at which the oscillation frequency of the output signal is equal to or higher than a predetermined frequency. The PLL circuit according to item 1.
(Supplementary note 7) The PLL circuit according to supplementary note 6, wherein the reference potential is a ground potential.
(Supplementary note 8) The PLL circuit according to any one of supplementary notes 1 to 7, further comprising a charge pump that charges or discharges the loop filter according to a phase difference between the reference signal and the feedback signal. .
(Supplementary note 9) A loop filter that charges or discharges charge according to the phase difference between the reference signal and the feedback signal, and an output signal from the output terminal at an oscillation frequency according to the input voltage based on the amount of charge accumulated in the loop filter. A control circuit for controlling a PLL circuit having a voltage controlled oscillator that oscillates,
A voltage detection circuit for detecting whether or not the input voltage input to the voltage controlled oscillator is a voltage within a predetermined range;
When the input voltage is different from the voltage within the predetermined range as a result of detection by the voltage detection circuit, the voltage control circuit charges or discharges the loop filter to bring the input voltage into a voltage within the predetermined range. A control circuit comprising:
(Supplementary Note 10) The voltage within the predetermined range is a voltage at which the output signal is oscillated by the voltage controlled oscillator at an oscillation frequency that can be divided by the frequency divider that divides the output signal and outputs the feedback signal. The control circuit according to appendix 9, wherein there is a control circuit.
(Supplementary Note 11) Connected between the loop filter connected to the power supply potential and the input terminal of the voltage controlled oscillator,
The control circuit according to appendix 9 or 10, wherein when the input voltage is a voltage at which an oscillation frequency of the output signal becomes a predetermined frequency or more, the loop filter is charged.
(Supplementary Note 12) Connected between the loop filter connected to a reference potential and an input terminal of the voltage controlled oscillator,
The control circuit according to appendix 9 or 10, wherein when the input voltage is a voltage at which an oscillation frequency of the output signal becomes a predetermined frequency or more, the loop filter is charged.

It is the schematic which shows the structural example of the PLL circuit by one Embodiment of this invention. It is a figure which shows an example of the PLL circuit by this embodiment. It is a figure which shows the other example of the PLL circuit by this embodiment. It is a figure which shows the convergence characteristic of the output frequency of the PLL circuit by this embodiment. It is a figure which shows the specific structural example of the PLL circuit by this embodiment. It is a figure which shows the specific structural example of the PLL circuit by this embodiment. It is a figure which shows the other specific structural example of the PLL circuit by this embodiment. It is a figure which shows the other specific structural example of the PLL circuit by this embodiment. It is a figure which shows the other specific structural example of the PLL circuit by this embodiment. It is a figure which shows the other specific structural example of the PLL circuit by this embodiment. It is a figure which shows the structure of the conventional PLL circuit. It is a figure which shows the structure of the conventional PLL circuit. It is a figure for demonstrating the problem in the conventional PLL circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 PLL circuit 11 Charge pump 20 Phase comparator 30 Loop filter 40 Limiter circuit 50 Voltage controlled oscillator (VCO)
60 Divider REF Reference signal FVCO Output oscillation signal FB Feedback signal

Claims (4)

A phase comparator that detects the phase difference by comparing the phase of the reference signal and the feedback signal, and outputs an up / down signal according to the detected phase difference;
A charge pump circuit that outputs a voltage signal corresponding to the up / down signal;
The resistor is provided between the output terminal of the charge pump circuit and the power supply line, and has a capacitor connected to the resistor, and the capacitor is charged or discharged based on the voltage signal. Loop filter,
A transistor in which one of a source and a drain is connected to a connection point between the resistance element and the capacitor, and the other of the source and the drain is connected to the power supply line;
A voltage controlled oscillator that oscillates an output signal at an oscillation frequency corresponding to an input voltage based on an amount of charge accumulated in the loop filter;
And a control circuit which is connected to the gate of the transistor and turns on the transistor when the input voltage is different from a voltage within a predetermined range. A frequency divider for dividing the output signal oscillated by the voltage controlled oscillator and outputting the feedback signal;
2. The PLL circuit according to claim 1, wherein the voltage within the predetermined range is a voltage at which an output signal is oscillated from the voltage controlled oscillator at an oscillation frequency that can be divided by the frequency divider. The loop filter is connected to the power supply potential,
3. The PLL circuit according to claim 1, wherein the control circuit turns on the transistor when the input voltage is a voltage at which an oscillation frequency of the output signal is equal to or higher than a predetermined frequency. The loop filter is connected to a reference potential,
3. The PLL circuit according to claim 1, wherein the control circuit turns on the transistor when the input voltage is a voltage at which an oscillation frequency of the output signal is equal to or higher than a predetermined frequency.

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