JP4359258B2 - Arithmetic apparatus and arithmetic method - Google Patents

Description

  The present invention relates to a calculation device and a calculation method for performing a calculation using a floating point.

  In general, when performing arithmetic operations such as multiplication and addition in an arithmetic device such as a computer, arithmetic operations are performed while rounding down or rounding up predetermined digits for numerical values expressed in binary numbers.

For example, IEEE (Institute of Electrical and Electronic Engineers) 754 defines binary floating point formats of single precision and double precision. Single precision expresses one numerical value with 32 bits (sign part 1 bit, exponent part 8 bits, mantissa part 23 bits), and double precision means one numerical value with 64 bits (sign part 1 bit) (Expression part 11 bits, mantissa part 52 bits)
In some cases, these single-precision and double-precision extended formats are used for computation.

As described above, IEEE 754 defines a floating-point format. However, an inner product operation in a computer using these floating-point numbers causes errors in rounding, information loss, and digit loss, so that an accurate inner product operation result can be obtained. There is a problem that it is not possible.
In view of this, several devices have been proposed to improve the accuracy of the inner product calculation.

  For example, Patent Document 1 discloses an apparatus that performs an inner product operation on an input vector x after subtracting the scalar number β from all vector components and then performing a transformation α (x−βI) multiplied by the scalar number α. Has been.

In Patent Document 2, based on bit slices corresponding to a plurality of input data, a partial inner product corresponding to the numerical array of the bit slice is detected and output from a lookup table, and the partial inner product is set to an initial value or an intermediate value. The final value obtained by adding the accumulated value and outputting the added output value, holding the numerical value of the lower-order truncation bit of the added output value, and repeating the above addition process for the number of digits of the input data There is disclosed an arithmetic device that improves the deterioration of the arithmetic accuracy by adding the value of the above-mentioned truncation bit from the last addition cycle to a predetermined cycle before the accumulated result value.
JP-A-11-96140 (paragraphs 0014 to 0031, FIG. 3) JP 2000-132539 A (paragraphs 0066 to 0073, FIG. 1)

However, in both Patent Document 1 and Patent Document 2, since the accuracy improvement method of the inner product calculation by hardware is adopted and the number of digits is limited at the hardware design stage, any one conforming to IEEE 754 is arbitrary. In the inner product calculation using the floating point, there is a problem that errors of rounding, information loss and digit loss may occur, and an accurate calculation result cannot be obtained.
Therefore, the present invention has been made in view of the above problems, and an object thereof is to perform a calculation using a more accurate floating point.

In order to solve the above-described problem, an arithmetic unit that performs an operation of a product of a first number and a second number to be multiplied using a binary floating point, the first number, the second number A storage unit that stores the number and the number generated by the operation as a number within a predetermined number of digits by rounding down or rounding up the bits of the digits lower than the predetermined number of digits, and a second number stored in the storage unit The number of 1 is separated into a first upper number that is a predetermined upper number digit and a first lower number that is a remaining lower number digit, and the second number stored in the storage unit is determined as a predetermined number Is divided into a second upper number that is the upper number digits of the second number and a second lower number that is the remaining lower number digits, and the first higher number and the second upper number are multiplied by the first higher number. Multiply the first higher number and the second lower number to obtain the second multiplication number, and multiply the first lower number and the second upper number. The third multiplication number, the first lower number and the second lower number are multiplied to obtain the fourth multiplication number, the first multiplication number, the second multiplication number, the third multiplication number, and the second multiplication number. When calculating the sum by multiplying the number of multiplications of 4 three times in an arbitrary order, the error of each time is stored in the storage unit separately from the sum at each time, and the total error is added to each time. And a processing unit that calculates an error and calculates a total sum by adding the total error to the sum after three additions, and also calculates a total error that is an error at that time. . Other means will be described later.

  According to the present invention, more accurate calculation using a floating point can be performed.

  Hereinafter, a data processing apparatus (arithmetic apparatus) according to the present invention will be described with reference to the drawings as appropriate.

First, the configuration of the data processing apparatus will be described with reference to FIG. FIG. 1 is a configuration diagram of a data processing apparatus.
The data processing apparatus 1 includes an auxiliary storage unit 101, a memory (storage unit) 102, a CPU (Central Processing Unit) 103 as a processing unit, an input unit 104, an output unit 105, and an input / output interface 106.

  The auxiliary storage unit 101 stores various types of information, and is realized by, for example, a hard disk, a ROM (Read Only Memory), or the like. Here, the auxiliary storage unit 101 stores a program 111, a compiler 112, and an execution module 113.

The program 111 is a program (hereinafter referred to as a source program) in which processing on the flowchart shown in FIG. 2 is described.
The compiler 112 compiles and links the program 111.
The execution module 113 is a module compiled and linked by the compiler 112.

The memory 102 is temporary storage means for storing various information, and is realized by, for example, a RAM (Random Access Memory).
The CPU 103 performs various arithmetic processes and plays a role of executing the execution module 113 via the memory 102 and the input / output interface 106.
The input unit 104 is an input device for inputting various execution commands.
The output unit 105 is an output device that outputs various execution results.
As shown in FIG. 1, the input / output interface 106 serves as an input / output interface between the components.

The data processing apparatus 1 configured as described above operates as follows.
First, a compile command input from the input unit 104 by the operator is stored in the memory 102 via the input / output interface 106. In the memory 102, the program 111 in the auxiliary storage unit 101 is compiled and linked by the compiler 112, and an execution module 113 that is a machine language code is generated.

Next, when an execution command is input from the input unit 104 by the operator, the CPU 103 loads the execution module 113 into the memory 102. When the execution module 113 is loaded into the memory 102, each process S201 to S208 in the flowchart shown in FIG. 2 is sequentially called from the memory 102 to the CPU 103 by the CPU 103, and each process is executed. 102.
The execution result stored in the memory 102 is output to the output unit 105 by the CPU 103 via the input / output interface 106.

  Subsequently, the processing of the data processing apparatus will be described with reference to FIG. 2 (see FIG. 1 as appropriate). FIG. 2 is a flowchart showing the overall processing of the data processing apparatus. Here, the case where the accuracy of the vectors A (i) and B (i) of the inner product calculation in i = N dimensions is improved will be described as an example.

  First, the input process S201 is called from the memory 102 to the CPU 103. In this input process S201, as shown in FIG. 3, the CPU 103 repeats the processes from S301 to S303, and i = N-dimensional data input from the input unit 104 by the operator, that is, A (i), B (I) is loaded into the memory 102.

  Returning to FIG. 2, next, the initialization process S <b> 202 is called from the memory 102 to the CPU 103. In this initialization process S202, as shown in FIG. 4, in S401, the CPU 103 secures the SUM and DSUM areas as variables on the memory 102, and initializes the SUM and DSUM values to 0, respectively.

SUM is a variable for substituting the sum that has not been corrected for the final error, and DSUM is a variable for substituting the error correction part.
By using such SUM and DSUM, when the data processing apparatus 1 performs operations such as multiplication and addition of numerical values, the following effects are obtained. In other words, since the number of digits that can be stored (held) by the memory 102 or the CPU 103 is determined, the deviation of the numerical value is stored as an error, and the error is used in subsequent calculations, thereby reducing the error of the entire calculation. Or can be eliminated.

  Next, in the processes S203 to S206 in FIG. 2, an iterative process for the N-dimensional number of vectors, that is, an inner product calculation process is performed. For example, in the two-dimensional case, N = 2, and in this case, A (i) and B (i) are A (A (1), A (2)) and B (B (1), B (2), respectively. )).

  Specifically, first, the CPU 103 corrects an error in A (i) * B (i) when i = N (S204). Next, the CPU 103 corrects an error in ΣA (i) * B (i) when i = N (S205).

FIG. 5 is a detailed view of S204 shown in FIG. First, in step S <b> 501, the CPU 103 secures areas for variables A (i), A1 (i), A2 (i), B (i), B1 (i), and B2 (i) on the memory 102.
Then, the CPU 103 separates A (i) into A1 (i) and A2 (i) so that the most significant digit and the least significant digit of one bit are separated.

Similarly, for B (i), the CPU 103 separates B (i) and B2 (i) so that the most significant digit and the least significant digit of one bit are separated.
Note that this separation may be performed only in one of A (i) and B (i).

In S502, the CPU 103 secures areas of variables S1, S2, S3, and S4 on the memory 102, A1 (i) * B1 (i) is S1, and A1 (i) * B2 (i) is S2, A2. (I) Substitute * B1 (i) for S3 and A2 (i) * B2 (i) for S4.
As a result, A (i) * B (i) is expressed as S1 + S2 + S3 + S4.

In S503, the CPU 103 secures the areas of the variables T1 and T2 on the memory 102, and substitutes the sum of S1 and S2 described above for T1. Further, an error of the sum of S1 and S2 is calculated from S2- (T1-S1) and substituted for T2.
Thereby, it is possible to follow an error caused by rounding or information loss caused by the sum S1 + S2.

In S504, the CPU 103 secures the areas of the variables T3 and T4 on the memory 102, and substitutes the sum of S3 and S4 described above for T3. Further, an error of the sum of S3 and S4 is calculated from S4- (T3-S3) and substituted for T4.
Thereby, it is possible to follow an error caused by rounding or information loss caused by the sum S3 + S4.

In S505, the CPU 103 secures the areas of variables T5 and T6 on the memory 102, and substitutes the sum of T1 and T3 described above for T5. Also, the error of the sum of T1 and T3 is calculated from T3- (T5-T1) and substituted for T6.
Thereby, it is possible to follow an error caused by rounding or information loss caused by the sum T1 + T3.

In step S506, the CPU 103 secures an area for the variable T7 on the memory 102, and substitutes the sum of the above-described T2, T4, and T6 for T7.
Since T7 is less likely to cause a large error, there is no problem even if the error is not followed.

In S507, the CPU 103 secures the areas of the variables D and E on the memory 102 and substitutes the sum of T5 and T7 described above for D. Further, an error of the sum of T5 and T7 is calculated from T7− (D−T5) and substituted for E.
Thus, the CPU 103 performs the processing of S501 to S507 for all given i.

  FIG. 6 is a detailed view of S205 shown in FIG. Note that S601 to S605 in FIG. 6 are the same processes as S503 to S507 in FIG.

  In S601, the CPU 103 secures the areas of the variables S11 and S12 on the memory 102, and substitutes the sum of the above SUM and D into S11. Further, the error of the sum of SUM and D is substituted into S12.

  In S602, the CPU 103 secures the areas of variables S13 and S14 on the memory 102, and substitutes the sum of DSUM and E into S13. Further, the error of the sum of DSUM and E is substituted into S14.

  In S603, the CPU 103 secures the areas of the variables S15 and S16 on the memory 102, and substitutes the sum of S11 and S13 described above for S15. Further, the error of the sum of S11 and S13 is substituted into S16.

  In S604, the CPU 103 secures an area for the variable S17 on the memory 102, and substitutes the sum of S12, S14, and S16 described above for S17.

In S605, the CPU 103 substitutes the sum of S15 and S17 described above for SUM, and substitutes the error of the sum of S15 and S17 for DSUM.
As described above, the CPU 103 performs the processing of S601 to S605 for all given i.

Returning to FIG. 2, in S207, the CPU 103 calculates the sum of the SUM and the correction term DSUM, and substitutes the sum into the SUM.
In S208, as an output process, the CPU 103 outputs the SUM value substituted in S207 to the output unit 105 as a calculation result.

As described above, by performing each processing of S201 to S208, it is possible to obtain an accurate calculation result for the inner product calculation A / B.
In addition, by obtaining accurate calculation results in this way, the present invention is applied to industries that require high-precision inner product calculation (for example, physics that requires neural network, vector quantization, and sensitive numerical simulation). Can be applied.

  Subsequently, specific examples of the inner product calculation described above will be described (refer to each figure as appropriate). Here, in order to facilitate understanding, a case of inner product calculation regarding a two-dimensional vector will be described as an example. Further, regarding the numerical values used by the data processing device 1 (see FIG. 1), the number of digits that can be held as the mantissa part is 8 bits (excluding the exponent part). When the numerical value of the operation result exceeds 8 bits, only the upper 8 bits are retained, and the remaining bits are discarded.

Under the above conditions, the two-dimensional vectors A and B are set as follows.
A = (A (1), A (2)), B = (B (1), B (2))
A (1), A (2), B (1), and B (2) are binary numbers, and their values are as follows.
A (1) = 10110111 (“183” in decimal notation: Similarly, parenthesized notation)
A (2) = 10010101 (149)
B (1) = 111011010 (218)
B (2) = 11100011 (227)

Under the above conditions, A · B (correct answer) which is the correct answer of the inner product operation A · B is as follows.
A / B (correct answer) = 1001101111010110 (39894) +
10,00010000011111 (33823)
= 100001111111110101 (73717)

When the data processing apparatus 1 (see FIG. 1) of the present embodiment is not used, that is, when the error caused by truncation is not corrected as in the prior art, A / B (conventional) is the result of the inner product calculation A / B. ) Is as follows.
A · B (conventional) = 10011011 * 2 ⁸ (39680) +
10,000 100 * 2 ⁸ (33792)
= 100001111 * 2 ⁹ (73216)

  That is, in the conventional calculation method, an error of 73717−73216 = 501 occurs.

  Next, an operation for calculating A · B (this application) as a result of the inner product operation A · B using the data processing device 1 (see FIG. 1) of the present embodiment under the above conditions will be described (as appropriate). (See each figure).

First, in S201, data is input from the input unit 104 as shown in S301. As a result, the array is initialized as follows.
A (1) = 10110111 (183)
A (2) = 10010101 (149)
B (1) = 111011010 (218)
B (2) = 11100011 (227)

Next, in S202, the CPU 103 initializes the values of the variables SUM and DSUM to 0 as shown in S401 of the variables SUM and DSUM.
In this example, in order to perform a two-dimensional inner product calculation, the variable N in S203 is initialized to 2.

Then, after S202 is executed, S204 is executed with i = 1. Next, in order to correct the error in the product A (1) * B (1), in S501, the CPU 103 separates the vector components as follows.
A (1) = A1 (1) + A2 (1)
B (1) = B1 (1) + B2 (1)
A1 (1) = 10110000 (176)
A2 (1) = 00000111 (7)
B1 (1) = 11010000 (208)
B2 (1) = 000001010 (10)

In this example, A (1) and B (1) are separated so that the lower 4 digits of A1 (1) and B1 (1) are 0, but the lower 3 digits, lower 2 digits, etc. May be separated so that becomes zero. Further, only one of A (1) and B (1) may be separated.
In any case, by separating A (1) and B (1) into two or more numbers so that the most significant digit and the least significant digit of one bit are separated in this way, The error can be reduced.

After S501 is executed, the variables S1, S2, S3, and S4 are as follows in S502.
S1 = 100001111 * 2 ⁸ (36608)
S2 = 111011100 * 2 ³ (1760)
S3 = 10110110 * 2 ³ (1456)
S4 = 0100011010 (70)

After S502 is executed, the variables T1 and T2 are as follows in S503.
T1 = 10010101 * 2 ⁸ (38144)
T2 = 111100000 (224)

In S504, the variables T3 and T4 are as follows.
T3 = 10111110 * 2 ³ (1520)
T4 = 00000110 (6)

Further, in S505, the variables T5 and T6 are as follows.
T5 = 10011010 * 2 ⁸ (39424)
T6 = 11110000 (240)

In S506, the variable T7 is as follows.
T7 = 11101011 * 2 ¹ (470)

In S507, the variables D and E are as follows.
D = 10011011 * 2 ⁸ (39680)
E = 111010110 (214)

  Subsequently, S205 is executed with i = 1. Here, since SUM and DSUM remain at their initial values, both are 0.

First, in S601, variables S11 and S12 are as follows.
S11 = 10011011 * 2 ⁸ (39680)
S12 = 000000000000 (0)

In S602, the variables S13 and S14 are as follows.
S13 = 11010110 (214)
S14 = 00000000 (0)

Further, in S603, the variables S15 and S16 are as follows.
S15 = 10011011 * 2 ⁸ (39680)
S16 = 11010110 (214)

In S604, the variable S17 is as follows.
S17 = 111010110 (214)

In S605, the variables SUM and DSUM are as follows.
SUM = 10011011 * 2 ⁸ (39680)
DSUM = 111010110 (214)

Next, S204 is executed with i = 2. First, in order to correct an error in the product A (2) * B (2), in S501, vector components are separated as follows.
A (2) = A1 (2) + A2 (2)
B (2) = B1 (2) + B2 (2)
A1 (2) = 10010000 (144)
A2 (2) = 00000101 (5)
B1 (2) = 111100000 (225)
B2 (2) = 00000011 (3)

After S501 is executed, the variables S1, S2, S3, and S4 are as follows in S502.
S1 = 11111100 * 2 ⁷ (32256)
S2 = 11011000 * 2 ¹ (432)
S3 = 1000101100 * 2 ³ (1120)
S4 = 00001111 (15)

After S502 is executed, the variables T1 and T2 are as follows in S503.
T1 = 11111111 * 2 ⁷ (32640)
T2 = 00110000 (48)

In S504, the variables T3 and T4 are as follows.
T3 = 10001101 * 2 ³ (1128)
T4 = 00000110 (7)

Further, in S505, the variables T5 and T6 are as follows.
T5 = 10000011 * 2 ⁸ (33536)
T6 = 11101000 (232)

In S506, the variable T7 is as follows.
T7 = 100001111 * 2 ¹ (286)

In S507, the variables D and E are as follows.
D = 10000100 * 2 ⁸ (33792)
E = 00011110 (30)

Subsequently, S205 is executed with i = 2. Here, the values of SUM and DSUM are as follows.
SUM = 10011011 * 2 ⁸ (39680)
DSUM = 111010110 (214)

First, in S601, variables S11 and S12 are as follows.
S11 = 100001111 * 2 ⁹ (73216)
S12 = 10000000 * 2 ¹ (256)

In S602, the variables S13 and S14 are as follows.
S13 = 11110100 (244)
S14 = 00000000 (0)

Further, in S603, the variables S15 and S16 are as follows.
S15 = 100001111 * 2 ⁹ (73216)
S16 = 11110100 (244)

In S604, the variable S17 is as follows.
S17 = 11111010 * 2 ¹ (500)

In S605, the variables SUM and DSUM are as follows.
SUM = 100111111 * 2 ⁹ (73216)
DSUM = 11111010 * 2 ¹ (500)

Finally, in S207, the CPU 103 substitutes SUM + DSUM for SUM to obtain SUM = 73716.
In S207, the SUM value and the DSUM value are actually stored in the memory 102 separately, so that no rounding error or the like occurs.

  In the output process S208, the CPU 103 outputs a calculation result, that is, A · B (this application) = 100111111110110100 (73716).

That is, when the decimal notation of the calculation results of A · B (correct answer), A · B (conventional) and A · B (this application) is written side by side, the error is as follows. -It turns out that it becomes very small compared with the error of B (conventional).
A ・ B (Correct) = 73717
A · B (conventional) = 73216 (error 501)
A · B (this application) = 73716 (error 1)

As another specific example, an accuracy improvement process in a three-dimensional inner product operation A / B using a double precision format defined in IEEE754 is shown below. In the following example, the numerical value is expressed in decimal.
When the three-dimensional vectors A and B are set as follows, the inner product calculation A · B (correct answer) is as follows.
A = (a00, a01, a02), B = (b00, b10, b20)
a00 = 1738663799
a01 = 773694423
a02 = 112614455
b00 = 1506009561
b10 = 2117293945
b20 = 421597465
A ・ B (Correct) = a00 * b00 + a01 * b10 + a02 * b20 = 4304060790507107549

First, when the present invention is not used under the above-described conditions, that is, when errors caused by rounding, information loss, and digit loss are not corrected, the inner product calculation A / B (conventional) has the following results.
A ・ B (conventional) = 0.43040607905071073 * 10 ¹⁹

On the other hand, when the present invention is used under the above conditions, the following results are obtained. First, in the input process S201, data is input from the input device 104 as in S301. As a result, the array is initialized as follows.
A (1) = 1738663799
A (2) = 773694423
A (3) = 112614455
B (1) = 1506009561
B (2) = 2117293945
B (3) = 421597465

  Next, the initialization process S202 initializes the variables SUM and DSUM to 0 like the variables SUM and S401. In this example, the variable N in S203 is initialized to 3 in order to perform the inner product calculation in three dimensions.

After the initialization process is executed, S204 is executed with i = 1. First, in order to correct an error in the product A (1) * B (1), in S501, vector components are separated as follows. Here, D indicates a decimal number and is irrelevant to the variable D. Also, the last two digits on the right side indicate the exponent part of the exponent with base 10.
A1 (1) = 0.173866377600000000000000000000D + 10
A2 (1) = 0.230000000000000000000000000000D + 02
B1 (1) = 0.150600953600000000000000000000D + 10
B2 (1) = 0.250000000000000000000000000000D + 02

After S501 is executed, the variables S1, S2, S3, and S4 are as follows by S502.
S1 = 0.261844422655376793600000000000D + 19
S2 = 0.434665944000000000000000000000D + 11
S3 = 0.346382193280000000000000000000D + 11
S4 = 0.575000000000000000000000000000D + 03

After S502 is executed, the variables T1 and T2 are as follows by S503.
T1 = 0.261844427002036224000000000000D + 19
T2 = 0.960000000000000000000000000000D + 02

After S503 is executed, the variables T3 and T4 are as follows by S504.
T3 = 0.346382199030000000000000000000D + 11
T4 = 0.000000000000000000000000000000D + 00

After S504 is executed, the variables T5 and T6 are as follows by S505.
T5 = 0.261844430465858201600000000000D + 19
T6 = 0.127000000000000000000000000000D + 03

After S505 is executed, the variable T7 becomes as follows by S506.
T7 = 0.223000000000000000000000000000D + 03

After S506 is executed, the variables D and E are as follows by S507.
D = 0.261844430465858201600000000000D + 19
E = 0.223000000000000000000000000000D + 03

After S204 is executed with i = 1, S205 is executed with i = 1.
First, the variables S11 and S12 are as follows by S601.
S11 = 0.261844430465858201600000000000D + 19
S12 = 0.000000000000000000000000000000D + 00

After S601 is executed, the variables S13 and S14 are as follows by S602.
S13 = 0.223000000000000000000000000000D + 03
S14 = 0.000000000000000000000000000000D + 00

After S602 is executed, the variables S15 and S16 are as follows by S603.
S15 = 0.261844430465858201600000000000D + 19
S16 = 0.223000000000000000000000000000D + 03

After S603 is executed, the variable S17 becomes as follows by S604.
S17 = 0.223000000000000000000000000000D + 03

After S604 is executed, the variables SUM and DSUM are as follows by S605.
SUM = 0.261844430465858201600000000000D + 19
DSUM = 0.223000000000000000000000000000D + 03

After S205 is executed with i = 1, S204 processing is executed with i = 2. First, in order to correct an error in the product A (2) * B (2), in S501, vector components are separated as follows.
A1 (2) = 0.773694416000000000000000000000D + 09
A2 (2) = 0.700000000000000000000000000000D + 01
B1 (2) = 0.211729392000000000000000000000D + 10
B2 (2) = 0.250000000000000000000000000000D + 02

After S501 is executed, the variables S1, S2, S3, and S4 are as follows by S502.
S1 = 0.163813848293475072000000000000D + 19
S2 = 0.193423604000000000000000000000D + 11
S3 = 0.148210574400000000000000000000D + 11
S4 = 0.175000000000000000000000000000D + 03

After S502 is executed, the variables T1 and T2 are as follows by S503.
T1 = 0.163813850227711104000000000000D + 19
T2 = 0.800000000000000000000000000000D + 02

After S503 is executed, the variables T3 and T4 are as follows by S504.
T3 = 0.346382199030000000000000000000D + 11
T4 = 0.000000000000000000000000000000D + 00

After S504 is executed, the variables T5 and T6 are as follows by S505.
T5 = 0.163813851709816857600000000000D + 19
T6 = 0.790000000000000000000000000000D + 02

After S505 is executed, the variable T7 becomes as follows by S506.
T7 = 0.159000000000000000000000000000D + 03

After S506 is executed, the variables D and E are as follows by S507.
D = 0.163813851709816883200000000000D + 19
E = -0.970000000000000000000000000000D + 02

After S204 is executed with i = 2, then S205 is executed with i = 2. First, the variables S11 and S12 are as follows by S601.
S11 = 0.425658282175675084800000000000D + 19
S12 = 0.000000000000000000000000000000D + 00

After S601 is executed, the variables S13 and S14 are as follows by S602.
S13 = 0.126000000000000000000000000000D + 03
S14 = 0.000000000000000000000000000000D + 00

After S602 is executed, the variables S15 and S16 are as follows by S603.
S15 = 0.425658282175675084800000000000D + 19
S16 = 0.126000000000000000000000000000D + 03

After S603 is executed, the variable S17 becomes as follows by S604.
S17 = 0.126000000000000000000000000000D + 03

After S604 is executed, the variables SUM and DSUM are as follows by S605.
SUM = 0.425658282175675084800000000000D + 19
DSUM = 0.126000000000000000000000000000D + 03

After S205 is executed with i = 2, S204 processing is executed with i = 3. First, in order to correct an error in the product A (3) * B (3), in S501, vector components are separated as follows.
A1 (3) = 0.773694416000000000000000000000D + 09
A2 (3) = 0.700000000000000000000000000000D + 01
B1 (3) = 0.211729392000000000000000000000D + 10
B2 (3) = 0.250000000000000000000000000000D + 02

After S501 is executed, the variables S1, S2, S3, and S4 are as follows by S502.
S1 = 0.474779682161446560000000000000D + 17
S2 = 0.112614454000000000000000000000D + 09
S3 = 0.421597464000000000000000000000D + 09
S4 = 0.100000000000000000000000000000D + 01

After S502 is executed, the variables T1 and T2 are as follows by S503.
T1 = 0.474779683287591120000000000000D + 17
T2 = -0.200000000000000000000000000000D + 01

After S503 is executed, the variables T3 and T4 are as follows by S504.
T3 = 0.421597465000000000000000000000D + 09
T4 = 0.000000000000000000000000000000D + 00

After S504 is executed, the variables T5 and T6 are as follows by S505.
T5 = 0.474779687503565760000000000000D + 17
T6 = -0.100000000000000000000000000000D + 01

After S505 is executed, the variable T7 becomes as follows by S506.
T7 = 0.159000000000000000000000000000D + 03

After S506 is executed, the variables D and E are as follows by S507.
D = 0.474779687503565760000000000000D + 17
E = -0.100000000000000000000000000000D + 01

After S204 is executed with i = 3, S205 is executed with i = 3. First, the variables S11 and S12 are as follows by S601.
S11 = 0.430406079050710732800000000000D + 19
S12 = 0.960000000000000000000000000000D + 02

After S601 is executed, the variables S13 and S14 are as follows by S602.
S13 = 0.125000000000000000000000000000D + 03
S14 = 0.000000000000000000000000000000D + 00

After S602 is executed, the variables S15 and S16 are as follows by S603.
S15 = 0.430406079050710732800000000000D + 19
S16 = 0.125000000000000000000000000000D + 03

After S603 is executed, the variable S17 becomes as follows by S604.
S17 = 0.221000000000000000000000000000D + 03

After S604 is executed, the variables SUM and DSUM are as follows by S605.
SUM = 0.430406079050710732800000000000D + 19
DSUM = 0.221000000000000000000000000000D + 03

Finally, in S206, by substituting the sum of the variables SUM and DSUM into SUM, the variable SUM becomes as follows.
SUM = 0.430406079050710754900000000000D + 19

From the above, when the present invention is used, the inner product calculation A · B (this application) has the following results.
A ・ B (this application) = 0.4304060790507107549 * 10 ¹⁹

In other words, when the calculation results of A · B (correct answer), A · B (conventional) and A · B (this application) are described side by side, it becomes as follows, and it can be seen that the accuracy of A · B (this application) is extremely high. .
A ・ B (Correct) = 4304060790507107549
A / B (conventional) = 0.43040607905071073 * 10 ¹⁹ (error 0.249 * 10 ³ )
A ・ B (this application) = 0.4304060790507107549 * 10 ¹⁹ (error 0)

This is the end of the description of the embodiments, but the aspects of the present invention are not limited to these.
For example, the calculation may be performed using a single precision format defined by IEEE754.
Further, although the inner product operation has been described, the present invention may be applied only to operations such as addition and multiplication.
Furthermore, the number of dimensions of the vector may be three or more.

Further, when the numerical value is within a predetermined number of digits, it may not be due to rounding down but may be due to rounding up.
Furthermore, when the numerical value is within a predetermined number of digits, another method such as rounding off when converted to a decimal number may be used.

Also, when performing the subtraction operation, a more accurate calculation result can be obtained by performing the same operation as in the addition operation.
In addition, a specific configuration such as a hardware configuration and a processing procedure can be appropriately changed without departing from the gist of the present invention. For example, the present invention may be applied when two or more arithmetic devices are used in combination.

It is a block diagram of a data processor. It is the flowchart which showed the process of the data processor. It is a detailed view of input processing S201. It is a detailed view of the initialization process S202. It is a detailed view of process S204. It is a detailed figure of processing S205.

Explanation of symbols

101 Auxiliary storage unit 102 Memory 103 CPU
104 Input section 105 Output section

Claims (4)

An arithmetic device that performs an operation of a product of a first number and a second number to be multiplied using a binary floating point,
A storage for storing the first number, the second number, and the number generated by the operation as a number within a predetermined number of digits by rounding down or rounding up the bits of a digit lower than the predetermined number of digits. And
Separating the first number stored in the storage unit into a first upper number which is a predetermined upper number digit and a first lower number which is a remaining lower number digit ;
Separating the second number stored in the storage unit into a second upper number that is the predetermined higher-order digits and a second lower number that is the remaining lower-order digits;
Multiplying the first upper number and the second upper number to obtain a first multiplication number;
Multiplying the first upper number and the second lower number to obtain a second multiplication number;
Multiplying the first lower number and the second upper number to obtain a third multiplication number;
Multiplying the first lower number and the second lower number to obtain a fourth multiplication number;
When the sum is calculated by adding the first multiplication number, the second multiplication number, the third multiplication number, and the fourth multiplication number three times in an arbitrary order, the sum at each time Separately, each error of each time is stored in the storage unit, and the total error is calculated by adding all the errors of each time, and the total error is added to the sum after the three times of addition. And a processing unit that calculates a total error that is an error at that time ,
An arithmetic device comprising: When performing an inner product operation of two vectors of one dimension or more,
  The processor is
  Calculate the sum and the sum error for each dimension, and add them to perform the inner product operation of the two vectors
  The arithmetic unit according to claim 1. An operation method in an operation device that performs an operation of a product of a first number and a second number to be multiplied using a binary floating point,
  The arithmetic unit may calculate the first number, the second number, and the number generated by the calculation within a predetermined number of digits by rounding down or rounding up the bits of the digits lower than the predetermined number of digits. A storage unit for storing numbers and a processing unit;
  The processor is
  Separating the first number stored in the storage unit into a first upper number which is a predetermined upper number digit and a first lower number which is a remaining lower number digit;
  Separating the second number stored in the storage unit into a second upper number that is the predetermined higher-order digits and a second lower number that is the remaining lower-order digits;
  Multiplying the first upper number and the second upper number to obtain a first multiplication number;
  Multiplying the first upper number and the second lower number to obtain a second multiplication number;
  Multiplying the first lower number and the second upper number to obtain a third multiplication number;
  Multiplying the first lower number and the second lower number to obtain a fourth multiplication number;
  When the sum is calculated by adding the first multiplication number, the second multiplication number, the third multiplication number, and the fourth multiplication number three times in an arbitrary order, the sum at each time Separately, each error of each time is stored in the storage unit, and the total error is calculated by adding all the errors of each time, and the total error is added to the sum after the three times of addition. And the total error, which is the error at that time, is also calculated
  An arithmetic method characterized by the above. When performing an inner product operation of two vectors of one dimension or more,
  The processor is
  Calculate the sum and the sum error for each dimension, and add them to perform the inner product operation of the two vectors
  The calculation method according to claim 3.

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