JP4355132B2 - Technology evaluation system and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a design technology evaluation system and method for evaluating a technical level of design using design software by a user who performs design using design software.
[0002]
[Prior art]
A qualification test and a qualification test using a computer have been conventionally proposed (for example, see Non-Patent Document 1). According to this proposal, the test questions of the conventional written test using paper are displayed as they are on the examinee terminal. That is, a question sentence and a plurality of options are displayed on the screen of the examinee terminal, and the examinee selects one of the plurality of options as an answer and inputs the number of the selected option in the answer column on the screen. .
[0003]
[Non-Patent Document 1]
"Digital testing to enable qualification and certification tests on demand", NTT Technical Journal, Telecommunications Association, July 1, 2002, Vol. 14, No. 7, p.55-59.
[0004]
[Problems to be solved by the invention]
The above-described conventional technology merely performs a conventional writing test using paper using a terminal. Therefore, using computer and related information equipment such as CAD (Computer Aided Design) / CAE (Computer Aided Engineering) / CAM (Computer Aided Manufacturing), product design, design analysis, production design, process design, work design, etc. As for the system that supports the system, the technology that actually uses the system has not been evaluated. It was merely a matter of checking the presence or absence of knowledge, and the design technology itself could not be evaluated.
[0005]
Here, CAD is a system that targets a product design process, and supports a process of creating a drawing or 3D model to be designed. CAE is a system that performs various analyzes and evaluations required during the product design and development stages. Specifically, various types of analysis such as product strength analysis, thermal analysis, kinematic analysis, and electrical analysis are performed by simulation using a mathematical model of the product, and the performance and function of the designed product are evaluated. . There are strength analysis by the finite element method and boundary element method, and kinematic analysis using a kinematic model. CAM inputs manufacturing drawing information or 3D product model created by the design system, performs information processing such as production design, process design, and work design, and generates production control information such as NC data. It is a system that controls the production process. For example, in NC machining, machining control information is directly generated from a three-dimensional product model created by CAD.
[0006]
In the field of electronic circuit and electronic device design, CAD / CAE is called EDA (Electronic Design Automation). In particular, EDA in LSI design covers all design processes such as LSI specification design, logic design, and layout design. In some cases, design software that supports a simulation-based part such as logic design is called CAE, and design software that supports layout design is called CAD. Designs using this type of software are sometimes collectively referred to as EDA (Electronic Design Automation).
[0007]
An object of the present invention is to provide a system and method capable of eliminating the above-described drawbacks of the prior art and evaluating the design technique itself.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a design technology evaluation system for evaluating the technical level of design using design software by a user who performs design using design software. A first storage means for storing certain test design data, and a second storage for storing an evaluation criterion for evaluating a design result obtained by designing using design software based on the test design data Storage means and design software are stored, design equipment for the user to design based on the test design data using the design software, and the design results performed by the user using this equipment And evaluation means for evaluating according to the evaluation standard and generating an evaluation result of the technical level of the user.
[0009]
According to the present invention, since the user actually performs the design using the design software, not only the presence / absence of the user's knowledge but also the user's design technology itself can be evaluated, and the skill of the engineer can be rated. It is.
[0010]
In this design technology evaluation system, it is possible to include training instruction means for instructing the user about the training contents regarding the design software based on the evaluation result, and training means for providing the instructed training contents to the user. .
[0011]
In this case, a new engineer or the like can acquire basic design skills through training and / or model answers. New engineers, etc. are introduced to training on their week points, can follow up, and can understand and learn the design software.
[0012]
Further, in the present design technology evaluation system, a management device different from the design device is provided, and the management device includes a second storage unit that stores an evaluation criterion, and an evaluation unit that generates an evaluation result, It is preferable to receive the design result of the user from the design equipment. This can prevent the user from knowing the evaluation criteria and the evaluation method. As a result, the evaluation is performed objectively and fairly, the trust of the third party for the evaluation is increased, and the evaluation system is socially recognized.
[0013]
In this design technology evaluation system, the management device and the design device are separated from the user by being connected via a wired or wireless communication line such as a public line network or an IP (Internet Protocol) network. Users can also be evaluated in places.
[0014]
In this design technology evaluation system, the user equipment used when the user designs based on the test design data has only the design software, and the design data, library, etc. are used from the server in the system, for example. May be.
[0015]
In the design technology evaluation system, the design software can be electronic circuit design software, for example, EDA.
[0016]
In the present design technology evaluation system, the evaluation standard is preferably updated. For example, it is updated every 6 months. As a result, the evaluation method can be improved, the design technique can be changed, and the reliability of the evaluation can be increased.
[0017]
By the way, in this design technology evaluation system, fee management means for confirming payment of a system usage fee by a user and supplying design software and / or test design data to a design device used by the user after confirmation. It is good also as including. Thereby, since user management can be automated, the burden on both the user side and the system management side is reduced.
[0018]
In the design technology evaluation system, the evaluation unit may receive designation of a device that notifies the evaluation result and transmit the evaluation result to the designated device. As an evaluation result notification destination, for example, there is a management department of a company to which a user belongs.
[0019]
The management department can centrally manage the skills of each engineer from the management point of view, and can systematically improve their skills based on the evaluation results. For example, when designing with a team, it becomes possible to assign an optimal work to each member of the team, and the productivity of the team can be improved.
[0020]
In order to solve the above-described problems, the present invention provides a design technology evaluation method for evaluating the technical level of design using design software by a user who performs design using design software. The first storage means stores the test design data in question in the first storage means, and the evaluation criteria for evaluating the design results obtained by designing using the design software based on the test design data. And a design result performed by the user based on the test design data using the design software stored in the design device and evaluating the design result according to the evaluation criteria. And a step of generating a technical level evaluation result. In this case, the same effect as that of the above-described evaluation system can be obtained.
[0021]
Preferably, the design technology evaluation method includes a step of instructing the user about the training content related to the design software based on the evaluation result, and a step of providing the instructed training content to the user.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of a design technology evaluation system according to the present invention will be described in detail with reference to the accompanying drawings. First, an outline of the present embodiment will be described. In the present embodiment, the present invention is applied to software for electronic circuit design (hereinafter referred to as “design tool”). It should be noted that illustration and description of portions not directly related to the present invention are omitted. Here, the reference number of the signal is represented by the reference number of the connecting line that appears. Moreover, what attached | subjected the same referential mark represents the same thing.
[0023]
The design technology evaluation system 10 shown in FIG. 1 is a system 10 constructed using an IP network 12. The user of the system 10, that is, the student, is an in-house evaluation system in the intranet 14 from the client machine 16 constituting the intranet (for example, an in-house network constructed using TCP / IP technology) 14 in the company to which the student belongs. The server 18 or the external evaluation system server 20 that is a management device managed by the management company of this system is accessed and evaluated. The external evaluation system server 20 is connected via the Internet 12. Also connected to the intranet 14 is an administrator machine 22 that collectively manages the evaluation results of the students.
[0024]
A plurality of evaluation system servers may be provided in the system, but one may be provided. In this embodiment, a case where there is one evaluation system server will be described. In FIG. 1, only one of the internal evaluation system server 18 and the external evaluation system server 20 is required. In FIG. 1, an example in which the evaluation system server is arranged in the company and outside the company is shown in one drawing for convenience of illustration. The internal evaluation system server 18 and the external evaluation system server 20 have the same configuration.
[0025]
FIG. 2 specifically shows the configuration when the evaluation system server is arranged outside the company. The external evaluation system server 20 is a data file 20a containing design data for testing, an evaluation file 20b containing model answers and evaluation criteria, a tool file 20c containing design tools, and design of students by evaluating design results according to the evaluation criteria. A control unit 20d that evaluates the technical level and generates an evaluation result, and receives the design result of the student from the design device 16. Further, the device is notified of the evaluation result, and the evaluation result is transmitted to the specified device, for example, the manager machine 22 used by the client machine 16 or the supervisor of the student.
[0026]
In addition to design data for testing design data (RTL (Register Transfer Level), netlist, etc., which shows a unit of circuit), the data file 20a includes general libraries and constraint files related to electronic circuits required for testing. It is.
[0027]
Further, the external evaluation system server 20 includes a training system constructed using TCP / IP technology. The training system includes a training instruction unit 20e that instructs the student on the training content related to the design tool based on the evaluation result, and a training unit 20f that provides the instructed training content to the student.
[0028]
The client machine 16 is a design device, and stores a tool file 20c including a design tool and a data file 20a including test design data, and a student designs based on the test design data using the design tool. To do. In this embodiment, a case where there are three client machines 16 is shown. There is no limit to the number of client machines 16. In addition, it is good also as using the design tool which is not included in the design tool and which is in the machine inside or outside the company.
[0029]
The test management data, model solutions, and evaluation criteria are prepared in advance by the management company of this system in accordance with the purpose of the evaluation and the level of skill of the engineer. The model answer and the evaluation criteria are updated regularly, for example, every six months. Within 6 months, students should not be able to attend multiple times to prevent fraud.
[0030]
The student activates the design tool in the same way as during product development, designs based on the given test design data, and uses the final results (answers) as the answer file as a data file in the client machine 16 Save in 20a. The answer file is sent to the external evaluation system server 20 via the Internet.
[0031]
When the number of client machines 16 connected to the intranet 14 is large, the communication load increases when the client machines 16 individually send and receive a large amount of data to and from the external evaluation system server 20. For example, when the data amount of the design tool or the test question is large, it is not preferable that the client machine 16 individually transmits and receives the same data. In that case, an in-house distribution server may be provided to allow the in-house distribution server to mediate between the client machine 16 and the external evaluation system server 20. That is, when the external evaluation system server 20 distributes the same data to the client machine 16, the data or the like is first sent to the in-house distribution server. Thereafter, it is sent from the in-house distribution server to each client machine 16. Also, when the client machine 16 sends data or the like to the external evaluation system server 20, the data is once collected by the internal distribution server and then sent to the external evaluation system server 20.
[0032]
Thereby, it is possible to reduce a communication load generated by transmitting and receiving a large amount of data between the client machine 16 and the external evaluation system server 20 individually. In addition, security management becomes easy.
[0033]
The control unit 20d of the external evaluation system server 20 automatically scores the answer file sent by the student, and summarizes the result into an evaluation result report as, for example, a 5-stage number. Display on the administrator machine 22. For example, the evaluation criteria are set in advance by causing a plurality of engineers to create answers in advance and statistically processing the distribution state of these answers. The evaluation criteria cannot be changed by the student or the manager of the company to which the student belongs.
[0034]
Test items vary depending on the type of design technology to be evaluated. For example, the number of gates contained in an electronic circuit, timing violation, timing convergence, electronic circuit performance (operating frequency), power consumption, and obtaining an answer There are times.
[0035]
The smaller the number of gates included in the designed circuit, the higher the technical level is usually evaluated. Timing violation means that the delay time of the circuit is longer than the requested delay time. The technical level is evaluated based on the number of portions that have violated timing in the designed circuit and the magnitude of the difference between the delay time of the circuit and the required delay time in the case of the violation. The smaller the number and the smaller the difference, the higher the technical level.
[0036]
Timing convergence is the length of the test time (design time) from when a student changes the design until the timing violation disappears, and how many times the design changes before the timing violation disappears. That is, the number of design changes. The lower the test time and frequency, the higher the technical level.
[0037]
For items with poor evaluation results, the training unit 20f in the external evaluation system server 20 and the client machine 16 can be automatically trained via the Internet for the design tool corresponding to the item. The item in the evaluation result report is linked.
[0038]
The design tools used for testing are not limited to those provided by a specific company. The external evaluation system server 20 prepares test design data and one model answer corresponding to multiple types of design tools, and if the student inputs the answer in a standard format (for example, ASCII code), You can also evaluate design results from other companies' design software. The model solution represents an excellent circuit and is common regardless of multiple design tools.
[0039]
The system 10 includes a fee management means for confirming payment of the fee for use of the system 10 by the student, and supplying the design software and / or test design data to the design equipment used by the student after the confirmation. .
[0040]
The administrator machine 22 receives a list of evaluation results of in-house students from the external evaluation system server 20 and stores it in the result file 22a.
[0041]
The external evaluation system server 20, the client machine 16, and the administrator machine 22 have input / output control units 20g, 16a, and 22b, respectively, and the input / output control units 20g, 16a, and 22b are connected via the communication control unit 24. Communicate with other devices. The communication control unit 24 controls communication within the intranet 14 and also controls communication between the intranet 14 and the Internet 12.
[0042]
Control units 20d, 16b, and 22c in the external evaluation system server 20, the client machine 16, and the administrator machine 22 control input / output of files in each device. The control units 20d and 16b of the client machine 16 also execute design tools to design electronic circuits.
[0043]
Next, a design tool targeted by the present embodiment will be described. This design tool is software for LSI design. Such software is sold as a product from a plurality of companies.
[0044]
With the sophistication and complexity of LSI design, design tools (EDA) have become necessary. Based on the design intention of the designer, LSI is designed using EDA, the design result is verified using EDA, the designer contradicts the design logic contradiction, and the designer changes the design. To do. In this way, logic design and layout design are performed, and finally the LSI design is completed.
[0045]
Generally, as shown in FIG. 3, LSI design is divided into a specification design 26, a logical design 28 (also called Front End), and a layout design 30 (Physical Design) 30 also called Back End. Can be divided roughly. EDA is usually used in logic design and layout design. However, EDA may be used for specification design. In specification design, interface design and architecture design are performed. The output of the specification design is a specification document. However, there are cases where the output of the specification design is electronic data.
[0046]
When the specifications are determined, the designer inputs design data and design conditions into EDA, performs logic design and layout design, finally completes the LSI circuit, and is necessary for manufacturing in the semiconductor manufacturing process. Output information to EDA.
[0047]
To further explain EDA, EDA includes a design tool and a simulation tool corresponding to each of the logic design stage and the layout design stage.
[0048]
For example, in the logic design stage, a designer creates a logic file by describing a logic circuit in RTL using a design language (generally Verilog HDL or VHDL called Hardware Description Language). When you enter information such as performance conditions, constraint conditions (timing, etc.), connection conditions, etc. into this computer together with this file and start the logical design tool, the logical design tool will be converted into a file and functional blocks stocked in the logical design tool Based on the logic synthesis, a netlist is output. The netlist is design data that represents the connection relationship of circuits, and is expressed in a design language. Output in human readable form. Some design tools have a function to display this in the form of a specific circuit.
[0049]
The simulation tool performs error analysis by performing simulation based on the netlist, and notifies the designer of the details of the error. This notification is performed by displaying the error location on a logical file created by the designer and / or on the net list. In addition, if the designer commits a grammatical error in the design language and / or a logic error in the circuit, the design tool cannot create the netlist itself. Notify that there is such an error on the logical file created by the designer. The designer corrects the logical file based on the error content and performs the above process again, and repeats this process if necessary. In this way, the net list is completed.
[0050]
Next, the layout design tool arranges the LSI in a chip having a limited area based on the net list obtained as described above. In the same way, the designer inputs each information such as arrangement and constraint conditions together with the netlist to the computer, and the layout design tool creates layout information called a floor plan based on this information. Simulation is performed to analyze the error, and the error details are specifically notified to the designer. The error information includes, for example, signal delay based on the distance between elements that did not cause a problem on the net list, short circuit, and the like. Based on the error content, the designer corrects the input to the layout information (floor plan) and repeats the above process, and repeats this process if necessary. If necessary, the process is repeated after returning to the logical design and changing the logical file.
[0051]
The LSI design information that has been finalized in this way is output in a form that can be processed by a computer and used as input information for LSI manufacturing in the next process.
[0052]
Errors in all the above processes include errors in the design language grammar, errors in which the logic circuit cannot be built up, such as logical inconsistencies in the electronic circuit expressed in the design language, and the number of required gates. There are different number of gates designed, timing violation (timing design error, timing delay due to wiring length, etc.), timing convergence, performance, power consumption, etc. it can. In addition, the time required from design start to completion can also be evaluated as a designer's design skill. These are considered as evaluation criteria.
[0053]
Next, schematic functions of the design tool used in the present system will be described with reference to FIGS. 4 to 20, the designer (that is, the student) shows the input screen and the output screen displayed on the client machine 16 when designing a circuit using the present design tool in the order of the design process.
[0054]
In FIG. 21 and subsequent figures, specific examples of questions regarding the layout design, examples of answers to the questions, and examples of evaluation of the answers are shown. In the test, the student can take the test for all the processes in the order of the processes. Also, only some of these processes can be tested.
[0055]
FIG. 4 is an input screen for logical design input by the designer. A designer performs RTL description of a circuit to be designed using a design language such as VHDL or VerilogHDL. The designer inputs all the data described on this screen in a design language such as VHDL or VerilogHDL. In this figure, the function of a circuit named topcir is described using VerilogHDL. In VerilogHDL, the description starts with “module” and ends with “endmodule”. FIG. 5 is another example of an input screen for logic design.
[0056]
FIG. 6 shows an example of data input to the HDL simulator for confirming whether the circuit described in HDL in FIGS. 4 and 5 performs a desired operation. A test pattern for testing and a program for observing the output from the circuit when the pattern is input to the circuit to be tested are collectively called a test bench, and FIG. 6 shows this. A pseudo signal is input to the designed circuit and its output condition is designed. This is also entered in HDL by the designer (student). FIG. 7 is a signal waveform diagram obtained by this design. This is the output of the design tool. FIG. 8 is a clock correction input that the designer inputs in the design language.
[0057]
FIG. 9 is a screen obtained by schematizing the netlist obtained by the above design. This is output by the design tool. FIG. 10 is a timing report obtained for the circuit shown in this netlist. This is also output by the design tool software. According to this timing report, the required delay time (Required time) 32 is 13.00 ns, whereas the design delay time (Arrival Time) 34 is 10.70 ns, and the difference 36 is 2.30. It can be seen that it is ns. Required time 32 and Arrival Time 34 are shown for the most severe signal path in the entire circuit.For each component circuit, each circuit is listed in the column of Delay Time (Required) 42 and Delay Time (Arrival Time) 40. Shown for each (Instance) 38. This table is arranged in ascending order of delay time (Required time) 42.
[0058]
FIG. 11 is a clock correction input input in HDL by the designer based on the result of the timing report. The correction input is the same as in FIG. 8, and the same contents as in FIG. 8 are displayed for convenience. This is the logic design, and the layout design is performed from the next.
[0059]
FIG. 12 is a part of an output screen in a design process for obtaining layout information called “Floor Plan”, and a circuit includes a cluster (a set of circuits generally called “macro” or “block”). In this case, the position and size of the cluster on the chip are shown using XY coordinates. The screen shown in FIG. 12 is information about one cluster. When there are a plurality of clusters, a screen is generated for each cluster.
[0060]
FIG. 13 is a semiconductor chip connection report optimized based on the floor plan. Output from the layout design tool. Connection relationships are displayed in a hierarchy. For example, circuit 44 named ACCUM STAT INST includes circuits 46, 48, 50 i 5183, i 5251, i 5317.
[0061]
FIG. 14 is a screen for inputting wiring information to the floor plan. The designer (student) inputs the data. FIG. 12 relates to a cluster, but the screen of FIG. 14 defines a wiring method for a region other than a portion where a cluster is present in a chip. For example, the Weight Control 52a defines the aspect ratio of the wiring. The Placement Control 52b defines what percentage of the available area of the chip is used. The Placement Mode 52c instructs what kind of reference is used for wiring. For example, when “Timing driven 52d” is selected, priority is given to the higher operating frequency. When Congestion driven 52e is selected, wiring is prioritized in terms of wiring congestion.
[0062]
In this screen, what kind of instruction is given depends on the experience of the designer, and therefore the wiring result varies depending on the experience. This way of designating the screen allows the designer to evaluate whether he / she is well using the design tool, that is, the technical level of the designer.
[0063]
FIG. 15 is a timing report based on the wiring information input in FIG. Output from the layout design tool. The timing report is output in various processes. This is because the timing report is output in various processes to check the influence of each input stage on the circuit timing.
[0064]
FIG. 16 shows arrangement information indicating the arrangement of the standard cells 54, which is output by the layout design tool. The cluster is composed of a plurality of standard cells. FIG. 17 is a timing report in the arrangement according to FIG. This is output by the layout design tool.
[0065]
FIG. 18 is an input screen for timing restriction performed by the designer (student). FIG. 19 is a diagram showing a result of automatic placement and wiring performed based on timing constraints, and is a design result of an IC completed as described above. Output from the layout design tool. The wiring may be multilayer wiring. The wiring can be displayed by designating a specific wiring. For example, it is possible to display only the wiring in the first layer, or display only the wiring between specific circuits. FIG. 20 is a final design evaluation report. This is output by the layout design tool.
[0066]
Next, specific examples of questions will be described. The questions will be explained by taking the layout design stage as an example. A case will be described in which a plurality of processes constituting the layout design stage are tested for each process. It is also possible to test the entire layout design stage without testing for each process. It is also possible to test a combination of the logic design stage and the layout design stage.
[0067]
FIG. 21 shows a plurality of steps constituting the layout design stage. In this embodiment, the layout design stage is divided into a floor plan process, a placement and routing process, a physical verification process, a delay calculation process, and a timing analysis process, and questions 56a, 56b, 56c, 56d, and 56e are performed for each process. Then, evaluation is performed by setting the evaluation items 58a, 58b, 58c, 58d, and 58e for each process.
[0068]
The floor plan process is a process of designing block or cluster unit arrangement (initial arrangement) and power consumption in the arrangement. Evaluation items 58a in the floor plan process include initial arrangement (referred to as “floor plan”) and Power (referred to as “power plan”).
[0069]
The placement and routing process is a process of designing more detailed placement (standard cell placement in a block, etc.) based on the result of the floor plan process. The evaluation item 58b of the placement and routing process includes the detailed placement result and the clock tree. And the wiring result. Here, the clock tree is obtained by connecting a large number of clock buffers on the tree.
[0070]
In the physical verification process, the circuit is physically verified based on the result in the placement and routing process. The verification items are, for example, DRC (Design Rule Checking), ERC (Electrical Rule Checking), and LVS (Layout Versus Schematic). DRC is to check geometric design rules such as the minimum line width and minimum interval of a mask pattern. ERC is a check of electrical design rules such as a short circuit. LVS is extracting connection information of an electronic circuit from layout data and verifying whether the layout data matches a given logic circuit element or a connection between elements. The evaluation items of the physical verification process 58c are, for example, DRC, ERC, and LVS.
[0071]
In the delay calculation process, for example, RC Ext (RC Extraction) is obtained based on the result in the placement and routing process. RC Ext (RC Extraction) is to extract the parasitic resistance (R), parasitic capacitance (C), and parasitic diode from the layout, and evaluate the delay amount of the circuit. The evaluation item 58d of the delay calculation process is RC Ext.
[0072]
Next, specific evaluation examples will be shown for the floor plan process, the placement and routing process, and the physical verification process. FIG. 22 shows an example 60 of questions in the floor plan process. One question example 60 includes a problem 60a, a netlist 60b obtained by logic design, a specification 60d, a constraint condition 60c, and a library 60e such as characteristic data of a standard circuit necessary for solving the problem. included. The question example 60 is stored in the data file 20a in the external evaluation system server 20, and then stored in the data file 20a in the client machine 16 via the Internet.
[0073]
Based on this problem 60, the user obtains a design result 62 using the design tool 20c. The result 62 includes a floor plan 62a and a report file 62b including a power plan. Note that the report file 62b may be output in binary format to prevent fraud. When this design result (answer) is sent to the external evaluation system server 20 via the Internet, the external evaluation system server 20 evaluates it according to the evaluation criteria for the floor plan process stored in the evaluation file 20b, and the evaluation result 64 Is displayed on the client machine 16 and the administrator machine 22. In the evaluation result 64, for example, the overall judgment 64a is displayed as 2, the operating frequency 64b is 3, the power 64c is 1, and the chip size (Die Size) 64d is 2.
[0074]
FIG. 23 shows an example 60 of questions in the placement and routing process. One question example 66 includes a problem 66a, a netlist 60b obtained by logic design, a specification 60d, a constraint condition 60c, and a library 60e such as characteristic data of a standard circuit necessary for solving the problem. The floor plan result 62a is included. The question examples 66 are stored in the data file 20a in the external evaluation system server 20, and then stored in the data file 20a in the client machine 16 via the Internet.
[0075]
Based on this problem 66, the user obtains a design result 68 using the design tool 20c. The result 68 includes a place and route result 68a and a report file 68b including information on the clock. When this design result (answer) is sent to the external evaluation system server 20 via the Internet, the external evaluation system server 20 evaluates according to the evaluation criteria for the placement and routing process stored in the evaluation file 20b, and the evaluation result 70 Is created and displayed on the client machine 16. In the evaluation result 70, for example, the overall judgment 70a is displayed as 3, the operating frequency 70b is displayed as 3, the setup violation 70c is displayed as 4, and the Hold violation 70d is displayed as 2 according to a 5-level evaluation. Setup violation and Hold violation are timing evaluations.
[0076]
FIG. 24 shows an example 60 of questions in the physical verification process. One question example 72 includes a problem 72a, a placement and routing result 68c, a specification 60d, and a rule file 72b necessary for verification. The question examples 66 are stored in the data file 20a in the external evaluation system server 20, and then stored in the data file 20a in the client machine 16 via the Internet.
[0077]
The user performs physical verification using the design tool 20c based on the problem 72, corrects the violation portion, and obtains a verification result 74. The result 74 includes information such as a design rule violation. When this design result (answer) is sent to the external evaluation system server 20 via the Internet, the external evaluation system server 20 evaluates according to the evaluation criteria for the physical verification process stored in the evaluation file 20b, and the evaluation result 76 Is created and displayed on the client machine 16. In the evaluation result 76, for example, the overall judgment 76a is displayed as 4, the processing time 76b is 3, the DRC violation 76c is 4, and the chip size 76d is 5 according to, for example, a five-step evaluation.
[0078]
Next, FIG. 25 shows an example of evaluating the entire layout design. In this case, the floor plan process input is presented to the user as a question. That is, the question 78 includes a netlist 60b obtained by logic design, a specification 60d, a constraint condition 60c, and a library 60e such as characteristic data of a standard circuit necessary for solving the problem. The example questions 78 are stored in the data file 20a in the external evaluation system server 20, and then stored in the data file 20a in the client machine 16 via the Internet.
[0079]
Based on this problem 60, the user obtains a design result 78 using the design tool 20c. The result 78 includes a floor plan result 78a, a placement and routing result 78b, a physical verification result 78c, a delay calculation result 78d, and a timing analysis result 78e. When this design result (answer) is sent to the external evaluation system server 20 via the Internet, the external evaluation system server 20 evaluates it according to the evaluation criteria for the entire layout design stored in the evaluation file 20b, and the result shown in FIG. The evaluation result 80 shown is created and displayed on the client machine 16. The evaluation result 80 includes, for example, a five-step evaluation, the overall evaluation is 2, the operating frequency is 3, the power is 2, the chip size is 1, the DRC is 1, and the processing time (design time) is 1. Is displayed.
[0080]
Next, based on the evaluation result of FIG. 26, the follow-up performed for the user will be described. The external evaluation system server 20 can also present the user evaluation screen 88 shown in FIG. 27 to the user in addition to the evaluation result as shown in FIG. This is a screen for presenting the evaluation result 80 of FIG. 26 and giving instructions for practicing the lacking technique. For practice, a training screen 86 for confirming the knowledge of those with low evaluation points and a follow-up screen 84 (Fig. 28) for practicing while sequentially guiding the design procedure in order to correctly solve the questions. is there. Screen 86 and screen 84 are displayed together with user evaluation screen 88 for the convenience of the user. The user evaluation screen 88 and the training screen 86 are linked.
[0081]
The follow-up screen 84 and the user evaluation screen 88 are output by the training instruction unit 20e of the external evaluation system server 20. The follow-up screen 84 and the evaluation screen 88 are HTML documents created in the HTML format, and a link is provided from the user evaluation screen 88 to the training screen 86. Further, a link is provided from the follow-up screen 84 to a screen (not shown). There are model answers 84a, 84b, 84c, 84d, and 84e at the link destination.
[0082]
FIG. 29 shows the user evaluation screen 88 in detail. In the evaluation screen, a target setting field 90 for strengthening the skill of the user is provided. The user finds a weak point from the evaluation result and describes a goal for overcoming the weak point.
[0083]
FIG. 30 shows an example of a screen displayed on the administrator machine 22. The screen includes a user evaluation screen 88 presented to the user and a user evaluation screen 92 presented only to the administrator. The user evaluation screen 92 displays field information suitable for the user, effort targets, and the like.
[0084]
As shown in FIG. 31, the user evaluation screen 88 displayed on the administrator machine 22 is linked to a screen 94 showing details of evaluation criteria and a screen 96 displaying user evaluations in a graph. A screen 94 showing the details of the evaluation criteria and a screen 96 displaying the user evaluation in a graph are shown in FIG.
[0085]
Thus, according to the present embodiment, the technology evaluation system has the following functions. It can be used for evaluation in various places in the company because it can use the company LAN (intranet) based on TCP / IP technology or the Internet. When there is only one evaluation system server, all evaluation results, target setting, and evaluation problems can be managed in an integrated manner.
[0086]
Regarding the evaluation standard setting function of the technical evaluation system, the system has an evaluation standard setting function. For example, an evaluation standard can be prepared for each question, and the standard can be reviewed in detail. In addition, it is preferable to provide follow-up items corresponding to the evaluation criteria. The evaluation results can be linked to follow-up or training. Regarding the information management function of the technical evaluation system, it is possible to accumulate information on questions and their evaluation criteria, and evaluation results and targets for each engineer.
[0087]
The present embodiment has the following effects. By diagnosing designer skills objectively, centrally, and regularly within the company, designers can be improved. In addition, engineer's self-development motivation can be enhanced.
[0088]
It is possible to manage and evaluate the design ability of external design subcontractor engineers, calculate appropriate costs, and optimize the market.
[0089]
Within a company, it is possible to train and discriminate project managers (people who manage design in a vertically integrated manner, not experts of individual tools). By using this system in mergers and integrations between companies, it is possible to effectively place personnel in the right place.
[0090]
If this system is used globally, the skills of engineers and project managers can be managed globally. In addition, if this system is used at universities, etc., it is possible to cultivate the young generation's ready-to-use skills at the Western level.
[0091]
According to this system, it is possible to evaluate skills at the engineer level and the worker level. Here, the engineer level is a level at which a solution to a given problem can be searched and solved by itself, and the worker level is a level at which a solution can be solved by a given method. In other words, the certification level of the system of the present embodiment is such that the basic function of the tool can be understood, the worker level that can understand the function of the tool necessary for performing a certain basic design, and a practical design. It is aimed at the engineer level, which can execute the functions of the above in necessary steps and can be completed within a predetermined time.
[0092]
One of the effects of this system is that it can motivate students to raise their consciousness to improve their skills and challenge new design methods. In addition, the skill evaluation of this system can be performed in about 1 or 2 days when the evaluation items are embedded in a test problem of about 1/10 of the actual design scale. There is no problem even if you take your time.
[0093]
The effects of the system as described above can be considered to satisfy the following social needs concerning the skills of engineers.
-It is necessary to assign an appropriate engineer for each role of project leader (administrator), engineer, and operator.
-In order to eliminate chronic engineer shortages, it is required to improve the skills of new engineers as quickly as possible.
-Each engineer needs to be aware of skill improvement.
-It is important how quickly mid-level engineers can use the latest design tools to cope with more sophisticated and complex designs.
-Project leaders need to understand the skills of engineers participating from each department and assign human resources to the right place.
-When working with external engineers (mergers, outsourcing, from other countries, etc.), a global industry standard method is needed that can objectively assess skills.
[0094]
Possible effects of this system include:
・ It is possible to rank and manage the skills of engineers in the company and subcontractors.
・ Engineer skills are rated practically and self-development is possible. Specifically, the design can be actually performed, and the design skill of the engineer can be measured (automatically as much as possible) from the result, and evaluated and rated. In addition, it is possible to set specific goals for skill improvement by the engineers themselves from the evaluation results.
・ New engineers can be trained in basic design skills. In other words, it can be surely understood through follow-up such as presentation of model answers and introduction of weekpoint training.
・ Skills for each engineer required for management work can be managed in a centralized manner, and each person's skill improvement can be promoted systematically. That is, a skill improvement plan for each engineer can be made from the evaluation result. In addition, engineers can be re-evaluated based on the achievement level of the skill improvement plan.
-Optimal work assignment is possible when teams perform design work.
・ With this system, a qualification system can be established in-house or in the industry.
[0095]
In the above embodiment, the design software for electronic circuits has been described. However, the present invention is not limited to this, and the present invention is generally applied to design software used for design such as electrical design or mechanical design. be able to.
[0096]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a system and a method capable of evaluating the design technique itself.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing an embodiment of a design technology evaluation system according to the present invention.
FIG. 2 is a block diagram of the design technology evaluation system shown in FIG.
FIG. 3 is a diagram showing a design flow by EDA.
FIG. 4 is an explanatory diagram showing an input screen for logical design input by a student.
FIG. 5 is an explanatory diagram showing another example of an input screen for logic design.
FIG. 6 is an explanatory diagram showing an example of data input to an HDL simulator.
FIG. 7 is a signal waveform diagram obtained by design.
FIG. 8 is an explanatory diagram showing clock correction input that a designer inputs in a design language;
FIG. 9 is an explanatory diagram showing a screen obtained by schematizing a net list obtained by design.
FIG. 10 is an explanatory diagram showing a timing report obtained for a circuit indicated by a netlist.
FIG. 11 is an explanatory diagram showing clock correction input.
FIG. 12 is an explanatory diagram showing an output screen in a design process for obtaining layout information.
FIG. 13 is an explanatory diagram showing a connection report of a semiconductor chip.
FIG. 14 is an explanatory diagram showing a screen for inputting wiring information.
FIG. 15 is an explanatory diagram showing a timing report based on wiring information.
FIG. 16 is an explanatory diagram showing arrangement information indicating the arrangement of standard cells.
FIG. 17 is an explanatory diagram showing a timing report in the arrangement according to FIG. 16;
FIG. 18 is an explanatory diagram showing an input screen for timing restriction.
FIG. 19 is an explanatory diagram showing a result of automatic wiring.
FIG. 20 is an explanatory diagram showing a final design evaluation report.
FIG. 21 is an explanatory diagram showing a plurality of steps constituting the layout design stage.
FIG. 22 is an explanatory diagram showing an example of questions in the floor plan process.
FIG. 23 is an explanatory diagram showing an example of questions in the placement and routing process.
FIG. 24 is an explanatory diagram showing an example of questions in the physical verification process.
FIG. 25 is an explanatory diagram showing an example of evaluating the entire layout design.
FIG. 26 is an explanatory diagram showing an example of an evaluation result.
FIG. 27 is an explanatory diagram showing an example of follow-up performed for a user.
FIG. 28 is an explanatory diagram showing an example of a follow-up screen.
FIG. 29 is an explanatory diagram showing a user evaluation screen in detail.
FIG. 30 is an explanatory diagram illustrating an example of a screen displayed on the administrator machine.
FIG. 31 is an explanatory diagram showing a link destination of a user evaluation screen.
FIG. 32 is an explanatory diagram showing a screen showing details of evaluation criteria and a screen displaying user evaluation in a graph.
[Explanation of symbols]
10 Design technology evaluation system
12 IP network
14 Intranet
16 Client machines
18 In-house evaluation system server
20 External evaluation system server
20a data files
20b evaluation file
20c tool file

Claims (7)

A function for executing a design according to user input data, a function for indicating to the user an error based on the executed design result and / or the user input, and the user to the design software Design technology using the design software of a user who performs design using design software having a function of executing design on the corrected input when the error corrected input is performed a design technique evaluation system for evaluating the level, the system comprising:
First memory means for storing the test design data is a matter for evaluation, and design results by the user using the design software for based on the test design data is obtained by the Tsu line design An evaluation device that includes second storage means for storing evaluation reference data for evaluating data, and that evaluates the design result data based on the evaluation reference data;
Wherein together designed for software are stored, and a the user to design equipment to create the design result data to execute the design based on the test design data by using the design software for,
The design result data is based on at least the number of design changes made to eliminate the error, the time taken to eliminate the error, the time required from design start to completion, and the test design data. Including the answer to the design
The evaluation device is communicably connected to the design device,
The evaluation device receives the design result data from the design device, and measures the presence / absence of the user's knowledge and the degree of utilization of the design software from the design result data based on the evaluation reference data Then, a design technology evaluation system comprising evaluation means for generating an evaluation result of the technical level of the user. The design technology evaluation system according to claim 1, wherein the system includes:
Training instruction means for instructing the user on the contents of training related to the design software based on the evaluation result;
And a training means for providing the instructed training content to the user.   3. The design technology evaluation system according to claim 1, wherein the evaluation device and the design device are connected via a wired or wireless communication line such as a public line network or an IP (Internet Protocol) network. Design technology evaluation system characterized by   4. The design technology evaluation system according to claim 1, wherein the design software is software for designing an electronic circuit.   5. The design technology evaluation system according to claim 1, wherein the evaluation standard and test design data are updated.   The design technology evaluation system according to any one of claims 1 to 5, wherein the system confirms payment of a usage fee of the system by the user, and after the confirmation, the system uses the design equipment used by the user. A design technology evaluation system comprising charge management means for supplying the design software and / or test design data.   The design technology evaluation system according to any one of claims 1 to 6, wherein the evaluation device receives designation of a device that notifies the evaluation result, and transmits the evaluation result to the designated device. Design technology evaluation system.

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