JP4352787B2 - Power converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power conversion device that obtains an output voltage having a staircase waveform by combining outputs of a plurality of inverter circuits.
[0002]
[Prior art]
Since there is a limitation on the capacity that can be obtained with one inverter circuit, there is a power conversion device configured using a plurality of inverter circuits as one of the inverter devices for large capacity use.
[0003]
Prior art
For example, Non-Patent Document 1 discusses a serial multiple inverter device (power conversion device). This will be described by taking a single-phase triple inverter device as an example, and has the basic configuration shown in FIG. That is, one DC voltage source (voltage E _d The output terminals of three single-phase self-excited inverter circuits connected in parallel to each other are transformer Tr ₁ ~ Tr ₃ Connected to the primary winding. Transformer Tr ₁ ~ Tr ₃ Secondary windings are connected in series with each transformer Tr ₁ ~ Tr ₃ The voltage v appearing at the secondary winding of ₁ ~ V ₃ Is the output voltage of the power conversion device. Output voltage v of each inverter circuit ₁ , V ₂ , V ₃ The size of the transformer Tr ₁ ~ Tr ₃ This is determined by the voltage ratio between the primary winding and the secondary winding. The output of each inverter circuit is multiplexed by providing a phase difference as shown in FIG. 23 (b), thereby reducing and removing harmonic components contained in the output voltage v of the power converter, and making it more sinusoidal. A close output voltage v can be obtained (see, for example, Non-Patent Document 1).
[0004]
Prior art 2.
In another conventional power conversion device, n single-phase output inverter bridges capable of three-level output are provided, and n inverters are connected in series. The amplitude ratio of the output voltages V1, V2, V3 and Vn of the inverter bridge is V1: V2: V3: Vn = 1: 2: 4: 2. ^(n-1) A voltage amplitude ratio distribution means, a command voltage generation means for generating a voltage closest to an output voltage command given to the power converter by a combination of the output voltages of the inverter bridge, and power conversion by pulse width modulating the inverter bridge Output voltage adjusting means for adjusting the generated voltage so that the average value of the output voltage of the entire apparatus becomes equal to the voltage command (see, for example, Patent Document 1).
[0005]
[Non-Patent Document 1]
"Power Electronics Circuit" The Institute of Electrical Engineers, Semiconductor Power Conversion System Research Special Committee, Ohmsha, November 30, 2000, p. 143-153
[Patent Document 1]
JP 11-89242 A (page 1-4, FIG. 1)
[0006]
[Problems to be solved by the invention]
In the power conversion device according to the prior art 1, a transformer Tr connected in series and having a different voltage ratio ₁ ~ Tr ₃ The current i passing through the secondary winding is common, but the current flowing through the primary winding is different for each transformer Tr. ₁ ~ Tr ₃ It depends on the turn ratio. Therefore, the rated current of each inverter circuit is ₁ ~ Tr ₃ Increase or decrease depending on the turn ratio. Therefore, it is necessary to use self-extinguishing semiconductor elements and diodes constituting the inverter circuit that have different rated currents, or have the same rated current and be connected in different numbers. Therefore, a power converter cannot be constituted by applying the same inverter circuit. For this reason, there exists a problem that cost increases.
Further, when the output voltage v of the power conversion device is increased, there is a problem that it is necessary to redesign the transformer and the inverter circuit connected thereto according to the voltage.
That is, there is a problem that the inverter circuit to be multiplexed cannot be standardized.
[0007]
Also in the power conversion device according to the prior art 2, the voltage values input to the single-phase output inverter bridges are different, so that the rated voltage of the self-extinguishing semiconductor element, the diode, or the DC capacitor constituting the inverter circuit is different. Therefore, there is the same problem as in the case of the prior art 1.
[0008]
The present invention has been made in order to solve the above-described problems of the prior art, and provides a power conversion device capable of multi-leveling an output voltage using a standardized unit power conversion unit. For the purpose.
[0009]
[Means for Solving the Problems]
The power conversion device according to the present invention includes an inverter circuit and an independent DC power supply, and is the same circuit capable of outputting three levels {1, 0, −1} with values normalized by the DC voltage value of the DC power supply. A power conversion device comprising a plurality of unit power conversion units having a configuration, wherein the output terminals of the unit power conversion units are connected in series, and m ₁ The unit power conversion unit is {m ₁ , ..., 0, ..., -m ₁ } 'S (2m ₁ A first unit power conversion unit group capable of +1) level output; and m ₂ The unit power conversion unit is {m ₂ , ..., 0, ..., -m ₂ } 'S (2m ₂ +1) a second unit power conversion unit group capable of level output, m _n Pieces (m ₁ , M ₂ , ..., m _n , And n are natural numbers, m ₁ <M ₂ <... <m _n , 3 ≦ n. ) Unit power conversion unit {m _n , ..., 0, ..., -m _n } 'S (2m _n +1) n-th unit power conversion unit group capable of level output, and each output voltage of each unit power conversion unit group At least one output voltage among the unit power conversion units belonging to the unit power conversion unit group by shifting the on / off control timing to form an output waveform having a stepped rise. Select as appropriate Pseudo sine wave An output voltage having a staircase waveform is obtained.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a diagram for explaining a power conversion apparatus according to Embodiment 1 of the present invention. More specifically, the number of unit power conversion units is 7, and the number of unit power conversion unit groups is 3 (n = 3). It is a figure which shows the circuit structure in the case of making the power converter device at the time of operate | move as a multiple inverter apparatus.
In FIG. 1, the power conversion apparatus 2 includes seven unit power conversion units 51 to 57 (may be represented by 5) all having the same circuit configuration, and each output terminal 81 to 87 ( 8) and 91 to 97 (may be represented by 9) are connected in series. Input power transformers 101 to 107 are provided for the unit power conversion units 51 to 57, respectively. The primary windings 111 to 117 of each of the input transformers 101 to 107 are all connected to the polyphase AC power source 1, and the secondary windings 121 to 127 are the first input terminal groups of the unit power conversion units 51 to 57, respectively. 71 to 77 (may be represented by 7).
The first input terminals 131 to 137 (may be represented by 13) of the unit power conversion units 51 to 57 are respectively connected via communication lines 151 to 157 (may be represented by 15). The control circuit 16 is connected to fifth output terminals 141 to 147 (may be represented by 14).
[0011]
The first unit power conversion unit group 61 (may be represented by 6) is 1 (= 2). ⁰ ) Unit power conversion units 51, and the second unit power conversion unit group 62 (may be represented by 6) is 2 (= 2). ¹ ) Unit power conversion units 52 and 53, and the third unit power conversion unit group 63 (may be represented by 6) is 4 (= 2). ² ) Unit power conversion units 54-57.
[0012]
The first output terminal 3 and the second output terminal 4 are output terminals of the power converter 2, and the first output terminal 3 is connected to the third output terminal 81 of the unit power conversion unit 51, The output terminal 4 is connected to the fourth output terminal 97 of the unit power conversion unit 57. Between the 1st output terminal 3 and the 2nd output terminal 4, the voltage of the output voltage total value of each power conversion unit 51-57 can be applied.
[0013]
FIG. 2 is a diagram illustrating a circuit configuration of a unit power conversion unit applied to the power conversion apparatus of FIG. The DC power supply of the power conversion device in the present embodiment is independent for each unit power conversion unit 51 to 57, and includes a DC link circuit 18 including the DC capacitor 20 and a three-phase rectifier circuit for charging the DC capacitor 20. 17. In FIG. 2, the three-phase rectifier circuit 17 rectifies the voltage of the first input terminal group 7 and charges the DC capacitor 20 of the DC link circuit 18 to the polarity shown in the figure. Note that the voltage of the DC capacitor 20 corresponding to the potential difference between the potential P and the potential N of the DC link circuit 18 is V.
The single-phase self-excited inverter circuit 19 can output the voltage of the DC capacitor 20 between the third output terminal 8 and the fourth output terminal 9 for an arbitrary period.
[0014]
FIG. 3 is a diagram showing a detailed circuit configuration of the unit power conversion unit of FIG. In FIG. 3, the first face modules 231 to 233 (may be represented by 23) constitute the three-phase rectifier circuit 17, and the second face modules 241 to 242 (may be represented by 24). Is a single-phase self-excited inverter circuit 19. Specifically, the first face modules 231 to 233 can be as shown in FIG. 4, and the second face modules 241 to 242 are specifically as shown in FIG. Is applicable.
[0015]
FIG. 4 is a diagram showing a circuit configuration of a first face module applied to the three-phase rectifier circuit of FIG. In FIG. 4, the first face module 23 includes diodes 311 and 312.
FIG. 5 is a diagram showing a circuit configuration of a second face module applied to the single-phase self-excited inverter circuit of FIG. In FIG. 5, the second face module 24 is represented by self-extinguishing semiconductor elements 321 and 322 (which may be represented by 32) and diodes 313 and 314 (31 which are connected in reverse parallel to them). There are also cases.)
The self-extinguishing semiconductor elements 321 and 322 are switched on and off by the gate drive circuit 33. The gate drive circuit 33 is a logic circuit for alternately turning on and off the self-extinguishing semiconductor elements 321 and 322, and is simultaneously turned on (DC circuit short circuit) due to a difference in turn-on characteristics and turn-off characteristics of the self-extinguishing semiconductor elements 321 and 322. ), A gate driver circuit for generating a gate pulse to be applied to the gates of the self-extinguishing semiconductor elements 321 and 322, and the like. In FIG. 5, the symbols of IGBTs (Insulated Gate Bipolar Transistors) are used as symbols of the self-extinguishing semiconductor elements 321 and 322, but other self-extinguishing semiconductor elements can also be used.
[0016]
The third input terminals 251 to 253 (may be represented by 25) of the first face modules 231 to 233 and the fifth input terminals 271 and 272 (represented by 27) of the second face modules 241 and 242. Is connected to the positive electrode P of the DC link circuit 18, and the fourth input terminals 261 to 263 (which may be represented by 26) of the first face modules 231 to 233 and the second. The sixth input terminals 281 and 282 (may be represented by 28) of the face modules 241 and 242 are connected to the negative electrode N. In addition, sixth output terminals 291 to 293 (may be represented by 29) of the first face modules 231 to 233 constitute the first input terminal group 7 and the second output of the second face module 241. 7 output terminal 301 (may be represented by 30) is the fourth output terminal 9 and seventh output terminal 302 of the second face module 242 (may be represented by 30). Constitutes a third output terminal 8.
[0017]
In the present embodiment, the unit power conversion units 51 to 57 are configured as described above. For example, by turning on and off the self-extinguishing semiconductor elements 321 and 322 of the second face modules 241 and 242, A voltage can be applied between the third output terminal 8 and the fourth output terminal 9.
[0018]
A specific operation of the single-phase self-excited inverter circuit 19 will be described.
When the voltage of the DC capacitor 20 of the DC link circuit 18 is V, the self-extinguishing semiconductor element 321 of the second face module 241 is turned on, the self-extinguishing semiconductor element 322 is turned off, and the second face module 242 When the self-extinguishing semiconductor element 321 is turned off and the self-extinguishing semiconductor element 322 is turned on, the potential of the fourth output terminal 9 with respect to the third output terminal 8 becomes V.
Further, the self-extinguishing semiconductor element 321 of the second face module 241 is turned off, the self-extinguishing semiconductor element 322 is turned on, and the self-extinguishing semiconductor element 321 of the second face module 242 is turned on, self-extinguishing type. When the semiconductor element 322 is turned off, the potential of the fourth output terminal 9 with respect to the third output terminal 8 becomes −V.
[0019]
Further, the self-extinguishing semiconductor element 321 of the second face module 241 is turned on, the self-extinguishing semiconductor element 322 is turned off, and the self-extinguishing semiconductor element 321 of the second face module 242 is turned on, self-extinguishing type. The semiconductor element 322 is turned off, or the self-extinguishing semiconductor element 321 of the second face module 241 is turned off, the self-extinguishing semiconductor element 322 is turned on, and the self-extinguishing semiconductor element 321 of the second face module 242 is turned off. When the self-extinguishing semiconductor element 322 is turned on, the potential of the fourth output terminal 9 with respect to the third output terminal 8 is equal to the on-voltage of the self-extinguishing semiconductor element 32 and the diode 31. If compared with V, it can be regarded as zero.
[0020]
The power conversion device 2 includes a control circuit 16, and a signal for driving the single-phase self-excited inverter circuit 19 of each unit power conversion unit 5 is created by the control circuit 16. FIG. 6 shows the configuration of the control circuit 16. Here, the signal processing performed by the control circuit 16 is constituted by a microcomputer-based controller such as a DSP (Digital Signal Processor). In FIG. 6, the gate signal generation circuit 34 includes an arithmetic circuit that calculates gate signals for the first to third unit power conversion unit groups 61 to 63 so that the power conversion device 2 obtains an output voltage having a predetermined waveform. ing. The signal generated by the gate signal generation circuit 34 is output from the eighth output terminals 351 to 353. Here, the signal output from the eighth output terminal 351 is a gate signal for driving the unit power conversion unit 51 in the first unit power conversion unit group 61. The signal output from the seventh output terminal 352 is a gate signal for driving the unit power conversion units 52 and 53 in the second unit power conversion unit group 62. Furthermore, the signal output from the eighth output terminal 353 is a gate signal for driving the unit power conversion units 54 to 57 in the third unit power conversion unit group 63.
As described above, the on / off control period of the self-extinguishing semiconductor elements 321 and 322 is performed in units of 6 unit power conversion unit groups. Here, the control by the unit power conversion unit group 6 (in units of the unit power conversion unit group 6) is referred to as group management control of the unit power conversion unit 5.
In this embodiment, the same group Genus The unit power conversion units to be turned on / off are simultaneously controlled.
[0021]
As shown in FIG. 1, for example, the fifth output terminal 141 of the control circuit 16 is connected to the first input terminal 131 of the unit power conversion unit 51. Further, as shown in FIG. 3, the signal received by the first input terminal 13 is sent to the gate signal distribution circuit 22. The gate signal distribution circuit 22 performs arithmetic processing for applying a predetermined voltage between the third output terminal 8 and the fourth output terminal 9 of the unit power conversion unit 5, and the second input terminal of the face module The gate signal is distributed to 211 and 212 (may be represented by 21). Here, the gate signal distribution circuit 22 is configured by a microcomputer-based controller such as a DSP (Digital Signal Processor). As shown in FIG. 5, the gate drive circuit 33 can drive the self-extinguishing semiconductor elements 321 and 322 on and off according to the signal received from the gate signal distribution circuit 22. Similarly, the other unit power conversion units 52 to 57 are connected to the control circuit 16.
[0022]
When the voltage of the DC capacitor 20 is V and the voltage of the DC capacitor 20 is normalized by V, it is applied between the third output terminal 8 and the fourth output terminal 9 of the unit power conversion unit 5. Since the possible voltage values are {-1, 0, 1}, Genus When the unit power conversion units 5 are driven in groups in a manner in which the unit power conversion units to be simultaneously turned on / off are controlled, between the third output terminal 81 and the fourth output terminal 91 in the first unit power conversion unit group 61 The voltage value that can be applied to is {-1, 0, 1}. Further, the voltage value that can be applied between the third output terminal 82 and the fourth output terminal 93 in the second unit power conversion unit group 62 is {−2, 0, 2}, and the unit power conversion unit. The voltage value that can be applied between the third output terminal 84 and the fourth output terminal 97 in the group 63 is {−4, 0, 4}. Between the first output terminal 3 and the second output terminal 4 of the power conversion device 2, it is possible to apply a voltage that is the sum of the voltages applied to the output terminals of each unit power conversion unit group. By combining output voltage values of the first to third unit power conversion unit groups 61 to 63, {−7, −6, −5, −4, −3, −2, −1, 0, 1, 2, A total of 15 levels of voltage of 3, 4, 5, 6, 7} can be output in an arbitrary period. Therefore, each output voltage of each unit power conversion unit group 61-63 can be appropriately selected to obtain an output voltage having a desired staircase waveform.
[0023]
FIG. 7 shows the output voltage waveform of the power conversion device operated by the group management control of the unit power conversion units described above and each unit power conversion unit group. In FIG. 7, the first voltage waveform 36 is a voltage (simply referred to as first unit power) applied between the third output terminal 81 and the fourth output terminal 91 in the first unit power conversion unit group 61. The second voltage waveform 37 is applied between the third output terminal 82 and the fourth output terminal 93 in the second unit power conversion unit group 62. The third output voltage waveform 38 is the third output terminal in the third unit power conversion unit group 63. The third output voltage waveform 38 is the output voltage of the second unit power conversion unit group 62. 84 and a fourth output terminal 97 are respectively applied to voltages (also simply referred to as an output voltage of the third unit power conversion unit group 63). The fourth voltage waveform 50 may be a voltage applied between the first output terminal 3 and the second output terminal 4 of the power converter 2 (simply simply referred to as the output voltage of the power converter 2). ). In FIG. 7, each voltage value is represented by a value normalized by the DC voltage value V of the DC power supply (DC capacitor 20).
[0024]
As shown in FIG. 7, the output voltage value 0 of the power conversion device 2 selects all 0 as the output voltages of the first to third unit power conversion unit groups 61 to 63, and the output voltage value of the power conversion device 2. 1 indicates that the output voltage of the first unit power conversion unit group 61 is 1, and the output voltage of the second and third unit power conversion unit groups 62 and 63 is 0, and the output voltage value 2 of the power conversion device 2 Is selected as 0 for the output voltage of the first and third unit power conversion unit groups 61 and 63, 2 for the output voltage of the second unit power conversion unit group 62, and so on. By appropriately selecting each output voltage of the unit power conversion unit groups 61 to 63, it is possible to obtain an output voltage having a staircase waveform close to a sine wave. Further, by appropriately selecting a period ΔT of each output, a more sine wave can be obtained. Output voltage with a staircase waveform close to It can be seen.
[0025]
As described above, since the power conversion device 2 according to the present embodiment can multiplex the unit power conversion units 5 without using transformers having different voltage ratios, the rated currents of the unit power conversion units 51 to 57 can be obtained. Can be equal. Therefore, the standardized inverter circuit 19 can be applied as the unit power conversion unit 5, and furthermore, the standardized unit power conversion unit 5 having the same circuit configuration can be used, thereby reducing the cost of the power conversion device. Can be reduced.
[0026]
Further, the capacity increase of the power conversion device 2 in the present embodiment can be dealt with by increasing the number of unit power conversion units 5 if the rated voltage of the applied load becomes high.
In addition, since the unit power conversion unit can be standardized, the maintenance is easy, and if any unit power conversion unit fails, the unit reliability can be easily replaced.
[0027]
In addition, by performing group management control of the plurality of unit power conversion units 52 and 53, 54 to 57, the output voltage of the power conversion device can be multi-leveled to obtain an output voltage having a staircase waveform close to a sine wave. It is also possible to reduce harmonics included in the voltage.
[0028]
Although the number of unit power conversion units 5 in FIG. 1 is set to 7, the number can be arbitrarily selected according to the required output voltage. Further, the number n of unit power conversion unit groups 6 and the number of unit power conversion units 5 in the unit power conversion unit group 6 can be arbitrarily selected in the same manner as the number of unit power conversion units 5.
That is, m ₁ Consisting of 5 unit power conversion units 5 {m ₁ , ..., 0, ..., -m ₁ } 'S (2m ₁ +1) a first unit power conversion unit group 6 capable of outputting a level, m ₂ The unit power conversion unit 5 is {m ₂ , ..., 0, ..., -m ₂ } 'S (2m ₂ +1) a second unit power conversion unit group 6 capable of level output,..., M _n Pieces (m ₁ , M ₂ , ..., m _n , And n are natural numbers, m ₁ <M ₂ <... <m _n , 3 ≦ n. ) Unit power conversion unit 5 {m _n , ..., 0, ..., -m _n } 'S (2m _n +1) level unit power conversion unit group 6 capable of output of level, and by combining the output voltage values of each unit power conversion unit group 6, multi-level (more specifically, 2 (m ₁ + M ₂ ... + m _n ) +1 voltage can be output in an arbitrary period, and it is only necessary that each output voltage of each unit power conversion unit group 6 is appropriately selected to obtain an output voltage having a staircase waveform.
[0029]
Note that, as in the present embodiment, the first unit power conversion unit group is m. ₁ = 2 ⁰ And {2 in {1, 0, -1} ¹ +1) level output is possible, and the second unit power conversion unit group is m ₂ = 2 ¹ {2, 1, 0, -1, -2} (2 ² +1) level output is possible, and the nth unit power conversion unit group is m _n = 2 ^n-1 And {2 ^n-1 , ..., 2, 1, 0, -1, -2, ..., -2 ^n-1 } (2 ⁿ If it is possible to output +1) level, 2 ^n-1 = 1, 2, 4, 8... ^n-1 (For example, 3 = 1 + 2, 5 = 1 + 4, 6 = 2 + 4, 7 = 1 + 2 + 4, 9 = 1 + 8, etc.), so that the output voltage value of the power converter is The effect that it can be comprised by the minimum number of unit power conversion units is acquired.
[0030]
In the present embodiment, the maximum output voltage, 0, and minimum output voltage of each unit power conversion unit group 6 are appropriately selected to obtain a multi-level output voltage. Genus The unit power conversion units 5 to be controlled can be simultaneously turned on / off. Therefore, the control is simple.
[0031]
Embodiment 2. FIG.
8 to 12 are diagrams for explaining the power conversion apparatus according to the second embodiment of the present invention. More specifically, FIG. 8 is a diagram showing a circuit configuration of a control circuit, and FIG. 9 is a third diagram. FIG. 10 is a diagram showing an example of the output voltage waveform of the unit power conversion unit group, FIG. 10 is a diagram showing an example of the output voltage waveform of each unit power conversion unit group and the power conversion device, and FIG. It is a figure which shows the output voltage value of each unit power conversion unit group when changing from 1 to 7 and 7 to 0 one by one. Since the other configuration is the same as that of the first embodiment, the difference from the first embodiment will be mainly described below.
[0032]
In the first embodiment, the same group Genus The case where the unit power conversion units 5 to be turned on / off at the same time and the maximum output voltage, 0, and minimum output voltage of each unit power conversion unit group 6 are appropriately selected to obtain a multilevel output voltage has been described.
In contrast, in the present embodiment, the same group Genus The unit power conversion unit 5 is controlled to be turned on / off by shifting the timing, and all the voltages that can be output from each unit power conversion unit group 6 are appropriately selected to obtain an output voltage having a predetermined waveform.
[0033]
FIG. 9 shows an example of the output voltage waveform of the third unit power conversion unit group 63 (the voltage applied between the third output terminal 84 and the fourth output terminal 97 in the third unit power conversion unit group 63). 9A shows a state in which the output voltage value (value normalized by the DC voltage value V of the DC capacitor 20) changes from 0 to 4, and FIG. 9B shows the output voltage value from 4 to 0. Each of them shows how they change.
In FIG. 9, the third voltage waveform 38 a is an output voltage waveform of the third unit power conversion unit group 63 in the first embodiment. The third voltage waveform 38b is an output voltage waveform of the third power conversion unit group 63 in the present embodiment.
[0034]
The third unit power conversion unit group 63 includes four unit power conversion units 5. In the first embodiment, the third unit power conversion unit group 63 includes the same third unit power conversion unit group 63. Genus By simultaneously turning on / off the unit power conversion units 54 to 57, the output voltage value of the third voltage waveform 38a changes from 0 to 4 at a time in four levels. On the other hand, in the present embodiment, the on / off timings of the unit power conversion units 54 to 57 are performed at certain time intervals ΔT11, ΔT12, and ΔT13, and the output voltage of the third unit power conversion unit group 63 (third By making the voltage waveform 38b) a step waveform so that the change always becomes the voltage V (1 level), the time change rate (dv / dt) of the output voltage in the third unit power conversion unit group 63 is reduced. .
Here, regarding the on / off timing of each of the unit power conversion units 54 to 57, the period when the output voltage value of the third unit power conversion unit group 63 is 1 is ΔT11, the period 2 is ΔT12, and the period 3 is ΔT13. . When the period until the output voltage value of the third unit power conversion unit group 63 changes from 0 to 4 is ΔT0, ΔT0 = ΔT11 + ΔT12 + ΔT13. Note that ΔT11, ΔT12, and ΔT13 may all be the same value or different values.
[0035]
In addition, although the 3rd unit power conversion unit group 63 was demonstrated above, each unit power conversion unit 52,53 is similarly applied also about the 2nd unit power conversion unit group 62 provided with the two unit power conversion units 5. FIG. The on / off timing is performed at certain time intervals, and the output voltage of the second unit power conversion unit group 62 can be a step waveform so that the change always becomes the voltage V (1 level).
This switching timing shift is performed in the signal distribution circuits 401 to 403 (may be represented by 40) in FIG. The signal distribution circuits 401 to 403 are constituted by, for example, a microcomputer-based controller such as a DSP (Digital Signal Processor).
[0036]
10, when the output voltage value of the power converter 2 (value normalized by the voltage V of the DC capacitor 20 as in the first embodiment) is changed from 3 to 4, 4 to 5, and 5 to 6. An example of the output voltage waveform of each unit power conversion unit group 61-63 and a power converter device is shown. In FIG. 10, the wavy line indicates that the middle is omitted.
[0037]
As shown in FIG. 10, the output voltage value 3 of the power conversion device 2 is 1 for the output voltage of the first unit power conversion unit group 61, 2 for the output voltage of the second unit power conversion unit group 62, The output voltage of the unit power conversion unit group 63 is realized by selecting 0. Further, the output voltage value 4 of the power conversion device 2 is finally set to the output voltage of the first and second unit power conversion unit groups 61 and 62, and the output voltage of the third unit power conversion unit group 63. This is realized by selecting 4 as in the first embodiment. However, in the present embodiment, in the initial ΔT0 when the output voltage value of the power conversion device 2 is changed from 3 to 4, the output voltage of the first unit power conversion unit group 61 is 1 (no change) during the period of ΔT11. The output voltage of the second unit power conversion unit group 62 is 2 (no change), the output voltage of the third unit power conversion unit group 63 is 1 (1 level change), and the next period of ΔT12 is The output voltage of the first unit power conversion unit group 61 is 0 (1 level change), the output voltage of the second unit power conversion unit group 62 is 2 (no change), and the output of the third unit power conversion unit group 63 The voltage is selected as 2 (1 level change), and during the next period ΔT13, the output voltage of the first unit power conversion unit group 61 is 0 (no change), and the output voltage of the second unit power conversion unit group 62 Is 1 (1 level change), 3rd The output voltage of the unit power conversion unit group 63 is selected as 3 (1 level change), and then the output voltage of the first unit power conversion unit group 61 is 0 (no change), and the second unit power conversion unit group 62 The output voltage of the third unit power conversion unit group 63 is selected to be 0 (1 level change), and the output voltage of the third unit power conversion unit group 63 is selected to be 4 (1 level change). Groups 62 and 63) Genus The unit power conversion units 5 (52 and 53 and 54 to 57) to be controlled are turned on and off at different timings so that the change in the output voltage of each unit power conversion unit group 6 is always the voltage V (1 level). A voltage that can be output from the unit power conversion unit group 6 is appropriately selected to obtain an output voltage having a predetermined waveform.
[0038]
Next, as for the output voltage value 5 of the power conversion device 2, the output voltage of the first unit power conversion unit group 61 is 1 (1 level change), and the output voltage of the second unit power conversion unit group 62 is 0 (change). None), the output voltage of the third unit power conversion unit group 63 is realized by selecting 4 (no change). In this case, the output voltage of the first unit power conversion unit group 61 changes by one level. This is the same as in the first embodiment.
[0039]
Next, the output voltage value 6 of the power converter 2 is finally set to the output voltage of the first unit power conversion unit group 61 being 0, the output voltage of the second unit power conversion unit group 62 being 2, The output voltage of the unit power conversion unit group 3 of 3 is realized by selecting 4 as in the first embodiment. However, in the present embodiment, the output voltage of the first unit power conversion unit group 61 is 1 (no change) during the initial period ΔT14 in which the output voltage value of the power conversion device 2 is changed from 5 to 6. The output voltage of the second unit power conversion unit group 62 is selected as 1 (1 level change), and the output voltage of the third unit power conversion unit group 63 is selected as 4 (no change), and then the first unit power conversion unit is selected. The output voltage of the group 61 is 0 (1 level change), the output voltage of the second unit power conversion unit group 62 is 2 (1 level change), and the output voltage of the third unit power conversion unit group 63 is 4 (no change). ) To the same group (second unit power conversion unit group 62) Genus The unit power conversion units 5 (52 and 53) to be controlled are turned on and off at different timings so that the change in the output voltage of each unit power conversion unit group 6 is always the voltage V (1 level). A voltage that can be output from the group 6 is appropriately selected to obtain an output voltage having a predetermined waveform.
[0040]
In FIG. 11, the output voltage value of each unit power conversion unit group when the output voltage value of the power converter device 2 changes 1 each from 0 to 7 and 7 to 0 is shown. In FIG. 11, the thick arrow indicates the time axis, and the thin arrow indicates the final change in the output voltage value of the second and third unit power conversion unit groups 62 and 63 when the output voltage value of the power conversion device 2 changes. This final change is the same as that in the first embodiment.
FIG. 10 illustrates the change in the output voltage value of each of the unit power conversion unit groups 61 to 63 when the output voltage value of the power conversion device 2 changes from 3 to 4, 4 to 5, and 5 to 6. As shown in FIG. 11, in this embodiment, when the output voltage value of the power conversion device 2 changes from 0 to 7 and from 7 to 0 one by one, Genus Each unit power conversion unit group 6 can be output so that the unit power conversion unit 5 to be controlled is turned on and off by shifting the timing so that the change in the output voltage of each unit power conversion unit group 6 is always the voltage V (1 level). An appropriate voltage is appropriately selected to obtain an output voltage having a predetermined waveform.
[0041]
For example, although the output voltage value of the power conversion device 2 changes from 1 to 2, in the first embodiment, the output voltage values of the first and third unit power conversion unit groups 61 and 63 are 1 to 0, respectively. Although there is no change, the output voltage value of the second unit power conversion unit group 62 has changed from 0 to 2 by two levels. In contrast, in the present embodiment, a transition period ΔT10 indicated by hatching is provided as shown in FIG. 11, so that the change in the output voltage of each unit power conversion unit group 6 is always the voltage V (1 level). Group management control. The transition periods ΔT11 to ΔT14 have already been described with reference to FIG.
[0042]
In addition, in FIG. 11, although the case where the output voltage value of the power converter device 2 changed on the positive side from 0 to 7 and 7 to 0 is shown, the negative side makes the polarity of each output voltage value negative. Can be explained by
[0043]
As described above, the unit power conversion unit 5 is group-managed and controlled so that the change of the output voltage of each unit power conversion unit group 6 becomes a step waveform whose change is always the voltage V, and each unit power conversion unit group 6 By appropriately selecting all the voltages that can be output, and obtaining an output voltage having a staircase waveform, the output voltage of the power conversion device 2 can be displayed without causing a steep and large voltage change in each unit power conversion unit group 6. Adjustment can be made in the same manner as in the first embodiment shown in FIG.
[0044]
Further, in the present embodiment, the unit power conversion unit 5 is group-managed and controlled so that the output voltage of each unit power conversion unit group 6 has a step waveform whose change is always the voltage V, and each unit power conversion unit is controlled. Since all the voltages that can be output from the group 6 are appropriately selected to obtain a staircase waveform output voltage, the following effects can also be obtained.
The amplitude ratios of the output voltages V1, V2, V3 and Vn of the n inverter bridges described in the prior art 2 are set to V1: V2: V3: Vn = 1: 2: 4: 2. ^(n-1) In the method of combining the output voltages of the inverter bridges, if the characteristics of the semiconductor switch (self-extinguishing semiconductor element) vary, the power conversion device may output an incorrect voltage. As an example, a case where the output voltage value of the power converter changes from 3 to 4 will be described. In this case, the inverter bridge whose output voltage amplitude is V1 (amplitude ratio 1) and the inverter bridge whose output voltage amplitude is V2 (amplitude ratio 2) respectively change from positive voltage output to 0 voltage output. Further, the inverter bridge whose output voltage amplitude is V3 (amplitude ratio 4) changes from 0 voltage output to positive voltage output. Here, if the characteristics of the semiconductor switch (self-extinguishing type semiconductor device) vary and there is a time lag in the output voltage of each inverter bridge, all inverter bridges output positive voltage instantaneously or all May be in a state of 0 voltage output. That is, 7 or 0 may be output at the moment when the output voltage of the power converter changes from 3 to 4.
On the other hand, in this Embodiment, when the output voltage value of the power converter device 2 changes, it is in the same group. Genus Each unit power conversion unit group 6 can output so that the change of the output voltage of each unit power conversion unit group 6 always becomes the voltage V (1 level) by shifting the timing of the unit power conversion unit 5 to be turned on and off. Therefore, even if there are variations in self-extinguishing semiconductor elements, instantaneous voltage errors can be suppressed to V (1 level) with respect to the desired output voltage. it can. That is, even when there is variation in the element characteristics of the self-extinguishing semiconductor element and the output voltage generation timing of each unit power conversion unit has a time lag, the power conversion device has a minimum level of output voltage error. An output voltage having a staircase waveform can be obtained.
[0045]
Generally, when a motor is connected as a load of an inverter device, the cable has wiring inductance and stray capacitance. Therefore, a voltage change due to switching of the inverter device generates a surge voltage due to LC resonance, and the motor winding May cause insulation deterioration. The surge voltage may reach about twice the output voltage peak value of the inverter device. Therefore, by installing a surge voltage suppression filter between the output terminal of the inverter device and the motor to suppress the peak value of the terminal voltage of the motor, or by installing an AC reactor at the inverter output terminal, the output voltage of the inverter device In general, the surge voltage is reduced by suppressing the rate of time change (dv / dt).
In the power conversion device 2 in the present embodiment, the output voltage of each unit power conversion unit group is generated stepwise, thereby suppressing the time change rate (dv / dt) of the output voltage of the power conversion device, and each unit. Since it is possible to prevent a steep and large voltage change from occurring in the power conversion unit group 6, surge voltage can be reduced, and a filter and a reactor used for these measures can be reduced in size or can be made unnecessary. That is, the reliability of the power conversion device can be improved and the cost can be reduced.
[0046]
ΔT0 can be arbitrarily selected. Further, ΔT10, ΔT11, ΔT12, ΔT13, and ΔT14 can be arbitrarily selected. However, ΔT0 (= ΔT11 + ΔT12 + ΔT13), ΔT10, and ΔT14 are obtained from the step width (period) ΔT of the voltage waveform 50 applied between the first output terminal 3 and the second output terminal 4 of the power converter 2, respectively. Set to a small value.
[0047]
Embodiment 3 FIG.
Hereinafter, modifications of the power conversion device shown in the first and second embodiments will be described. For the three-phase rectifier circuit shown in FIG. 3, a face module having a circuit configuration different from that of the face module shown in FIG. 4 can be used. For example, the second face module 24 composed of self-extinguishing semiconductor elements 321 and 322 and diodes 313 and 314 connected in reverse parallel to them as shown in FIG. By applying it, a three-phase self-excited rectifier circuit can be obtained.
Thus, the voltage of the DC capacitor 20 in the DC link circuit 18 can be controlled by making the three-phase rectifier circuit self-excited.
[0048]
There are various waveform synthesis methods in the multiplexing system of the inverter device. In general, the step width and height are determined so that the multiplexed stepped output voltage approaches a sine wave. Since the voltage of the DC capacitor 20 can be freely controlled, not only the width (period) of the step but also the height of the step can be adjusted, so that the power converter can output a voltage having a staircase waveform closer to a sine wave. Become.
Further, by using a three-phase self-excited rectifier circuit, it is possible to control the AC input current, and it is possible to suppress the harmonic current flowing out to the multi-phase AC power source and to increase the power factor.
[0049]
Embodiment 4 FIG.
12 to 14 are diagrams for explaining the power conversion device according to the fourth embodiment of the present invention. More specifically, FIG. 12 is a diagram showing a circuit configuration of a control circuit, and FIG. 13 is a gate drive. FIG. 14 is a diagram for explaining signal switching, and FIG. 14 is a diagram showing output voltage waveforms of each unit power conversion unit and power conversion apparatus. Since the other configuration is the same as that of the first embodiment, the difference from the first embodiment will be mainly described below.
[0050]
In the present embodiment, the control circuit 16 switches the gate signal so that the operation responsibilities of the self-extinguishing semiconductor elements 32 of the unit power conversion units 5 constituting the unit power conversion unit group 6 are averaged (each unit The assignment of the power conversion units 51 to 57 to the unit power conversion unit groups 61 to 63 is switched).
[0051]
In the control circuit 16 shown in FIG. 12, the signal generated by the gate signal generation circuit 34 is output from the eighth output terminals 351 to 353. Here, the signal output from the eighth output terminal 351 is a gate signal for driving the unit power conversion units 5 constituting the first unit power conversion unit group 61. The signal output from the eighth output terminal 352 is a gate signal for driving the unit power conversion units 5 constituting the second unit power conversion unit group 62. Further, the signal output from the eighth output terminal 353 is a gate signal for driving the unit power conversion units 5 constituting the third unit power conversion unit group 63.
[0052]
Each gate signal is input to seventh input terminals 5201 to 5203 (may be represented by 520) of the signal distribution circuits 401 to 403, respectively, and constitutes each unit power conversion unit group 61 to 63. The signals are distributed to gate signals corresponding to the number of unit power conversion units 5 and output from ninth output terminals 5301 to 5307 (which may be represented by 530). The gate signals output from the ninth output terminals 5301 to 5307 are input to the eighth input terminals 5401 to 5407 (which may be represented by 540) of the gate signal switching circuit 510. The gate signal switching circuit 510 outputs tenth output terminals 5501 to 5507 (for the input gate signal so that the number of switching times of the self-extinguishing semiconductor element 32 of each unit power conversion unit 5 is averaged. 550).) And switch at regular time intervals. The gate signal output from the gate signal switching circuit 510 is sent from the fifth output terminals 141 to 147 of the control circuit 16 to the unit power conversion units 51 to 57, respectively, and the single phase of each unit power conversion unit 51 to 57 is transmitted. The self-excited inverter circuit 19 is driven.
[0053]
Hereinafter, the operation of the gate signal switching circuit 510 shown in FIG. 12 will be described in detail. For the gate signal input from the eighth input terminals 5401 to 5407, the weighting amount is set according to the number of switching times per cycle of the AC output voltage.
As an example, the weight P of the signal output from the seventh output terminal 5301 of the signal distribution circuit 401 is 3 (P = 3), and the signal output from the seventh output terminals 5302 and 5303 of the signal distribution circuit 402 is The weight amount P is set to 2 (P = 2), and the weight amount P of the signal output from the seventh output terminals 5304 to 5307 of the signal distribution circuit 403 is set to 1 (P = 1).
[0054]
FIG. 13 shows a correspondence relationship between the gate signal input from the eighth input terminals 5401 to 5407 of the gate signal switching circuit 510 and the unit power conversion units 51 to 57 to be driven. Symbols A to G in FIG. 13 correspond to the unit power conversion units 51 to 57, respectively. The gate signal is switched at intervals of ΔT2. Hereinafter, as an example, a gate signal switching method when ΔT2 is set to a time corresponding to one cycle of the AC output voltage will be described.
[0055]
At times T = T (0) to T (1), the unit power conversion units 51 to 57 are sequentially arranged with respect to the signals input from the eighth input terminals 5401 to 5507, and the unit power conversion units 51 to 57 are arranged. 57 is driven. Here, the weight amount P according to the gate signal connected to each unit power conversion unit 51-57 is added. The calculation formula is shown below.
X (1) = X ′ (0) + P (X = A to G, P = 1, 2, 3)
Here, X ′ (0) = 0.
Next, the minimum value of X (1) calculated for each unit power conversion unit is set to Xmin (1), and the value of X ′ (1) is calculated by the following equation.
X ′ (1) = X (1) −Xmin (1)
[0056]
At time T = T (1), the arrangement of the unit power conversion units 51 to 57 with respect to the gate signals input from the eighth input terminals 5401 to 5407 is rearranged in ascending order of X (1), and the gate signals are switched according to the arrangement. . Similarly, X (n) and X ′ (n) are calculated using the following equations in accordance with the gate signals connected to the unit power conversion units 51 to 57, and the unit power to be switched at the next timing Determine the conversion unit.
X (n) = X ′ (n−1) + P
X ′ (n) = X (n) −Xmin (n)
[0057]
FIG. 14 shows output voltage waveforms of each unit power conversion unit and power conversion apparatus when ΔT2 is set to a time corresponding to one cycle of the AC output voltage. In FIG. 14, the eleventh voltage waveform 560 represents the output voltage of the unit power conversion unit 51, the twelfth voltage waveform 570 represents the output voltage of the unit power conversion unit 52, and the thirteenth voltage waveform 580 represents the unit power conversion unit 53. The 14th voltage waveform 590 shows the output voltage of the unit power conversion unit 54, the 15th voltage waveform 600 shows the output voltage of the unit power conversion unit 55, and the 16th voltage waveform 610 shows the unit power conversion unit. The output voltage of 56 and the 17th voltage waveform 620 indicate the output voltage of the unit power conversion unit 57, respectively. The 18th voltage waveform 630 shows the combined output voltage of each unit power conversion unit 51-57, that is, the output voltage 50 of the power converter.
[0058]
In this way, by using the gate signal switching circuit 510 to switch the gate signal input to each of the unit power conversion units 51 to 57 according to the switching frequency, that is, the switching frequency of each self-extinguishing semiconductor element 32 can be increased. By switching the allocation of the unit power conversion units 51 to 57 to the unit power conversion unit groups 61 to 63 so as to be averaged, the duty of the gate drive circuit that switches the on / off state of the self-extinguishing semiconductor element 32 is averaged. Has the effect of being
Since the duty of the gate drive circuit of the self-extinguishing semiconductor element 32 is averaged, the heat loss (switching loss) generated in the self-extinguishing semiconductor element 32 is averaged. As a result, the self-extinguishing semiconductor element 32 junction temperatures are averaged.
In the self-extinguishing semiconductor element 32 and the diode 31, heat generated by the loss generated in the element needs to be cooled by using a cooling fin so that the junction temperature of the element is lower than an allowable value. Since the loss of the semiconductor element 32 is averaged, the junction temperature of the element is averaged, and the cooling system including the cooling fins can be standardized.
[0059]
In the present embodiment, means for switching the allocation of the unit power conversion units 51 to 57 to the unit power conversion unit groups 61 to 63 so that the number of times of switching of the self-extinguishing semiconductor elements 32 is averaged is as follows. The gate signal switching circuit 510 is configured.
The gate signal switching circuit 510 is configured by a microcomputer-based controller such as a DSP (Digital Signal Processor).
[0060]
Note that although the weight amount P is set to 1, 2, and 3 for simplicity, other values can naturally be used depending on the value of the number of switching times. An arbitrary period can be set for ΔT2.
[0061]
Further, when the junction temperature of the self-extinguishing semiconductor element 32 can be directly detected, the weight amount P can be set according to the junction temperature of the self-extinguishing semiconductor element 32 instead of setting according to the switching frequency. is there. Thus, by switching the allocation of the unit power conversion units 51 to 57 to the unit power conversion unit groups 61 to 63 according to the level of the junction temperature of the self-extinguishing semiconductor element 32, the self-extinguishing semiconductors It becomes possible to average the junction temperature of the element 32. Therefore, the cooling system including the cooling fins can be standardized.
[0062]
In addition, although the case where it applied mainly to Embodiment 1 was demonstrated above, it cannot be overemphasized that this Embodiment is applicable not only to Embodiment 1, but Embodiment 2 and 3. FIG.
[0063]
Embodiment 5 FIG.
15 to 18 are diagrams for explaining the power conversion device according to the fifth embodiment of the present invention. More specifically, FIG. 15 is a diagram showing a circuit configuration of the power conversion device, and FIG. FIG. 17 is a diagram showing an example of the current bypass path of the unit power conversion unit shown in FIG. 4, FIG. 17 is a diagram showing another example of the current bypass path of the unit power conversion unit shown in FIG. 3 and FIG. It is a figure which shows the circuit structure of a control circuit. Since the other configuration is the same as that of the first embodiment, the difference from the first embodiment will be mainly described below.
[0064]
In each of the embodiments described above, the number of unit power conversion units 5 that matches the allocation to each unit power conversion unit group 61 to 63, that is, (m ₁ + M ₂ + M ₃ + ... + m _n ) Pieces.
In contrast, in the present embodiment, the unit power conversion unit is (m ₁ + M ₂ + M ₃ + ... + m _n ) A unit power conversion unit that is provided in more than one unit and has not been assigned to any unit power conversion unit group is set to a standby operation state, and is assigned to any unit power conversion unit that is assigned to the unit power conversion unit group and is in an operation state. When an abnormality occurs, the unit power conversion unit in which the abnormality has occurred is placed in a standby operation state, and unit power that has not been assigned to any unit power conversion unit group in place of the unit power conversion unit in which the abnormality has occurred The conversion unit was configured to be in an operating state.
[0065]
In FIG. 15, eight unit power conversion units 51 to 58 all having the same circuit configuration are provided, and the output terminals 81 to 88 and 91 to 98 are connected in series. Input power transformers 101 to 108 are provided for the unit power conversion units 51 to 58, respectively. The primary windings 111 to 118 of the input transformers 101 to 108 are all connected to the polyphase AC power source 1, and the secondary windings 121 to 128 are first input terminal groups of the unit power conversion units 51 to 58, respectively. 71-78. The first input terminals 131 to 138 of the unit power conversion units 51 to 58 are connected to the fifth output terminals 141 to 148 of the control circuit 16 via the communication lines 151 to 158, respectively.
[0066]
The unit power conversion unit 51 is in the first unit power conversion unit group 61, the unit power conversion units 52 and 53 are in the second unit power conversion unit group 62, and the unit power conversion units 54 to 57 are in the third unit power conversion. Each unit group 63 is assigned. The unit power conversion unit 58 is a spare unit and is not assigned to any unit power conversion unit group 61-63.
Inverter operation when the power converter 2 is normal is performed by the unit power conversion units 51 to 57, and the single-phase self-excited inverter circuit 19 in the unit power conversion unit 58 is set in a standby operation state.
[0067]
Here, for example, as shown in FIGS. 16 and 17, the standby operation state means that both the self-extinguishing semiconductor elements 321 of the second face modules 241 and 242 of the single-phase self-excited inverter circuit are turned off. Both the semiconductor elements 322 are turned on, or although not shown, both the self-extinguishing semiconductor elements 321 are turned on and both the self-extinguishing semiconductor elements 322 are turned off. At this time, the current passing through the unit power conversion unit 58 flows without passing through the DC link circuit 18. In this way, the voltage applied between the third output terminal 88 and the fourth output terminal 98 in the unit power conversion unit 58 can be reduced to the on-voltage level of the self-extinguishing semiconductor element 32 and the diode 31. it can.
[0068]
Next, a protection method of the power conversion device 2 when an abnormality occurs in the single-phase self-excited inverter circuit 19 in the unit power conversion unit 54 among the unit power conversion unit groups 61 to 63 will be described.
[0069]
16 and 17 showing the second face modules 241 and 242 of the unit power conversion unit 5, the self-extinguishing semiconductor element 322 of the second face module 242 constituting the single-phase self-excited inverter circuit 19 is shown. When an abnormality has occurred, the self-extinguishing semiconductor element 322 of another healthy second face module 241 in the same array as the self-extinguishing semiconductor element 322 in which the abnormality has occurred is forcibly ignited and the others The self-extinguishing semiconductor element 321 is forcibly extinguished. As a result, as shown in FIG. 16 and FIG. 17, it is possible to secure a path through which bidirectional current flows without passing through the DC link circuit 18, so that an overvoltage is applied to the unit power conversion unit 54 in which an abnormality has occurred. Can be protected so that there is no.
[0070]
Here, the unit power conversion unit 54 in which an abnormality has occurred cannot apply a voltage between the third output terminal 84 and the fourth output terminal 94, but unit power conversion is performed instead of the unit power conversion unit 54. By operating the unit 58, the power conversion device 2 can apply a voltage between the first output terminal 3 and the second output terminal 4 without any shortage. Therefore, the reliability of the apparatus can be improved by adding the operation continuation function of the power conversion apparatus.
Thus, according to the present embodiment, even when an abnormality occurs in any unit power conversion unit in the operating state, the operation can be continued without reducing the rated capacity of the device, and thus the device Can improve the reliability.
[0071]
A unit power conversion unit (unit power conversion unit 58 in FIG. 15) that has not been assigned to any unit power conversion unit group is set to a standby operation state, and any unit power conversion unit group that is assigned to a unit power conversion unit group is in an operation state. When an abnormality occurs in the unit power conversion unit (the unit power conversion unit 54 in the above description), the unit power conversion unit 54 in which the abnormality has occurred is put into a standby operation state, and is replaced with the unit power conversion unit 54 in which the abnormality has occurred. The means for setting the unit power conversion unit 58 that is not assigned to any of the unit power conversion unit groups and is in the standby operation state to the operation state is configured by the control circuit 16 shown in FIG.
[0072]
In the control circuit 16 shown in FIG. 18, the signal generated by the gate signal generation circuit 34 is output from the eighth output terminals 351 to 354. Here, the signal output from the eighth output terminal 351 is a gate signal for driving the unit power conversion units 5 constituting the first unit power conversion unit group 61. The signal output from the eighth output terminal 352 is a gate signal for driving the unit power conversion units 5 constituting the second unit power conversion unit group 62. Further, the signal output from the eighth output terminal 353 is a gate signal for driving the unit power conversion units 5 constituting the third unit power conversion unit group 63. The signal output from the eighth output terminal 354 is a gate signal for setting the standby unit power conversion unit 5 in the standby operation state.
[0073]
The respective gate signals are respectively input to seventh input terminals 5201 to 5204 (may be represented by 520) of the signal distribution circuits 401 to 404 (may be represented by 40). The number of unit power conversion units constituting the unit power conversion unit groups 61 to 63 and the number of unit power conversion units (unit power conversion units 58 in FIG. 15) not assigned to any of the unit power conversion unit groups 61 to 63 are the same. The signals are distributed to the corresponding gate signals and output from the ninth output terminals 5301 to 5308 (which may be represented by 530). The gate signals output from the ninth output terminals 5301 to 5308 are input to the eighth input terminals 5401 to 5408 (which may be represented by 540) of the gate signal switching circuit 510. When an abnormality occurs in any of the unit power conversion units 5, the gate signal switching circuit 510 sets the unit power conversion unit to a standby operation state, and sets a gate signal to set the spare unit power conversion unit to an operation state. Switch. The gate signals output from the tenth output terminals 5501 to 5508 (which may be represented by 550) of the gate signal switching circuit 510 are converted into unit power conversions from the fifth output terminals 141 to 148 of the control circuit 16. It is sent to each of the units 51 to 58, and drives the single-phase self-excited inverter circuit 19 of each unit power conversion unit 51 to 58.
[0074]
Here, the operation continuation method by the unit power conversion unit 58 when an abnormality occurs in the unit power conversion unit 54 has been described. However, the unit power conversion unit regardless of which of the unit power conversion units 51 to 57 has an abnormality. It is clear from the above description that the operation can be continued by 58.
[0075]
FIG. 15 shows a case where one spare unit power conversion unit 58 that is not assigned to any unit power conversion unit group 61 to 63 is provided, but a plurality of unit power conversion units 58 may be provided. It becomes possible to cope with the abnormality of the unit power conversion unit 5.
[0076]
In the above, as shown in the first embodiment, the same group Genus However, the present invention is not limited to this, and as shown in the second embodiment, the change in the output voltage of each unit power conversion unit group 6 is always a voltage. Needless to say, each unit power conversion unit 5 may be controlled to have a step waveform V. Furthermore, the present invention can be applied to the third and fourth embodiments.
[0077]
Embodiment 6 FIG.
In the present embodiment, a countermeasure example different from that in the fifth embodiment when an abnormality occurs in any unit power conversion unit will be described.
In the power conversion device 2 that can control the voltage of the DC capacitor 20 in the DC link circuit 18 using the three-phase self-excited rectifier circuit described in the third embodiment, the unit is assigned to each unit power conversion unit group 61-63. Among the seven unit power conversion units 51 to 57, for example, when an abnormality occurs in the single-phase self-excited inverter circuit 19 in the unit power conversion unit 54, the unit power conversion unit 54 in which the abnormality has occurred is In the same manner as described with reference to FIGS. 16 and 17 in the fifth embodiment, a path for allowing the load current to flow without passing through the DC link circuit 18 is secured. Moreover, the power converter device 2 is set to a normal state by increasing the voltage of the DC capacitors 20 of the six unit power conversion units 51 to 53, 55 to 57 other than the unit power conversion unit 54 in which the abnormality has occurred by 7/6 times. The same average voltage can be output.
Therefore, the operation can be continued without reducing the rated capacity of the device, and the reliability of the device can be improved.
[0078]
Embodiment 7 FIG.
FIG. 19 is a diagram showing a circuit configuration of a multi-phase output power converter according to Embodiment 7 of the present invention. Other configurations are the same as those in the first embodiment.
In the present embodiment, power is supplied from the multiphase AC power supply 1 to the multiphase AC load 640 using the single-phase output power converter 2 (210, 220, 230) shown in the first embodiment. explain.
[0079]
The first output terminals 310, 320, and 330 of the power converters 210, 220, and 230 with single phase output are connected to the neutral point 680, and the second output terminals 410, 420, and 430 are connected to the polyphase AC load 640. Connected.
By distributing the voltage command output from the voltage command generation circuit 650 to the control circuits 161, 162, and 163 of the power conversion devices 210, 220, and 230, the power conversion devices 210, 220, and 230 are supplied with their output voltages. It can be driven while being controlled.
[0080]
Note that the single-phase output power conversion device 2 (210, 220, 230) is not limited to that shown in the first embodiment, and any of the power conversion devices 2 of the second to sixth embodiments may be used. Needless to say.
[0081]
Embodiment 8 FIG.
20-22 is a figure for demonstrating the power converter device by Embodiment 8 of this invention, More specifically, FIG. 20 is a unit power converter unit when a power converter device is applied to an electric power grid | system. FIG. 21 is a diagram showing a circuit configuration when the power converter is operated as a self-excited series compensator, and FIG. 22 is a diagram for explaining the operation principle of the self-excited series compensator. Since the other configuration is the same as that of the first embodiment, the difference from the first embodiment will be mainly described below.
[0082]
As shown in FIG. 20, in the present embodiment, the unit power conversion unit 5 is composed of a single-phase self-excited inverter circuit 19 and a DC link circuit 18, and the DC power source of the power conversion device has each unit power Each of the conversion units 51 to 57 is independent of the DC link circuit 18 including the DC capacitor 20.
[0083]
As shown in FIG. 21, the first output terminals 310 and 320 of the three power conversion devices 210, 220, and 230 (may be represented by 2) using the unit power conversion unit 5 shown in FIG. , 330 are connected to the first AC system 660, and the second output terminals 410, 420, 430 are connected to the second AC system 670. The power converters 210, 220, and 230 connected in this way can be operated as a self-excited series compensator SSSC (Static Synchronous Series Compensator).
[0084]
FIG. 22 is a diagram for explaining the operation principle of the self-excited series compensator constituted by the power conversion device 2, where the voltage of the power system 660 is V, the voltage of the power system 670 is V ′, and the system current is I. FIG. When the output voltage of the power converter is VX, the impedance of the transmission line can be equivalently changed by outputting the output voltage VX in a direction perpendicular to the phase of the system current I.
[0085]
As shown in FIG. 22A, when the phase of the output voltage VX is advanced by 90 ° with respect to the system current I, it acts as a variable series reactor. Further, as shown in FIG. 22B, when the phase of the output voltage VX is 90 ° behind the system current I, it acts as a variable series capacitor. Thereby, the impedance of the transmission line can be changed equivalently, and the power system can be stabilized.
[0086]
Furthermore, according to the present embodiment, the same power conversion device 2 as described in the first embodiment is used, and the same effects as those in the first embodiment as described below can be obtained. Since the unit power conversion units 5 can be multiplexed without using transformers having different voltage ratios, the rated currents of the unit power conversion units 5 can be made equal. Therefore, the standardized inverter circuit 19 can be applied as the unit power conversion unit 5, and furthermore, the standardized unit power conversion unit 5 having the same circuit configuration can be used, thereby reducing the cost of the power conversion device. Can be reduced.
Further, the increase in the capacity of the power conversion device 2 in the present embodiment can be dealt with by increasing the number of unit power conversion units 5 when the rated voltage of the load to be applied becomes high. In the case of applying to the power converter, the series transformer is not necessary, and the installation area of the power converter can be reduced.
Furthermore, since the unit power conversion unit can be standardized, the maintenance is easy, and the reliability of the apparatus can be improved, for example, when any unit power conversion unit breaks down.
[0087]
In addition, although what was shown in Embodiment 1 was shown about the case where the structure of the DC power supply was changed and used, it is not restricted to this, Any power converter device 2 of Embodiment 2-6 is used. Needless to say, the configuration of the DC power supply may be changed.
Furthermore, a three-phase rectifier circuit 17 may be provided in the same manner as in the first to sixth embodiments in order to initially charge the DC capacitor 20.
[0088]
In particular, in the same group shown in the second embodiment Genus The unit power conversion unit 5 to be turned on / off is controlled at different timings so that the output voltage of each unit power conversion unit group 6 always changes to the voltage V (1 level). When using a power converter configured to obtain an output voltage having a predetermined waveform by appropriately selecting a possible voltage, the stray capacitance existing between the terminals of the transformer connected to the power system or in the power cable Therefore, it is possible to suppress the surge voltage generated due to the influence of the transformer, so that the insulation deterioration of the transformer or the power cable can be prevented.
[0089]
【The invention's effect】
As described above, according to the present invention, an inverter circuit and an independent DC power source are included, and three-level output {1, 0, −1} is possible with values normalized by the DC voltage value of the DC power source. A power conversion device comprising a plurality of unit power conversion units having the same circuit configuration, wherein the output terminals of the unit power conversion units are connected in series, and m ₁ The unit power conversion unit is {m ₁ , ..., 0, ..., -m ₁ } 'S (2m ₁ A first unit power conversion unit group capable of +1) level output; and m ₂ The unit power conversion unit is {m ₂ , ..., 0, ..., -m ₂ } 'S (2m ₂ +1) a second unit power conversion unit group capable of level output, m _n Pieces (m ₁ , M ₂ , ..., m _n , And n are natural numbers, m ₁ <M ₂ <... <m _n , 3 ≦ n. ) Unit power conversion unit {m _n , ..., 0, ..., -m _n } 'S (2m _n +1) n-th unit power conversion unit group capable of level output, and each output voltage of each unit power conversion unit group At least one output voltage among the unit power conversion units belonging to the unit power conversion unit group by shifting the on / off control timing to form an output waveform having a stepped rise. Select as appropriate Pseudo sine wave Since the output voltage of the staircase waveform is obtained, the output voltage can be multi-leveled using a standardized (fixed) unit power conversion unit. It can be handled by increasing the number. In addition, since a standardized unit power conversion unit is used, maintenance is easy, and even if any unit power conversion unit fails, it can be easily replaced, improving the reliability of the power conversion device To do.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit configuration when a power conversion device according to a first embodiment of the present invention is operated as a multiple inverter device.
FIG. 2 is a diagram illustrating a circuit configuration of a unit power conversion unit applied to the power conversion device of FIG. 1 according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating a detailed circuit configuration of the unit power conversion unit of FIG. 2 according to the first embodiment of the present invention.
4 is a diagram illustrating a circuit configuration of a face module according to the first embodiment of the present invention and applied to the three-phase rectifier circuit of FIG. 3;
5 is a diagram showing a circuit configuration of a face module applied to the single-phase self-excited inverter circuit of FIG. 3 according to the first embodiment of the present invention.
6 is a diagram illustrating a circuit configuration of a control circuit according to the first embodiment of the present invention and applied to the power conversion device of FIG. 1;
FIG. 7 is a diagram illustrating output voltage waveforms of each unit power conversion unit group and a power conversion device according to the first embodiment of the present invention.
FIG. 8 is a diagram showing a circuit configuration of a control circuit applied to a power conversion device according to a second embodiment of the present invention.
FIG. 9 is a diagram illustrating an output voltage waveform of a unit power conversion unit group according to the second embodiment of the present invention.
FIG. 10 is a diagram illustrating output voltage waveforms of each unit power conversion unit group and a power conversion device according to the second embodiment of the present invention.
FIG. 11 is a diagram illustrating output voltage values of each unit power conversion unit group and a power conversion device according to the second embodiment of the present invention.
FIG. 12 is a diagram showing a circuit configuration of a control circuit applied to a power conversion device according to a fourth embodiment of the present invention.
FIG. 13 is a diagram for describing switching of gate drive signals according to the fourth embodiment of the present invention.
FIG. 14 is a diagram illustrating output voltage waveforms of each unit power conversion unit and a power conversion device according to Embodiment 4 of the present invention.
FIG. 15 is a diagram showing a circuit configuration when the power conversion device according to the fifth embodiment of the present invention is operated as a multiple inverter device.
FIG. 16 is a diagram illustrating an example of a current bypass path of a unit power conversion unit according to the fifth embodiment of the present invention.
FIG. 17 is a diagram illustrating another example of the current bypass path of the unit power conversion unit according to the fifth embodiment of the present invention.
FIG. 18 is a diagram illustrating a circuit configuration of a control circuit according to the fifth embodiment of the present invention.
FIG. 19 is a diagram showing a circuit configuration of a multi-phase output power converter according to a seventh embodiment of the present invention.
FIG. 20 is a diagram showing a circuit configuration of a unit power conversion unit that is a main part of a power conversion device according to an eighth embodiment of the present invention.
FIG. 21 is a diagram illustrating a circuit configuration when the power conversion device is operated as a self-excited series compensator according to the eighth embodiment of the present invention.
FIG. 22 is a diagram for explaining the operation principle of the self-excited series compensator according to the eighth embodiment of the present invention.
FIG. 23 is a diagram showing a circuit configuration of a conventional power converter.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Polyphase alternating current power supply, 2,210,220,230 Power converter device, 3,310,320,330 1st output terminal, 4,410,420,430 2nd output terminal, 5,51-58 Unit power Conversion unit, 6, 61-63 Unit power conversion unit group, 7, 71-78 First input terminal group, 8, 81-88 Third output terminal, 9, 91-98 Fourth output terminal, 10, 101-108 input transformer, 11, 111-118 primary winding, 12, 121-128 secondary winding, 13, 131-138 first input terminal, 14, 141-148 fifth output terminal, 15 151-158 communication line 16, 161-163 control circuit, 17 three-phase rectifier circuit, 18 DC link circuit, 19 single-phase self-excited inverter circuit, 20 DC capacitor, 21, 211, 212 second input terminal, 2 Gate signal distribution circuit, 23, 231 to 233 First face module, 24, 241 to 242 Second face module, 25, 251 to 253 Third input terminal, 26, 261 to 263 Fourth input terminal, 27,271 to 272 Fifth input terminal, 28,281,282 Sixth input terminal, 29,291 to 293 Sixth output terminal, 30,301,302 Seventh output terminal, 31,311 to 314 Diode , 32, 321, 322 Self-extinguishing semiconductor device, 33 gate drive circuit, 34 gate signal generation circuit, 351-354 eighth output terminal, 40, 401-404 signal distribution circuit, 510 gate signal switching circuit, 520, 5201-5204 7th input terminal, 530, 5301-5308 9th output terminal, 540, 5401-5408 8 input terminals of 550,5501～5508 tenth output terminal of, 640 polyphase AC load, 650 voltage command generating circuit, 660 a first AC system, 670 a second AC system, 680 neutral point.

Claims (9)

A plurality of unit power conversion units having the same circuit configuration including an inverter circuit and an independent DC power supply and capable of outputting three levels of {1, 0, -1} with values normalized by the DC voltage value of the DC power supply comprising, an output terminal of the unit power conversion unit to a power converter connected in series, m ₁ pieces of it from the unit power conversion unit _{{m 1, ..., 0,} ..., -m 1} of (2m ₁ +1) (2m ₂ +1) level of {m ₂ ,..., 0,..., −m ₂ }, which includes a first unit power conversion unit group capable of outputting a level and m ₂ unit power conversion units. , M _n (where m ₁ , m ₂ ,..., M _n , and n are natural numbers, and m ₁ <m ₂ <... <m _n, it is 3 ≦ n.) of it from the unit power conversion unit {m _n, ..., 0, , A -m _n} of (2m _n +1) level output n-th unit power conversion unit group capable of, said at least one output voltage among the output voltages of the unit power conversion unit group Staggered output waveforms are obtained by staggering the on / off control timing between unit power conversion units belonging to the unit power conversion unit group, and a staircase waveform output voltage that is a pseudo sine wave is obtained by appropriately selecting each output voltage. The power converter characterized by the above-mentioned. The first unit power conversion unit group has m ₁ = 2 ⁰ and can output {1, 0, −1} (2 ¹ +1) level, and the second unit power conversion unit group has m ₂ = 2 ¹ , (2 ² +1) level output of {2, ¹ , 0, −1, −2} is possible, and the nth unit power conversion unit group is m _n = 2 ⁿ⁻¹ . , {2 ⁿ⁻¹ ,..., 2, 1, 0, −1, −2,..., −2 ⁿ⁻¹ }, (2 ⁿ +1) level output is possible. The power converter described. 2. The power conversion device according to claim 1, wherein an output voltage having a staircase waveform is obtained by appropriately selecting a maximum output voltage, 0, and a minimum output voltage of each unit power conversion unit group. 2. The power conversion device according to claim 1, wherein an output voltage having a staircase waveform is obtained by appropriately selecting all the voltages that can be output from each unit power conversion unit group. Each unit power conversion unit includes a three-phase self-excited rectifier circuit connected to a multi-phase AC power source via an input transformer, a single-phase self-excited inverter circuit, and a DC capacitor. The power converter according to claim 1, further comprising: a DC link circuit that connects the phase self-excited inverter circuit in parallel. When any unit power conversion unit has an abnormality, the unit power conversion unit in which the abnormality has occurred is put into a standby operation state, and means for increasing the voltage of the DC capacitor in the remaining healthy unit power conversion unit is provided. The power conversion device according to claim 5 . The unit power conversion unit includes a single-phase self-excited inverter circuit including a self-extinguishing semiconductor element, and each unit power conversion unit of each unit power conversion unit so as to average the number of switching times of each self-extinguishing semiconductor element. 2. The power conversion apparatus according to claim 1, further comprising means for switching assignment to a group. The unit power conversion unit includes a single-phase self-excited inverter circuit including a self-extinguishing semiconductor element and means for detecting a junction temperature of the self-extinguishing semiconductor element, and a junction temperature of each self-extinguishing semiconductor element. The power conversion device according to claim 1, further comprising means for switching the allocation of each unit power conversion unit to each unit power conversion unit group according to the above. More than (m ₁ + m ₂ + m ₃ +... + M _n ) unit power conversion units, unit power conversion units that have not been assigned to any unit power conversion unit group are set in a standby operation state, and unit power conversion unit groups If an error occurs in any unit power conversion unit that is assigned to the operation status, the unit power conversion unit in which the error has occurred is placed in the standby operation state and replaced with the unit power conversion unit in which the error has occurred. The power conversion device according to claim 1, further comprising means for setting a unit power conversion unit not assigned to any unit power conversion unit group to an operating state.

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