JP4349636B2 - Packet processing apparatus and program - Google Patents

Description

  The present invention relates to a packet processing device and a program, and more particularly to a packet processing device that performs communication data protocol processing and packet data transfer processing based on path information in a communication system.

A packet processing apparatus connected to a communication line stores data in a packet memory and then packetizes the data in a protocol processing unit and performs protocol processing in order to send the data on the line. Thereafter, data transfer using DMA (Direct Memory Access) is performed to the line corresponding unit.
Packets transferred to the line corresponding unit by DMA are sequentially sent out on the communication line. After the packet is sent to the communication line, the packet memory area used for holding the sent packet is released.
Processing from the packet transfer to the release of the packet memory is performed by a fixed processing method during transmission of the packet processing device.
In order to receive a packet from the communication line, data transfer using DMA is performed from the line corresponding unit upon arrival of the packet from the communication line, and the arrived packet is stored in the packet memory.
At the same time, the line corresponding unit generates a hardware interrupt notifying the reception of the packet and makes a request for starting the forced synchronization process. Thereafter, the processor of the packet processing device starts a forced synchronization process for forcibly delivering the received packet in the packet memory to the protocol processing unit, and performs the packet reception process.
The processor of the packet processing device releases the area of the packet memory used for holding the packet after all reception processes are completed. Processing from the arrival of the packet to the release of the packet memory is performed by a fixed processing method during reception of the packet processing device.

As prior art documents related to the invention of the present application, there are the following.
Takahiro Sajima, "Solaris Device Driver", O'Reilly Japan, Chapter 3, ISBN 4-87311-143-9 Ilhwan Kim, Junghwan Moon, and Heon Y. Yeom, "Timer-Based Interrupt Mitigation for High Performance Packet Processing", 5th International Conference on High-Performance Computing in the Asia-Pacfic Region, September, 2001, (Gold Coast, Australia)

In a conventional packet processing apparatus, transmission of a packet is generally realized with the configuration shown in FIG.
In FIG. 1 showing packet transmission processing, a packet input from the packet input unit 11 is stored in the packet memory 12, processed by the transmission processing unit 13 in a specific transmission processing method, and then transmitted to the line corresponding unit 14 by the DMA. Transferred.
In addition, after the packet is transmitted from the line corresponding unit 14, the transmission processing unit 13 releases the area of the packet memory 12 that holds the transmitted packet.
In this configuration, processing from data transmission to memory area release is performed by a fixed transmission processing method during transmission of the packet processing apparatus, and thus has the following problems.
(1) The resource consumption (processor time, packet memory) of the packet processing device changes dynamically during data transmission.
In response to this change, the packet processing capability of the packet processing device changes. On the other hand, the transmission processing method of the transmission processing unit 13 is fixed during data transmission, so that the active transmission processing method is the packet of the packet processing device. If it does not match the processing capability, the transmission performance is degraded.
In particular, the consumption of the packet memory varies greatly depending on the processing speed of the processor, and when the processing capacity of the processor is high, the data transfer speed to the line correspondence unit 14 is not in time and the packet memory 12 is consumed much. For this reason, the packet memory 12 becomes insufficient and the transmission performance is reduced.
(2) The packet processing apparatus generally provides a plurality of services, but the characteristics required for the operation of the transmission processing unit differ for each service. For example, whether or not data transmission is performed immediately in response to a transmission request from the packet processing apparatus, that is, the real-time property of data transmission.
In addition, in order to activate the transmission processing unit 13, the characteristics of the amount of resources required by the packet processing device also affect the operation of the service that provides it. However, since the transmission processing method of the transmission processing unit 13 is fixed during data transmission, the transmission processing method in operation may not satisfy the transmission characteristics required for each service.

In FIG. 2 showing the packet reception process, the packet received by the line corresponding unit 14 is DMA-transferred to the packet memory 12. Thereafter, the line correspondence unit 14 makes a request for starting the forced synchronization processing.
When receiving the activation request, the reception processing unit 29 activates the forced synchronization processing unit 29 a and passes the packet in the packet memory to the protocol processing unit 30. After the processing in the protocol processing unit 30 is completed, the reception processing unit 29 releases the area of the packet memory 12 that holds the received packet.
In this configuration, the processing from the arrival of data to the release of the memory area is performed by a fixed reception processing method during reception of the packet processing apparatus, and thus has the following problems.
(3) The resource consumption (processor time, packet memory) of the packet processing device changes dynamically during the data reception process.
In response to this change, the packet processing capability of the packet processing device changes, while the reception processing method of the reception processing unit 29 is fixed during data reception, so that the active reception processing method is the packet of the packet processing device. If the processing capability is not met, the reception performance is degraded.
In particular, the amount of consumption of the packet memory 12 varies greatly depending on the traffic characteristics on the communication line and the processing speed of the processor, and when the packet arrival time interval is short, the release processing of the packet memory 12 in the packet processing device is not in time. Since a large amount of packet memory 12 is consumed, the packet memory 12 becomes insufficient and the reception performance deteriorates.

(4) The traffic characteristics of the packets flowing on the communication line change dynamically even during packet reception by the packet processing device.
On the other hand, the packet processing apparatus performs reception by the reception processing unit 29 having a specific reception processing method during reception of the packet. If the reception processing method does not conform to the traffic characteristics on the communication line, the packet reception device receives the packet. Performance decreases.
In particular, when the packet size changes over a wide range from several bytes to several tens of kilobytes, or when there is a large change in the arrival time interval of packets, the number of times of forced synchronization processing that is started when a packet arrives is wide. Change. At this time, the processing capability of the processor becomes a bottleneck, and the reception performance decreases.
(5) Although the packet processing apparatus may provide a plurality of services, the characteristics required for the reception processing method of the reception processing unit 29 differ for each service.
For example, the immediateness of the response to the reception of the packet, the resource of the packet processing apparatus necessary for operating the reception processing method, and the like.
However, since the packet processing device uses a reception processing unit that operates in a specific reception processing method during reception of a packet, the packet processing device does not conform to the service provided by the active reception processing method. The required reception characteristics may not be satisfied.

The present invention has been made to solve the above-described problems of the prior art, and the object of the present invention is that the reception processing unit does not adapt even if the traffic characteristics and the protocol type on the communication line vary. High reception performance can be maintained by selecting and operating a reception processing method suitable for the traffic characteristics and protocol type on the line without causing a decrease in reception performance due to operation with the reception processing method. Is to provide a simple packet processing apparatus.
Another object of the present invention is to provide a program for causing a computer to execute the packet processing described above.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
That is, in the present invention, packet processing comprising a line corresponding unit that receives data from a communication line, a protocol processing unit that executes protocol processing of received data, and a packet memory that stores data received by the line corresponding unit. in the apparatus, in response to receiving the traffic characteristic, the line interface unit is characterized in that it comprises means for switching the time from reception of data until drive the protocol processing unit.

Specifically, the traffic pattern acquisition unit measures the data length of the data received by the packet processing device and the arrival time interval of the data, and stores the measured value in the counter to perform the following processing.
(1) The traffic pattern acquisition unit provided in the packet processing device measures the data length of the data received by the packet processing device and the arrival time interval of the data, and holds the measured value in the counter.
(2) The statistical processing unit calculates an average data length and an average arrival time interval of data arriving in a certain period from the data length and the data arrival time interval obtained in (1), and this average data length And the average arrival time interval. Here, the average data length and the average arrival time interval are traffic characteristics.
(3) After the data transfer from the line corresponding unit to the packet memory is completed for the range of the average data length and the average arrival time of the traffic characteristics output in (2), forced synchronization is performed after each different delay time. A reception processing unit table that associates a plurality of reception processing units that activate the processing unit is set in advance. However, instead of a plurality of reception processing units that start the forced synchronization processing unit after different delay times, a single reception processing unit that can start the forced synchronization processing unit after an arbitrary delay time, and the delay time It is also possible to configure with a setting unit capable of differentiating.
(4) The traffic characteristic and the reception processing unit table are compared in the comparison unit, and based on the result, the reception processing unit selector selects a reception processing unit that delivers the packet to the protocol processing unit.
(5) For the selected reception processing unit, the reception processing unit switch sets the destination of the packet.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, even if the change traffic patterns of packets flowing on communication line, by selecting the transmission and reception processing unit that executes the appropriate transmission and reception processing, the packet processing device provides a high transmission and reception characteristics Is possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Reference Example 1]
FIG. 3 is a block diagram showing a schematic configuration of the packet processing apparatus according to the first embodiment of the present invention. FIG. 3 shows a case where there are two transmission processing units that operate in different transmission processing methods.
In the figure, 14 is a line corresponding unit, 15 and 16 are transmission processing units that operate in different transmission processing methods, 17 is a transmission processing unit switch for switching transmission processing units, 18 is a transmission processing unit selector, and 12 is a packet. Reference numeral 19 denotes a comparison unit, 11 a packet input unit, 20 a transmission processing unit table, 21 a counter, and 22 a resource consumption acquisition unit.
Here, the transmission processing unit 15 is a forced memory release transmission processing unit, the transmission processing unit 16 is a non-forced memory release transmission processing unit, and the transmission processing units (15, 16) are installed on a general-purpose personal computer or workstation. And a hardware such as a DMA controller that operates in cooperation with the program on the communication board.

The transmission processing unit (15, 16) can also be configured by a single transmission processing unit and a setting unit capable of making the operation of the transmission processing unit different. In this case, the setting unit operates on a general-purpose personal computer and can be configured by a program for setting a register such as a communication board or a program for setting a variable value.
The packet input unit 11, the transmission processing unit switching unit 17, the transmission processing unit selector 18, and the comparison unit 19 can be configured by being described by a program that operates on a general-purpose personal computer.
The packet memory 12 can be configured as a general-purpose personal computer, a communication device, or a memory on a communication board.
The transmission processing unit table 20 and the counter 21 can be realized by holding them in a memory as values of variables of a program operating on a general-purpose personal computer. The counter 21 can also be configured by a general up / down counter or the like.
The resource consumption acquisition unit 22 can be configured as a program that reads hardware registers and reads counter variables held in a memory.

Next, the operation of the packet processing apparatus of this reference example will be described with reference to FIG.
In FIG. 4, data is transferred from the packet processing device A23 to the packet processing device B24 using the line 25 and the line 26 as a transmission line and a reception line, respectively. Each of the two packet processing devices is assigned a unique address.
Assume that an address to be used has a 32-bit address system conforming to IP (Intenet Protocol 1), and the packet processing device A23 is 10.1.2.3. The data transfer destination packet processor B24 has an address 10.1.2.4.
FIG. 5 is a diagram showing an actual operation in the configuration of FIG.

[Correspondence between specific implementation example and logical configuration diagram]
First, a specific example in which the invention of this reference example is implemented in the network driver portion of an operating system operating on a general-purpose personal computer is shown in FIG. 6 to explain the operation of this network driver. Clarify the correspondence.
This network driver drives a communication card mounted on an expansion bus of a general-purpose personal computer.
According to the numbers in the figure, the network driver and the communication card operate for the following.
(1) Step 1
The kernel of the operating system copies the data requested for transmission from the application to the buffer in the kernel area, performs protocol processing and packetization processing, and then starts transmission processing of the network driver.
(2) Step 2
The driver reads the value of the buffer amount reserved for the transmission packet from the variable managed in the kernel area.
(3) Step 3
Based on the value obtained in step 2, the driver switches the method for releasing the memory reserved for the packet that has been transmitted.

As a method, the following two types are generally performed.
(A) In step 7, the TxBD is released with a No TxBD interrupt issued when no TxBD (Buffer Descriptor for transmission) is registered in the TxBD address FIFO (First In First Out).
(B) Before step 4, a memory that secures a packet already sent on the communication line among the previously sent packets is calculated and released.
Switching between the above two methods is performed by operating the interrupt mask register on the communication card from the driver and using a flag variable that specifies which method is to be enabled in the driver.
(4) Step 4
The driver sets the address of the packet requested to be transmitted in TxBD (Buffer Descriptor for transmission) that manages the transmission packet.
(5) Step 5
The driver queues the TxBD address in the TxBD address FIFO on the communication card. At this time, if there is no free space in the TxBD address FIFO, a TxBDfu11 interrupt is issued.
(6) Step 6
Enable the DMA controller's transmittable register on the communication card.
As long as there is a data transmission request from the application, the kernel and the driver repeatedly perform the operations from Step 1 to Step 6 described above.

The subsequent operations are performed by the communication card.
(7) Step 7
When the transmittable register is validated, the communication card extracts the TxBD address from the TxBD address FIFO. At this time, if TxBD is not registered in the TxBD address FIFO, a NoTxBD interrupt is issued.
(8) Step 8
Based on the transmission packet address set in TxBD acquired in step 7, the packet is DMA-transferred from the main memory of the personal computer to the FIFO memory on the communication card.
(9) Step 9
When the DMA transfer is completed, the framer is notified that the transmission packet has been transferred to the FIFO. Thereafter, the framer sends a packet from the FIFO memory onto the communication line.

The two types of memory release methods described in (3) above have the following characteristics.
In the method (A), the memory is surely released because it is driven by an interrupt. However, when short packets are transmitted in bursts, interrupts occur frequently, so that the associated scheduling processing, etc. As a result, the load on the processor increases and transmission performance decreases.
In the method (B), since no interrupt is used, the load on the processor is small, and even a short packet can be transmitted at a higher speed than the method (A).
However, when a high-speed processor is used, the DMA transfer speed cannot keep up with the speed of the packet transmission request from the processor to the communication card, and the buffer cannot be released in time. As a result, the buffer begins to run short, and finally it becomes impossible to secure the buffer in one step.
In the method (B), since the buffer release step is not executed in such a situation, a deadlock in which transmission is completely stopped occurs. However, in the method (A), even in such a situation, an interrupt is caused. Since the buffer release is driven, packet transmission can be continued.
In order to take advantage of the advantages of the above two types of methods, in this reference example, in step 3, the two types of memory release methods are switched based on the buffer consumption.
In FIG. 6, the portions surrounded by the squares of the kernel and the driver operate on the processor of the personal computer.
The correspondence with FIG. 5 is as follows.

In FIG. 5, the packet input from the packet input unit 11 is transferred to the packet memory 12. In the packet memory, it is assumed that the data to be transferred contains both the header portion and the content portion of the protocol.
The resource consumption acquisition unit 22 acquires the usage amount of the packet memory 12. The acquired value is held in the counter 21.
The range that the value of the counter 21 can take is divided in advance for each specific range, and the transmission processing unit table 20 includes the forced memory release transmission processing unit 15, the non-forced for the divided ranges. The memory release transmission processing unit 16 is described in association with it.
The forced memory release transmission processing unit 15 and the non-forced memory release transmission processing unit 16 operate by the following transmission processing methods, respectively.

FIG. 7 shows a flowchart of operations of the forced memory release transmission processing unit 15 and the line correspondence unit 14.
When there is a packet input from the packet input unit 11 (step 101), the packet is held in the memory 12 (step 102), and immediately, the packet is DMA-transferred from the packet memory 12 to the line corresponding unit 14 (step 103). .
When the transmission of the packet onto the communication line is completed (step 111), the line corresponding unit 14 generates a hardware interrupt using the forced synchronization processing unit 15a of the forced memory release transmission processing unit 15. (Step 112)
When the forced memory release transmission processing unit 15 detects this interrupt (step 104), the forced memory release transmission processing unit 15 releases the area in the packet memory 12 where the transmitted packet has been secured (step 105).

In this transmission process, since the forced synchronization processing unit 15a activates the release of the packet memory 12, the memory can be surely released after the packet transmission on the communication line is completed.
On the other hand, since the forced synchronization processing is performed with a high processing priority in the processor of the packet processing device, when the forced synchronization processing unit 15a is frequently activated, the load on the processor of the packet processing device becomes high, and transmission is performed. There is a disadvantage that the performance decreases.
A general packet processing apparatus also performs processing for receiving a packet from a communication line. At that time, the same forced synchronization processing is also performed to notify the packet processor of the arrival of the packet.
Utilizing this property, a forced memory release processing method for releasing the packet memory 12 for transmission in cooperation with the activation of the forced synchronization processing unit 15a in the reception processing of the packet processing device is also conceivable.
Specifically, in order to reduce the load on the processor, a packet was received from the communication line even when an interrupt notifying that the transmission of the packet on the communication line was completed did not occur. At times, an interrupt is generated to activate the reception process in the processor. By releasing the packet memory that holds the transmission packet simultaneously with the detection of the interrupt at the time of receiving the packet, it is possible to trigger the release of the packet memory without using the interrupt at the completion of transmission.
Further, in a packet processing device having a plurality of transmission / reception interfaces, a forced memory release processing method for releasing the packet memory 12 in cooperation with the activation of the forced synchronization processing unit 15a observed in other interfaces is also conceivable.
Specifically, in order to reduce the load on the processor, even when an interrupt notifying that the transmission of the packet on the communication line has been completed does not occur, the transmission process is not performed in other transmission / reception interfaces. An interrupt occurs when it completes or receives a packet. By releasing the packet memory holding the transmission packet simultaneously with the detection of the interrupt in the other transmission / reception interface. It is possible to trigger the release of the packet memory without using an interrupt at the completion of transmission.

A flowchart of the operation of the non-forced memory release transmission processing unit 16 is shown in FIG.
When there is a packet input from the packet input unit 11 (step 121), the packet is held in the memory 12 (step 122), and the transmitted packet is secured in the packet memory 12 before the packet is transferred to the line corresponding unit 14. The calculated area is calculated (step 123), and the area of the packet memory 12 is released (step 124).
Thereafter, the packet is DMA-transferred from the packet memory 12 to the line corresponding unit 14 (step 125).
Since this transmission process does not use the forced synchronization processing unit 15a, the load on the processor of the packet processing device can be greatly reduced as compared with the forced memory release transmission processing unit 15. However, this transmission process has a drawback of consuming a large amount of memory resources.
The characteristics of each transmission processing unit are shown in FIG.

In this state, the operations of the comparison unit 19 and the transmission processing unit selector 18 are as follows.
(1) The comparing unit 19 compares the count value of the counter 21 with a preset entry in the transmission processing unit table 20.
(2) The count value of the counter 21 holds the usage amount of the packet memory 12, and here, the value is 50% or more of the entire packet memory 12 area.
(3) The comparison unit 19 selects the forced memory release transmission processing unit 15.
(4) The transmission processing unit selector 18 instructs the transmission processing unit switch 17 to select the forced memory release transmission processing unit 15.
The packet input by the packet input unit 11 is DMA-transferred to the line corresponding unit 14 using the forced memory release transmission processing unit 15.
After the transmission of the packet onto the communication line is completed, the line correspondence unit 14 activates the forced synchronization processing unit 15a to release the packet memory 12.
Thereafter, (5) the count value becomes less than 50% of the total packet memory 12 area.
(6) The comparison unit 19 selects the non-forced memory release transmission processing unit 16.
(7) The transmission processing unit selector 18 instructs the transmission processing unit switch 17 to select the non-forced memory release transmission processing unit 16.
The packet input by the packet input unit 11 uses the non-forced memory release transmission processing unit 16 to release the packet memory area of the transmitted packet, and then DMA-transfers the packet to the line corresponding unit 14.

FIG. 10 shows an operation example in this reference example.
In FIG. 10, the time in which the vertical direction elapses is shown, and each vertical line shows the elapse of the operation processing time of each part.
FIG. 10 shows a case where data packets continuously input from the packet input unit 11 to the packet memory 12 are sequentially output from the packet memory 12 to the line corresponding unit 14.
After the packet transmission request from the packet input unit 11, the comparison and the transmission processing unit are switched.
When the usage rate of the packet memory 12 is 50% or more, it is transmitted by the forced memory release transmission processing unit 15 and DMA-transferred to the line corresponding unit 14.
When the subsequent packet is transmitted from the packet memory 12, the usage rate of the packet memory 12 is read again from the count value, and the comparison and transmission processing unit are switched.
When the usage rate of the packet memory 12 becomes less than 50%, the non-forced memory release transmission processing unit 16 is selected and transmission is performed.

[Reference Example 2]
FIG. 11 is a block diagram showing a schematic configuration of the packet processing apparatus according to the second embodiment of the present invention. FIG. 11 shows a case where there are two transmission processing units each having a different transmission processing method as in FIG.
In the figure, reference numeral 48 denotes a calculation processing capacity acquisition unit. The calculation processing capability acquisition unit 48 can be configured by a program operating on a general-purpose PC or a register on the processor.
The counter 21 can be realized by holding it in the memory as the value of the counter variable in the program. It can also be configured with a general up / down counter or the like.
Other components are the same as those in FIG.
In FIG. 11, the data packet input from the packet input unit 11 is transferred to the packet memory 12. It is assumed that the data transferred in the packet memory 12 includes both a header portion and a content portion of the protocol.
The calculation processing capacity acquisition unit 48 acquires the usage rate of the processor of the packet processing device. The acquired value is held in the counter 21.
The range that the value of the counter 21 can take is divided in advance for each specific range, and the transmission processing unit table 49 indicates that the forced memory release transmission processing unit 15, non-forced for the divided ranges. The memory release transmission processing unit 16 is described in association with it.
Further, it is assumed that the forced memory release transmission processing unit 15 and the non-forced memory release transmission processing unit 16 are the same as those shown in Reference Example 1 described above.

In this state, the operations of the comparison unit 19 and the transmission processing unit selector 18 are as follows.
(1) The count value of the counter 21 is compared with a preset entry in the transmission processing unit table 49.
(2) The count value holds the usage rate of the processor of the packet processing device, and here the value is assumed to be 50% or more.
(3) The comparison unit 19 selects the non-forced memory release transmission processing unit 16.
(4) The transmission processing unit selector 18 instructs the transmission processing unit switch 17 to select the non-forced memory release transmission processing unit 16.
The packet input by the packet input unit 11 is DMA-transferred to the line corresponding unit 14 using the non-forced memory release transmission processing unit 16.
Thereafter, (5) the count value becomes less than 50%.
(6) The comparison unit 19 selects the forced memory release transmission processing unit 15.
(7) The transmission processing unit selector 18 instructs the transmission processing unit switch 17 to select the forced memory release transmission processing unit 15.
The packet input by the packet input unit 11 is DMA-transferred to the line corresponding unit 14 using the forced memory release transmission processing unit 15.
After the transmission of the packet onto the communication line is completed, the line correspondence unit 14 activates the forced synchronization processing unit 15a to release the packet memory 12.

[Reference Example 3]
FIG. 12 is a block diagram showing a schematic configuration of a packet processing apparatus according to Reference Example 3 of the present invention. Note that FIG. 12 shows a case where there are two transmission processing units each having a different transmission processing method as in FIG.
In the figure, 28 is a transmission protocol acquisition unit, 27 is a transmission processing unit table, and 51 is a statistical processing unit.
The sending protocol acquisition unit 28 can be configured by a pattern matching program that operates on a general-purpose PC or a pattern matching circuit, and the statistical processing unit 51 can be configured by a program that operates on a general-purpose PC.
The counter 21 can be realized by holding it in the memory as the value of the counter variable in the program. It can also be configured with a general up / down counter or the like.
Other components are the same as those in FIG.
In FIG. 12, the data packet input from the packet input unit 11 is transferred to the packet memory 12. It is assumed that the data transferred in the packet memory 12 includes both a header portion and a content portion of the protocol.
The transmission protocol acquisition unit 28 determines the protocol based on the destination port number of the transmission packet, the transmission source port number, or the combination of the destination port number and the transmission source port number, and the counter 21 determines the number of transmission packets for each protocol. save.

The statistical processing unit 51 calculates the ratio of the number of packets of a specific protocol with respect to the total number of packets transmitted in a certain period, and a threshold is provided in advance for this ratio.
Based on the count value of the counter 21, a protocol for outputting a ratio equal to or higher than the threshold value for a certain period is output. At this time, if all the protocols are less than the threshold, the protocol with the largest number of transmitted packets is output.
In the transmission processing unit table 27, the forced memory release transmission processing unit 15 and the non-forced memory release transmission processing unit 16 are described in association with each protocol.
Protocol A and protocol B in the figure each have the following requirements for communication characteristics.
In response to the transmission request, the protocol A needs to send the packet from the packet memory 12 to the line corresponding unit 14 immediately. However, the resources of the packet memory 12 are not consumed much. Therefore, the non-forced memory release transmission processing unit 16 is suitable.
In response to the transmission request, the protocol B does not need to immediately send a packet from the packet memory 12 to the line corresponding unit 14. However, many resources of the packet memory 12 are consumed. Therefore, the forced memory release transmission processing unit 15 is suitable.
Further, it is assumed that the forced memory release transmission processing unit 15 and the non-forced memory release transmission processing unit 16 are the same as those shown in Reference Example 1 described above.

In this state, the operations of the comparison unit 19 and the transmission processing unit selector 18 are as follows.
(1) Based on the count value of the counter 21 that holds the number of packets transmitted for each protocol, the output of the statistical processing unit 51 and the entry of the transmission processing unit table 27 are compared.
(2) Based on the value held in the counter 21, the statistical processing unit 51 calculates that the protocol B packet accounts for 50% or more of the total number of packets transmitted in the last minute, and determines the protocol B Output.
(3) The comparison unit 19 selects the forced memory release transmission processing unit 15.
(4) The transmission processing unit selector 18 instructs the transmission processing unit switch 17 to select the forced memory release transmission processing unit 15.
The packet input by the packet input unit 11 is DMA-transferred to the line corresponding unit 14 using the forced memory release transmission processing unit 15. After the transmission of the packet onto the communication line is completed, the line correspondence unit 14 activates the forced synchronization processing unit 15a to release the packet memory 12.
Thereafter, (5) based on the count value held in the counter 21, the statistical processing unit 51 calculates that the protocol A packet indicates 50% or more of the total number of packets transmitted in the last minute, Outputs protocol A.
(6) The comparison unit 19 selects the non-forced memory release transmission processing unit 16.
(7) The transmission processing unit selector 18 instructs the transmission processing unit switch 17 to select the non-forced memory release transmission processing unit 16.
The packet input by the packet input unit 11 is DMA-transferred to the line corresponding unit 14 using the non-forced memory release transmission processing unit 16.

[Example 1]
FIG. 13 is a block diagram illustrating a schematic configuration of the packet processing device according to the first embodiment of this invention. FIG. 13 shows a case where there are two reception processing units that operate in different reception processing methods.
In the figure, 14 is a line corresponding unit, 31 is a reception processing unit table, 47 is a resource consumption acquisition unit that acquires the resource consumption of the packet processing device, 46 is a counter, and 34 is the value of the counter 46 and the reception processing unit table. 31 is a comparison unit that compares 31, 35 is a reception processing unit selector that selects a reception processing unit based on the result of the comparison unit 34, 36 is a reception processing unit switch that switches the reception processing unit, and 40 and 44 are different reception processing methods. A reception processing unit 12 operates, 12 is a packet memory, and 30 is a protocol processing unit.
The reception processing unit table 31 can be realized by holding it as a variable on a program that operates on a general-purpose personal computer or workstation.
The resource consumption acquisition unit 47 can be realized by a program that operates on a general-purpose personal computer.
The counter 46 can be realized by using a variable on a program that operates on a general-purpose personal computer or workstation, or a general up / down counter. Other components are the same as those in FIG.

The comparison unit 34, the reception processing unit selector 35, and the reception processing unit switching unit 36 can be described by a program that operates on a general-purpose personal computer.
The reception processing units (40, 44) can be configured by hardware such as a program that operates on a general-purpose personal computer or a DMA controller that operates in cooperation with the program on a communication board.
The reception processing unit (40, 44) can also be configured by a single reception processing unit and a setting unit capable of making the operation of the reception processing unit different. In this case, the setting unit can be configured by a program that operates on a general-purpose personal computer and sets a register such as a communication board or a program that sets a value of a variable.
The packet memory 12 can be configured as a general-purpose personal computer, a communication device, or a memory on a communication board.
FIG. 14 is a diagram showing an actual operation in the configuration of FIG.

[Correspondence between specific implementation example and logical configuration diagram]
First, a specific example in which the invention of this embodiment is implemented in the network driver portion of an operating system operating on a general-purpose personal computer is shown in FIG. 15 to explain the operation of this network driver. Clarify the correspondence.
This network driver drives a communication card mounted on an expansion bus of a general-purpose personal computer. According to the numbers in the figure, the network driver and the communication card operate as follows.
(1) Step 1
The kernel of the operating system secures a buffer area for storing received packets and sets the address of the secured buffer in an RxBD (Buffer Descriptor for transmission) that manages the reception state of the received packets. A certain number of RxBDs are secured when the driver is initialized, and then a certain number is queued in the RxBD address FIFO of the communication card.
(2) Step 2
The driver reads the value of the buffer amount reserved for the received packet from the variable managed in the kernel area.

(3) Step 3
Based on the value obtained in step 2, the driver varies the delay time from when the packet is received until the protocol processing of the packet processing device is started.
In order to make the delay times different, the driver sets in the register of the communication card how many times the time is delayed with the timer time realized by the hardware on the communication card as a unit time. .
The communication card starts a timer for a set time after a packet arrives on the communication line, and generates an interrupt after the timer ends.
When the driver detects the interrupt, the driver requests the processor to start protocol processing.
(4) Step 4
Enable the DMA controller receivable register on the communication card.
The driver performs the operations from Step 1 to Step 4 before the packet arrives from the communication line.

The following operations are performed by the communication card.
(5) Step 5
A packet arrives from the communication line.
(6) Step 6
The packet is processed by a framer that performs packet framing processing and stored in a FIFO memory on the communication card. At the same time, the framer notifies the DMA controller that the received packet has been transferred to the FIFO.
(7) Step 7
The DMA controller retrieves the RxBD address from the RxBD address FIFO when the receivable register is enabled.
(8) Step 8
Based on the received packet storage buffer address set in RxBD acquired in step 7, the packet is DMA-transferred from the FIFO memory on the communication card to the main memory of the personal computer.
At the same time, the DMA controller writes a flag indicating the length and reception state of the received packet in RxBD.
(9) Step 9
The communication card starts the timer for the delay time set in step 3, and issues an RxBD Modify interrupt indicating that information necessary for reception processing has been written to the RxBD simultaneously with the end of the timer.
Every time a packet arrives from the communication line, the communication card repeats the operations from step 6 to step 9 described above.

The interrupt issued in step 9 is detected by the driver.
Subsequent operations are performed by the driver after detecting the interrupt.
(10) Step 10
After detecting the aforementioned RxBD Modify interrupt, the driver releases the association between the buffer area address of the received packet and the RxBD. At the same time, the buffer address of the received packet is set in a predetermined management structure for performing protocol processing in the kernel.
In addition, the newly reserved buffer area address is set in the RxBD from which the buffer area has been cut off. At this time, the received packets indicate all packets transferred to the main memory during the delay time of step 9.
As a result, processing for a plurality of packets arriving during the delay time can be performed in one batch with a single interrupt, and the load on the processor due to frequent activation of interrupt processing can be greatly reduced.
(11) Step 11
Thereafter, the driver requests the kernel to start protocol processing. The buffer area of the received packet subjected to the protocol processing is copied to the buffer area of the application or released when necessary processing is completed.

Depending on the length of the delay time set in step 3 described above, there are the following characteristics.
When the delay time is long, more packets are processed by a single interrupt on a communication line where packets frequently arrive, so that the effect of reducing the processor load is great.
On the other hand, in step 10, since the delay time until a new reception buffer is allocated becomes longer, the amount of memory consumption increases, and when the memory becomes insufficient, the reception performance deteriorates. In particular, when the size of the arriving packet changes significantly, if a long delay time is set assuming a short packet, a shortage of memory is caused when a long packet arrives frequently.
If the delay time is short, the delay time until a new receive buffer is assigned in step 10 is short, so that the amount of memory consumption is small, and the reception performance is hardly deteriorated due to a memory shortage.
However, since the number of packets processed by one interrupt becomes relatively small, the load on the processor is high on the communication line where packets frequently arrive, and the reception performance deteriorates. In particular, when the size of the arriving packet changes significantly, assuming that a long packet arrives and setting the delay time short, the load on the processor increases when short packets arrive frequently.
In this embodiment, in order to take advantage of the advantages and disadvantages of the delay time, in step 3, the length of the delay time is varied based on the buffer consumption.
In FIG. 15, the portion surrounded by the squares of the kernel and the driver, and step 4 operate with the processor of the personal computer.
The correspondence with FIG. 14 is as follows.

In FIG. 14, the data packet received from the line corresponding unit 14 is transferred to the packet memory 12. It is assumed that the data received from the line corresponding unit 14 includes both the header portion and the content portion of the protocol.
The resource consumption acquisition unit 47 acquires the usage amount of the packet memory 12. The acquired usage amount of the packet memory is held in the counter 46.
The range that the value of the counter 46 can take is divided in advance for each specific range, and the reception processing unit table 31 includes the reception processing unit A (41) and the reception processing for these divided ranges. Each reception processing unit of the part B (42) and the reception processing unit C (43) is described in association with each other.
The reception processing unit A (41), the reception processing unit B (42), and the reception processing unit C (43) have the following differences in reception processing methods.

A flowchart of the operation of the reception processing unit is shown in FIG.
When a packet arrives at the line corresponding unit 14 (step 131), the packet is DMA-transferred to the packet memory 12 (step 132).
Thereafter, a request for starting the forced synchronization processing unit is made to the reception processing unit (step 133).
When the reception processing unit detects that the activation request for the forced synchronization processing unit has been made (step 141), it performs a delay process for a predetermined time (step 142), and then starts the forced synchronization processing (step 143). Then, the address of the area where the packet in the packet memory 12 is stored is passed to the protocol processing unit 30 (step 144).
However, on a high-speed line with a short packet arrival time interval, forced synchronization processing is frequently started, which increases the load on the processor of the packet processing device and lowers reception performance.
To solve this problem, a method is adopted in which a delay process is performed for a predetermined time until the forced synchronization processing unit is activated, and reception of packets that have arrived during the delay time is performed in a single forced synchronization process.
However, when the length of the arriving packet varies over a wide range such as several tens of bytes to several tens of kilobytes, the suitable delay time depends on the length of the packet size for the following reason. Changes.

When the packet length is short, interrupts occur frequently, so the load on the processor is particularly high. However, since the amount of consumption of the packet memory 12 is not large, it is better that the delay time is long.
When the packet length is long, the consumption amount of the packet memory 12 is large. Therefore, if the delay time is lengthened, the packet memory 12 becomes insufficient. Therefore, the delay time cannot be increased even when the load on the processor increases. However, when the packet length is long, the delay time may be short because the load on the processor is originally low.
The reception processing unit A (41), the reception processing unit B (42), and the reception processing unit C (43) have different delay times, the reception processing unit A (41) is the shortest, and the reception processing unit The delay time is set to gradually increase as C (43) is reached.
The characteristics of the reception processing unit determined by the length of each delay time are shown in FIG.

In this state, the operations of the comparison unit 34 and the reception processing unit selector 35 are as follows.
(1) The count value of the counter 46 is compared with the entry in the reception processing unit table 31.
(2) The counter 46 holds the usage amount of the packet memory 12 acquired by the resource consumption acquisition unit 47, and here, the usage amount of the packet memory 12 is 60% or more of the total packet memory 12. .
(3) The comparison unit 34 selects the reception processing unit B (42).
(4) The reception processing unit selector 35 instructs the reception processing unit switch 36 to select the reception processing unit B (42).
Packets arriving at the line corresponding unit 14 are DMA transferred to the packet memory 12. The reception processing unit B (42) activates the forced synchronization processing unit 42a after the set delay time has elapsed, and passes the address of the area in the packet memory 12 where the packet is stored to the protocol processing unit 30.
Thereafter, (5) in the value of the counter 46, the usage amount of the packet memory 12 becomes 40%. (6) The comparison unit 34 selects the reception processing unit C (43).
(7) The reception processing unit selector 35 instructs the reception processing unit switch 36 to select the reception processing unit C (43).
Thereafter, the packet arriving at the line corresponding unit 14 is DMA-transferred to the packet memory 12, and the forced synchronization processing unit 43a is activated after the delay time set in the reception processing unit C (43) has elapsed.

FIG. 18 shows an operation example in the present embodiment.
In FIG. 18, the time in which the vertical direction elapses is shown, and each vertical line shows the progress of the operation processing time of each part. FIG. 18 shows a case in which data packets continuously arriving from the line correspondence unit 14 are DMA-transferred to the packet memory 12 one after another and the protocol processing unit 30 performs protocol processing.
When a packet is input from the line corresponding unit 14, the comparison and the reception processing unit are switched.
When the usage rate of the packet memory is 80%, reception processing is performed after the time set in the reception processing unit A (41) has elapsed, and the packet is passed to the protocol processing unit 30.
At the time of subsequent packet input, the usage rate of the packet memory 12 is calculated again. At the same time when the usage rate changes to 40%, the reception processing unit C (43) is selected and the reception process is performed.

[Example 2]
FIG. 19 is a block diagram illustrating a schematic configuration of the packet processing device according to the second embodiment of the present invention. Note that FIG. 19 shows a case where there are three reception processing units that operate in different reception processing methods, as in FIG.
In the figure, reference numeral 48 denotes a calculation processing capacity acquisition unit. The calculation processing capacity acquisition unit 48 can be configured as a register reading of a processor or a program operating on a general personal computer.
The counter 46 can be realized by holding it in the memory as the value of the counter variable in the program. It can also be configured with a general up / down counter or the like.
Other components are the same as those in FIG.
In FIG. 19, the data packet received from the line corresponding unit 14 is transferred to the packet memory 12. It is assumed that the data received from the line corresponding unit 14 includes both the header portion and the content portion of the protocol.
The calculation processing capacity acquisition unit 48 acquires the usage rate of the processor of the packet processing device. The acquired value is held in the counter 46.
The range that the value of the counter 46 can take is divided in advance for each specific range, and the reception processing unit table 31 includes the reception processing unit A (41) and the reception processing for these divided ranges. Each reception processing unit of the part B (42) and the reception processing unit C (43) is described in association with each other.
The reception processing unit A (41), the reception processing unit B (42), and the reception processing unit C (43) are the same as those in the first embodiment.

In this state, the operations of the comparison unit 34 and the reception processing unit selector 35 are as follows.
(1) The count value of the counter 46 is compared with the entry in the reception processing unit table 31.
(2) Here, the usage rate of the processor is 60% or more.
(3) The comparison unit 34 selects the reception processing unit B (42).
(4) The reception processing unit selector 35 instructs the reception processing unit switch 36 to select the reception processing unit B (42).
Packets arriving at the line corresponding unit 14 are DMA transferred to the packet memory 12. The reception processing unit B (42) activates the forced synchronization processing unit 42a after the set delay time has elapsed, and passes the address of the area where the received packet is stored in the packet memory 12 to the protocol processing unit 30. .
Thereafter, (5) the processor usage rate is assumed to be 40%.
(6) The comparison unit 34 selects the reception processing unit A (41) .
(7) The reception processing unit selector 35 instructs the reception processing unit switch 36 to select the reception processing unit A (41) .
Thereafter, the packet arriving at the line corresponding unit 14 is DMA-transferred to the packet memory 12, and the forced synchronization processing unit 43a is activated after the delay time set in the reception processing unit A (41) has elapsed.

[Example 3]
FIG. 20 is a block diagram illustrating a schematic configuration of the packet processing apparatus according to the third embodiment of this invention. Note that FIG. 20 illustrates a case where there are three reception processing units that operate in different reception processing methods, similarly to FIG.
In the figure, 45 is a reception protocol acquisition unit, and 50 is a statistical processing unit.
The reception protocol acquisition unit 45 can be configured with a program for performing pattern matching that operates on a general-purpose PC or a pattern matching circuit, and the statistical processing unit 51 can be configured with a program that operates on a general-purpose PC.
The counter 46 can be realized by holding it in the memory as the value of the counter variable in the program. It can also be configured with a general up / down counter or the like. Other components are the same as those in FIG.
In FIG. 20, the data packet received from the line corresponding unit 14 is transferred to the packet memory 12. It is assumed that the data received from the line corresponding unit 14 includes both the header portion and the content portion of the protocol.
The reception protocol acquisition unit 45 determines the protocol based on the destination port number of the received packet, the source port number, or a combination of the destination port number and the source port number, and the counter 46 determines the number of received packets for each protocol. Remember.

The statistical processing unit 50 calculates the ratio of the number of packets of a specific protocol with respect to the total number of packets received in a certain period, and a threshold is provided in advance for this ratio.
Then, based on the value of the counter 46, a protocol that outputs a ratio equal to or higher than a threshold value for a certain period is output. At this time, if all the protocols are less than the threshold value, the protocol having the largest number of received packets is output.
In the reception processing unit table 31, a reception processing unit is described in association with each registered protocol.
Protocol A and protocol C each have the following requirements for reception characteristics.
Protocol A requires immediate responsiveness to received packets. There is little processing in the processor. Therefore, the reception processing unit A (41) with a short delay processing time is suitable.
Protocol C does not require immediate responsiveness to received packets, but many processes are performed by the processor. Therefore, the reception processing unit C (43) with a long delay processing time is suitable.
The reception processing unit A (41), the reception processing unit B (42), and the reception processing unit C (43) are the same as those in the first embodiment.

In this state, the operations of the comparison unit 34 and the reception processing unit selector 35 are as follows.
(1) Based on the count value of the counter 46 that holds the number of received packets for each protocol, the output of the statistical processing unit 50 and the entry of the reception processing unit table 31 are compared.
(2) Based on the value held in the counter 46, the statistical processing unit 50 calculates that the protocol A packet indicates 50% or more of the total number of packets received in the last minute, and determines the protocol A Output.
(3) The comparison unit 34 selects the reception processing unit A (41).
(4) The reception processing unit selector 35 instructs the reception processing unit switch 36 to select the reception processing unit A (41).
Packets arriving at the line corresponding unit 14 are DMA transferred to the packet memory 12. The reception processing unit A (41) activates the forced synchronization processing unit 41a after the set delay time elapses, and passes the address of the area where the received packet is stored in the packet memory 12 to the protocol processing unit 30. .
Thereafter, (5) based on the count value held in the counter 46, the statistical processing unit 50 calculates that the protocol C packets represent 50% or more of the total number of packets received in the last minute, Outputs protocol C.
(6) The comparison unit 34 selects the reception processing unit C (43) .
(7) The reception processing unit selector 35 instructs the reception processing unit switch 36 to select the reception processing unit C (43) .
Thereafter, the packet arriving at the line corresponding unit 14 is DMA-transferred to the packet memory 12, and the forced synchronization processing unit 43a is activated after the delay time set in the reception processing unit C (43) has elapsed.

[Example 4]
FIG. 21 is a block diagram showing a schematic configuration of the packet processing apparatus according to the fourth embodiment of the present invention. Note that FIG. 21 shows a case where there are three reception processing units that operate in different reception processing methods as in FIG.
In the figure, reference numeral 39 denotes a traffic pattern information acquisition unit. The traffic pattern information acquisition unit 39 can be realized by a packet arrival time analysis function or a received packet length analysis function of the communication board. It can also be realized by examining variables in a program that runs on a general-purpose personal computer.
The counter 46 can be realized by holding it in the memory as the value of the counter variable in the program. It can also be configured with a general up / down counter or the like. Other components are the same as those in FIG.
In FIG. 21, the data packet received from the line corresponding unit 14 is transferred to the packet memory 12. It is assumed that the data received from the line corresponding unit 14 includes both the header portion and the content portion of the protocol.
The traffic pattern information acquisition unit 39 acquires the arrival time interval and the packet length of the data packet received from the line correspondence unit 14 and stores them in the counter 46.
The statistical processing unit 50 classifies the traffic characteristics into several traffic patterns in advance, calculates the traffic characteristics (here, average packet length, average arrival time interval) based on the value of the counter 46, and determines the traffic pattern The value of this pattern is output by applying to either.
The reception processing unit table 31 describes a reception processing unit to be applied to each registered traffic characteristic.
The reception processing unit A (41), the reception processing unit B (42), and the reception processing unit C (43) are the same as those in the first embodiment.

In this state, the operations of the comparison unit 34 and the reception processing unit selector 35 are as follows.
(1) The output of the statistical processing unit 50 is compared with the entry of the reception processing unit table 31.
(2) Based on the count value held in the counter 46, the statistical processing unit 50 calculates that the average packet length of the received packets in the last one minute is 1500 bytes and the average arrival time interval is 200 msec. It is determined that it corresponds to the traffic pattern A.
(3) The comparison unit 34 selects the reception processing unit A (41).
(4) The reception processing unit selector 35 instructs the reception processing unit switch 36 to select the reception processing unit A (41).
Packets arriving at the line corresponding unit 14 are DMA transferred to the packet memory 12. The reception processing unit A (41) activates the forced synchronization processing unit 41a after the set delay time has elapsed, and passes the address of the area in which the received packet is written in the packet memory 12 to the protocol processing unit 30. .
Thereafter, (5) the statistical processing unit 50 calculates that the average packet length of the most recently received packet is 250 bytes and the average arrival time interval is 10 msec, and determines that this value corresponds to the traffic pattern B.
(6) The comparison unit 34 selects the reception processing unit B (42).
(7) The reception processing unit selector 35 instructs the reception processing unit switch 36 to select the reception processing unit B (42).
Thereafter, the packet arriving at the line corresponding unit 14 is DMA-transferred to the packet memory 12, and the forced synchronization processing unit 42a is activated after the delay time set in the reception processing unit B (42) has elapsed.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

It is a figure for demonstrating the transmission process of the conventional packet processing apparatus. It is a figure for demonstrating the reception process of the conventional packet processing apparatus. It is a block diagram which shows schematic structure of the packet processing apparatus of the reference example 1 of this invention. It is a figure for demonstrating the connection structure of the packet processing apparatus of the reference example 1 of this invention. FIG. 4 is a diagram showing a state of actual operation in the configuration of FIG. 3. It is a figure which shows the case where the packet processing apparatus of the reference example 1 of this invention is comprised on a general purpose computer. It is a flowchart explaining operation | movement of the forced memory release transmission process part shown in FIG. It is a flowchart explaining the operation | movement of the non-forced memory open | release transmission process part shown in FIG. It is a figure explaining the characteristic of each transmission process part shown in FIG. It is a figure which shows the operation example of the packet processing apparatus of the reference example 1 of this invention. It is a block diagram which shows schematic structure of the packet processing apparatus of the reference example 2 of this invention. It is a block diagram which shows schematic structure of the packet processing apparatus of the reference example 3 of this invention. It is a block diagram which shows schematic structure of the packet processing apparatus of Example 1 of this invention. It is a figure which shows the mode of an actual operation | movement in the structure of FIG. It is a figure which shows the case where the packet processing apparatus of Example 1 of this invention is comprised on a general purpose computer. It is a flowchart explaining operation | movement of the reception process part shown in FIG. It is a figure explaining the characteristic of each reception process part shown in FIG. It is a figure which shows the operation example of the packet processing apparatus of Example 1 of this invention. It is a block diagram which shows schematic structure of the packet processing apparatus of Example 2 of this invention. It is a block diagram which shows schematic structure of the packet processing apparatus of Example 3 of this invention. It is a block diagram which shows schematic structure of the packet processing apparatus of Example 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Packet input part 12 Packet memory 13 Transmission process part 14 Line | wire corresponding | compatible part 15 Forced memory release transmission process part 15a, 29a, 40a, 41a, 42a, 43a, 44a Forced synchronous process part 16 Non-forced memory release transmission process part 17 Transmission process Unit switch 18 Transmission processing unit selector 19, 34 Comparison unit 20, 27, 49 Transmission processing unit table 21, 46 Counter 22, 47 Resource consumption acquisition unit 23 Packet processing device A
24 Packet processing device B
25 Transmission Line 26 Reception Line 28 Transmission Protocol Acquisition Units 29, 40, 44 Reception Processing Unit 30 Protocol Processing Unit 31 Reception Processing Unit Table 35 Reception Processing Unit Selector 36 Reception Processing Unit Switcher 39 Traffic Pattern Information Acquisition Unit 41 Reception Processing Part A
42 Reception Processing Unit B
43 Reception processing unit C
45 Receiving protocol acquisition unit 48 Calculation processing capability acquisition unit 50, 51 Statistical processing unit

Claims (2)

A line corresponding unit for receiving data from the communication line;
A packet memory for storing data received by the line corresponding unit;
A protocol processing unit that performs protocol processing of data received by the line corresponding unit;
A forced synchronization processing unit for forcibly starting the protocol processing unit;
A plurality of reception processing units for starting the forced synchronization processing unit after different delay times after data transfer from the line corresponding unit to the packet memory is completed;
A traffic pattern acquisition unit that measures the data length of the data received by the packet processing device and the arrival time interval of the data;
A counter that holds the data length measured by the traffic pattern acquisition unit and the arrival time interval of the data;
A statistical processing unit that estimates traffic characteristics on the communication line from the count value of the counter;
A reception processing unit table that associates a plurality of reception processing units that activate the forced synchronization processing unit after the different delay times with respect to the output value of the statistical processing unit,
A comparison unit that compares the output value of the statistical processing unit with the reception processing unit table;
A reception processing unit selector that selects one reception processing unit corresponding to the output value of the statistical processing unit from the plurality of reception processing units based on the result of the comparison unit;
A reception processing unit switch for switching the reception processing unit based on an instruction of the reception processing unit selector ;
The statistical processing unit calculates an average packet length and an average arrival time interval of data received from the count value of the counter, and applies it to any one of a plurality of traffic patterns previously classified as traffic characteristics on a communication line. Output the pattern value,
The reception processing unit table includes a plurality of reception processing units that activate the forced synchronization processing unit after the different delay times with respect to a traffic pattern that is an output value of the statistical processing unit. A packet processing apparatus, wherein the delay time is shortened as a traffic pattern having a longer time interval, and the delay time is increased as a traffic pattern having a shorter average packet length and arrival time interval . A program for causing a packet processing device according to claim 1 to be executed by a computer,
The program is stored in a computer according to claim 1 , a protocol processing unit, a forced synchronization processing unit, a plurality of reception processing units, a traffic pattern acquisition unit, a counter, a statistical processing unit, a comparison unit, a reception processing unit selector, and a reception A program for executing processing of a processing unit switching unit.

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