JP4349392B2 - Processor and program generation device - Google Patents

Description

  The present invention relates to a processor, a program generation device, and a recording medium that reduce instruction decoding processing.

  In recent years, the development of electronic technology and information processing technology has improved the performance of microprocessors, and they are widely used by being incorporated into various devices. Such processors achieve high performance by pipeline processing. Pipeline processing is to divide an instruction process into a plurality of parts and shift them in time to process other instructions in parallel. Especially for embedded applications, it is necessary to adopt an instruction system with a variable instruction word length in order to suppress an increase in code size. Is often divided into multiple pipelines.

  FIG. 16 shows an instruction format in the first prior art.

There are two types of prior art instructions, 21 bits as a unit (hereinafter referred to as a unit) consisting of one unit shown in FIG. 1A and two instructions shown in FIG. The two instructions are distinguished by the value of the instruction format information 101 of the leading 0th bit of each instruction. When the 0th bit is 0, 1 unit instruction, and when the 0th bit is 1, Indicates two unit instructions. In addition, these instructions are stored in the memory in the form of 3 units in 64 bits, which is the fetch width of one time, as shown in (c).

  FIG. 17 is a block diagram of a processor in the first prior art.

  This processor is a processor that simultaneously executes two instructions every cycle, and the branch destination is always the head of the instruction fetch unit.

  The instruction sequence 321 supplied from the memory system 210 is input to the instruction supply issuing unit 1620.

  In the instruction supply / issuance unit 1620, the fixed-length instruction converter 1622 converts the variable instruction word-length instruction into a fixed-length instruction that can be easily decoded. The converted fixed-length instruction is temporarily stored in the instruction buffer 223 and supplied to the instruction register 224 by two instructions according to a request from the instruction decoding unit 230. The two instructions stored in the instruction register 224 are supplied to the instruction decoding unit 230. In the instruction decoding unit 230, the two instruction decoders 233 and 234 decode the instruction. In the instruction execution unit 240, operations are performed by the two calculators 243 and 244.

  FIG. 18 is a detailed diagram of the fixed length instruction converter 1622.

The instruction fetch state storage 1631 normally stores a state as to whether or not an instruction straddles the previous instruction fetch and the current instruction fetch. If the instruction does not straddle, the head of the current instruction fetch matches the head of the instruction. If straddled, the head of the current instruction fetch is the second half of the instruction consisting of two units. It is shown that. When a branch occurs, the PC control unit 242 in the instruction execution unit 21 is informed via the instruction fetch control unit 1621 that the branch has occurred in synchronization with the instruction fetch. In this case, the value of the instruction fetch state storage 1631 is initialized to a state where no instruction is straddled, and indicates that the head of the instruction fetch becomes the head of the instruction. The second head detector 322b determines whether the second unit 321b is the head of the instruction from the instruction fetch state storage 1631 and the information of the head bit of the head unit 321a. Similarly, the third head detector 322c determines whether the third unit 321c is the head of the instruction from the information of the second head detector 322b and the head bit of the second unit 321b. Finally, the next state generator 1622d determines whether or not the instruction starting from 321c ends with the current instruction fetch from the information of the first bit of the third head detector 322c and the third unit 321c and fetches the result to the instruction fetch The third unit 321c is stored in the temporary storage register 323 when it is stored in the state storage 1631 and does not end with the instruction fetch.

  When the current instruction fetch starts from the middle of the instruction, the MIXa 324a concatenates the value of the first half of the instruction stored in the temporary storage register 323 and the value of the second half of the instruction 321a. If it is an instruction that ends with one unit at the beginning, as shown in FIG. 4 (a), the value 321a and one unit of meaningless data are output. If the instruction is an end instruction, as shown in FIG. 4B, the concatenation of the value of 321a and the value of 321b is output to the instruction buffer 223, otherwise nothing is output.

  Similarly, if 321b is an instruction that ends with one unit at the beginning of the instruction, MIXb 324b is obtained by concatenating the value of 321b and one unit of meaningless data, and 321b is the first two instructions at the beginning of the instruction. If the instruction ends with, the concatenation of the value of 321b and the value of 321c is output to the instruction buffer 223, otherwise nothing is output.

Similarly, when 321c is an instruction that ends with one unit at the beginning of the instruction, MIXc 324c outputs the result of concatenating the value of 321c and one unit of meaningless data to the instruction buffer 223, and otherwise. In case of, nothing is output.

  The next state generator 1622d outputs information indicating whether or not the instruction is straddling the current instruction fetch and the next instruction fetch to the instruction fetch state storage 1631. Save the beginning of the instruction.

  Up to six units of instructions 325 are supplied from the fixed-length instruction converter 1622 to the instruction buffer 223.

  The instruction sequence converter 332 inputs up to six units of the instruction 325 supplied to the instruction buffer 223 every time into the FIFO unit 333 by four units.

  The FIFO unit 333 outputs four units of instructions to the instruction register 224 in accordance with a request from the instruction decoding unit 230.

  As described above, in order to improve the performance of the processor, it is necessary to perform some advance processing before the instruction is decoded. In the case of a processor with a variable instruction word length instruction system often used for embedding etc. In this case, it is necessary to determine the start position of the instruction. For this purpose, an instruction fetch state storage 1631 for storing the state of the previous instruction fetch is required, and that state needs to be reset when a branch occurs. In addition to the problem that the hardware increases and a critical path occurs, there is a problem that it is complicated in terms of control and may cause a bug.

In order to solve the above-mentioned problem , the present invention is a processor that executes a variable-length instruction consisting of a plurality of units in parallel, fetching an instruction using a fixed number of units as a fetch unit, and the number that the processor can execute in parallel An instruction supply / issuance unit that outputs an instruction using the unit of the instruction as an execution unit, an instruction decoding unit that decodes an instruction output from the instruction supply / issuance unit, and an instruction execution that executes an instruction according to a decoding result of the instruction decoding unit A boundary of the execution unit is set independently of the boundary of the fetch unit, and whether or not the boundary of the fetch unit matches the boundary of the execution unit and each variable included in the execution unit The length of the long instruction is determined according to the values of multiple bits included in the fetch unit.

  As is apparent from the above description, the present invention simplifies the structure of the processor by arranging additional information in an instruction and performing control based on this information.

  Hereinafter, embodiments of a processor, a program generation device, and a recording medium according to the present invention will be described in detail with reference to the drawings.

(First embodiment)
(Instruction format)
FIG. 1 shows an instruction format of the processor according to the first embodiment of the present invention.

  This processor uses 21 bits as a unit (hereinafter referred to as a unit), and includes two types of instructions consisting of one unit shown in FIG. The two instructions are distinguished by the value of the instruction format information bit 101 in the 0th bit at the beginning of each instruction. When the 0th bit is 0, 1 unit instruction is used, and when the 0th bit is 1, Indicates two unit instructions. In addition, as shown in FIGS. 2C and 2D, these instructions are composed of 3 units of instructions in 64 bits, which is a fetch width, and the first unit in the fetch unit is an instruction. The head information 102 of the instruction indicating whether or not the head is stored is stored.

  When the head information 102 of the instruction is 1, the head of the instruction exists in the first unit as shown in FIG. 10C. When the head information 102 is 0, the latter half of the instruction becomes the first unit as shown in FIG. Indicates that it exists.

(Processor hardware configuration)
FIG. 2 is a block diagram of the processor according to the first embodiment of this invention.

  This processor is a processor that can execute two instructions at the same time, and the branch destination is always the head of the instruction fetch unit.

  210 is a memory system that stores an instruction sequence, 220 is an instruction supply issuer in charge of instruction fetching to conversion to a fixed-length instruction, 221 is an instruction fetch control unit that controls instruction fetching, and 222 is a variable that fetches an instruction. Fixed-length instruction converter for converting long instructions into fixed-length instructions, 223 is an instruction buffer for buffering fixed-length instructions, 224 is an instruction register for storing instructions to be decoded, 230 is an instruction decoding unit for performing general instruction decoding, 231 Is an instruction issue controller for controlling instruction decoding, 232 is an instruction decoder for decoding instructions, 233 is a first instruction decoder for decoding instructions, 234 is a second instruction decoder for decoding instructions, and 240 is according to the decoding result An instruction execution unit that executes instructions, 241 is an instruction execution control unit that controls instruction execution, 242 is a PC control unit that takes charge of a branching relationship, 243 is a first Calculator, 244 the second operating unit, 245 is a register file that stores the register.

  FIG. 3 is a detailed block diagram of the instruction supply issue unit 220.

321 is 64-bit instruction fetch data supplied from the memory system, 321a is data of the first unit in the instruction fetch data 321, 321b is data of the second unit in the instruction fetch data 321, and 321c is an instruction. The data of the third unit in the fetch data 321, 321 d is the position information bit of the instruction in the instruction fetch data 321, and 322 b is the second head detection for determining whether the data 321 b of the second unit is the head of the instruction 322c is a third head detector for determining whether the data 321c of the third unit is the head of the instruction, and 322d is for determining whether the data 321a of the first unit of the next instruction fetch is the head of the instruction. The next state generator 323, the second half of the instruction in the current instruction fetch is the next instruction fetch If there is a temporary storage register that stores the first half of the instruction, 324a outputs the first unit at the end or MIXa that outputs two units of fixed-length instruction 325a at the beginning, 324b starts the second unit MIXb and 324c that output two units of fixed-length instruction 325b at the time of MIXc and 331 that output two units of fixed-length instruction 325c when the third unit is the head of one unit instruction, an instruction buffer that controls the instruction buffer The control unit 332 is an instruction string converter that converts 6 units of instructions output from the fixed-length instruction converter 222 into a sequence of 2 unit instructions, and 333 is a FIFO that accumulates instructions.

  The operation of the processor according to the first embodiment of the present invention configured as described above will be described below.

  The instruction sequence 321 supplied from the memory system 210 is input to the instruction supply issuing unit 220. In the instruction supply / issuance unit, the fixed-length instruction converter 222 converts the variable-length instruction into a fixed-length instruction that can be easily decoded. The converted fixed-length instruction is temporarily stored in the instruction buffer 223 and supplied to the instruction register 224 by two instructions according to a request from the instruction decoding unit 230. The two instruction sequences stored in the instruction register 224 are supplied to the instruction decoding unit 230. In the instruction decoding unit 230, the two instruction decoders 233 and 234 decode the instruction. In the instruction execution unit 240, operations are performed by the two calculators 243 and 244.

(Detailed configuration of fixed-length instruction converter)
Details of the converter to fixed-length instructions are described below.

The instruction position information bit 321d in the instruction fetch data 321 stores a state as to whether or not an instruction has straddled between the previous instruction fetch and the current instruction fetch. If the instruction does not straddle, the head of the current instruction fetch matches the head of the instruction. If straddled, the head of the current instruction fetch is the second half of the instruction consisting of two units. It is shown that.

  The second head detector 322b determines whether the second unit 321b is the head of the instruction from the instruction position information bit 321d in the instruction fetch data 321 and the information of the head bit of the head unit 321a.

  Similarly, the third head detector 322c determines whether the third unit 321c is the head of the instruction from the information of the second head detector 322b and the head bit of the second unit 321b. Finally, the next state generator 322d determines whether the instruction starting from 321c ends with the current instruction fetch from the third head detector 322c and the information of the first bit of the third unit 321c, and ends with the instruction fetch. If not, the third unit 321 c is stored in the temporary storage register 323.

  When the current instruction fetch starts from the middle of the instruction, the MIXa 324a concatenates the value of the first half of the instruction stored in the temporary storage register 323 and the value of the second half of the instruction 321a. If it is an instruction that ends with one unit at the beginning, as shown in FIG. 4 (a), the 321a value is linked with meaningless data for one unit, and 321a is two units at the beginning of the instruction. If the instruction is an end instruction, as shown in FIG. 4B, the concatenation of the value of 321a and the value of 321b is output to the instruction buffer 223, otherwise nothing is output.

  Similarly, if 321b is an instruction that ends with one unit at the beginning of the instruction, MIXb 324b is obtained by concatenating the value of 321b and one unit of meaningless data, and 321b is the first unit of the instruction with two units. If the instruction ends with, the concatenation of the value of 321b and the value of 321c is output to the instruction buffer 223, otherwise nothing is output.

  Similarly, when 321c is an instruction that ends with one unit at the beginning of the instruction, MIXc 324c outputs the result of concatenating the value of 321c and one unit of meaningless data to the instruction buffer 223, and otherwise. In case of, nothing is output.

(Detailed configuration of instruction sequence converter and FIFO)
FIG. 7 is a table for explaining the operation of the instruction sequence converter.

  There are always 0 units or 2 units of instruction sequence in the instruction sequence converter 332.

  The instruction string converter 332 receives 2-unit, 4-unit, or 6-unit instructions from the fixed-length instruction converter.

  As a result of receiving the instruction, when four or more units of instructions are prepared, the instruction sequence converter 332 outputs four units of instructions to the FIFO 333. When there are instructions of less than 4 units, they are not output to the FIFO 333 but are stored in the instruction sequence converter 332.

  The FIFO 333 outputs instructions prepared therein to the instruction register 224 in units of four according to a request from the instruction decoding unit 230.

(Processor operation)
Next, the operation of this processor when a specific instruction is decoded and executed will be described.

  FIG. 5C shows an example of a program in the first embodiment of the present invention.

In this program example, from the address 0x1000 ("0x" represents a hexadecimal number, the same applies hereinafter), add r0, r1 instructions composed of one unit, add 0x1234, r2 instructions composed of two units, add 0x2345, r3 It is assumed that the instruction, sub 0x3456, r4 instruction, nop instruction composed of one unit, cmp r1, r2 instruction, sub r3, r4 instruction, sub r5, r6 instruction, sub r6, r7 instruction follow. In this instruction sequence, the instruction fetch at address 0x1004 is the instruction following the next instruction fetch, so the instruction position information bit 102 is 0, and the others are 1 (originally a binary machine language instruction, Here, mnemonic notation).

  When a branch instruction to address 0x1000 is detected, the instruction execution control unit 241 outputs a branch instruction to the PC control unit 242. The PC control unit 242 outputs a branch instruction to the instruction fetch control unit 221 and outputs a branch address to the IA bus 211. The memory system 210 outputs a 64-bit instruction sequence corresponding to the IA bus 211 to the ID bus 212, which is received by the fixed-length instruction converter 222 in the instruction supply issue unit 220.

  In the fixed length instruction converter 222, first, since the head information bit 102 of the instruction in the instruction fetch data is 1, it can be seen that the data 321a of the first unit is the head of the instruction. Further, in the second head detector 322b, it can be seen that the second unit is also the head of the instruction because 321a is the head of the instruction and the head bit of the first unit 321a is 0. . Similarly, in the third head detector 322c, the third unit is the second unit because 321b is the head of the instruction and the first bit of the second unit 321b is 1. You can see that it is the second half of the instruction starting with. Finally, in the next state generator 322d, it can be seen that the instruction is finished in the third unit without seeing the first bit of the third unit 321c since 321c is the end of the instruction. It can be seen that the temporary storage register 323 does not need to store the data 321c of the third unit.

Further, since the data 321a of the first unit is the head of the instruction and is a unit instruction, the MIXa 324a outputs the instruction data 321a and the meaningless data 21 bits concatenated to the instruction buffer 223. . Similarly, the MIXb 324b outputs the concatenated instruction data 321b and 321c to the instruction buffer 223 because the second data 321b is the head of the instruction and the head of the two unit instruction. Similarly, the MIXc 324c outputs nothing because the third data 321c is the second half of the 2-unit instruction.

  As a result, instructions of 4 units are output to the instruction buffer 223 as shown in FIGS. 6 (a1), 6 (b1) and 6 (c1) by instruction fetch at address 0x1000.

  Next, instruction fetch at address 0x1004 is performed.

  By performing the same processing, since MIXa 324a is the head of the two unit instruction, the data 321a of the first unit and the data 321b of the second unit are connected and output to the instruction buffer 223. Since MIXb 324b is the second half of the 2-unit instruction, nothing is output. Since MIXc 324c is the first half of a two-unit instruction, nothing is output. The next state generator 322d stores the data of 321c in the temporary storage register 323 because 321c is the first half of the next instruction.

  Thus, two units of instructions are output to the instruction buffer 223 as shown in FIGS. 6 (a2), 6 (b2), and 6 (c2) by the instruction fetch at address 0x1004.

  Next, instruction fetch at address 0x1008 is performed.

By performing the same processing, since MIXa 324a is the second half of the two unit instruction, the first half instruction stored in the temporary storage register 323 and the data 321a of the first unit are connected and output to the instruction buffer 223. Since MIXb 324b is a one-unit instruction, data 321b of the second unit and 21-bit meaningless data are concatenated and output to the instruction buffer 223. MIXc324c
Since the third unit is a one-unit instruction, the data 321c of the third unit and 21-bit meaningless data are concatenated and output to the instruction buffer 223.

  As a result, 6 units of instructions are output to the instruction buffer 223 as shown in FIGS. 6 (a3), 6 (b3), and 6 (c3) by the instruction fetch at address 0x1008.

  By the same processing, six units of instructions are output to the instruction buffer 223 as shown in FIGS. 6 (a4), 6 (b4), and 6 (c4) by instruction fetch at address 0x100c.

  The instruction decoding unit 230 decodes the instruction converted into the fixed length instruction by the fixed length instruction converter 222 by two instructions via the instruction buffer 223 and the instruction register 224.

(Configuration of program generator)
FIG. 14 is a block diagram of the program generation apparatus according to the first embodiment of the present invention.

  1410 is a source program storage means before adding position information of an instruction, 1420 is an instruction extracting means for dividing the unit into groups of 3 units, 1430 is a head position information generating means for determining whether or not the instruction is across groups, and 1440 is An instruction sequence generation unit 1450 for combining the grouped instruction sequence and the head position information, and 1450 is an instruction sequence storage unit for storing the generated instruction sequence.

  The operation of the program generating apparatus according to the first embodiment of the present invention configured as described above will be described below.

The source program storage unit 1410 stores a source program composed of one unit or two units. The instruction extraction unit 1420 acquires the source program from the source program storage unit 1410 and divides it into groups each composed of three units. The head position information generation means 1430 acquires the instructions divided into groups output by the instruction extraction means 1420, determines whether the head of the group matches the head of the instruction, and if they match, 1 If the values do not match, 0 is output. The instruction sequence generation unit 1440 combines the output of the instruction extraction unit 1420 and the output of the head position information generation unit 1430 and outputs an instruction sequence to which position information is added.

(Operation of program generator)
Next, the operation of this instruction sequence generation apparatus when a specific instruction is decoded and executed will be described.

  FIGS. 5A and 5B are examples of an input program and an output program of the program generation device according to the first embodiment of the present invention.

The source program storage means 1410 includes an add r0, r1 instruction composed of one unit, an add 0x1234, r2 instruction composed of two units, an add 0x12345, r3 instruction, sub 0x3456, r4 shown in FIG. Instruction, nop instruction composed of one unit, cmp r1, r2 instruction, sub
r3 and r4 instructions, sub r5 and r6 instructions, and sub r6 and r7 instructions are stored.

  The instruction extracting means 1420 extracts three units of add r0 and r1 instructions and an add 0x1234 and r2 instructions composed of two units from the source program stored in the source program storage means 1410 as shown in FIG. 5 (b1). And output to the head position information generating means 1430 and the instruction sequence generating means 1440.

When the head position information generating means 1430 receives three units of instructions from the instruction extracting means 1420, it determines whether or not the head unit is the head of the instruction. Since the add r0, r1 instruction is the head of the instruction, 1 is output.

  The instruction sequence generation unit 1440 combines the 3 units of instructions output from the instruction extraction unit 1420 and the 1-bit value 1 output from the head position information generation unit 1430, and outputs a 64-bit instruction sequence.

  Next, similarly, the instruction extraction means 1420 outputs the add 0x2345, r3 instruction and the first three units of the sub 0x3456, r4 instruction as shown in FIG. 5 (b2), and the leading unit is add 0x2345, r3. Since it is the head of the instruction command, the head position information generating means 1430 outputs 1.

  Next, in the same manner, the instruction extraction unit 1420 outputs the second unit of the sub 0x3456, r4 instruction and three units of the nop instruction composed of one unit as shown in FIG. 5B3, and the first unit is the sub unit. Since it is the latter half of the 0x3456, r4 instruction, the head position information generating unit 1430 outputs 0.

  By repeating the above processing, the instruction sequence generator 1440 outputs an instruction sequence to which instruction position information is added.

  FIG. 5C is an instruction sequence in which instruction position information is added to the instruction sequence of FIG.

(Second Embodiment)
(Instruction format)
FIG. 8 shows an instruction format of the processor in the second embodiment of the present invention.

  The processor has two instruction sets.

  FIG. 2A shows a first instruction set composed of 21-bit fixed length instructions, and FIG. 2B shows a second instruction set composed of 63-bit fixed length instructions.

  The two instruction sets are selected by instruction set selection information existing within a 64-bit instruction fetch unit.

  FIG. 5C shows a 3-instruction sequence composed of three first instruction sets when the 1-bit instruction set selection information FM is 0. FIG. 10D shows a 1-bit instruction. When the set selection bit FM is 1, it is an instruction sequence composed of one second instruction set.

  FIG. 9 is a configuration diagram of the processor according to the second embodiment of the present invention.

  910 is a memory system that stores an instruction sequence, 920 is an instruction supply issue unit that stores an instruction fetched instruction in an instruction register, 921 is an instruction fetch control unit that controls instruction fetch, and 924 is an instruction that stores an instruction to be decoded Register, 930 is an instruction decoding unit for general instruction decoding, 931 is an instruction issue control unit for controlling instruction decoding, 932 is an instruction decoder for decoding instructions, and 933a is an instruction sequence composed of three 21-bit instructions. First instruction decoder for decoding, 933b is a second instruction decoder for decoding an instruction sequence composed of one 63-bit instruction, 935 is a MUX for selecting a decoding result of one of the instruction decoders, and 936 is an instruction An instruction set selector for determining a set; 940, an instruction execution unit for executing an instruction according to the result of decoding; 941, an instruction execution control unit for controlling instruction execution; PC control unit in charge of branch relationship 943 calculator, 945 is a register file that stores the register.

  The operation of the processor according to the second embodiment of the present invention configured as described above will be described below.

The instruction sequence supplied from the memory system 910 is input to the instruction supply issuing unit 920. In the instruction supply / issuance unit, 64 bits are supplied to the instruction register 924 in accordance with a request from the instruction decoding unit 930. The instruction sequence stored in the instruction register 924 is supplied to the instruction decoding unit 930. In the instruction decoding unit 930, the first instruction decoder 933a and the second instruction decoder 933b decode the 64-bit instruction as two types of instruction sequences. The instruction set selector 936 determines which of the two decoding results, and based on the information, the MUX 935 selects one of the two decoding results. In the instruction execution unit 940, calculation is performed by the calculator 943.

(Detailed configuration of instruction decoder)
Details of the instruction decoder are described below.

  The 64-bit instruction sequence supplied from the instruction supply issue unit 920 is decoded by the first instruction decoder 933a and the second instruction decoder 933b.

  The first instruction decoder 933a decodes the first 21 bits of the 64-bit instruction sequence and outputs a microinstruction 934a.

  The second instruction decoder 933b decodes 63 bits in the 64-bit instruction sequence and outputs a microinstruction 934b.

  The instruction set selector 936 selects an instruction set using 1-bit instruction set selection information in a 64-bit instruction sequence. When the instruction set selection information is 0, the instruction stored in the current instruction register 924 is composed of three instructions of the first instruction set. When the instruction set selection information is 1, the current instruction register 924 Indicates that the instruction stored in is composed of one instruction of the second instruction set. The MUX 935 uses the instruction set information selected by the instruction set selector 936 to select either the microinstruction 934a output from the first instruction decoder 933a or the microinstruction 934b output from the second instruction decoder 933b. . As a result, the instruction decoder 932 decodes the instruction sequence stored in the instruction register 924 as a correct instruction, and issues an operation instruction to the instruction execution unit 940.

When the instruction set selector 936 selects the first instruction set, the first instruction decoder 933a continues to decode the instructions of the remaining two first instruction sets stored in the instruction register 924. The microinstruction 934a is output to the instruction execution unit.

(Processor operation)
Next, the operation of this processor when a specific instruction is decoded and executed will be described.

  FIGS. 10 (c1) and (c2) are examples of programs in the second embodiment of the present invention.

  From address 0x1000, add1 r0, r0 instruction, sub1 r2, r1 instruction, cmp1 r4, r1 instruction, which are the instructions of the first instruction set, continue, and add2 r5, r6, which is the instruction of the second instruction set from address 0x1004 Instruction, sub2 r7, r6 instruction, cmp2 r9, r6 instruction, jmp2 0x2000 instruction, and apart from address 0x2000, are instructions of the first instruction set, mul1 r0, r1 instruction, div1 r2, r3 instruction, sub1 r1 , R2 instruction continues. In this instruction sequence, instruction fetches at addresses 0x1000 and 0x2000 store the instruction of the first instruction set because the instruction of the first instruction set is stored, and the instruction of the second instruction set is stored otherwise. (It is originally a binary machine language instruction, but here it is written in mnemonic. Also, the machine language of the add1 instruction and the sub2 instruction is the same. May be assigned different instructions, or the same instruction may be assigned to the same machine language even if the instruction set is different, such as the add1 instruction and the add2 instruction are in the same machine language.

When a branch instruction to address 0x1000 is detected, the instruction execution control unit 941 outputs a branch instruction to the PC control unit 942. The PC control unit 942 outputs a branch instruction to the instruction fetch control unit 921 and outputs a branch address to the IA bus 911. The memory system 910 outputs to the ID bus 912 a 64-bit instruction string starting from address 0x1000 corresponding to the IA bus 911, and the instruction register 924 in the instruction supply issue unit 920 receives it.

  The first instruction decoder 933a in the instruction decoder 932 refers to the first 21 bits 925a of the instruction register 924 to decode the add1 r0, r0 instruction, and the second instruction decoder 933b includes the first 63 bits 925a of the instruction register 924. , 925b, and 925c, and the microinstruction 934a and the microinstruction 934b are output. At the same time, the instruction set selector 936 refers to the instruction register 924 and determines that the instruction set is the first instruction set because the instruction set selection information is 0. Since the MUX 935 selects the microinstruction 934a output from the first instruction decoder 933a, the instruction execution unit 940 executes the add1 r0, r0 instruction.

  Subsequently, since the first instruction set is selected, the first instruction decoder 933a continues to decode the instructions of the remaining two first instruction sets stored in the instruction register 924. The microinstruction 934a is output to the execution unit 940. As a result, the sub1 r2, r1 instruction and the cmp1 r4, r1 instruction are executed.

  Next, the instruction at address 0x1004 is executed. Since the instruction set selection information of the instruction fetch data at address 0x1004 stored in the instruction register 924 is 1, the add2 r5 and r6 instructions are decoded as the second instruction set and executed by the instruction execution unit 940.

Similarly, address 0x1008 is the second instruction set, sub2 r7, r6 instruction, address 0x100c is the second instruction set, cmp2 r9, r6 instruction, and address 0x1010 is the second instruction set, jmp2. The 0x2000 instruction is the branch destination address 0x2000, and the first instruction set mul1 r0,
The r1 instruction, the div1 r2, r3 instruction, and the sub1 r1, r2 instruction are executed.

(Configuration of program generator)
FIG. 15 is a block diagram of a program generation apparatus according to the second embodiment of the present invention.

  1610 is a source program storage means before adding instruction position information, 1620 is an instruction extracting means for dividing into groups of three units, and 1630 is instruction set selection information for generating information on which instruction set the instruction belongs to Generation means 1640 is an instruction string generation means for synthesizing the grouped instruction strings and instruction set selection information, and 1650 is an instruction string storage means for storing the generated instruction strings.

  The operation of the program generating apparatus according to the second embodiment of the present invention configured as described above will be described below.

  The source program storage means 1610 stores a source program of instructions belonging to a first instruction set composed of one unit and instructions belonging to a second instruction set composed of three units. The instruction extraction unit 1620 acquires the source program from the source program storage unit 1610 and divides it into groups each composed of three units. The instruction set selection information generation unit 1630 acquires the instructions divided into groups output by the instruction extraction unit 1620, determines which instruction set the instructions in the group belong to, and belongs to the first instruction set 0 is output when it is, and 1 is output when it belongs to the second instruction set. The instruction sequence generation unit 1640 combines the output of the instruction extraction unit 1620 and the output of the instruction set selection information generation unit 1630 and outputs an instruction sequence to which instruction set selection information is added.

(Operation of program generator)
Next, the operation of this instruction sequence generation apparatus when a specific instruction is decoded and executed will be described.

  FIGS. 10A and 10B are examples of the input program and the output program of the program generation apparatus according to the second embodiment of the present invention.

  The source program storage means 1610 is followed by an add1 r0, r0 instruction, sub1 r2, r1 instruction, cmp1 r4, r1 instruction, which are instructions of the first instruction set shown in FIG. Assume that an instruction set instruction, add2 r5, r6 instruction, sub2 r7, r6 instruction, cmp2 r9, r6 instruction, and jmp2 0x2000 instruction follow.

  The instruction extraction means 1620 is a command of the first instruction set, which is an instruction of the first instruction set, which is an instruction for three units as shown in FIG. 10 (b1) from the source program stored in the source program storage means 1610, The sub1 r2, r1 instruction and the cmp1 r4, r1 instruction are extracted and output to the instruction set selection information generating unit 1630 and the instruction sequence generating unit 1640.

  When the instruction set selection information generating means 1630 receives three units of instructions from the instruction extracting means 1620, it determines which instruction set the instruction sequence belongs to. Since these three units of instructions are the first instruction set, 0 is output.

  The instruction sequence generation means 1640 combines the 3 units of instructions output from the instruction extraction means 1620 and the 1-bit value 0 output from the instruction set selection information generation means 1630, and outputs a 64-bit instruction sequence.

Next, similarly, the instruction extraction means 1620 outputs three units of add2 r5 and r6 instructions, which are instructions of the second instruction set as shown in FIG. 10 (b2), and the corresponding unit outputs the second instruction. Since it is an instruction belonging to a set, the instruction set selection information generating means 1630 outputs 1.

  By repeating the above processing, the instruction sequence generator 1640 outputs an instruction sequence to which instruction set selection information is added.

  FIG. 10 (c1) is an instruction sequence in which instruction set selection information is added to the instruction sequence of FIG. 10 (b).

(Problems with the conventional instruction set selection method)
As described above, in the conventional instruction set selection method, the instruction set is selected by the T bit mounted in the program counter 1830. However, there is a problem that this method cannot be used in a processor having an instruction of 1 byte unit. In addition, the selection of the instruction set is determined only by the value of the program counter 1830 at the time of execution. Since the instruction set cannot be determined unless it is actually operated, for example, when the instruction sequence at address 0x1000 is viewed, which instruction set it is. It is difficult to make a decision, and debugging at the machine language level is difficult. For example, a branch instruction is described in 0x1001, and the least significant bit is set to 1 in a program described in the first instruction set by a programmer error. There is a problem that the operation cannot be guaranteed when branching at a branch address.

Further, in the method of selecting an instruction set by writing to the instruction set switching register mounted in the processor status register, like the VAX11 computer described as a conventional example in Japanese Patent Laid-Open No. 8-44557, the processor status Since an instruction to write to the register is required, there is a problem that an extra program is required, the program area is enlarged, and the performance of the processor is lowered by the writing process. In addition, since normal register writing is performed in a pipeline stage after instruction decoding, such as a write back stage, for example, decoding of a write instruction to the processor status register and actual processing to the processor status register are performed. Since a time difference occurs during writing, there is also a problem that switching of instruction sets cannot be performed at high speed.

(Third embodiment)
(Instruction format)
FIG. 11 shows an instruction format of the processor according to the third embodiment of the present invention.

  This processor has a fixed-length instruction format with 21 bits as a unit, as shown in FIG. The 64-bit instruction fetch unit includes three 21-bit instructions and 1-bit instruction cache control information. When the instruction cache control information is 0, the instruction included in the instruction fetch unit is not registered in the cache. When the instruction cache control information is 1, the instruction included in the instruction fetch unit is registered in the cache. FIG. 4B shows that when the instruction cache control information is 0, three instructions included in the instruction fetch unit are not registered in the instruction cache. FIG. 4C shows that the instruction cache control information is 1, and three instructions included in the instruction fetch unit are registered in the instruction cache.

(Processor hardware configuration)
FIG. 12 is a block diagram of a processor according to the third embodiment of the present invention.

Reference numeral 1210 denotes a memory system that stores an instruction sequence; 1250, an instruction cache device that controls a cache for the instruction sequence; 1252, an instruction cache control decoder that determines whether to register an instruction sequence in the instruction cache device 1250; Instruction cache, 1220 is an instruction supply issuing unit that obtains an instruction from the memory system 1210 or the instruction cache device 1250, 1221 is an instruction fetch control unit that controls instruction fetch, 1224 is an instruction register that stores an instruction to be decoded, and 1230 is general instruction decoding 1231 is an instruction issuance control unit that controls instruction decoding, 1232 is an instruction decoder that decodes instructions, 1240 is an instruction execution unit that executes instructions according to the decoding results, and 1241 is an instruction execution that controls instruction execution Control unit, 12
Reference numeral 42 denotes a PC control unit in charge of branching relationships, 1243 denotes an arithmetic unit, and 1245 denotes a register file for storing registers.

  The operation of the processor according to the third embodiment of the present invention configured as described above will be described below.

  When the instruction fetch address is issued from the instruction fetch control unit 1221, the instruction cache device 1250 checks whether the corresponding instruction is stored in the instruction cache 1253. If the instruction cache 1253 is not stored in the instruction cache 1253, the memory system The instruction fetch address is output to 1210 through the IA bus 1211.

  The memory system 1210 supplies the instruction sequence to the instruction cache device 1250 through the ID bus 1212.

  In the instruction cache device 1250, the instruction cache control decoder 1252 decodes the instruction cache control information in the instruction sequence. When the instruction cache control information is 1, the instruction cache control information is registered in the instruction cache 1253. When the instruction cache information is 0, Registration in the instruction cache 1253 is not performed.

  The instruction cache device 1250 supplies the instruction sequence stored in either the memory system 1210 or the instruction cache 1253 to the instruction supply issuing unit 1220 via the CD bus 1255.

  The instruction supply / issuance unit 1220 supplies an instruction string to the instruction register 1224 64 bits at a time in accordance with a request from the instruction decoding unit 1230. The instruction sequence stored in the instruction register 1224 is supplied to the instruction decoding unit 1230. In the instruction decoding unit 1230, the 64-bit instruction is converted into three 21-bit instructions and is decoded by the instruction decoder 1232.

  In the instruction execution unit 1240, the arithmetic unit 1243 performs an operation.

(Processor operation)
Next, the operation of this processor when a specific instruction is decoded and executed will be described.

  FIG. 13 shows an example of a program in the third embodiment of the present invention.

  Unlike a normal program flow such as an interrupt processing program, it is assumed that this program is not stored in the instruction cache when branching to this program.

  In this program example, the clr r1 instruction, mov imm, r4 instruction, mov r5, r0 instruction, mov (r0), r3 instruction, mul r3, r4 instruction, add r4, r1 instruction, sub imm, r0 instruction from address 0x1000, The cmp r1, r0 instruction, bne 0x1004 instruction, and rti instruction are arranged, and in this instruction sequence, the six instructions stored at the addresses 0x1004 and 0x1008 are repeatedly executed internally. This instruction is executed only once. For this reason, the instructions stored at the addresses 0x1004 and 0x1008 are more efficient when they are registered in the instruction cache, so the instruction cache control information is set to 1 and the other instruction cache information is set to 0.

  When a branch instruction to address 0x1000 is detected due to an interrupt or the like, the instruction execution control unit 1241 outputs a branch instruction to the PC control unit 1242. The PC control unit 1242 outputs a branch instruction to the instruction fetch control unit 1221 and outputs a branch address to the CA bus 1254.

Since these programs are not stored in the instruction cache 1253, the instruction cache device 1250 requests an instruction string from the memory system 1210 through the IA bus 1211. The memory system 1210 supplies the instruction sequence to the instruction cache device 1250 through the ID bus 1212.

  The instruction cache device 1250 supplies the instruction sequence to the instruction register 1224 in the instruction supply issue unit 1220 via the CD bus 1255. Further, the cache control decoder 1252 decodes the instruction cache control information in the instruction sequence, and does not register the instruction cache 1253 because the instruction cache control information is 0.

  The instruction decoder 1232 decodes the instruction in the instruction register 1224 21 bits at a time, as a clr r1 instruction, a mov imm, r4 instruction, a mov r5, r0 instruction, and the instruction execution unit 1240 performs an operation.

  Similarly, six instructions of addresses 0x1004 and 0x1008 are executed. Since the instruction cache control information is set to 1 for these instruction sequences, an instruction is fetched from the memory system 1210, and at the same time, the instruction cache device 1250 registers in the instruction cache 1253. As a result, mov (r0), r3 instruction, mul r3, r4 instruction, add r4, r1 instruction, sub imm, r0 instruction, cmp r1, r0 instruction, bne 0x1004 instruction are decoded and executed, and at the same time, to instruction cache 1253 Is registered.

  Next, when six instructions at addresses 0x1004 and 0x1008 are executed again, these instruction sequences are already stored in the instruction cache 1253, and therefore are executed at high speed without accessing the memory system 1210.

  Finally, when the rti instruction at address 0x100c is executed, the instruction sequence is acquired from the memory system 1210 and executed as in the case of executing the instruction at address 0x1000, but is not registered in the instruction cache 1253.

(Problems with conventional cache control methods)
VAX1 described as a conventional example in JP-A-8-44557
As in the case of one computer, in the method of controlling operations such as cache registration and reference by writing to the cache control register implemented in the processor status register, an instruction to write to the processor status register is required, so there is an extra program There is a problem that the program area is enlarged and the performance of the processor is lowered due to the writing process. In addition, normal register writing is performed in a pipeline stage after the decoding stage, such as a write back stage. Therefore, decoding of a write instruction to the processor status register and actual writing to the processor status register are performed. There is also a problem that the cache cannot be controlled at high speed because a time difference occurs between the two.

  Although the illustrated embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited only to these embodiments, and those skilled in the art will recognize the invention described in the claims. It should be understood that various modifications and changes can be made without departing from the spirit of the invention.

  Regarding the first embodiment, the instruction fetch width and the instruction length are defined in the present embodiment, but they are not particularly limited.

  The unit for storing the instruction position information is the instruction fetch width, but this unit is not particularly limited as long as it is a fixed interval or for each branch destination instruction. For example, the instruction fetch width or an integer of the instruction fetch width It may be double or an integer fraction of the instruction fetch width.

  In addition, the instruction position information does not necessarily exist in the unit. For example, the instruction position information exists only in the unit including the branch destination, exists only in the next unit of the unit including the branch destination, It may exist only in a unit including a memory access instruction.

In addition, the position information of the instruction is the position information of the instruction located at the lowest address in the unit. This position information indicates which part of the instruction the instruction at the lowest address in the unit is. It may also be information on the position of all the instructions included in the unit.

  Moreover, although the position information of the instruction is used for conversion from the variable word length instruction to the fixed length, there is no particular limitation on what the information is used for. For example, it may be pre-decoding processing for the purpose of load distribution of processing at the time of decoding, or may be used for branch prediction for predicting the branch destination of a branch instruction or for pre-speculative execution.

  The data handled by the source program storage means may be mnemonic, machine language, or a high-level language such as C language.

  In addition, the instruction extracting means extracts a fixed length for every three units, but the fixed length may be anything, and it is a function for extracting an instruction having a length corresponding to the interval of branch destination instruction words. It doesn't matter.

  Further, the instruction sequence storage means is not specifically limited. For example, a medium such as a floppy (registered trademark) disk, a hard disk, or an optical disk may be used.

  Regarding the second embodiment, the instruction fetch width and the instruction length are defined in the present embodiment, but they are not particularly limited.

  In addition, although the unit for storing the instruction set selection information is the instruction fetch width, this unit is not particularly limited as long as it is a fixed interval or for each branch destination instruction, for example, an instruction fetch width or an integer of the instruction fetch width. It may be double or an integer fraction of the instruction fetch width.

The instruction set selection information does not necessarily exist in the unit. For example, the instruction set selection information exists only in a unit including a branch destination, exists only in a unit next to a unit including a branch destination, or includes a branch instruction. Or a unit including a memory access instruction.

  In addition, the instruction set selection information is used to invalidate the microinstruction output from the decoder, but there is no particular limitation on what this information is used for. For example, it may be used for invalidation processing of an instruction sequence input to the decoder, or may be used for controlling the operation state of the decoder.

  In addition, although the instruction set is a fixed-length instruction, it is not limited thereto. For example, all of them may be variable length instructions or may be mixed. In the case of a variable-length instruction, it may be instruction set selection information in units in which the beginning or end of the instruction is stored.

  The data handled by the source program storage means may be mnemonic, machine language, or a high-level language such as C language.

  Further, the instruction extracting means has extracted a fixed-length instruction string for every three units. However, the fixed-length instruction string may be any length, and a variable-length instruction string corresponding to the interval between branch destination instruction words. It may be a function to extract.

  Further, the instruction sequence storage means is not specifically limited. For example, a medium such as a floppy (registered trademark) disk, a hard disk, or an optical disk may be used.

  Regarding the third embodiment, the instruction fetch width and the instruction length are defined in the present embodiment, but they are not particularly limited.

The unit for storing the cache control information is the instruction fetch width, but this unit is not particularly limited as long as it is a fixed interval or for each branch destination instruction. For example, the instruction fetch width or an integer multiple of the instruction fetch width Or, it may be 1 / integer of the instruction fetch width.

  The cache control information does not necessarily exist in the unit. For example, the cache control information exists only in the unit including the branch destination, exists only in the next unit after the unit including the branch destination, or stores the branch instruction. It may exist only in a unit including a memory access instruction.

  Further, the cache control information is used for the registration control of the instruction sequence to the instruction cache, but it may be the access control to the instruction cache, or the registration control to the data cache or the access control.

  In addition, although the instruction set is a fixed-length instruction, it is not limited thereto. For example, all of them may be variable length instructions or may be mixed. In the case of a variable-length instruction, it may be instruction set selection information in units in which the beginning or end of the instruction is stored.

  Further, the control information is not limited to cache control information. Specifically, it may be preceding instruction fetch control, interrupt control, or control information for the MMU. In the case of the preceding instruction fetch, it is temporary prohibition information of the preceding instruction fetch, software control of the number of bytes stored in the instruction buffer for temporarily storing the instruction fetched instruction sequence, or the preceding instruction fetch It may be the fetch bus width. In the case of interrupt control information, it may be interrupt prohibition information or interrupt prohibition level information. Further, a plurality of control information may be mixed instead of a single control information. When they are mixed, they may be mixed in the same unit, or may be in a format incorporating different control information for each unit.

  Further, the control information may be control information for the current unit, or may be control information for the next unit.

The figure which shows the instruction format of the processor in the 1st Embodiment of this invention, and the arrangement | sequence of the instruction sequence at the time of instruction fetch The block block diagram of the processor in the 1st Embodiment of this invention The block block diagram of the instruction supply issue part in the 1st Embodiment of this invention The figure which shows the output format of the fixed length instruction converter in the 1st Embodiment of this invention The figure which shows the program in the 1st Embodiment of this invention The figure which shows the fixed-length instruction which converted the program in the 1st Embodiment of this invention Explanatory drawing of operation | movement of the instruction sequence converter in the 1st Embodiment of this invention The figure which shows the instruction format of the processor in the 2nd Embodiment of this invention, and the arrangement | sequence of the instruction sequence at the time of instruction fetch The block block diagram of the processor in the 2nd Embodiment of this invention The figure which shows the program in the 2nd Embodiment of this invention The figure which shows the instruction format of the processor in the 3rd Embodiment of this invention, and the arrangement | sequence of the instruction sequence at the time of instruction fetch The block block diagram of the processor in the 3rd Embodiment of this invention The figure which shows the program in the 3rd Embodiment of this invention The block block diagram of the program generation apparatus in the 1st Embodiment of this invention The block block diagram of the program generator in the 2nd Embodiment of this invention The figure which shows the instruction format of the conventional processor, and the sequence of the instruction sequence at the time of instruction fetch Block diagram of a conventional processor Block diagram of the instruction supply and issue unit in a conventional processor Diagram showing a conventional program

Explanation of symbols

101 Instruction format information 102 Instruction head information 210 Memory system 220 Instruction supply issuing unit 221 Instruction fetch control unit 222 Fixed length instruction converter 223 Instruction buffer 224 Instruction register 230 Instruction decoding unit 231 Instruction issue control unit 232 Instruction decoder 233 1st Instruction Decoder 234 Second Instruction Decoder 240 Instruction Execution Unit 241 Instruction Execution Control Unit 242 PC Control Unit 243 First Operator 244 Second Operator 245 Register File 910 Memory System Storing Instruction Sequence 920 Instruction Fetched Instruction Instruction supply and issue unit 921 for storing instruction in the instruction register Instruction fetch control unit 924 for controlling instruction fetch 924 Instruction register for storing instruction to be decoded 930 Instruction decoding unit for general instruction decoding 931 Instruction issue control unit 93 for controlling instruction decoding Instruction Decoder 933a for Decoding Instruction 933a First Instruction Decoder 933b for Decoding Instruction Sequence Comprising Three 21-bit Instructions 933b Second Instruction Decoder for Decoding Instruction Sequence Consisting of One 63-Bit Instruction 935 MUX that selects the decoding result of any instruction decoder
936 An instruction set selector that determines an instruction set 940 An instruction execution unit that executes an instruction according to a decoding result 941 An instruction execution control unit that controls instruction execution 942 A PC control unit that takes charge of a branching relationship 943 An arithmetic unit 945 A register that stores a register File 1210 Memory system storing instruction sequence 1220 Instruction supply issuing unit for obtaining instruction from memory system 1210 or instruction cache device 1250 1221 Instruction fetch control unit for controlling instruction fetch 1224 Instruction register for storing instruction to be decoded 1230 Instruction decoding General instruction decoding unit 1231 Instruction issuing control unit for controlling instruction decoding 1232 Instruction decoding unit for decoding instructions 1240 Instruction execution unit for executing instructions according to the decoding result 1241 Instruction execution control unit for controlling instruction execution 1242 PC control unit in charge of branching relationship 1243 arithmetic unit 1245 register file for storing register 1250 instruction cache device 1252 for controlling cache for instruction sequence cache control decoder 1253 for determining whether instruction sequence is registered in instruction cache device 1250 Instruction cache

Claims (3)

A processor for executing a variable-length instruction composed of a plurality of units in parallel,
An instruction supply issuing unit that fetches an instruction with a fixed number of units as a fetch unit and outputs an instruction with the number of units that can be executed in parallel by the processor;
An instruction decoding unit for decoding an instruction output from the instruction supply issuing unit;
An instruction execution unit that executes an instruction according to a result of decoding by the instruction decoding unit;
The execution unit boundary is set independently of the fetch unit boundary, and
Whether the boundary of the fetch unit matches the boundary of the execution unit and the length of each variable-length instruction included in the execution unit are determined according to the values of a plurality of bits included in the fetch unit. A processor characterized by that. The instruction supply issuing unit, when one variable length instructions contained in the fetch unit is composed of a smaller number of units than the predetermined fixed number, by linking the meaningless data unit fetched, the 2. The processor according to claim 1, wherein the processor outputs the unit as a predetermined fixed number of units to the instruction decoding unit.   2. The processor according to claim 1, wherein the plurality of bits include a bit indicating information on a length of a variable-length instruction and a bit indicating whether or not the variable-length instruction is arranged across fetch units. .

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