JP4342989B2 - Differential transmission circuit - Google Patents

Description

  The present invention relates to a differential transmission circuit, and more particularly to a differential transmission circuit that can be used particularly preferably for driving a LAN of an automobile.

  A local area network (LAN) called CAN (Controller Area Network) or LIN (Local Interconnect Network) is used to transmit control signals for automobile engines and lamps and other accessory devices. ing. In particular, a CAN that transmits differential signals is used to transmit control signals for engines, brakes, steering, and the like that require high speed. Each electronic control unit (ECU) is connected by a cable (BUS line) via a transceiver, and the transceiver receives a signal from the BUS line and a driver circuit (differential transmission circuit) that transmits a signal toward the BUS line. And a receiver circuit. FIG. 3 is a circuit diagram showing a configuration of a conventional differential transmission circuit.

  The differential transmission circuit 100A includes a positive-polarity pulse output unit 10 having a Pch output transistor P2, a negative-polarity pulse output unit 20 having an Nch output transistor N5, and both signal transmission paths VH and VL during the recessive period. It consists of a resistance voltage dividing circuit 30 that holds two levels, and both signal output units 10 and 20 are driven by an input signal TX. In the dominant period in which the input signal TX is at the H level, in the positive pulse output unit 10, the switch SW1 is turned off and the switch SW2 is turned on, and the ground (low) from the gate electrode of the Pch transistor P2 via the constant current source I7. Electric charges are discharged toward the potential power source. As a result, in the dominant period, the Pch transistor P2 is turned on, charges one signal transmission path VH, and outputs a positive pulse. At the same time, in the negative polarity pulse output unit 20, the switch SW3 is turned on and the switch SW4 is turned off, and a charging current flows from the VDD power source (high potential power source) through the constant current source I8 toward the gate electrode of the Nch transistor N5. Therefore, the Nch transistor N5 is turned on. As a result, the other signal transmission line VL is discharged toward the ground, and a negative pulse is transmitted. The receivers (loads) connected to both signal transmission paths VH and VL are driven by the H level signal transmission path VH and the L level signal transmission path VL, and as a result, receive the input signal TX.

  On the other hand, in the recessive period when the input signal TX is at the L level, in the positive pulse output unit 10, the switch SW1 is turned on and the switch SW2 is turned off, and the gate of the Pch transistor P2 from the power supply VDD via the constant current source I6. A charging current flows through the electrode. As a result, the Pch transistor P2 is turned off. At the same time, in the negative polarity pulse output unit 20, the switch SW3 is turned off and the switch SW4 is turned on, and the charge is discharged from the gate electrode of the Nch transistor N5 to the ground via the constant current source I9, and the Nch transistor N5 is turned off. It becomes. When both transistors P2 and N5 are turned off, both signal transmission lines VH and VL are shifted to the potential of VDD / 2 level by the action of the resistance voltage dividing circuit 30, and to the H level of the next input signal TX. Wait for the transition.

  In the differential transmission circuit 100A, the constant current sources I6 to I9 are used to charge and discharge the gate electrodes of the Pch and Nch transistors P2 and N5 so that the rising speed and the falling speed of both gate potentials are equal. The gate potential slew rate is controlled. This is to reduce radiation noise radiated from the signal transmission path toward the periphery by symmetrically increasing and decreasing the potentials of the signal transmission paths VH and VL.

  However, only by controlling the slew rate of the gate potential of the transistor, it is difficult to shift the symmetric signal potential of the signal transmission path, and it is not possible to effectively reduce the radiation noise from the signal transmission path. This will be described with reference to FIG. FIG. 4A shows an ideal signal voltage at the time of signal transition in the signal transmission line, and FIGS. 4B and 4C are respectively shown in A part and B part of FIG. 4A. It shows the situation of asymmetry that actually occurs during signal transition.

  As shown in FIG. 4A, when the input signal TX is “0”, the signal potentials VH and VL of both signal transmission paths are both held at VDD / 2. When the input signal TX becomes “1”, the signal potential VH rises from the VDD / 2 level and shifts to a predetermined H level somewhat lower than the VDD level, and the signal potential VL falls from the VDD / 2 level, It shifts to a predetermined L level that is somewhat higher than the ground level. When the input signal TX shifts to “0” again, the signal potential VH shifts from the H level to the VDD / 2 level, and the signal potential VL shifts from the L level to the VDD / 2 level.

FIG. 4B shows details of the asymmetry of the signal transition in the part A shown in FIG. 4A when the input signal TX shifts from “0” to “1”. The asymmetric state occurs in the following cases as shown in these figures.
(I) When the transistor P2 is turned on before the transistor N5 (II) When the slew rate of the signal potential VH is faster than the slew rate of the signal potential VL (III) When the transistor P2 is turned on later than the transistor N5 (IV) When the slew rate of the signal potential VH is slower than the slew rate of the signal potential VL

FIG. 4C shows details of the asymmetry of the signal transition in the B part shown in FIG. 4A when the input signal TX shifts from “1” to “0”. The asymmetric state occurs in the following cases as shown in these figures.
(V) When the transistor P2 is turned off later than the transistor N5 (VI) When the slew rate of the signal potential VH is faster than the slew rate of the signal potential VL (VII) When the transistor P2 is turned off before the transistor N5 (VIII) When the slew rate of the signal potential VH is lower than the slew rate of the signal potential VL

  The above asymmetry is often caused by differences in conductivity types between the two transistors, manufacturing variations, and the like. Moreover, even if the characteristics of both transistors can be matched so that the signal symmetry can be obtained under specific conditions, the characteristics of both transistors can be changed under conditions other than the specific conditions due to differences in temperature characteristics of both transistors. It is impossible to make them completely coincide with each other, and the above asymmetry is inevitable. When an asymmetric signal voltage is generated, the currents flowing in both signal transmission paths are not completely in reverse phase, and in-phase current components (common mode currents) flow in both signal transmission paths, generating radiated noise. Let

Patent Document 1 describes a technique for reducing the radiation noise for a differential output buffer in which both signal transmission lines operate in opposite phases. In this patent document, when one signal transmission path shifts from the H level to the L level and at the same time the other signal transmission path shifts from the L level to the H level, both signal transmission paths have the same potential. Focuses on the existence of points. The cross-point voltage is compared with a reference voltage, and the phase at which both coincide with each other is adjusted to adjust the signal timing of both signal transmission paths.
JP 2001-177391 A

  According to the configuration of the differential output buffer described in the above-mentioned patent document, a configuration is adopted in which the cross-point voltage of both signal transmission paths is compared with the reference voltage, so that the signal change in both signal transmission paths is the total signal change. The signal for adjusting the timing is obtained only when it becomes about ½ of. Therefore, at the initial rise time or fall time of the signal change shown in FIG. 4, the asymmetry of the signal voltage cannot be eliminated, and as a result of the common mode current flowing, the resulting radiation noise reduction effect is not sufficient.

  An object of the present invention is to improve a conventional differential transmission circuit that transmits a differential signal, and in particular to provide a differential transmission circuit that can effectively reduce radiation noise that occurs when a differential signal changes. To do.

In order to achieve the above object, a differential transmission circuit according to a first aspect of the present invention includes a first conductive type transistor and a second conductive type transistor that drive the first and second transmission lines, respectively.
A first conductivity type transistor that selectively charges the gate electrode of the first conductivity type transistor from a high potential power source or discharges the gate electrode of the first conductivity type transistor to a low potential power source in response to one of the complementary signals A control unit;
Selectively discharging from the gate electrode of the second conductivity type transistor to the low potential power source or charging the gate electrode of the second conductivity type transistor from the high potential power source in response to the other of the complementary signals; A conductive transistor control unit;
A difference signal detection unit that detects a difference value between a change amount of the potential of the first signal transmission path and a change amount of the potential of the second signal transmission path and outputs the difference value;
Each of the first conductivity type transistor control unit and the second conductivity type transistor control unit calculates the current value when discharging from the gate electrode of the corresponding first conductivity type or second conductivity type transistor to the low potential power source. And a feedback control unit that performs feedback control so as to be determined based on the signal.

A differential transmission circuit according to a second aspect of the present invention includes a first conductivity type and a second conductivity type transistor for driving the first and second transmission lines,
A first conductivity type transistor that selectively charges the gate electrode of the first conductivity type transistor from a high potential power source or discharges the gate electrode of the first conductivity type transistor to a low potential power source in response to one of the complementary signals A control unit;
Selectively discharging from the gate electrode of the second conductivity type transistor to the low potential power source or charging the gate electrode of the second conductivity type transistor from the high potential power source in response to the other of the complementary signals; A conductive transistor control unit;
A difference signal detection unit that detects a difference value between a change amount of the potential of the first signal transmission path and a change amount of the potential of the second signal transmission path and outputs the difference value;
Each of the first conductivity type transistor control unit and the second conductivity type transistor control unit calculates a current value when the gate electrode of the corresponding first conductivity type or second conductivity type transistor is charged from the high potential power source by the difference. And a feedback control unit that performs feedback control so as to be determined based on the signal.

According to the differential transmission circuit according to the first and second aspect of the present invention, detects a difference value of the amount of change in the potential of both signal transmission paths, the detected difference value first conductivity type (e.g., Pch) and a second conductivity type (for example, Nch) transistor are fed back to control the charging current or discharging current of the gate electrode, and are generated between the rise time and fall time of both signal transmission paths. Since the asymmetry can be compensated for, good signal symmetry can be obtained and the common mode current can be effectively suppressed. As a result, the radiated noise from the signal transmission path is effectively reduced.

  In a preferred aspect of the present invention, each of the first conductivity type transistor control unit and the second conductivity type transistor control unit charges the gate electrode of the corresponding first conductivity type or second conductivity type transistor from the high potential power source. The current value when discharging from these gate electrodes to the low potential power source is made constant. By keeping the charge or discharge current of the gate electrode of the transistor on the side where slew rate control is not performed constant, the slew rate of signal change in the signal transmission path can be kept stable.

  The feedback control unit includes a constant current source that defines a constant current, a difference current generation unit that generates a difference current between the constant current and a signal current proportional to the difference value, and is proportional to the difference current. A current mirror circuit for defining a discharge current for turning back the current from the gate electrodes of the first conductivity type and second conductivity type transistors to the low potential power source or a charging current for charging the gate electrodes from the high potential power source; It is also a preferred embodiment of the present invention. The above functions can be obtained with a simple configuration.

  The present invention can be applied particularly suitably for the improvement of the conventional differential transmission circuit shown in FIG. 3 that outputs positive and negative pulses, for example. The present invention can also be applied to a differential transmission circuit used for driving a signal transmission path that transmits a signal in a complementary signal mode.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a configuration of a differential transmission circuit according to an embodiment of the present invention. The differential transmission circuit 100 includes a positive pulse output unit 10 that generates a positive pulse during a dominant period when the input signal TX is at an H level, and a negative pulse output unit 20 that generates a negative pulse during a dominant period. And a resistance voltage dividing circuit 30 having resistors R3 and R4 (R3 = R4) and holding both signal transmission lines VH and VL at a potential of VDD / 2 in a recessive period, and both signal output units 10 and 20 are generated. And a slew rate control circuit (feedback control unit) 40 for controlling the slew rate of the positive polarity pulse and the negative polarity pulse based on the difference in absolute value of the signal voltage to be transmitted. The differential transmission drive circuit 100 supplies a differential signal to a receiver (load) RC of another device via a pair of signal transmission paths VH and VL.

  The positive pulse output unit 10 includes a Pch output transistor P2, selection switches SW1 and SW2 responding to the input signal TX, and a constant current that is selected by the switch SW1 during the recessive period and charges the gate electrode of the Pch output transistor P2 from the VDD power source. A source I6 and an Nch transistor N3 that is selected by the switch SW2 during the dominant period and discharges from the gate electrode of the Pch output transistor P2 toward the ground. A diode D1 is inserted between the drain of the Pch output transistor P2 and the signal transmission path VH.

  The negative pulse output unit 20 includes an Nch output transistor N5, selection switches SW3 and SW4 that respond to the input signal TX, and an Nch transistor that is selected by the switch SW4 during the recessive period and discharges from the gate electrode of the Nch output transistor N5 to the ground. N4 and a constant current source I8 that is selected by the switch SW3 during the dominant period and charges the gate electrode of the Nch transistor N5 from the VDD power supply. A diode D2 is inserted between the drain of the Nch output transistor N5 and the signal transmission path VL.

The slew rate control circuit 40 detects a difference value between the change amount of the potential of the signal transmission path VH and the change amount of the potential of the signal transmission path VL, and outputs a difference signal detection unit 41 that outputs the difference value as a current signal I3. The sum current I5 of the current signal I3 input from the signal detection unit 41 and the constant current I4 is used as a reference-side current, which is turned back and given to the positive-polarity pulse output unit 10 and the negative-polarity pulse output unit 20 as an output-side current. And a mirror circuit 42. The differential signal detector 41 includes an operational amplifier (voltage follower) 43 that receives a signal potential (VH) from the signal transmission path VH, a Pch transistor P1 whose gate electrode is controlled by the output of the operational amplifier 43, and a signal from the signal transmission path VL. An operational amplifier 44 for inputting a potential (VL) and an Nch transistor N1 whose gate electrode is controlled by the output of the operational amplifier 44 are provided. The source of the Pch transistor P1 is connected to the VDD power supply via the resistor R1, the source of the Nch transistor N1 is connected to the ground via the resistor R2, and the drains of both transistors P1 and N1 are connected to each other. The resistance value of the resistor R1 is equal to the resistance value of the resistor R2.

  The current mirror circuit 42 includes a reference-side transistor N2 through which a reference-side current I5 flows, and the Nch transistor N3 of the positive polarity pulse output unit 10 and the Nch transistor N4 of the negative polarity pulse output unit 20 return the reference-side current. It is a transistor. The current ratio between the transistors N2 and N3 is 1: A, and the current ratio between the transistors N2 and N4 is 1: B. For example, A = B = 1 may be set.

With the above configuration, the current values I1 to I5 of each part are as follows.
I1 = (VDD−VH) / R1
I2 = VL / R2
I3 = I1-I2
I4 = constant I5 = I3 + I4
Therefore, the currents I7 and I9 of the Nch transistors N3 and N4 constituting the output side transistor of the current mirror circuit 42 are
I7 = A × I5
I9 = B × I5
It is expressed as

  The differential transmission circuit 100 of the present embodiment operates as follows. In the dominant period in which the input signal TX is at the H level, in the positive pulse output unit 10, the switch SW1 is turned off and the switch SW2 is turned on, and the current flows from the gate electrode of the Pch transistor P2 to the ground via the transistor N3. I7 flows. As a result, the Pch transistor P2 is turned on, one of the signal transmission lines VH is charged, and the signal transmission line VH becomes H level. At the same time, in the negative polarity pulse output unit 20, the switch SW3 is turned on and the switch SW4 is turned off, and the charging current flows toward the gate electrode of the Nch transistor N5 via the constant current source I8. Therefore, the Nch transistor N5 is turned on. Become. As a result, electric charges are discharged from the other signal transmission path VL, and the signal transmission path VL becomes L level. A receiver (load) RC having both ends connected to both signal transmission paths VH and VL is driven by an H level signal transmission path VH and an L level signal transmission path VL, and as a result, receives an input signal TX. To do.

  On the other hand, in the recessive period when the input signal TX is at the L level, in the positive pulse output unit 10, the switch SW1 is turned on and the switch SW2 is turned off, and the gate of the Pch transistor P2 from the power supply VDD via the constant current source I6. A charging current flows toward the electrode. As a result, the Pch transistor P2 is turned off. At the same time, in the negative polarity pulse output unit 20, the switch SW3 is turned off and the switch SW4 is turned on, the current I9 flows from the gate electrode of the Nch transistor N5 to the ground via the transistor N4, and the Nch transistor N5 is turned off. . When both transistors P2 and N5 are turned off, the signal transmission lines VH and VL shift to the potential of the VDD / 2 level by the action of the resistance voltage dividing circuit 30, and the next dominant period, that is, the input signal Wait for TX to transition to H level.

  FIG. 2 shows signal voltage waveforms of the signal transmission lines VH and VL in each case where the relationship between the timing and the driving capability is different between the transistors P2 and N5. FIG. 5A shows a case where there is no difference in timing and drive capability between the transistors P2 and N5, and the signal voltage transition is ideally performed, and the other figures show between the transistors P2 and N5. There is a difference in timing or driving capability, and asymmetry (unbalance) occurs in the signal potentials VH and VL of the signal transmission path. Specifically, FIG. 5B shows a case where the transistor P2 is turned on and off earlier than the transistor N5, and FIG. 8C shows a case where the transistor N5 is turned on and off earlier than the transistor P2. d) shows a case where the positive pulse has a larger slew rate than the negative pulse, and FIG. 9 (e) shows a case where the negative pulse has a larger slew rate than the positive pulse. Numbers I to VIII shown in each figure correspond to each case shown in FIG. Such asymmetry of the potentials VH and VL of the signal transmission path generates radiated noise caused by the common mode current. Therefore, in the differential transmission driver circuit of this embodiment, the asymmetry is excluded. Yes.

図２（ａ）に示した理想的な状態では、電位ＶＨと電位ＶＬとが、
ＶＨ−（０．５×ＶＤＤ）＝（０．５×ＶＤＤ−ＶＬ
となり、ＶＤＤ／２を中心として対称性を持つ。つまり、表１の最上段に示すように、双方の信号伝送路間の不平衡電圧：
｛（ＶＨ−（０．５×ＶＤＤ））−｛（０．５×ＶＤＤ−ＶＬ）｝
が零になるので、電流Ｉ１と電流Ｉ２とが均衡し、電流Ｉ３が零になる。従って、Ｉ４＝Ｉ５となる。ここで、レセシブ期間からドミナント期間に移行する際には、Ｉ７＝Ａ×Ｉ４の一定電流でトランジスタＰ２のゲート電極からグランドに向けて電荷が放電し、トランジスタＮ５のゲート電極は定電流Ｉ８で充電される。また、レセシブ期間からドミナント期間に移行する際には、トランジスタＰ２のゲート電極の電荷は定電流Ｉ７で放電し、トランジスタＮ５のゲート電極は、Ｉ９＝Ｂ×Ｉ４の定電流で充電される。その結果、双方の信号伝送路の電位ＶＨ、ＶＬは、対称性が保たれる。 Table 1 shows the differential transmission driver circuit according to the present embodiment for each of the transition from the dominant period to the recessive period and the transition from the recessive period to the dominant period in each case shown in FIG. It shows the action. The numbers I to VIII shown in the state column in Table 1 correspond to the numbers appended to each figure of FIG.

In the ideal state shown in FIG. 2A, the potential VH and the potential VL are
VH− (0.5 × VDD) = (0.5 × VDD−VL)
And has symmetry about VDD / 2. That is, as shown at the top of Table 1, the unbalanced voltage between both signal transmission paths:
{(VH− (0.5 × VDD)) − {(0.5 × VDD−VL)}
Becomes zero, current I1 and current I2 are balanced, and current I3 becomes zero. Therefore, I4 = I5. Here, when shifting from the recessive period to the dominant period, the charge is discharged from the gate electrode of the transistor P2 to the ground with a constant current of I7 = A × I4, and the gate electrode of the transistor N5 is charged with the constant current I8. Is done. Further, when shifting from the recessive period to the dominant period, the charge of the gate electrode of the transistor P2 is discharged with a constant current I7, and the gate electrode of the transistor N5 is charged with a constant current of I9 = B × I4. As a result, the potentials VH and VL of both signal transmission paths are kept symmetrical.

  When the transistor P2 is turned on before N5 as shown in FIG. 2B (I), and the rising slew rate (SR) of the signal potential VH is equal to the signal potential VL as shown in FIG. (II), the unbalanced voltage becomes positive, the current I1 flowing through the transistor P1 decreases, and the current I3 becomes negative. Therefore, the reference side current I5 of the current mirror 42 is negative. Decrease. As a result, the current I7 flowing through the transistor N3 decreases, so that the potential drop of the gate electrode of the transistor P2 is suppressed, the on-state of the transistor P2 is delayed, and the slew rate of the positive pulse transmission path is delayed. Accordingly, the waveforms shown in FIGS. 2B and 2D approach the waveform shown in FIG.

  When the transistor P2 is turned on later than N5 (III) and when the signal potential VH has a slower slew rate than the signal potential VL (IV), as shown in Table 1, similarly, the current I5 Increases, and the current I7 flowing through the transistor P2 increases, so that the transistor P2 is turned on faster and the slew rate of the signal potential VH is increased. Similarly, when the transistor N5 is turned off before P2 (V) and the rising slew rate of the signal potential VL is faster than the falling slew rate of the signal potential VH (VI), the current I5 Decreases, and the current I9 flowing through the transistor N5 decreases. Therefore, the transistor N5 is delayed to be turned off, and the rising slew rate of the signal potential VL is delayed. When the transistor N5 is turned off later than P2 (VII) and when the rising slew rate of the signal potential VL is slower than the falling slew rate of the signal potential VH (VIII), the current I5 increases and the transistor Since the current I9 flowing through N5 increases, the transistor N5 is quickly turned off, and the rising slew rate of the signal potential VL is increased. In this way, in the differential transmission circuit according to the present embodiment, the asymmetry generated at the transition of both signals is alleviated, so the signal waveforms shown in FIGS. The signal waveform approaches the signal waveform shown in FIG. As a result, the symmetry of both signal voltages is improved, the currents flowing through both signal transmission paths are in opposite phases, and the magnetic field changes caused by the current changes in both signal transmission paths are canceled out, so that the radiated noise is reduced. Can be reduced.

  In the above-described embodiment, the configuration in which the charging current of the gate electrodes of the Pch transistor and the Nch transistor is made constant and the discharge current is feedback controlled by the potential difference between both signal transmission paths has been exemplified. In addition, it is possible to adopt a configuration in which the charging current is feedback-controlled. In this case, the current mirror circuit may control the charging current as it is with a current proportional to the difference between the two signals.

  In the above-described embodiment, an example in which the present invention is applied to a differential transmission circuit that outputs a positive pulse and a negative pulse is shown. However, the present invention is also applicable to a differential transmission circuit that transmits a differential signal to a signal transmission path that transmits a signal in the form of a complementary signal.

  Although the present invention has been described based on the preferred embodiment thereof, the differential transmission circuit of the present invention is not limited to the configuration of the above embodiment example. Those modified and changed as described above are also included in the scope of the present invention.

1 is a circuit diagram of a differential transmission circuit according to an embodiment of the present invention. 4 is a timing chart showing each case of signal asymmetry in the differential transmission circuit of FIG. 1. The circuit diagram of the conventional differential transmission circuit. 9 is a timing chart showing signal asymmetry in a conventional differential transmission circuit.

Explanation of symbols

100: differential transmission circuit 10: positive polarity pulse output unit 20: negative polarity pulse output unit 30: resistance voltage dividing circuit 40: slew rate control circuit (feedback control unit)
41: differential signal detector 42: current mirror circuit 43, 44: operational amplifier P1, P2: Pch transistors N1 to N5: Nch transistors R1 to R4: resistors D1, D2: diode TX: input signals I4, I6, I8: constant current I1 to I5, I7, I9: Current VH: Signal transmission line (Signal transmission line signal)
VL: signal transmission line (signal transmission line signal)

Claims (7)

A first conductivity type and a second conductivity type transistor for driving the first and second transmission lines, respectively;
A first conductivity type transistor that selectively charges the gate electrode of the first conductivity type transistor from a high potential power source or discharges the gate electrode of the first conductivity type transistor to a low potential power source in response to one of the complementary signals A control unit;
Selectively discharging from the gate electrode of the second conductivity type transistor to the low potential power source or charging the gate electrode of the second conductivity type transistor from the high potential power source in response to the other of the complementary signals; A conductive transistor control unit;
A difference signal detection unit that detects a difference value between a change amount of the potential of the first signal transmission path and a change amount of the potential of the second signal transmission path and outputs the difference value;
Each of the first conductivity type transistor control unit and the second conductivity type transistor control unit calculates the current value when discharging from the gate electrode of the corresponding first conductivity type or second conductivity type transistor to the low potential power source. A differential transmission circuit comprising: a feedback control unit that performs feedback control so as to be determined based on a signal.   Each of the first conductivity type transistor control unit and the second conductivity type transistor control unit has a constant current value when charging the gate electrode of the corresponding first conductivity type or second conductivity type transistor from the high potential power source. The differential transmission circuit according to claim 1, wherein:   The feedback control unit includes a constant current source that defines a constant current, a difference current generation unit that generates a difference current between the constant current and a signal current that is proportional to the difference value, and a current that is proportional to the difference current. The differential transmission circuit according to claim 1, further comprising: a current mirror circuit that regulates a current discharged from the gate electrodes of the first conductivity type and second conductivity type transistors to the low potential power source. A first conductivity type and a second conductivity type transistor for driving the first and second transmission lines, respectively;
A first conductivity type transistor that selectively charges the gate electrode of the first conductivity type transistor from a high potential power source or discharges the gate electrode of the first conductivity type transistor to a low potential power source in response to one of the complementary signals A control unit;
Selectively discharging from the gate electrode of the second conductivity type transistor to the low potential power source or charging the gate electrode of the second conductivity type transistor from the high potential power source in response to the other of the complementary signals; A conductive transistor control unit;
A difference signal detection unit that detects a difference value between a change amount of the potential of the first signal transmission path and a change amount of the potential of the second signal transmission path and outputs the difference value;
Each of the first conductivity type transistor control unit and the second conductivity type transistor control unit calculates a current value when the gate electrode of the corresponding first conductivity type or second conductivity type transistor is charged from the high potential power source as the difference. A differential transmission circuit comprising: a feedback control unit that performs feedback control so as to be determined based on a signal.   Each of the first conductivity type transistor control unit and the second conductivity type transistor control unit has a constant current value when discharging from the gate electrode of the corresponding first conductivity type or second conductivity type transistor to the low potential power source. The differential transmission circuit according to claim 4, wherein:   The feedback control unit includes a constant current source that defines a constant current, a difference current generation unit that generates a difference current between the constant current and a signal current that is proportional to the difference value, and a current that is proportional to the difference current. 6. The differential transmission circuit according to claim 4, further comprising: a current mirror circuit that regulates a current charged from the high potential power source at a gate electrode of each of the first conductivity type and second conductivity type transistors.   The differential transmission circuit according to claim 1, wherein the first conductivity type transistor and the second conductivity type transistor output a positive polarity pulse and a negative polarity pulse, respectively.

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