JP4339323B2 - Switching circuit, switching module, and switching circuit control method - Google Patents

Description

The present invention relates to a switching circuit , a switching module, and a switching circuit control method .

A circuit configuration of a semiconductor switch 100 according to the prior art is shown in FIG. As shown in FIG. 1, a conventional semiconductor switch 100, an input signal is a radio frequency signal inputted to the input terminal T _in, selectively outputted from one of a plurality of output terminals (T _out1, T _out2) It has a configuration. FIG. 1 shows a configuration of a semiconductor switch 100 of SPDT (Single Pole Double Throw).

  Such a semiconductor switch 100 is used, for example, in a configuration in which an antenna is shared by a transmitting circuit and a receiving circuit, to cut off that one circuit is connected to the antenna while the other circuit is using the antenna. Is done.

  Here, since the source voltage Vs of the switching transistor (Tr1 / Tr2) in the non-selected state is determined by the potential supplied via the source from the gate of the switching transistor (Tr2 / Tr1) in the selected state. In the switching transistor (Tr1 / Tr2) in the selected state, a bias potential difference is generated between the gate and the source, and this is turned off (OFF state).

However, when all the output terminals (T _out1 , T _out2 ) are cut off in the above configuration, the source voltage Vs cannot be set to a predetermined level because there is no switching transistor in the selected state. For this reason, there exists a problem that each switching transistor cannot be cut off sufficiently.

  In the prior art, there is a switch circuit 200 having a configuration in which the bias voltage Vba is fixedly supplied in order to set the gate-source potential difference of the switching transistors (Tr1, Tr2) to a predetermined level. The configuration of the switch circuit 200 is shown in FIG. Moreover, the technique which achieves the same objective is disclosed by patent document 1 shown below, for example.

JP 2000-223902 A

  However, these conventional techniques are techniques for setting the source voltage Vs of the switching transistor in the non-selected state to a predetermined level when any of the switching transistors is in the selected state. For this reason, it is impossible to solve the problem that the switching transistors cannot be cut off when all the switching transistors are in the non-selected state.

Therefore, an object of the present invention is to provide a switching circuit , a switching module, and a switching circuit control method that can surely cut off all the switching transistors when they are in a non-selected state.

The present invention, as claimed in claim 1, and a plurality of switching transistors having a source or drain connected in common to either the input terminal or an output terminal, a source or drain of said plurality of switching transistors A control bias supply circuit for supplying a control bias , wherein the control bias supply circuit operates by receiving a voltage signal applied from the outside, and includes a diode connected in a forward direction to the voltage signal. consists comprise only when all of the switching transistors by the selection control signal input from the outside to the gate of the switching transistor is in a non-selected state, between the gate and the source or drain of all of the plurality of switching transistors The control via so that the Wherein the control bias is supplied from the supply circuit, when at least one of said switching transistors are selected, the control bias from the control bias supply circuit is not supplied. Thereby, when any switching transistor is in the selected state, it is possible to prevent the current from the gate of the switching transistor in the selected state from flowing backward to the control bias supply circuit side.

Further, in the switching circuit, for example, as in claim 2 , any one of the input terminal and the output terminal is a plurality, and each of the plurality of switching transistors is connected to the one of the plurality of the input terminals and the output terminals. Any one of the source and drain is connected, the other one of the source and drain is connected to the other of the input terminal and the output terminal at a common connection point, and the bias supply circuit is biased to the common connection point. supplies may be configured that the resistance is connected between ground and the common connection point.

As another example, the switching circuit includes a bias transistor in which the diode includes a MES field effect transistor, as in claim 3 , and the control bias is a gate of the bias transistor. It can also be configured to be supplied based on a voltage signal applied to the.

Further, the switching circuits are preferably as claimed in claim 4, wherein said bias either one of the source and the drain of the transistor is connected to the common connection point to said plurality of switching transistors, the other one is capacitive It has a configuration that is connected to a ground potential via an element. Thereby, the isolation between the input side and the output side is enhanced, and the cutoff of the switching transistor is ensured.

In addition, the control bias supply circuit in the switching circuit may be configured to change the voltage value of the control bias, for example, as in claim 5 . Thereby, since a desired control bias can be applied according to a predetermined event, the controllability of the switching circuit is improved.

As another example, the switching circuit may be configured so that the control bias supply circuit selectively supplies any one of a plurality of control biases, for example, as in claim 6. it can.

As another example, the switching circuit may be configured such that the control bias supply circuit sets the voltage value of the control bias when all of the plurality of switching transistors are in a non-selected state, as in claim 7. It can also be configured to be variable.

As another example, the switching circuit, for example as in claim 8, wherein the control bias supply circuit, and when at least one of said plurality of switching transistors are selected, the plurality of switching transistors It is also possible to supply the control bias having a voltage value different from that in the case where all of these are not selected.

Further, the switching circuit, for example, as according to claim 9, it can also be applied when it is connected in common to the input terminal or the output terminal the comprising switching transistors at least three.

Further, the switching circuits are preferably as claimed in claim 10, having a shunt transistor connected to the source of the switching transistor, the gate of the shunt transistor, the switching transistor that do not correspond with the shunt transistor A voltage signal applied to the gate may be applied. As a result, the input side and the output side can be sufficiently isolated, and the switching transistor in the non-selected state can be reliably cut off.

Further, the switching circuits are preferably as claimed in claim 11, wherein said switching transistor is formed in the MES field-effect transistor.

The above-mentioned switching transistor, preferably as claimed in claim 12, wherein the common connection point to said plurality of switching transistors have a structure which is grounded through a resistor. Thereby, the high frequency component of the signal applied to the input side can be attenuated.

Further, the switching circuits are preferably as claimed in claim 13, wherein, between the source and the drain of the switching transistor has a connected through a ballast resistor.

A switching module according to the present invention, as described in claim 14 , is a voltage signal and / or a selection control signal for operating the switching circuit by decoding the data signal input from the switching circuit and the outside. And a decoding circuit for generating. Thereby, when all the switching transistors are in a non-selected state, a switching module can be provided in which a switching circuit capable of reliably cutting off these transistors is mounted.

In addition, the switching module preferably as claimed in claim 15, having the structure and the switching circuit and the decoding circuit is formed by a single chip. Thereby, the switching module which can complete | finish and implement | achieve switching operation by 1 chip | tip can be provided.

As described above, according to the present invention, when all the switching transistors are in a non-selected state, a switching circuit and a switching circuit control method that can reliably cut off the switching transistors are realized. Further, the present invention prevents the potential from the gate of the switching transistor not in the selected state from flowing back to the control bias supply circuit when any of the switching transistors is in the selected state. In addition, the present invention improves the controllability of the switching circuit by applying a desired control bias according to a predetermined event. Furthermore, a switching module equipped with this switching circuit is provided.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
First, a first embodiment of the present invention will be described. In the switching circuit having a plurality of switching transistors commonly connected to either the input terminal or the output terminal, the basic concept of this embodiment is selectively when all the switching transistors are in a non-selected state, A control bias for supplying these to a cut-off state is supplied. Thereby, in this embodiment, the switching transistor in the non-selected state can be sufficiently and surely turned off (OFF state). When any one of the switching transistors is in a selected state, the control bias is not supplied because the potential is supplied to the source of the other non-selected switching transistor through the selected switching transistor. This is effective in reducing power consumption.

  Hereinafter, the configuration and operation of the present embodiment will be described in detail with reference to the drawings. FIG. 3 is a circuit diagram showing a configuration of the switching circuit 1 according to the present embodiment.

  As shown in FIG. 3, the switching circuit 1 has a configuration of an SPDT switch having one input and two outputs having two switching transistors Tr1 and Tr2. Note that the switching transistors Tr1 and Tr2 are configured by MES type field effect transistors (MESFETs) formed of, for example, gallium arsenide (GaAs). However, you may comprise this with a HEMT type field effect transistor (High Electron Mobility Transistor: HEMTFET).

  In such a configuration, the switching transistor Tr1 has the gate to which the selection control signal V1 is applied via the resistor R1 for attenuating the high-frequency signal propagated from the input terminal Tin, and the drain blocks the DC component DC of the high-frequency signal. Is connected to the output terminal Tout1 via a capacitor C1 which is a capacitive element for performing the operation, and the source is connected to the input terminal Tin via a capacitor C3 for blocking the DC component DC of the high frequency signal. Similarly, the switching transistor Tr2 is applied with the selection control signal V2 through the resistor R2 for attenuating the high frequency signal propagated from the input terminal Tin to the gate, and the drain blocks the DC component DC of the high frequency signal. Is connected to the output terminal Tout2 through a capacitor C2, which is a capacitive element, and the source is connected to the input terminal Tin through a capacitor C3 for blocking the DC component DC of the high-frequency signal. For example, a high frequency signal received by an antenna is input to the input terminal Tin. Capacitors C1, C2, and C3 for blocking the DC component DC of the high-frequency signal input from the antenna may be included in the internal configuration of the switching circuit 1 or in other configurations. In the following description, the case where it is included in another configuration will be taken as an example.

  The source and drain of the switching transistors Tr1 and Tr2 are connected by ballast resistors R3 and R4, respectively. This ballast resistor is provided to make the potential between the source and drain of the switching transistor common (substantially eliminate the potential difference). In the present embodiment, resistors of about 10 kΩ are used for the ballast resistors R3 and R4.

  In the above configuration, the sources of the switching transistors Tr1 and Tr2 are connected to the capacitor C3 through a common connection point Ps. Further, this connection point Ps is grounded via a resistor Rs. Further, the connection point Ps is connected to the control bias supply circuit 10, and the control bias is supplied to the sources of the switching transistors Tr1 and Tr2 via this connection point Ps.

  Here, the configuration of the control bias supply circuit 10 according to the present embodiment will be described. As shown in FIG. 3, the control bias supply circuit 10 has a configuration in which a diode D11 is provided in series between two resistors R11 and R12, and a voltage signal V10 for generating a control bias therein. Is applied. The diode D11 is connected to conduct in the forward direction with respect to the application direction of the voltage signal V10.

In this way, the diode D11 connected in the forward direction with respect to the bias direction is interposed in the control bias supply circuit 10 that selectively supplies the control bias when all the switching transistors Tr1 and Tr2 are in the non-selected state. Thus, when any output (switching transistor) is in the selected state, it is possible to prevent the current from the gate of the switching transistor not in the selected state from flowing backward to the control bias supply circuit 10 side.

  The voltage signal V10 applied to the control bias supply circuit 10 is generated by decoding a data signal input from an external CPU or the like by a decoder (see FIG. 4) 11 provided outside the switching circuit 1. Here, the data signal is data composed of, for example, 2 bits (however, in the case of an SPDT switch), and any one of the switching transistors Tr1 and Tr2 is selected (= any output is obtained) or all This signal includes data indicating that the switching transistors Tr1 and Tr2 are not selected (= a control bias is supplied). That is, when the data signal indicates that all the switching transistors Tr1 and Tr2 are in a non-selected state (= supplied with a control bias), the decoder 11 decodes this and outputs a voltage signal V10 having a predetermined voltage value. Is applied to the control bias supply circuit 10. The control bias supply circuit 10 converts the applied voltage signal V10 into a control bias in the resistors R11 and R12 and the diode D11, and supplies this to the connection point Ps. As a result, the gate and source of the switching transistors Tr1 and Tr2 are reversely biased, and the switching transistors Tr1 and Tr2 are completely cut off.

  Further, the switching circuit 1 configured as described above can be integrated and provided as a single chip, as shown in FIG. 4, for example. Further, the switching circuit 1 made into one chip can be combined with other circuits (decoder 11 or the like) and provided as one switching module 1A. The capacitors C1, C2, and C3 may be provided inside the switching module 1A as shown in FIG. 4, but the present invention is not limited to this, and the outside of the input terminals Tin and output terminals Tou1 and Tout2 in the figure is not limited thereto. It is good also as a structure provided in.

  Further, the above-described decoder 11 may be included in the chip of the switching circuit 1 described above. As a result, the switching operation according to the present embodiment can be realized with one chip.

  In the above description, the SPDT switch having one input and two outputs has been described as an example. However, the present invention is not limited to this, and for example, one input and one output, or two inputs and three outputs, or more. Various modifications are possible.

[Second Embodiment]
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. This embodiment shows another example of the control bias supply circuit.

  FIG. 5 is a circuit diagram showing a configuration of the switching circuit 2 configured to include the control bias supply circuit 20 according to the present embodiment.

  As apparent from FIG. 5, the control bias supply circuit 20 according to the present embodiment is configured to include a bias transistor Tr21, and the source of the bias transistor Tr21 is connected to the connection point Ps. The bias transistor Tr21 is applied with a voltage signal V10 through a resistor R21 for attenuating a high-frequency signal propagated from the input terminal Tin to the gate. The bias transistor Tr21 is composed of a MES type field effect transistor.

  Therefore, when all the switching transistors Tr1 and Tr2 are in a non-selected state, the control bias (= gate-source potential difference) generated by the bias transistor Tr21 is applied by applying the voltage signal V10 to the gate of the bias transistor Tr21. Is supplied to the sources of the switching transistors Tr1 and Tr2 via the connection point Ps. As a result, the gate and source of the switching transistors Tr1 and Tr2 are reversely biased, and the switching transistors Tr1 and Tr2 are completely cut off.

  In addition, as shown in FIG. 5, the drain of the bias transistor Tr21 is grounded via a capacitor C21, which is a capacitive element, so that the isolation between the input terminal Tin and the output terminals Tout1 and Tout2 is increased, and a more reliable cutoff is achieved. It is also possible to configure so that That is, by grounding the drain of the bias transistor Tr21 via the capacitor C21 for cutting off the direct current component DC of the high frequency signal, when all the switching transistors Tr1 and Tr2 are in the non-selected state, this is applied to the high frequency signal. Acts as a shunt transistor. For this reason, as described above, the isolation between the input terminal Tin and the output terminals Tout1 and Tout2 is increased, and the cutoff of the switching transistor in the non-selected state can be made more reliable. Other configurations are the same as those of the first embodiment, and thus description thereof is omitted here.

[Third Embodiment]
Next, a third embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment, the control bias voltage value is variably supplied.

  FIG. 6 is a circuit diagram showing a configuration of the switching circuit 3 having the control bias supply circuits 31 and 32 according to the present embodiment. The present embodiment is an example in which the control bias is variably supplied in the switching circuit 1 according to the first embodiment.

  As apparent from FIG. 6, the switching circuit 3 according to the present embodiment includes a plurality (two in the drawing) of control bias supply circuits 31 and 32. Therefore, in the present embodiment, the control bias supplied to the sources of the switching transistors Tr1 and Tr2 is appropriately switched by setting which control bias supply circuit 31 or 32 is used by a data signal input from the outside. It becomes possible. This setting can be realized, for example, by adding a 1-bit flag to the data signal.

  Further, FIG. 7 shows a configuration when the switching circuit 3 according to the present embodiment is made into one chip. The switching module 3A shown in FIG. 7 has the same configuration as that of the switching module 1A according to the first embodiment. When all the switching transistors Tr1 and Tr2 are in a non-selected state, the decoder 33 uses the voltage signal based on the data signal. It has a configuration for outputting V31 or V32. As a result, the control bias supply circuit (31/32) to which the voltage signal (31/32) is applied supplies the individually controlled control bias to the sources of the switching transistors Tr1 and Tr2 via the connection point Ps. Other configurations are the same as those of the first embodiment, and thus description thereof is omitted here.

  In the present embodiment, the switching circuit provided with two control bias supply circuits has been exemplified with reference to the drawings. However, the present invention is not limited to this, and may be a plurality of, for example, three or more. However, when a plurality of control bias supply circuits are provided in this way, the number of bits added to the data signal in order to select them in the data signal is determined depending on the number of control bias supply circuits.

  In the above description, the control bias supplied when all the switching transistors Tr1 and Tr2 are in the non-selected state is switched. However, the present invention is not limited to this, and according to various situations and purposes, Even when any one of the switching transistors is selected, the control bias to be supplied can be switched. In addition, the control bias to be supplied is switched between when all the switching transistors Tr1 and Tr2 are in a non-selected state and when any one of the switching transistors (Tr1 and Tr2) is in a selected state. It is also possible. Thereby, in this embodiment, since a desired control bias can be applied according to a predetermined event, the controllability of the circuit is improved.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings. This embodiment is an example when a switching circuit is configured using a switching transistor with a shunt circuit.

  FIG. 8 is a circuit diagram showing a configuration of the switching circuit 4 according to the present embodiment. As shown in FIG. 8, shunt transistors Tr41 and Tr42 are connected to the sources of the switching transistors Tr1 and Tr2 in the switching circuit 4 according to the present embodiment, respectively.

  The shunt transistor Tr41 has a gate to which a selection control signal V2 is applied via a resistor R41 and a resistor R2 for attenuating a high-frequency signal, and a drain that has a capacitor C41 that is a capacitive element for blocking the DC component DC of the high-frequency signal. Is grounded. Similarly, the shunt transistor Tr42 is a capacitive element for applying a selection control signal V1 to the gate via a resistor R42 and a resistor R1 for attenuating a high frequency signal, and for draining the DC component DC of the high frequency signal. It is grounded through a certain capacitor C42.

  Therefore, the shunt transistor Tr41 shorts the source of the non-selected switching transistor Tr1 when the switching transistor Tr2 is selected. Further, the shunt transistor Tr42 short-circuits the source of the non-selected switching transistor Tr2 when the switching transistor Tr1 is selected. As a result, the input terminal Tin and the output terminals Tout1 and Tout2 can be sufficiently isolated, and the switching transistor in the non-selected state can be reliably cut off. Other configurations are the same as those of the first embodiment, and thus description thereof is omitted here.

[Other Embodiments]
The embodiment described above is merely a preferred embodiment of the present invention, and the present invention can be variously modified and implemented without departing from the gist thereof.

It is a circuit diagram which shows the structure of the switching circuit 100 by a prior art. It is a circuit diagram which shows the structure of the switching circuit 200 by a prior art. 1 is a circuit diagram showing a configuration of a switching circuit 1 according to a first embodiment of the present invention. It is a block diagram which shows the structure of 1 A of switching modules in which the switching circuit 1 shown in FIG. 3 was integrated. It is a circuit diagram which shows the structure of the switching circuit 2 by the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the switching circuit 3 by the 3rd Embodiment of this invention. FIG. 6 is a block diagram showing a configuration of a switching module 3A in which the switching circuit 3 shown in FIG. 5 is incorporated. It is a circuit diagram which shows the structure of the switching circuit 4 by the 4th Embodiment of this invention.

Explanation of symbols

1, 2, 3, 4 Switching circuit 1A, 3A Switching module 10, 20, 31, 32 Control bias supply circuit 11, 33 Decoder C21, C41, C42 Capacitor D11 Diode R3, R4 Ballast resistor R11, R12, R21, R22, R31, R32, R33, R34, R41, R42 Resistor Tr21 Bias transistor Tr41, Tr42 Shunt transistor V10, V31, V32 Voltage signal

Claims (22)

Switching having a plurality of switching transistors whose sources or drains are connected in common to either the input terminal or the output terminal, and a control bias supply circuit for supplying a control bias to the sources or drains of the plurality of switching transistors In the circuit
The control bias supply circuit operates by receiving a voltage signal applied from the outside, and includes a diode connected in a forward direction with respect to the voltage signal;
Only when all the switching transistors are in a non-selected state by a selection control signal inputted from the outside to the gates of the switching transistors, the gates and the sources or drains of all the switching transistors are reversely biased. said control bias from the control bias supply circuit is supplied to, at least when one of them is selected, the switching circuit, wherein the control bias from the control bias supply circuit is not supplied out of the switching transistor . One of the input terminal and the output terminal is a plurality, and one of the plurality of switching transistors is connected to the one of the plurality of the input terminals and the output terminal, respectively, and the input terminal and the output terminal The other of the source and drain is connected to the other of the output terminals at a common connection point,
The bias supply circuit supplies a bias to the common connection point;
The switching circuit of claim 1, wherein a resistor is connected between ground and the common connection point. The diode is a bias transistor configured to include a MES type field effect transistor,
2. The switching circuit according to claim 1, wherein the control bias is supplied based on a voltage signal applied to a gate of the bias transistor.   4. One of the source and drain of the bias transistor is connected to a connection point common to the plurality of switching transistors, and the other is connected to a ground potential through a capacitive element. The switching circuit described.   2. The switching circuit according to claim 1, wherein the control bias supply circuit has a variable voltage value of the control bias.   The switching circuit according to claim 1, wherein the control bias supply circuit selectively supplies any one of a plurality of control biases.   2. The switching circuit according to claim 1, wherein the control bias supply circuit varies the voltage value of the control bias when all of the plurality of switching transistors are in a non-selected state.   The control bias supply circuit supplies the control bias having different voltage values when at least one of the plurality of switching transistors is in a selected state and when all of the plurality of switching transistors are not selected. The switching circuit according to claim 1.   The switching circuit according to claim 1, comprising at least three switching transistors commonly connected to the input terminal or the output terminal. A shunt transistor connected to the source of the switching transistor;
2. The switching circuit according to claim 1, wherein a voltage signal applied to the gate of the switching transistor not corresponding to the shunt transistor is applied to the gate of the shunt transistor.   The switching circuit according to claim 1, wherein the switching transistor is a MES field effect transistor.   3. The switching circuit according to claim 2, wherein a current flows from the control bias supply circuit to the resistor, whereby a potential at the common connection point becomes higher than a ground potential.   2. The switching circuit according to claim 1, wherein a source and a drain of the switching transistor are connected via a ballast resistor. The switching circuit according to any one of claims 1 to 13,
A switching module comprising: a decoding circuit that decodes a data signal input from the outside and generates a voltage signal and / or a selection control signal for operating the switching circuit.   15. The switching module according to claim 14, wherein the switching circuit and the decoding circuit are formed by a single chip. In a control method of a switching circuit having a plurality of switching transistors having sources or drains connected in common to either an input terminal or an output terminal,
Only when all of the switching transistors are in a non-selected state by a selection control signal input from the outside to the gates of the switching transistors, a reverse bias is applied between the gates and the sources or drains of all the switching transistors. A control bias is supplied, and when at least one of the switching transistors is in a selected state, the control bias is not supplied ,
The step is a step of supplying the control bias through a diode connected in a forward direction to the voltage signal based on a voltage signal applied from the outside.   17. The switching circuit according to claim 16, wherein the step is a step of supplying the control bias to a connection point common to the plurality of switching transistors and having a resistor connected to ground. Control method.   18. The method of controlling a switching circuit according to claim 16, wherein the step includes a step of causing a potential of the common connection point to be higher than a ground potential by passing a current through the resistor.   19. The control bias according to claim 16, wherein the step of supplying the control bias is based on a voltage signal applied to a gate of a bias transistor, which is a diode including a MES type field effect transistor. The switching circuit control method according to claim 1.   19. The switching circuit control method according to claim 16, wherein in the step, the voltage value of the control bias is variably supplied.   The method of controlling a switching circuit according to any one of claims 16 to 18, wherein the step changes the voltage value of the control bias when all of the plurality of switching transistors are in a non-selected state.   The step of supplying the control bias having a voltage value different between a case where at least one of the plurality of switching transistors is in a selected state and a case where all of the plurality of switching transistors are in a non-selected state; The method for controlling a switching circuit according to any one of claims 16 to 18.

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