JP4324282B2 - IC for receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a receiver, particularly a receiver IC (integrated circuit) such as a radio receiver and a cellular phone.
[0002]
[Prior art]
With the advance of semiconductor technology, most of electronic circuits have been integrated into ICs. However, in particular, portable circuits (portable) receivers that need to be reduced in size and weight are preferably integrated into ICs. In addition, it is preferable to accommodate as many circuits as possible in as few IC packages as possible in order to reduce the size and weight and reduce the cost.
[0003]
A general receiver 100 employs a superheterodyne system as shown in FIG. 4 in order to achieve high sensitivity. That is, an RF (radio frequency) signal received from the antenna 101 is amplified by the RF amplifier 111 and then mixed with a local oscillation signal from a local oscillator described later by the mixer 112. The IF (intermediate frequency) signal obtained by the mixer 112 is amplified to a predetermined amplitude by the IF amplifier 113, then detected by the detector 114, and is a sound (audio) that is a modulation signal included in the RF signal from the broadcasting station. Demodulate the signal. The output of the detector 114 is amplified to a predetermined power by an output (or audio) amplifier 130 to drive the speaker 140.
[0004]
Here, the local oscillation circuit 120 has a function of changing the local oscillation frequency and selecting, for example, RF signals from a plurality of broadcasting stations. In recent receivers, the local oscillation circuit 120 is generally composed of a PLL frequency synthesizer 121. The PLL frequency synthesizer 121 includes a VCO (voltage controlled oscillator), a programmable counter (frequency divider), a reference oscillator, a phase comparator, and a low-pass filter. The control circuit 122 counts the programmable counter or variable frequency divider. Alternatively, a local oscillation signal having an arbitrary frequency can be obtained by setting a frequency division ratio.
[0005]
That is, a general receiver (for example, a radio receiver) includes a signal receiving analog circuit unit 110 including an RF amplifier 111 to a detector 114, and a control digital circuit unit 120 including a PLL frequency synthesizer 121 and a control circuit 122. Is included.
[0006]
[Problems to be solved by the invention]
There are various problems when the receiver circuit including the analog circuit unit 110 and the digital circuit unit 120 is integrated into an IC. First, the digital circuit is suitable for the MOS type IC process and can be manufactured relatively easily and inexpensively. However, the digital circuit generates noise, and particularly the S / N ratio of the receiving circuit of the AM (amplitude modulation system) receiver. Therefore, it is impossible or difficult to form the same chip or substrate. On the other hand, since the analog circuit section needs to operate at a relatively high frequency and linearly, a bipolar IC is generally used.
[0007]
Therefore, in a conventional receiver such as a radio, a plurality of ICs are used by separating an analog circuit unit and a digital circuit unit. However, in this case, there is a problem that the number of parts increases, and the reduction in size and weight is hindered, resulting in an increase in cost.
[0008]
OBJECT OF THE INVENTION
An object of the present invention is to provide an IC for a receiver that is suitable for a portable radio receiver or the like and can form an analog circuit part and a digital circuit part on a single chip or a substrate by a MOS process. .
[0009]
Another object of the present invention is to provide a receiver IC including both an analog circuit section and a digital circuit section while maintaining electrical characteristics such as an S / N ratio.
[0010]
[Means for solving the problems]
According to the receiver IC of the present invention, the reception analog signal processing analog circuit unit and the control digital circuit unit are integrated on the same substrate, and the analog circuit unit mixer and IF amplifier are configured by a balanced circuit. It is characterized by that. This effectively cancels out noise (common mode noise) jumping from the digital circuit section, and obtains electrical characteristics such as an S / N ratio required by the analog circuit section.
[0011]
With such a configuration, the receiver IC of the present invention can be a MOS IC having a relatively simple manufacturing process, low cost, and low power consumption.
[0012]
Preferably, the analog circuit portion of the receiver IC according to the present invention has a so-called multiplier configuration including a pair of input stage MOS transistors cascode-connected to two pairs of MOS transistors coupled to a source. In addition, as the gate bias resistance of the input stage MOS transistor, by using the MOS transistor biased to the on state, an extremely high resistance can be easily obtained in a very small area on the substrate, which is effective for IC implementation. is there.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred embodiment of a receiver IC according to the present invention will be described in detail with reference to FIGS.
[0014]
First, FIG. 1 shows a block diagram of the main part of the analog signal processing unit 110 of the receiver IC of the present invention. An analog signal processing unit (analog unit) 110 of the receiver IC shown in FIG. 1 receives an RF signal that is received through an antenna and amplified by a radio frequency (RF) amplifier, not shown. And a balanced mixer 10 having an LO input terminal 12 to which a local oscillation signal (LO) from a local oscillator of the digital circuit unit 120 is input, and a differential (balanced) IF (intermediate frequency) output from the mixer 10 A plurality of differential IF amplifiers 20a to 20n that amplify via the coupling capacitor 21. The outputs of the IF amplifiers 20a to 20n are obtained at the IF output terminal 25.
[0015]
The receiver IC of the present invention includes the analog circuit unit 110 and the digital circuit unit 120. Since the digital circuit unit 120 basically performs a switching operation, a large amount of noise is generated. In the receiver IC, the analog circuit unit 110 is affected by noise generated by the digital circuit unit 120. Noise includes conduction noise, radiation noise and electromagnetic or electrostatic coupling noise conducted through a power supply line. The analog circuit unit 110 arranged close to the digital circuit unit 120 is affected by all types of noise. However, if the analog circuit unit 110 has a balanced or differential configuration as shown in FIG. 1, it is possible to cancel or reduce these noises and to effectively amplify or process the signal components. This is because the noise described above is input substantially equally to both input terminals and appears equally to the power supply terminals, so that the noise component is canceled out in the difference signal.
[0016]
Next, FIG. 2 is a detailed circuit diagram of a specific example of the IF amplifier 20 of the analog circuit unit 110 of FIG. The IF amplifier 20 shown in FIG. 2A includes a pair of input MOS transistors 32a and 32b having sources connected via a resistor 31 and connected via MOS transistors 33a and 33b operating as variable resistors. Have. The gates of the MOS transistors 33a and 33b are connected to a bias terminal for applying a bias voltage. The gates of the input MOS transistors 32a and 32b are connected to the reference voltage source REF via bias resistors 34a and 34b, respectively. An input signal is applied to the gate terminals 35a and 35b of the input MOS transistors 32a and 32b from the preceding circuit through the coupling capacitor 21.
[0017]
The drains of the input MOS transistors 32a and 33b are connected to the sources of two pairs of output MOS transistors 36a to 36b and 36c to 36d, respectively, whose sources are commonly connected and connected in parallel. The gates of the MOS transistors 36a and 36d are commonly connected to the terminal 37a, and the gates of the remaining MOS transistors 36b and 36c are commonly connected to the terminal 37b. The drains of the MOS transistors 36a and 36c are connected to the output terminal 38a and to the power supply Vdd via the load resistor 39a. Similarly, the drains of the MOS transistors 36b and 36d are connected to the output terminal 38b and to the power source Vdd via the load resistor 39b.
[0018]
As described above, the drains of the input MOS transistors 32a-32b are cascade-connected to the sources of the output MOS transistors 36a-36d to form a so-called cascode amplifier. The gain of the cascode amplifier is determined by the source resistance 31 of the input stage and the load resistance 39 of the output stage. In other words, the IF input signal input to the gate input terminals 35a-35b of the input MOS transistors 32a-32b is amplified with a gain determined by the ratio of the resistors 39 and 31 described above. The gain can be controlled by a control signal of an AGC (automatic gain control) circuit input to the gate input terminals 37a-37b of the output MOS transistors 36a-36d. The load resistors 39a-39b may be LC (inductor and capacitor) resonance or tank circuits tuned to the intermediate frequency (IF) as necessary.
[0019]
The bias resistors 34a and 34b in FIG. 2A may be ordinary resistance elements, but it is not easy to stably obtain a high resistance on the order of 20 MΩ in an IC circuit. Therefore, in the present invention, as shown in FIG. 2B, a MOS transistor 40 biased to an on state is used. That is, the drain-source resistance of the MOS transistor 40 is used as the bias resistors 34a and 346b. As a result, a high resistance of 20 MΩ or more can be formed on the substrate in a very small area, which contributes to the miniaturization of the receiver IC. By making the bias resistors 34a and 346b high resistance, the coupling capacitor 21 shown in FIG. 1 can be reduced in capacity, for example, on the order of 1PF, and can be formed inside the IC. That is, it is not necessary to externally connect a coupling capacitor outside the IC, and the number of parts and the number of manufacturing and assembly processes can be reduced.
[0020]
Next, FIG. 3 shows a specific circuit diagram of the mixer circuit 10 of the analog circuit unit 110 of the receiver IC of the present invention. As described above with reference to FIG. 1, the mixer 10 is also a balanced type. That is, a bias MOS transistor 50 having a source connected and a bias voltage applied to the gate via a terminal 51, a pair of input MOS transistors 52a-52b commonly connected to the drain of the MOS transistor 50, and the input MOS It includes two pairs of output MOS transistors 54a-54b and 54c-54d cascode-connected to the drains of transistors 52a-52b. The drains of the output MOS transistors 54a-54d are cross-connected, the drains of 54a-54c are connected to the load 56a, and the drains of 54b-54d are connected to the load 56b. Next, the output voltage appearing at the load 56a is connected via a series circuit of a resistor 57a and a capacitor 58a, and 59a of a pair of MOS transistors 59a-60a in which the connection point voltage is connected in series between the power supply Vdd and the connection. Enter the gate. The load 56b has the same configuration.
[0021]
The gates of the input MOS transistors 52a-52b are input terminals 53a and 53b, which receive an RF signal received by an antenna and amplified by an RF amplifier. On the other hand, the gates of the output MOS transistors 54a and 54d are commonly connected to the terminal 55a, the gates of the MOS transistors 54b and 54c are commonly connected to the terminal 55b, and a local oscillation signal is input between the terminals 55a and 55b. The gates of the MOS transistors 60a and 60b are connected to the bias terminal 61, and a bias voltage is applied to the gates of both the transistors 60a to 60b. Further, the output terminal 62a is connected to the source of the MOS transistor 59a and the drain of the MOS transistor 60a. Similarly, an output terminal 62b is connected to the source of the MOS transistor 59b and the drain of 60b.
[0022]
The mixer 10 described above constitutes a multiplier, and an output of the product of the RF input signal between the input terminals 53a and 53b and the local oscillation signal between the LO input terminals 55a and 55b appears between the output terminals 62a and 62b. Many signal components including the frequency sum and difference signals of the RF input signal and the local oscillation signal appear in this output. However, if the load 56a, 56b connected to the drain output terminals of the MOS transistors 54a-54d is an LC tank circuit having a resonance frequency of an intermediate frequency (IF) equal to the difference between both signal frequencies, the IF signal is output as an output signal. It is obtained from the output terminals 62a and 62b. The circuit composed of the resistors 57a and 57b and the capacitors 58a and 58b constitutes a low-pass filter, and prevents signals other than the above-described frequency difference from being output.
[0023]
The configuration and operation of the receiver IC of the present invention, particularly its analog circuit section, have been described in detail. However, it should be readily understood by those skilled in the art that the present invention should not be limited to such specific examples, and that various modifications and changes can be made without departing from the spirit of the present invention. For example, the mixer need not be only one stage, and may be amplified by sequentially changing the RF frequency to a low-frequency IF signal using a mixer having two or more stages as necessary. Further, the mixer and IF amplifier of the analog circuit section are not necessarily limited to the specific circuit described above as long as they are differential or balanced. Furthermore, although only one stage of the IF amplifier has been illustrated and described, it is also possible to have a multistage configuration of two or more stages having substantially the same configuration.
[0024]
【The invention's effect】
As understood from the above description, according to the receiver IC of the present invention, the analog signal processing circuit such as the mixer or the IF amplifier is made a balanced type so that the digital signal processing circuit is placed on the same substrate. It was possible to arrange and make an IC as a single chip. In particular, by using a MOS IC, the number of manufacturing steps can be reduced and the manufacturing can be performed at low cost, and the size and weight can be reduced and the power consumption can be reduced.
[0025]
In addition, since the MOS transistor biased to the ON state is used as the bias resistance of the MOS transistor, a very high bias resistance can be easily obtained, and the coupling capacitor can be made to have a minute capacity such as IPF. Therefore, it is advantageous for IC.
[Brief description of the drawings]
FIG. 1 is a block diagram of an analog signal processing unit of a receiver IC according to the present invention.
2 shows a circuit diagram of an IF amplifier of the analog signal processing unit shown in FIG. 1, (A) shows a circuit diagram of a single-stage IF amplifier, and (B) shows a bias resistor circuit diagram thereof.
FIG. 3 is a circuit diagram of an example of the mixer circuit shown in FIG. 1;
FIG. 4 is a block diagram of a general receiver.
[Explanation of symbols]
10 mixer 20a-20n IF amplifier 21 coupling capacitor 32, 53 input stage MOS transistor 36, 54 output stage MOS transistor 34 bias resistor 110 analog circuit section 120 digital circuit section

Claims (1)

In the receiver IC that integrates the signal receiving analog circuit portion and the control digital circuit portion in the same chip,
Each of the signal receiving analog circuit units includes a mixer having a differential input / output terminal and an intermediate frequency amplifier connected to a subsequent stage of the mixer, each of the mixer and the intermediate frequency amplifier having a balanced circuit configuration,
The signal receiving analog circuit part and the control digital circuit part are formed by a MOS process,
Reduce interference to the signal receiving analog circuit section by the control digital circuit section ,
As the intermediate frequency amplifier, two pairs of MOS transistors whose sources are commonly connected are connected in parallel, and the source is connected to the commonly connected sources via a resistor and is biased to an ON state as an input gate bias resistor. The drain of the differential input MOS transistor to which the MOS transistor is connected is configured by cascode connection,
Wherein the intermediate frequency amplifier, IC receiver to signal through the coupling capacitor and said Rukoto entered.

Images