JP4323393B2 - Processor - Google Patents

Description

  The present invention relates to a compiler device, an optimization device, an assembler device, a linker device, a debugger device, and a disassembler device, and relates to a compiler device for a processor that executes an instruction in a unit unrelated to a read instruction unit, and optimization The present invention relates to a device, an assembler device, a linker device, a debugger device, and a disassembler device.

Generally, a processor reads an instruction from a memory and executes it based on a program counter. FIG. 43 is a block diagram illustrating an example of a basic configuration of a processor.
The instruction memory 4301 stores an instruction sequence constituting a program. Here, one instruction is 8 bits long, and four instructions are one instruction packet.
The program counter 4300 designates the address of the instruction packet in the instruction memory 4301.

The instruction reading unit 4302 reads an instruction packet designated by the program counter 4300 from the instruction memory 4301.
The instruction execution unit 4303 executes all four instructions included in the read instruction packet within one cycle.
As described above, the processor generally reads an instruction packet designated by one program counter, and can execute the read four instructions in one cycle.

  However, in such a processor, all instructions in the read instruction packet are used as one cycle of execution units, so instructions that cannot be executed in one instruction packet because resources such as I / O and memory cannot be used. If there is even one, the execution of all instructions in the instruction packet is waited until the resource becomes available. As a result, such a processor has a low instruction execution speed.

  In view of the above problems, an object of the present invention is to provide a processor capable of executing a program having different units for instruction reading and instruction execution, and a program development environment capable of creating such a program.

  In order to achieve the above object, according to the present invention, in a processor for reading an instruction from a memory, one unit data of at least one memory consisting of a natural number of bytes is read from the memory, and the one unit data of the memory performs one operation. 1 unit instruction of the processor shown, 1 unit data of each memory is executed by the processor, and the number of 1 unit data in the memory of the 1 unit instruction of the processor showing one operation is 2 A processor that is a natural number excluding power, the first program counter indicates a storage position of one unit of data in the memory, and the second program counter indicates one operation included in the one unit of data in the memory 1 unit instruction stored in the memory, and 1 unit data in the memory 1 indicates the storage position of one unit instruction of the processor indicating the one operation in the memory, and after the second program counter makes a round of the storage position, the first program counter stores the next unit data of the memory in the memory. The storage position is indicated.

  With the configuration as described above, the address calculation based on the carry method can perform an address calculation with continuity between the upper bit calculation and the lower bit calculation of the program counter and the PC relative value.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (First embodiment)
The first embodiment relates to an optimizing device, an assembler device, a linker device, and a processor that executes the program, which generate a program in which the instruction reading unit and the instruction execution unit are different. (Format of instructions executed by the processor)
First, the format of instructions executed by the processor according to the present embodiment will be described.

  FIG. 1A to FIG. 1E are diagrams showing the format of instructions executed by the processor of the present embodiment. The instruction executed by the processor is composed of 21 bits as one unit (one unit). There are two types of instructions: a 21-bit instruction (one unit instruction) composed of one unit and a 42-bit instruction (two unit instructions) composed of two units. (Hereinafter, “instruction” refers to either a 21-bit instruction or a 42-bit instruction).

  The 1-bit format information 101 indicates which length the instruction is. Specifically, when the format information 101 is “0”, a unit including the format information 101 forms one instruction, that is, a 21-bit instruction. When the format information 101 is “1”, a unit including the format information 101 and a subsequent unit constitute one instruction, that is, a 42-bit instruction.

  The 1-bit parallel execution boundary information 100 indicates whether or not a parallel execution boundary exists between the instruction and the subsequent instruction. Specifically, when the parallel execution boundary information 100 is “1”, a parallel execution boundary exists between an instruction including the parallel execution boundary information 100 and a subsequent instruction, and these instructions are executed in different cycles. The When the parallel execution boundary information 100 is “0”, there is no parallel execution boundary between the instruction including the parallel execution boundary information 100 and the subsequent instruction, and these instructions are executed in the same cycle.

  Portions other than the format information 101 and the parallel execution boundary information 100 indicate operations. That is, an operation is specified with a length of 19 bits for a 21-bit instruction and a length of 40 bits for a 42-bit instruction. Specifically, the “Op1”, “Op2”, “Op3”, and “Op4” fields are the opcodes indicating the type of operation, the “Rs” field is the register number of the register that is the source operand, The field “Rd” indicates the register number of the register serving as the destination operand. The fields “imm5” and “imm32” indicate 5-bit and 32-bit arithmetic constant operands, respectively. The fields “disp13” and “disp32” indicate 13-bit and 32-bit displacements, respectively.

Transfer instructions and arithmetic instructions that handle long constants such as 32-bit constants, and branch instructions that specify large displacements are defined as 42-bit instructions, and most other instructions are defined as 21-bit instructions. Of the two units that are components of the 42-bit instruction, only a part of the long constant or displacement is arranged in the rear unit, and no opcode is arranged. (Processing to read and execute processor instructions)
Next, instruction read and execution operations by the processor of the present embodiment will be described. The processor of the present embodiment is a processor based on static parallel scheduling. FIG. 2A is a diagram illustrating an instruction packet which is a unit for storing and reading instructions. The instruction packet is composed of three units (63 bits) and dummy data (1 bit). The processor reads an instruction with a fixed length of 64 bits (hereinafter referred to as “packet”) in one cycle. That is, since one instruction is in units of 21 bits and is inconvenient for reading from the memory, an instruction packet in units of bytes in which a plurality of instructions are combined is used as a reading unit. In addition, this example is particularly effective when the number of units in the instruction packet is not a power of 2 as in this example. This is because, as will be described later, it is not convenient to represent the position of the unit in the instruction packet in a normal binary number. Hereinafter, the three units constituting one packet are referred to as a first unit, a second unit, and a third unit in order from the smallest address value.

FIG. 2B is a diagram showing the order of reading instructions. As shown in the figure, the instruction is read in one cycle and one packet.
FIG. 2C is a diagram showing the order of instruction execution. As shown in the figure, the unit of instructions executed in one cycle is up to the boundary of parallel execution. That is, instructions up to the instruction whose parallel execution boundary information 100 is “1” are executed in parallel in each cycle. Units that have been read but not executed are stored in the instruction buffer and executed after the next cycle.

  As described above, the processor according to the present embodiment reads instructions in units of fixed-length packets and executes an appropriate number of units according to the degree of parallelism in each cycle. As described above, the processor of the present embodiment can set the execution start position of one cycle even for an instruction other than the first instruction in the instruction packet by changing the position of the instruction in the instruction packet as described later. This is based on the designated “intra-packet address” (lower PC).

  The processor of the present embodiment has a feature that it is particularly suitable for executing an instruction that is not byte-aligned, that is, an instruction whose word length is not in units of bytes. In other words, even if an instruction does not have a length in bytes, if it is read into the processor in the unit of an instruction packet having a length in bytes, the instruction in the instruction packet can be specified by the address in the packet. It is.

  FIG. 3 shows an example of a method for storing and reading instructions when executing a non-byte-aligned instruction in a general processor. If the instruction is not byte-aligned with 21 bits, a 3-bit unused area is added to the instruction so that the instruction can be read in byte units to have a 24-bit length. That is, one instruction that is originally 21 bits long is stored in the memory in units of 24 bits and is read out. In this case, the length of the three instructions is 72 bits, whereas in the present embodiment, the length of the three instructions is 64 bits, and the program size can be kept small.

In this embodiment, the configuration of the packet when the word length of the instruction is in units of 21 bits is described. However, the present invention is not limited to this, and for instructions having other word lengths, A packet can be configured and instructions can be read out in packet units. For example, if the word length of the instruction is in n-bit units, (n × m + r) mod 8 = 0, and a combination of m and r that maximizes n × m / (n × m + r) is used. One packet may be composed of m pieces of n-bit instruction units and r-bit dummy data. As a result, an instruction packet having a byte unit length with a small dummy data ratio can be configured. (Expression method of instruction address)
Next, a method for expressing an instruction address in the present embodiment will be described. The instruction address means an address for specifying the position of the unit, and is expressed by 32 bits.

The upper 29 bits of the 32 bits specify an instruction packet and are called a “packet address”. The “packet address” is expressed in 29'h01234567 of hexadecimal 29 bits. A value obtained by shifting the value of the “packet address” to the left by 3 bits is a memory address where the instruction packet is stored.
The lower 3 bits of the 32 bits specify a unit included in the instruction packet and are referred to as “intra-packet address”. The “intra-packet address” is expressed in 3′b001 of binary 3 bits. The in-packet address 3′b000 indicates the first unit in the packet, indicates the second unit in the 3′b010 packet, and indicates the third unit in the 3′b100 packet. The in-packet address is not limited to this. If three units are represented by three numerical values, they may be expressed by other numerical values.

In addition, in the designation of the instruction address in this embodiment, 3 bits are assigned to one instruction packet of 8 bytes. Therefore, in the method for specifying an instruction address in the present embodiment and the method for specifying an address for assigning one address for each byte in a general processor, the addresses specified by the upper 29 bits are the same memory address. Will be shown. (How to create object code to be executed by the processor)
A method for creating an object code executed by the processor according to the present embodiment will be described.

First, some terms used in this embodiment will be described.
“PC relative value” is a difference value between the addresses of two instructions.
The “label” is included in the program and indicates the destination (branch destination) of a branch instruction such as a conditional branch, an unconditional branch, a branch to a subroutine, or a return from a subroutine.

  “Label” includes “label to be resolved to an instruction address” and “label to be resolved to a PC relative value”. The “label to be resolved to the address of the instruction” is replaced by the absolute address of the instruction in the process of converting the program into the object code. For example, the instruction “movL2, r1” for transferring the instruction from the memory to the register r1 The inside label L2 corresponds. The “label to be resolved to the PC relative value” is replaced with the PC relative value in the process of converting the program into the object code. For example, the label L1 in the unconditional branch instruction “braL1” to the PC relative value is used. Is applicable. As another classification, labels include “local labels” and “external labels”. That is, when a label and an instruction including the label are included in the same module, that is, a group of subprograms having one processing function, the label is referred to as a “local label” and the instruction including the label and the label is included. Is included in a separate module, the label is called an “external label”.

FIG. 4 is a diagram illustrating a process in which object code executed by the processor according to the present embodiment is created by a compiler device, an optimization device, an assembler device, and a linker device. Here, an outline of each function will be described.
The compiler device 301 analyzes the contents of the source code 300 written in a high-level language such as C language, and outputs an assembler code 302.

  The optimization device 303 assigns a temporary address to the assembler code 302, concatenates the instruction sequence every three units, and outputs an optimization code 304 as a result. In the process, for the local label, the PC relative value or the address of the instruction is calculated, and based on the value, the size of the instruction is determined as to whether the instruction is represented by one unit or two units. It is done.

The assembler device 305 outputs a relocatable code 306 which is a relocatable address format from the optimization code 304. In the process, a local label that is to be resolved to a PC relative value is converted into a PC relative value.
The linker device 307 combines a plurality of modules. That is, a plurality of relocatable codes 306 are combined, and the resulting object code 308 is output. In the process, unresolved labels are converted to PC relative values or instruction addresses.

The processor 309 executes the object code 308.
As described above, a program written in a high-level language is converted into an object code in a format that can be executed by a processor by the compiler device 301, the optimization device 303, the assembler device 305, and the linker device 307. The labels in the program are converted into PC relative values or instruction addresses in any of the object code generation processes. In other words, the assembler device 305 performs address resolution of a label that is a local label and should be resolved to a PC relative value. The linker unit 307 performs address resolution of a label that is a local label and should be resolved to an instruction address, and address resolution of an external label.

Hereinafter, the configuration and operation details of the processor 309, the linker device 307, the assembler device 305, and the optimization device 303 illustrated in FIG. 3 will be described. (Processor)
FIG. 5 is a block diagram showing details of the processor 309 and the external memory.
The processor 309 is a processor capable of executing up to three instructions in parallel, and includes arithmetic units 401 a to 401 c, general-purpose registers 402, upper PC 403, lower PC 404, upper PC arithmetic unit 411, lower PC arithmetic unit 405, and INC 412. An instruction buffer 408, a prefetch upper counter 410, a prefetch lower counter 413, instruction decoders 409a to 409c, a PC relative value selector 420, an immediate value selector 421, an operand data buffer 423, and an operand buffer 422. The The external memory includes a data memory 406 and an instruction memory 407.

Hereinafter, the upper PC 403 and the lower PC 404 are collectively referred to as a PC, and the upper PC calculator 411 and the lower PC calculator 405 are collectively referred to as a PC calculator.
The first computing unit 401a, the second computing unit 401b, and the third computing unit 401c each perform one computation. These computing units can be executed simultaneously.
The general-purpose register 402 stores data, addresses, and the like.

The upper PC 403 holds the upper 29 bits of the address of the first instruction of the instruction group to be executed in the next cycle, that is, the packet address.
The lower PC 404 holds the lower 3 bits of the address of the first instruction of the instruction group to be executed in the next cycle, that is, the in-packet address.
The instruction memory 407 stores an instruction represented by the object code 308.

The instruction buffer 408 stores the instruction read from the instruction memory 407.
The first instruction decoder 409a, the second instruction decoder 409b, and the third instruction decoder 409c decode the instruction, and if the decoded instruction can be executed, instructs the other processor components to execute the instruction. The first instruction decoder 409a receives the first instruction stored in the instruction buffer 408, the second instruction decoder 409b receives the next instruction, and the third instruction decoder 409c receives the next instruction. An instruction is entered. The instruction decoders 409a to 409c check the parallel execution boundary information of the unit and execute only instructions that can be executed in the cycle. For example, in the case of an instruction for calculating a constant value, the constant value is sent to the calculator 401a via the immediate value selector 421 to execute the calculation. In the case of a branch instruction, the PC relative value is sent to the upper PC calculator 411 and the lower PC calculator 405 via the PC relative value selector 420 to update the PC. Then, the instruction decoders 409a to 409c send the executed unit number to the INC 412 by the control signal to update the PC, send the executed unit number to the instruction buffer 408 by the control signal, and execute the executed unit in the instruction buffer 408. To erase.

The PC relative value selector 420 outputs the PC relative value output from the instruction decoders 409 a to 409 c to the upper PC calculator 411 and the lower PC calculator 405.
The immediate value selector 421 outputs the immediate value output from the instruction decoders 409a to 409c to the general-purpose register 402 or the arithmetic units 401a to 401c. Acquire and increment the values of the upper PC 403 and lower PC 404 accordingly. As a result, the packet address of the first instruction in the instruction group to be executed in the next cycle is set in the upper PC, and the in-packet address is set in the lower PC.

  The upper PC calculator 411 and the lower PC calculator 405 update the upper PC 403 and the lower PC 404, respectively. When the instruction decoders 409a to 409c decode the branch instruction, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC computing unit 411, and the lower 3 bits of the PC relative value are sent to the lower PC computing unit 405. It is done. The lower PC calculator 405 adds or subtracts the current value of the lower PC 404 and the lower 3 bits of the PC relative value, and sends the calculation result to the lower PC 404 as an update value. The upper PC calculator 411 adds or subtracts the current value of the upper PC 403 and the upper 29 bits of the PC relative value, and sends the calculation result to the upper PC 403 as an update value. The operation of the PC calculator, that is, the calculation method will be described later. As described above, when executing a branch instruction, the packet address of the branch destination instruction to be executed next is set in the upper PC 403 and the in-packet address is set in the lower PC 404. Further, the upper PC calculator 411 and the lower PC calculator 405 may update the PC by calculating the PC relative value and the address stored in the general-purpose register 402.

  The prefetch upper counter 410 indicates the upper 29 bits of the address of the first instruction of the instruction group read from the instruction memory 407, that is, the packet address. The prefetch upper counter 410 normally increments its value by one for each cycle. If the instruction executed in the previous cycle is a branch instruction, the packet address of the branch destination instruction set in the upper PC 403 as described above is sent from the upper PC 403 to the prefetch upper counter 410. The value of the prefetch upper counter 410 is set to the same value as the upper PC 403.

  The prefetch lower counter 413 designates the lower 3 bits of the address of the first instruction of the instruction group read from the instruction memory 407, that is, the address within the packet. In the present embodiment, the prefetch lower counter 413 is set to 3'b000. Therefore, the instruction to be read is specified in units of instruction packets, and one packet is sent from the instruction memory 407 to the instruction buffer 408 every cycle.

The data memory 406 stores operand data.
The operand data buffer 423 and the operand address buffer 422 are buffers between the data memory and the processor.
Next, an instruction address increment method and calculation method, which is the most characteristic feature of this embodiment, will be described. (Increment method of instruction address)
A method for incrementing the address of an instruction in this embodiment will be described. The instruction address is incremented by adding an increment value to the address in the packet of the instruction, and if there is a carry, the carry number is added to the packet address.

  FIG. 6 is an increment table showing the rules for incrementing the in-packet address. As shown in the figure, the instruction address is incremented by adding 2 to the value of the lower 3 bits when the in-packet address is 3'b000 or 3'b010. When the in-packet address is 3'b100, a carry is generated in the packet address (that is, 1 is added to the value of the upper 29 bits), and the value of the lower 3 bits is set to 3'b000. That is, the increment of the in-packet address is a ternary operation that cycles through 3'b000, 3'b010, and 3'b100. For example, if the increment value is 2 and the value of the in-packet address before the increment is 3'b100, the in-packet address after the increment is 3'b010, and one carry occurs in the packet address.

Thus, in this embodiment, it is not necessary to represent the in-packet address by a normal binary number. This is particularly effective when the number of units in the instruction packet is not a power of two. In other words, when the number of units in the instruction packet is not a power of two, even if the unit position in the instruction packet is expressed by a normal binary number, a binary arithmetic method is used when moving the unit position. Cannot be used. However, in the present embodiment, the unit position in the packet is expressed using specific m numerical values, and an operation in which m numerical values circulate is used as an operation for moving the unit position. Even when the number of units in the packet is not a power of two, calculations for specifying the position of the unit and moving the position of the unit are possible. (Instruction address calculation method)
Next, a carry method which is one of the instruction address calculation methods in this embodiment will be described. In addition to the carry method, the instruction address calculation method includes a separation method, an absolute position designation method, and a linear address method, which will be described later. In the carry method, the instruction address is divided into upper 29 bits and lower 3 bits for calculation. That is, the packet address and the intra-packet address are calculated separately. However, when the upper bit is calculated, an operation including the carry number or the borrow number generated by the lower 3 bit operation is performed.

  First, a method performed by the processor 309 to obtain the address of the branch destination instruction by adding the address of the branch instruction and the PC relative value will be described. The lower PC calculator 405 shown in FIG. 5 adds the lower 3 bits of the branch instruction address and the lower 3 bits of the PC relative value. FIG. 7A is an addition table showing an addition rule for the lower 3 bits of the branch instruction address and the lower 3 bits of the PC relative value. As shown in the figure, the addition of the lower 3 bits is a ternary operation that cycles through 3'b000, 3'b010, and 3'b100, unlike a normal binary operation. When a carry as shown in the figure occurs, the lower PC calculator 405 sends the carry number to the upper PC calculator 411.

The upper PC calculator 411 shown in FIG. 5 adds the upper 29 bits of the branch instruction address and the upper 29 bits of the PC relative value. At this time, if a carry occurs in the calculation of the lower PC calculator 405, the carry number is also added. The addition method is a normal binary operation.
The addition result calculated as described above becomes the address of the branch destination instruction. That is, the lower 3 bits of the addition result are set in the lower PC 404, and the upper 29 bits of the addition result are set in the upper PC 403.

  Next, an operation for obtaining the PC relative value performed by the optimization device 303, the assembler device 305, and the linker device 307, that is, a method of subtracting the branch instruction address from the branch destination instruction address will be described. Subtraction is performed by separating the upper 29 bits and the lower 3 bits as in the addition. The lower address subtracting means 907 of the optimizing device 303 to be described later, the lower address subtracting means 806 of the assembler device 305, and the lower address subtracting means 706 of the linker device 307 are the lower order of the address of the branch instruction from the lower 3 bits of the address of the branch destination instruction. Subtract 3 bits. FIG. 7B is a subtraction table showing a subtraction rule between the lower 3 bits of the branch destination instruction address and the lower 3 bits of the branch instruction address. As shown in the figure, the subtraction of the lower 3 bits is a ternary operation that cycles through 3'b000, 3'b010, and 3'b100, unlike a normal binary operation. When borrowing as shown in the figure occurs, the lower address subtracting means 907 sends the borrowing number to the upper address subtracting means 910 described later.

  The upper address subtracting means 910 of the optimizing device 303 described later, the upper address subtracting means 809 of the assembler device 305, and the upper address subtracting means 709 of the linker device 307 are the upper 29 bits of the address of the branch instruction and the upper address of the branch destination instruction. Subtract 29 bits. At this time, when borrowing occurs in the calculation by the lower address subtracting means 907, the borrowing number is also subtracted. The subtraction method is a normal binary operation.

The value obtained by subtracting the lower 3 bits calculated as described above from the lower 3 bits and the upper 29 bits from the subtraction result from the upper 29 bits is the PC relative value. Further, when the address of the branch destination instruction obtained by subtracting the address of the branch instruction performed by the processor and the PC relative value is obtained, the same method as described above is used.
As described above, the optimization device 303, the assembler device 305, the linker device 307 that calculate the program counter relative value from the difference between the address of the branch destination instruction and the address of the branch instruction, and the branch destination using the program counter relative value. The processor 309 that calculates the address of the instruction performs address calculation using the same carry method, so that the processor can calculate the address of the branch destination instruction without error from the program relative value when the branch instruction is executed. In addition, this carry-over address calculation has a feature that enables an address calculation having continuity between the high-order bit calculation and the low-order bit calculation of the program counter and the PC relative value. (Optimizer)
FIG. 8 is a block diagram showing the components and input / output data of the optimization apparatus 303 shown in FIG. Details of the optimization device 303 will be described. The optimization device 303 optimizes the assembler code 302 generated by the compiler device 301, concatenates the instruction sequence into a packet having a unit of 3 units, and outputs the optimization code 915 as a result. The optimization device 303 includes a code optimization unit 902, an address assignment unit 904, a label detection unit 905, a lower address subtraction unit 907, an upper address subtraction unit 910, an address difference calculation unit 912, and a label information resolution unit. 914.

The code optimization unit 902 optimizes the assembler code 302 and generates an optimization processing code 903. Since the processing of the code optimization unit 902 is the same as the processing by a known optimization device, detailed description is omitted.
The address assigning means 904 predicts the address of each instruction of the optimization processing code 903 obtained by the code optimizing means 902, and assigns the predicted address to each instruction (hereinafter, this address is referred to as “temporary address”). The address assignment code 916 that is the result is output.

  The label detection unit 905 detects a “local label” from the address assignment code 916. If the detected label is “label to be resolved to the instruction address”, the label detecting means 905 takes in the temporary address of the instruction in which the label is located. If the detected label is “label to be resolved to PC relative value”, the temporary address of the branch instruction and the temporary address of the branch destination instruction are fetched. Then, the label detection unit 905 outputs label information 906 composed of information about the instruction including the label and the value for which the label is resolved.

The lower address subtracting means 907, the upper address subtracting means 910, and the address difference calculating means 912 calculate the PC relative value for “label to be resolved to the PC relative value” in the label information 906.
The lower address subtracting means 907 subtracts the lower 3 bits of the temporary address of the branch instruction from the lower 3 bits of the temporary address of the branch destination instruction to calculate a borrow number 908 and a lower subtraction result 909.

The upper address subtracting means 910 subtracts the upper 29 bits of the temporary address of the branch instruction from the upper 29 bits of the temporary address of the branch destination instruction and the borrow number 908 calculated by the lower address subtracting means 907, and obtains the upper subtraction result 911. calculate.
The address difference calculation unit 912 calculates an address difference 913 in which the lower subtraction result 909 calculated by the lower address subtraction unit 907 is the lower 3 bits and the upper subtraction result 911 calculated by the upper address subtraction unit 910 is the upper 29 bits.

  The label information resolution unit 914 calculates an instruction including the label in the optimization processing code 903 from the address predicted by the address addition unit 904 or the address difference 913 calculated by the address difference calculation unit 912. Convert to instructions according to size. That is, an instruction including a label is converted into a 21-bit instruction if the given address or the address difference value can be expressed within 13 bits, and is converted into a 42-bit instruction otherwise.

Then, the label information resolution unit 914 concatenates the instruction sequence after the label resolution into a packet having a unit of 3 units, and outputs an optimization code 915 as a result.
Next, the operation of the optimization apparatus will be described using a specific example.
FIG. 9 is a flowchart showing an operation procedure of the optimization apparatus.
First, the code optimizing unit 902 optimizes the input assembler code 302 and generates an optimized code 903. FIG. 10 shows a part of the optimization processing code 903 generated by the code optimization unit 902. Several instructions in FIG. 10 will be described. “L1: movr2, r1” 1000 indicates the position of the label L1, and is an instruction for transferring from the register r2 to the register r1. “Jsrf” 1001 is a function call and is an instruction for performing a relative branch to label f (external label). The ret instruction returns to this address again. “Addr0, r4” 1002 is an instruction for adding the register r0 and the register r4 and storing the result in r4. “Andr1, r3” 1003 is an instruction that takes the logical product of the registers r1 and r3 and stores the result in r3. “MovL2, r2” 1004 is an instruction for transferring the address of the instruction in which the label L2 is placed to the register r2. “Ld (r2), r0” 1005 is an instruction to transfer the data stored at the address indicated by the register r2 to the register r0. “BraL1” 1006 is an instruction for performing a relative branch to the label L1 (local label). In FIG. 10, the instruction following the instruction 1007 is omitted, but it is assumed that the instruction at the label f does not exist in the subsequent instructions (step S3901).

Next, the address assignment unit 904 assigns a temporary address to each instruction of the optimization processing code 903 to generate an address assignment code 916. FIG. 11 shows an address assignment code 916 generated from the optimization processing code of FIG. Here, a temporary address starting from 32'h00000080 is assigned (step S3902).
The label detection unit 905 searches for a local label from the address assignment code 916, and outputs label information including an instruction including the searched label and information on a value to be resolved of the label. FIG. 12 shows label information 906 generated from the address assignment code 916 of FIG. As shown in the figure, L2 of the instruction 1104 is detected as a label to be resolved to the address of the instruction, and L1 of the instruction 1106 is detected as a label to be resolved to the PC relative value. For label L2, the instruction “movL2, r2” including L2 is fetched, and for label L1, the instruction “braL1” including L1 and the branch destination instruction for calculating the PC relative value are included. Address and branch instruction address information is captured. Since the label f of the instruction 1101 is an external label, it is not subject to optimization (steps S3903 and S3904).

  If there is a label to be resolved in the PC relative value in the label information 906, the PC relative value is calculated. The lower address subtraction means 907 calculates the lower bit of the value indicated by L1 which is the PC relative value. The lower address subtracting means 907 subtracts the lower 3 bits 3'b010 of the temporary address 32'h000000812 of the branch instruction 1106 from the lower 3 bits 3'b000 of the temporary address 32'h000000800 of the branch destination instruction 1100. As a result, 1 is obtained as the borrowing number 908, and 3'b100 is obtained as the lower-order subtraction result 909 (steps S3905 and S3906).

  The upper address subtraction means 910 calculates the upper bits of the value indicated by L1 which is the PC relative value. The high-order address subtracting means 910 subtracts the high-order 29 bits 29'h0000102 of the temporary address of the branch instruction 1106 from the high-order 29 bits 29'h00000102 of the temporary address of the branch destination instruction 1100 and 1 which is the number of borrows 908. As a result, 29'h1ffffffd (decimal number is -3, hereinafter, the negative number is represented by 2's complement) is obtained as the high-order subtraction result 911 (step S3907).

The address difference calculation unit 912 calculates an address difference, that is, a PC relative value, in which the lower operation result 900 is the lower bit and the upper operation result 911 is the upper bit. Here, 32′hffffffec, which is the address difference 913, is obtained by setting 3′b100 as the lower bit and 29′h1ffffffd as the upper bit (step S3908).
The label information resolution unit 914 determines the size of the instruction including the label depending on whether or not the value by which the label of the label information 906 is resolved can be expressed by 13 bits. The value to which the label L2 shown in FIG. 12 is resolved is 32′h12345678 and cannot be represented by 13 bits. Therefore, the instruction 1104 including the label L2 is a 42-bit instruction. Further, the value to be resolved by the label L1 is 32′hffffffec and can be represented by 13 bits. Therefore, the instruction 1106 including the label L1 is a 21-bit instruction (steps S3909, S3910, and S3911).

  Further, the label information resolution unit 914 concatenates the instruction sequence into a packet having a unit of 3 units based on the address assignment code 916. At this time, the instruction having the label is made to coincide with the size determined as described above. That is, one unit is used for a 21-bit instruction and two units are used for a 42-bit instruction. Then, the label information resolution unit 914 outputs the packetized instruction sequence as an optimization code. FIG. 13 shows an optimization code 915 generated from the address assignment code 916 of FIG. In FIG. 13, instructions constituting one packet are described in one line, and the instructions in the packet are delimited by the symbol ||. Further, the 42-bit instruction indicates that the instruction uses the area for two units by following the instruction enclosed in parentheses (step S3912).

As described above, it is possible to realize a processor optimization apparatus corresponding to the carry method by performing the prediction by performing the address operation by the carry method.
The temporary address assigned by the address assigning unit 904 and the PC relative value calculated by the address difference calculating unit 912 are all predicted values for determining the size of the instruction including the label, and are actually Since it may be different from the value, it will not be used in the subsequent processing. (Assembler device)
FIG. 14 is a block diagram showing a configuration of the assembler device 305 shown in FIG. 4 and related input / output data. Details of the assembler device 305 will be described. The assembler device 305 converts the optimization code 304 generated by the optimization device 303 into a relocatable code 306 that is a relocatable address format. The assembler device 305 includes machine language code generation means 802, label detection means 804, lower address subtraction means 806, upper address subtraction means 809, address difference calculation means 811, and label information resolution means 813.

  The machine code generation unit 802 converts the optimization code 304 into machine code 803 that can be executed by the processor 309. However, labels whose values are unresolved are stored in the machine language code 803 without being converted. At that time, the machine language code generation unit 802 gives a packet address and an in-packet address to each machine language code. Based on the assigned address, the label described later is resolved.

The label detection unit 804 searches for a difference between two instruction addresses, that is, a label to be resolved to a PC relative value, and takes in the branch instruction address and the branch destination instruction address. Then, the label detection unit 804 outputs label information 805 composed of an instruction including the label and information about a value to which the label is resolved.
In order to solve the label information 805 obtained by the label detection unit 804, the lower address subtraction unit 806, the upper address subtraction unit 809, and the address difference calculation unit 811 calculate the PC relative value as follows.

The lower address subtracting means 806 subtracts the lower 3 bits of the branch instruction address from the lower 3 bits of the branch destination instruction address to calculate a borrow number 807 and a lower subtraction result 808.
The upper address subtracting means 809 subtracts the upper 29 bits of the temporary address of the branch instruction from the upper 29 bits of the temporary address of the branch destination instruction and the number of borrows 807 calculated by the lower address subtracting means 806 to obtain the upper subtraction result 810. calculate.

The address difference calculation unit 811 calculates an address difference 812 in which the lower subtraction result 808 calculated by the lower address subtraction unit 806 is the lower 3 bits and the upper subtraction result 810 calculated by the upper address subtraction unit 809 is the upper 29 bits.
The label information resolution unit 813 replaces the label in the machine language code 803 with the address difference 812 calculated by the address difference calculation unit 811 and outputs the relocatable code 306 as a result.

Next, the operation of the assembler apparatus will be described using an example in which the optimization code of FIG. 13 output by the optimization apparatus 303 is input to the assembler apparatus 305.
FIG. 15 is a flowchart showing an operation procedure of the assembler apparatus.
First, the machine language code generation unit 802 converts the optimization code 304 into a machine language code 803 corresponding to the processor 309 for each packet. However, labels whose values are unresolved are stored in the machine language code 803 without being converted. The machine language code generation unit 802 allocates a packet address (hereinafter referred to as “local packet address”) and an in-packet address to each machine language code 803. FIG. 16 shows machine language code 803 generated from the optimized code of FIG. Note that the actual machine language code is expressed in a binary format consisting of only 0 and 1, but in FIG. 16, it is shown in a mnemonic format for convenience of explanation. Further, the parallel execution boundary information 100 and the bit format information 101 of each instruction have already been clarified at this stage, but are not particularly shown in this figure. In FIG. 16, packet addresses (local packet addresses) starting from 29'h00000000 are assigned. Further, since the label f in the instruction “jsrf” of the packet 1300, the label L2 in the instruction “movL2, r2” of the packet 1301, and the label L1 in the instruction “braL1” of the packet 1302 are unresolved, Not converted (steps S1500 and S1501).

  Next, the label detection unit 804 detects a label that is a local label among unresolved labels in the machine language code 803 and should be resolved to a PC relative value, and an address of an instruction including the label. That is, the address of the branch instruction and the address of the branch destination instruction are fetched. Then, the label detection unit 804 outputs label information 805 including information about the instruction including the label and the value to which the label is resolved. FIG. 17 shows label information created from the machine language code of FIG. The label L1 is detected as a local label that should be resolved to the PC relative value, 32'h00000012 is fetched as the branch instruction address, and the branch destination instruction address 32'h00000000 is fetched (step). S1502, S1503).

  Next, the lower address subtracting means 806 calculates the lower bits of the value indicated by L1 which is the PC relative value. The lower address subtracting means 806 subtracts the lower 3 bits 3'b010 of the address 32'h00000012 of the branch instruction 1409 from the lower 3 bits 3'b000 of the address 32'h00000000 of the branch destination instruction 1401. As a result, 1 is obtained as the number of borrows 807, and 3'b100 is obtained as the lower-order subtraction result 808 (step S1504).

  Next, the upper address subtracting means 809 calculates the upper bits of the value indicated by L1 which is the PC relative value. The high-order address subtracting means 809 subtracts the high-order 29 bits 29'h00000002 of the branch instruction 1409 address and 1 which is the borrow number 807 from the high-order 29 bits 29'h00000000 of the branch destination instruction 1401. As a result, 29'h1ffffffd (denotes -3 in decimal number, hereinafter, the negative number is represented by 2's complement) is obtained as the high-order subtraction result 810 (step S1505).

The address difference calculation means 811 calculates an address difference, that is, a PC relative value, with the lower order subtraction result 808 as the lower bits and the upper operation result 810 as the upper bits. In this example, 3′b100 is set as the lower bit and 29′h1ffffffd is set as the upper bit, so that 32′hffffffec as the address difference 812 is obtained (step S1506).
Next, when the address difference 812 can be expressed by the lower 13 bits, the label information resolution unit 813 uses the lower 13 bits of the address difference as a PC relative value, and when the address difference 812 cannot be expressed by the lower 13 bits, the address difference Is replaced with the label PC relative value in the machine language code 803 as the PC relative value. The address difference for resolving the label L1 in the label information of FIG. 16 is 32′hffffffec and can be represented by the lower 13 bits 13′h1fec. Therefore, the label L1 in the machine language code of FIG. Converted to a value. In this way, the machine language code is converted to generate a relocatable code. FIG. 18 shows a relocatable code generated from the machine language code 803 of FIG. An instruction 1609 in FIG. 18 is an instruction in which the label L1 is converted into a PC relative value. FIG. 18 shows the parallel execution boundary information 100 and the bit format information 101 of each instruction that has already been clarified when the machine language code 803 is output, and also shows that one bit in the packet is an unused bit. (Steps S1507, S1508, S1509).

As described above, it is possible to realize an assembler device for a processor corresponding to the carry method by calculating the PC relative value by performing the address calculation by the carry method. (Linker device)
FIG. 19 is a block diagram showing a configuration of the linker device 307 shown in FIG. 4 and related input / output data. Details of the linker device 307 will be described. The linker device 307 combines a plurality of relocatable codes 701 to determine the address of each instruction, and outputs an object code 308 that is an absolute address format that can be executed by the processor 309. The linker device 307 includes code combination means 702, relocation information detection means 704, lower address subtraction means 706, upper address subtraction means 709, address difference calculation means 711, and relocation information resolution means 713. The

The code combining unit 702 combines a plurality of input relocatable codes 701 and determines the addresses of all instructions. Then, the code combining means 702 resolves the label to be resolved to the instruction address to the above determined address, and outputs the resultant combined code 703.
The relocation information detection unit 704 searches for an external label to be resolved to a PC relative value, and takes in the address of the branch instruction and the address of the branch destination instruction. Then, the rearrangement information detection unit 704 outputs rearrangement information 705 including information about a command including a label and a value for which the label is resolved. In order to solve the relocation information obtained here, the lower address subtraction means 706, the upper address subtraction means 709, and the address difference calculation means 711 calculate the PC relative value as follows.

The lower address subtracting means 706 subtracts the lower 3 bits of the branch instruction address from the lower 3 bits of the branch destination instruction address to calculate a borrow number 707 and a lower subtraction result 708.
The upper address subtracting unit 709 subtracts the upper 29 bits of the branch instruction address from the upper 29 bits of the branch destination instruction address and the number of borrows 707 calculated by the lower address subtracting unit 706 to calculate the upper subtraction result 710. .

The address difference calculation unit 711 calculates an address difference 712 in which the lower subtraction result 708 calculated by the lower address subtraction unit 706 is the lower 3 bits and the upper subtraction result 710 calculated by the upper address subtraction unit 709 is the upper 29 bits.
The rearrangement information resolution unit 713 replaces the label in the combined code 703 with the address difference 712 calculated by the address difference calculation unit 711, and outputs the resulting object code 308.

Next, the operation of the linker device will be described using an example in which the relocatable code of FIG. 18 output from the assembler device 305 is input to the linker device 307.
FIG. 20 is a flowchart showing an operation procedure of the linker device.
First, the cord coupling means 702 couples a plurality of relocatable cords 701. FIG. 22 shows a state where the relocatable code 306 shown in FIG. 18 and the relocatable code shown in FIG. 21 generated separately are combined. That is, the first packet address of the relocatable code shown in FIG. 21 is 29'h00000000, and the first packet address of the relocatable code shown in FIG. 18 is 29'h00000001, and these two relocatable codes are combined (step S2000, S2001).

  As a result, the addresses of all the instructions have been determined. Therefore, the code combining means 702 further resolves the address of the label to be resolved into the address of the instruction, and obtains the combined code 703 as a result. Output. The address of the label L2 of the instruction 1810 “movL2, r2” illustrated in FIG. 22 is the head address of the packet 1815. Since the code combining means determines that the address is 32'h12345680, the label L2 is replaced with this value. FIG. 23 shows the connection code 703. The combined code 1910 in FIG. 23 indicates that the label L2 has been replaced with 32'h12345680 (step S2002).

  Next, the rearrangement information detection means 704 detects an external label to be resolved to the PC relative value in the combined code 703, and the address of the instruction included in the label, the address of the instruction where the label is placed, That is, the address of the branch instruction and the address of the branch destination instruction are fetched. Then, the rearrangement information detection unit 704 outputs rearrangement information 705 including information about a command including a label and a value for which the label is resolved. FIG. 24 shows label information created from the combined code of FIG. The label f is detected as an external label to be resolved to the PC relative value, 32'h0000000a is fetched as the branch instruction address, and the branch destination instruction address 32'h00000000 is fetched (steps S2003 and S2004).

  The lower address subtracting means 706 calculates the lower bits of the value indicated by f which is the PC relative value. The lower address subtracting means 706 subtracts the lower 3 bits 3'b010 of the address 32'h0000000a of the branch instruction 1906 from the lower 3 bits 3'b000 of the address 32'h00000000 of the branch destination instruction 1901. As a result, 1 is obtained as the number of borrows 707, and 3'b100 is obtained as the lower-order subtraction result 708 (step S2005).

  Next, the upper address subtracting means 709 calculates the upper bits of the value indicated by f which is the PC relative value. The high-order address subtracting means 709 subtracts 1 which is the number of borrows 707 from the high-order 29 bits 29'h00000001 of the address 32'h0000000a of the branch instruction 1906 from the high-order 29 bits 29'h00000000 of the address 32'h00000000 of the branch destination instruction 1901. . As a result, 29'h1ffffffe is obtained as the higher order subtraction result 710 (step S2006).

The address difference calculation means 811 calculates an address difference, that is, a PC relative value, with the lower order subtraction result 708 as the lower bits and the upper operation result 710 as the upper bits. 32′hfffffff4 which is an address difference 712 is obtained by setting 3′b100 as a lower bit and 29′h1ffffffe as an upper bit (step S2007).
Next, when the address difference 712 can be expressed by the lower 13 bits, the rearrangement information resolution unit 713 uses the lower 13 bits of the address difference as a PC relative value. Using the difference as the PC relative value, the label in the combined code 703 is replaced with the PC relative value. The address difference in which the label f in the relocation information in FIG. 23 is resolved is 32′hfffffff4 and can be represented by the lower 13 bits 13′h1ff4. Therefore, the label f in the combined code of FIG. Converted to a value. In this way, the combined code is converted and an object code is generated. FIG. 25 shows the object code. In FIG. 25, the object code 2106 indicates that the label f has been converted into a PC relative value (steps S2008, S2009, S2010).

As described above, by calculating the PC relative value by performing the address calculation by the carry method, it is possible to realize a linker device for a processor that supports the carry method. (Specific operation of the processor)
The operation of the processor will be described using an example in which the object code of FIG. 25 is stored in the instruction memory 407.

At the start of object code execution, the upper PC 403 is set to 29'h00000000, and the lower PC 404 is set to 3'b000. The prefetch upper counter 410 is set to 29′h00000000 in response to an input from the upper PC 403.
Reading of instructions from the instruction memory 407 is performed on a packet basis based on the prefetch upper counter 410. That is, of the instruction sequence stored in the instruction memory 407, the packet 2100 specified by the prefetch upper counter 410 is stored in the instruction buffer 408. Since the value of the prefetch upper counter 410 is incremented by 1 every cycle, it becomes 29′h00000001. Thereafter, the packet designated by the prefetch upper counter 410 is read from the instruction memory 407 to the instruction buffer 408 every cycle.

  Next, the operation of decoding and executing the instruction when the packet 2104 is designated by the upper PC 403 and the instruction 2107 in the packet 2104 is designated by the lower PC 404 will be described. The instructions stored in the instruction buffer 408 are interpreted by the instruction decoders 409a to 409c. The first instruction decoder 409a takes in the first unit 2107 stored in the instruction buffer 408 and checks whether the unit is a one-unit instruction or a parallel execution boundary. Since the unit 2107 is a single unit instruction and not a parallel execution boundary, the second instruction decoder 409b fetches the next unit 2109 and checks whether the unit is a single unit instruction or a parallel execution boundary. Since the unit 2109 is a single unit instruction and not a parallel execution boundary, the third instruction decoder 409c takes in the next unit, and checks whether the unit is a single unit instruction or a parallel execution boundary. Since that unit is not a single unit instruction, the third instruction decoder 409c also captures the next unit. Then, the third instruction decoder 409c knows that the unit is a parallel execution boundary. From the above, it can be seen that the instruction 2107, the instruction 2109, and the instruction 2110 can be executed in parallel.

  The first instruction decoder 409a decodes the instruction “addr0, r4” and outputs a control signal to the first arithmetic unit 401a. The first computing unit 401a adds the values of the register r0 and the register r4 and stores the result in the register r4. The second instruction decoder 409b decodes the instruction “andr1, r3” and outputs a control signal to the second arithmetic unit 401b. The second computing unit 401b performs a logical operation on the values of the register r1 and the register r3, and stores the result in the register r3. The third instruction decoder 409c decodes the instruction “mov32′h12345680, r2” and transfers the immediate value 32′h12345680 to the register r2.

  In addition, the instruction decoders 409a to 409c notify the INC 412 by the control signal that four units have been executed in this example. The INC 412 increments the values of the upper PC 403 and the lower PC 404 by four units. As a result, the lower PC 404 becomes 3'b000, the upper PC 403 has two carry and becomes 29'h00000003, and the head instruction to be executed in the next cycle becomes the instruction 2112.

  Next, the first instruction decoder 409a takes in the first unit 2112 stored in the instruction buffer 408 and checks whether the unit is a one-unit instruction or a parallel execution boundary. Since the unit 2112 is a single unit instruction and not a parallel execution boundary, the second instruction decoder 409b fetches the next unit 2113 and checks whether the unit is a single unit instruction or a parallel execution boundary. The second instruction decoder 409b knows that the unit 2113 is a single unit instruction and is a parallel execution boundary. From the above, it can be seen that the instruction 2112 and the instruction 2113 can be executed simultaneously in parallel.

  The first instruction decoder 409a decodes the instruction “ld (r2), r0”, fetches operand data having the value of the register r2 as an operand address from the data memory 406, and stores it in the register r0. The second instruction decoder 409b decodes the instruction “bra13′h1fec” and updates the upper PC 403 and the lower PC 404 to the addresses of the branch destination instructions because the instruction 2113 is a branch instruction.

  First, the addresses designated by the upper PC 403 and the lower PC 404 are corrected. The PC relative value is the difference in address from the branch instruction to the branch destination instruction, whereas the upper PC 403 and the lower PC 404 specify the address of the first instruction to be executed in that cycle, and are consistent. Therefore, the upper PC 403 and the lower PC 404 are corrected so as to specify the address of the branch instruction. That is, the INC 412 increments the values of the upper PC 403 and the lower PC 404 by the number of units 1 existing from the first instruction 2112 to the branch instruction 2113 in the execution unit. As a result, the upper PC is 29'h00000003 and the lower PC is 3'b010.

  Next, the upper PC calculator 411 and the lower PC calculator 405 add the values of the upper PC 403 and the lower PC 404 corrected as described above and the PC relative value 13'h1fec obtained from the second instruction decoder 409b. Here, a value 32'hffffffec that is sign-extended to 32 bits is used as the PC relative value. The addition is performed separately for the upper 29 bits and the lower 3 bits.

The lower PC calculator 405 adds the lower PC 3′b010 and the lower 3 bits 3′b100 of the PC relative value. As a result, the carry number 1 and the lower calculation result 3′b000 are obtained, the carry number is sent to the upper PC calculator 411, and the lower calculation result is transferred to the lower PC 404.
Next, the upper PC computing unit 411 adds the upper PC 29′h00000003, the upper 29 bits 29′h1ffffffd of the PC relative value, and the carry number 1. The upper calculation result 29′h00000001 is transferred to the upper PC 403 and is transferred from the upper PC to the prefetch upper counter 410. With the above processing, the prefetch upper counter 410 becomes 29'h00000001, and the next prefetch packet becomes the packet 2104. Further, the upper PC 403 is 29'h00000001, the lower PC 404 is 3'b000, and the first instruction to be executed in the next cycle is the instruction 2105.

In the same manner, the object code is sequentially read and executed in the same manner. The description of subsequent instructions is omitted.
The detailed configuration of the processor 309, the linker device 307, the assembler device 305, and the optimization device 303 shown in FIG. Since the compiler device 301 has the same configuration as a known compiler device, detailed description thereof is omitted.

Although the processor of this embodiment includes three instruction decoders 409a, 409b, and 409c and three arithmetic units 401a, 401b, and 401c, the present invention is not limited to this. These instruction decoders and one arithmetic unit may be included.
Alternatively, the function of the optimization device 303 may be taken into the compiler device 301, and the object code 308 may be generated from the source code 300 by the compiler device 301, the assembler device 305, and the linker device 307.

In this embodiment, the prefetch lower counter 413 is always set to 3′b000. However, the present invention is not limited to this. For example, the prefetch lower counter 413 may be incremented by 1 every cycle. In this case, 1-byte data is read from the instruction memory 407 to the instruction buffer 408 every cycle. (Second Embodiment)
The second embodiment relates to a processor, an optimization device, an assembler device, and a linker device using different PC relative values from those of the first embodiment as PC relative values for resolving labels in branch instructions.

In the first embodiment, the PC relative value of the branch instruction is a difference value between the address of the branch destination instruction and the address of the branch instruction. In this embodiment, the PC relative value of the branch instruction is the branch destination. The difference value between the instruction address and the start address of the execution unit.
In this embodiment, the meaning of the PC relative value is different from that in the first embodiment. However, the PC relative value is calculated on the program generation side, that is, the optimization device, the assembler device, and the linker device that calculate the program relative value, and on the program execution side, that is, the processor that calculates the original address from the program relative value. If used in the same meaning, the processor can correctly shift the value of the program counter to the branch destination instruction when the branch instruction is executed.

First, the optimization device 303, the assembler device 305, the linker device 307, and the processor 309 of this embodiment will be described.
The label detection unit 905 of the optimization device 303 creates label information for the “label to be resolved to the PC relative value” by fetching the temporary address of the branch instruction and the temporary address of the branch destination instruction in the first embodiment. Instead, the label information 906 is created by fetching the temporary address of the branch destination instruction and the address of the first instruction of the instruction group belonging to the same execution unit as the branch instruction. From this label information 906, as in the first embodiment, an address difference 913 that is a difference between two temporary addresses is calculated, and an optimization code 915 is calculated. The same applies to the assembler device and the linker device.

A specific example in which an object code is generated according to the present embodiment will be described.
The assembler device 305 subtracts the label L1 of the instruction 1409 in the machine language code of FIG. 16 by subtracting the address 32′h00000010 of the instruction 1408 that is the head of the execution unit of the instruction 1409 from the address 32′h00000000 of the branch destination instruction Replace with 13'h1ff0. Similarly, the linker device 307 also subtracts the label f of the instruction 1906 in the combined code of FIG. 23 by subtracting the address 32′h00000008 of the instruction 1907 that is the head of the execution unit of the instruction 1906 from the branch destination address 32′h00000000. Replace with 13'h1ff8. FIG. 26 shows the object code generated in this way. 26 shows that the PC relative values of the instruction 2206 and the instruction 2213 are different from those shown in FIG.

Next, the processor of this embodiment will be described.
The processor 309 executes the object code created as described above. When the processor 309 executes a branch instruction, the PC relative value in the branch instruction is a difference value between the address specified by the upper PC 403 and the lower PC 404 at that time and the address of the branch destination instruction. Accordingly, the processor 309 does not perform the process of correcting the values of the upper PC 403 and the lower PC 404, and similarly to the first embodiment, the value of the upper PC 403 and the value of the lower PC 404 and the PC relative value in the branch instruction. And the addition result is updated to the values of the upper PC 403 and the lower PC 404. When the processor executes the object code shown in FIG. 26, when the instruction 2213 is executed, the current PC value 32'h00000008 and the PC relative value 13'h1ff8 are added, and PC is added to the added value 32'h00000000. Update.

As described above, the processor according to the present embodiment does not require the process of correcting the value of the program counter as in the first embodiment when executing the branch instruction, and directly compares the PC relative value and the PC value. The address of the branch destination can be obtained by adding and so the execution time can be shortened. (Third embodiment)
The third embodiment relates to a processor capable of specifying the execution position of an instruction by fully utilizing the lower 3 bits of the instruction address.

In the first embodiment, the positions of the three units are specified using the lower 3 bits of the instruction address. However, in this embodiment, the lower 3 bits of the instruction address are fully utilized. The position of 8 units is designated.
FIG. 27A is a diagram illustrating a configuration of an instruction packet according to the present embodiment. The instruction packet is composed of 8 units. One unit of the instruction packet is 8 bits long, and the length of the instruction packet is 64 bits long. The processor reads an instruction with a fixed length of 64 bits in one cycle.

FIG. 27B shows the types of instructions. Each instruction is configured in units of 8 bits, and there are 2 unit instructions, 3 unit instructions, 5 unit instructions, and 6 unit instructions.
FIG. 27C is a diagram showing the relationship between the in-packet address and the unit in the packet specified by the in-packet address. The position in the instruction packet is designated by the lower 3 bits of the instruction address, as in the first embodiment. As shown in the figure, if the in-packet address is 3'b000, the first unit is specified. If 3'b001, the second unit is specified. If 3'b010, the third unit is specified. If 3'b011, the fourth unit is specified. 3′b100 specifies the fifth unit, 3′b101 specifies the sixth unit, 3′b110 specifies the seventh unit, and 3′b111 specifies the eighth unit.

As described above, the processor according to the present embodiment can specify the execution position of an instruction by making the maximum use of 3 bits of the lower address of the instruction, so that the execution unit of the instruction in one cycle can have variations. . (Fourth embodiment)
The fourth embodiment relates to a method for calculating the address of an instruction using the no carry method.
In the first embodiment, a processor that executes a program and an optimization device, an assembler device, and a linker device that create a program all use a carry address calculation method in common, so that the processor uses a PC relative Although the address of the branch destination instruction could be reproduced without error from the value, the processor, the optimization device, the assembler device, and the linker device could share the same operation method for addresses other than the carry method. As long as an arithmetic method is used, there is a processor that can reproduce the address of the branch destination instruction without error. The present embodiment relates to a no carry method, which is one of such other address calculation methods.

The no carry method is the same as the carry method of the first embodiment in that the instruction address is divided into upper 29 bits and lower 3 bits and is operated. It differs from the carry method in that no borrowing is generated.
First, a method performed by the processor 309 to obtain the address of the branch destination instruction by adding the address of the branch instruction and the PC relative value will be described. The lower PC calculator 405 shown in FIG. 5 adds the lower 3 bits of the branch instruction address and the lower 3 bits of the PC relative value. FIG. 28A is an addition table showing an addition rule between the lower 3 bits of the address of the branch instruction and the lower 3 bits of the PC relative value by the address operation of the no carry method according to the present embodiment. As shown in the figure, the addition of the lower 3 bits is a ternary operation that cycles through 3′b000, 3′b010, and 3′b100, unlike a normal binary operation. This operation does not generate a carry.

The upper PC calculator 411 shown in FIG. 5 adds the upper 29 bits of the branch instruction address and the upper 29 bits of the PC relative value. The method of adding the upper 29 bits of the address of the branch instruction to the upper 29 bits of the PC relative value is a normal binary operation.
The addition result calculated as described above becomes the address of the branch destination instruction. That is, the lower 3 bits of the addition result are set in the lower PC 404, and the upper 29 bits of the addition result are set in the upper PC 403.

  Next, an operation for obtaining the PC relative value performed by the optimization device 303, the assembler device 305, and the linker device 307, that is, a method of subtracting the branch instruction address from the branch destination instruction address will be described. Subtraction is performed by separating the upper 29 bits and the lower 3 bits as in the addition. The lower address subtracting means 907 of the optimizing device 303, the lower address subtracting means 806 of the assembler device 305, and the lower address subtracting means 706 of the linker device 307 are the lower 3 bits of the branch instruction address from the lower 3 bits of the branch destination instruction address. Is subtracted. FIG. 28B is a subtraction table showing a subtraction rule between the lower 3 bits of the address of the branch destination instruction and the lower 3 bits of the address of the branch instruction by the address operation of the no carry method according to the present embodiment. As shown in the figure, the subtraction of the lower 3 bits is a ternary operation that cycles through 3'b000, 3'b010, and 3'b100, unlike a normal binary operation. This operation does not cause borrowing.

The upper address subtracting means 910 of the optimizing device 303, the upper address subtracting means 809 of the assembler device 305, and the upper address subtracting means 709 of the linker device 307 are the upper 29 bits of the branch instruction address and the upper 29 bits of the branch destination instruction. And subtract. The subtraction method is a normal binary operation.
The value obtained by subtracting the lower 3 bits calculated as described above from the lower 3 bits and the upper 29 bits from the subtraction result from the upper 29 bits is the PC relative value.

FIG. 29 shows an object code generated by address calculation using the no carry method according to the present embodiment. In FIG. 29, the PC relative values of the instruction 2406 and the instruction 2413 are different from those in FIG. A method for calculating the PC relative value of the instruction 2406 will be described.
The lower address subtraction means 706 subtracts the lower 3 bit address 3′b010 of the instruction 2406 from the lower 3 bit address 3′b000 of the instruction 2401 according to the subtraction table shown in FIG. obtain.

The upper address subtracting means 709 subtracts the upper 29-bit address 29′h00000001 of the instruction 2406 from the upper 29-bit address 29′h00000000 of the instruction 2401 to obtain an upper subtraction result 29′h1ffffffff.
The address difference calculation means 711 calculates an address difference 32′h1ffffffc with the upper subtraction result 29′h1fffffff as the upper 29 bits and the lower subtraction result 3′b100 as the lower 3 bits.

Since the address difference 32′h1ffffffc can be expressed by the lower 13 bits 13′h1ffc, the rearrangement information resolution unit 713 generates the instruction 2406 by replacing the label with 13′h1ffc as the PC relative value.
The processor 309 executes the object code created as described above. When executing the branch instruction, the processor 309 adds the PC relative value in the branch instruction and the values of the upper PC 403 and the lower PC 404 corrected so as to specify the address of the branch instruction by the no carry method.

  When the processor executes the instruction 2406 in the object code shown in FIG. 29, the lower PC calculator 405 adds the corrected value 3′b010 of the lower PC 404 and the lower 3 bits 3′b100 of the PC relative value. Then, the lower PC 404 is updated to the addition value 3′b000, and the upper PC computing unit 411 adds the corrected value 29′h00000001 of the upper PC 403 and the upper 29 bits 29′h1fffffff of the PC relative value to add. The upper PC 403 is updated to the value 29′h00000000.

As described above, in the address calculation based on the no carry method, the carry number or the borrow number is not sent from the lower PC calculator to the upper PC calculator, so that the address calculation can be realized by simple hardware. (Fifth embodiment)
The fifth embodiment relates to an instruction address calculation method using an absolute value method.
The absolute value method is the same as the carry method of the first embodiment in that the instruction address is divided into upper 29 bits and lower 3 bits for operation, but the lower 3 bit address value of the instruction is lower. It differs from the carry method in that it is a 3-bit operation result.

  First, a method performed by the processor 309 to obtain the address of the branch destination instruction by adding the address of the branch instruction and the PC relative value will be described. The lower PC calculator 405 shown in FIG. 5 adds the lower 3 bits of the branch instruction address and the lower 3 bits of the PC relative value. FIG. 30A is an addition table showing an addition rule for the lower 3 bits of the address of the branch instruction and the lower 3 bits of the PC relative value by the absolute value type address calculation according to the present embodiment. As shown in the figure, the lower 3 bits of the PC relative value become the addition result of the lower 3 bits.

The upper PC calculator 411 shown in FIG. 5 adds the upper 29 bits of the branch instruction address and the upper 29 bits of the PC relative value. The method of adding the upper 29 bits of the address of the branch instruction to the upper 29 bits of the PC relative value is a normal binary operation.
The addition result calculated as described above becomes the address of the branch destination instruction. That is, the lower 3 bits of the addition result are set in the lower PC 404, and the upper 29 bits of the addition result are set in the upper PC 403.

  Next, an operation for obtaining a PC relative value performed by the optimization device 303, the assembler device 305, and the linker device 307, that is, a subtraction method for subtracting the branch instruction address from the branch destination instruction address will be described. Subtraction is performed by separating the upper 29 bits and the lower 3 bits as in the addition. The lower address subtracting means 907 of the optimizing device 303, the lower address subtracting means 806 of the assembler device 305, and the lower address subtracting means 706 of the linker device 307 are the lower 3 bits of the branch instruction address from the lower 3 bits of the branch destination instruction address. Is subtracted. FIG. 30B is a subtraction table showing a subtraction rule between the lower 3 bits of the address of the branch destination instruction and the lower 3 bits of the address of the branch instruction by the absolute value type address calculation according to the present embodiment. As shown in the figure, the lower 3 bits of the address of the branch destination instruction become the addition result of the lower 3 bits.

The upper address subtracting means 910 of the optimizing device 303, the upper address subtracting means 809 of the assembler device 305, and the upper address subtracting means 709 of the linker device 307 are the upper 29 bits of the branch instruction address and the upper 29 bits of the branch destination instruction. And subtract. The subtraction method is a normal binary operation.
The value obtained by subtracting the lower 3 bits calculated as described above from the lower 3 bits and the upper 29 bits from the subtraction result from the upper 29 bits is the PC relative value.

FIG. 31 shows an object code generated by an absolute value type address calculation according to the present embodiment. In FIG. 31, the PC relative values of the instruction 2606 and the instruction 2613 are different from those in FIG. A method for calculating the PC relative value of the instruction 2606 will be described.
The lower address subtraction means 706 subtracts the lower 3 bit address 3'b010 of the instruction 2606 from the lower 3 bit address 3'b000 of the instruction 2601 according to the subtraction table shown in FIG. obtain.

The upper address subtracting means 709 subtracts the upper 29-bit address 29′h00000001 of the instruction 2606 from the upper 29-bit address 29′h00000000 of the instruction 2601 to obtain the upper subtraction result 29′h1ffffffff.
The address difference calculation means 711 calculates an address difference 32′h1ffffff8 with the upper subtraction result 29′h1fffffff as the upper 29 bits and the lower subtraction result 3′b000 as the lower 3 bits.

Since the address difference 32′h1ffffff8 can be expressed by the lower 13 bits 13′h1ff8, the rearrangement information resolution unit 713 generates the instruction 2606 by replacing the label with 13′h1ff8 as the PC relative value.
The processor 309 executes the object code created as described above. When executing the branch instruction, the processor 309 adds the PC relative value in the branch instruction and the values of the upper PC 403 and the lower PC 404 corrected so as to specify the address of the branch instruction by an absolute value method.

  When the processor executes the instruction 2606 in the object code shown in FIG. 31, the lower PC calculator 405 adds the corrected value 3′b010 of the lower PC 404 and the lower 3 bits 3′b000 of the PC relative value. Then, the lower PC 404 is updated to the addition value 3′b000, and the upper PC computing unit 411 adds the corrected value 29′h00000001 of the upper PC 403 and the upper 29 bits 29′h1fffffff of the PC relative value to add. The upper PC 403 is updated to the value 29′h00000000.

As described above, in the address calculation based on the absolute value method, the calculation of the lower bits is unnecessary, so that the calculation speed can be increased. (Sixth embodiment)
The sixth embodiment relates to an instruction address calculation method using a linear method.
In the linear method, unlike the other embodiments, the instruction address is calculated by separating the upper 29 bits and the lower 3 bits.

  First, a method performed by the processor to obtain the address of the branch destination instruction by adding the address of the branch instruction and the PC relative value will be described. The carry type processor had a high-order PC computing unit that computes an upper 29-bit address and a low-order PC computing unit that computes a low-order 3 bit address, whereas a linear type processor computes a 32-bit address. One PC arithmetic unit is provided. The linear PC calculator adds the address of the 32-bit branch instruction and the 32-bit PC relative value. The addition method is a normal binary operation.

The addition result calculated as described above becomes the address of the branch destination instruction. That is, the lower 3 bits of the addition result are set in the lower PC 404, and the upper 29 bits of the addition result are set in the upper PC 403.
Next, an operation for obtaining the PC relative value performed by the optimization device 303, the assembler device 305, and the linker device 307, that is, a method of subtracting the branch instruction address from the branch destination instruction address will be described. The linear optimization device 303, the assembler device 305, and the linker device 307 are provided with one address subtracting means for calculating a 32-bit address, like the linear processor. The linear address subtracting means subtracts the address of the 32-bit branch instruction from the address of the 32-bit branch destination instruction. The subtraction method is a normal binary operation.

The subtraction result calculated as described above becomes the PC relative value.
FIG. 32 shows an object code generated using the linear address calculation according to the present embodiment. FIG. 32 shows that the PC relative values of the instruction 2706 and the instruction 2713 are different from those in FIG. A method for calculating the PC relative value of the instruction 2706 will be described.

The linear address subtracting means subtracts the 32-bit address 32′h0000000a of the instruction 2706 from the 32-bit address 32′h00000000 of the instruction 2701 to obtain an address difference 32′hfffffff6.
Since the relocation information resolution means 713 can express the address difference 32′hfffffff6 with the lower 13 bits 13′h1ff6, the instruction 2706 is generated by replacing the label with 13′h1ff6 as the PC relative value.

The processor 309 executes the object code created as described above. When executing the branch instruction, the processor 309 adds the PC relative value in the branch instruction and the values of the upper PC 403 and the lower PC 404 corrected so as to specify the address of the branch instruction by a linear method.
When the processor executes the instruction 2706 in the object code shown in FIG. 32, the PC computing unit of the present embodiment sets the corrected value of the upper PC 403 as the upper 29 bits and sets the corrected value of the lower PC 404 as the lower 3 The 32-bit PC value 32′h0000000a, which is a bit, is added to the PC relative value 32′hfffffff6 to obtain an addition result 32′h00000000. Then, the PC computing unit updates the lower PC 404 to the lower 3 bits 3′b000 of the addition value, and updates the upper PC 403 to the upper 29 bits 29′h00000000 of the addition value.

As described above, in the address calculation by the linear method, a normal arithmetic unit can be used as the PC arithmetic unit, so that the configuration of the processor can be simplified. (Seventh embodiment)
The seventh embodiment relates to a processor that interprets and executes a PC addition instruction and a PC subtraction instruction, and a compiler apparatus that generates these instructions.

FIG. 33 is a block diagram of the processor according to the present embodiment. The processor of this embodiment is different from the processor according to the first embodiment shown in FIG. 5 in that a second lower PC calculator 2800 and a second upper PC calculator 2802 are added, and a first instruction decoder 2801a The functions of the second instruction decoder 2801b and the second instruction decoder 2801c have been added.
The instruction decoders 2801a, 2801b, and 2801c decode a PC addition instruction and a PC subtraction instruction in addition to a normal instruction. FIG. 34 (a) shows the correspondence between mnemonics of PC addition instructions and operations. As shown in the figure, the PC addition instruction adds the PC relative value disp and the PC value stored in the register, and stores the result in the same register. FIG. 34 (b) shows the correspondence between mnemonics of PC subtraction instructions and operations. The PC subtraction instruction subtracts the PC relative value disp from the PC value stored in the register and stores the result in the same register.

The second lower PC calculator 2800 and the second upper PC calculator 2802 are arranged in accordance with the same operation rules as those of the lower PC calculator 405 and the upper PC calculator 411 in the first embodiment. Execute.
FIG. 35 is a configuration diagram of the compiler apparatus according to the present embodiment.
The source code 2901 is a program written in a high-level language such as C language.

The intermediate code conversion unit 2902 converts the source code 2901 into intermediate code 2903 that is an internal representation of the compiler apparatus. Since the intermediate code conversion unit 2902 is a known technique, a detailed description thereof is omitted.
The PC value addition instruction conversion unit 2904 converts the intermediate code for adding the PC value and the variable in the intermediate code 2903 into the assembler code 2906 of the PC addition instruction shown in FIG.

The instruction conversion unit 2905 converts other intermediate codes into corresponding assembler codes 2906. Since the instruction conversion unit 2905 is a known technique, a detailed description thereof is omitted.
Next, the operation of the compiler apparatus will be described using a specific example.
FIG. 36 is a flowchart showing the operation procedure of the compiler apparatus.
First, source code is input to the compiler apparatus. FIG. 37 shows source code written in C language. In the figure, external functions g1, g2, g3, and g4 are declared, and a function f is defined as a function that receives an int type variable i. The function f substitutes the address of the function g1 for the pointer fp if the value of i is 1, substitutes the address of the function g2 for the pointer fp if the value of i is 2, and the pointer fp if the value of i is 3. The address of the function g3 is substituted for, and if i is not the above value, the address of the function g4 is substituted for the pointer fp, and finally the function indicated by fp is called (step S3600).

  Next, the intermediate code conversion unit 2902 converts the source code into an intermediate code. At that time, in particular, the intermediate code conversion unit 2902 assigns the source code for assigning the pointer to the external function to the pointer variable, the difference value between the top address of the function and the top address of the external function, and the top of the function. The temporary variable in which the address is stored is added, and the result is converted into an intermediate code that is assigned to the pointer variable.

  FIG. 38 shows intermediate code obtained by converting the source program of FIG. In the figure, an intermediate code 3201 is an intermediate code having a label f at the head of a function and substituting the current PC value, that is, the head address of the function f into a temporary variable tmp. The intermediate code 3202 is an intermediate code for determining whether the variable i is not equal to 1. The intermediate code 3203 is an intermediate code that branches to the label L1 when the determination of the intermediate code 3202 is true, that is, when i is not equal to 1. The intermediate code 3204 is executed when i is equal to 1, and a difference value obtained by subtracting the head address of the function f from the head address of the function g1 and a temporary variable tmp to which the head address of the function f is substituted are obtained. This is an intermediate code that adds and assigns the result to the variable fp. The intermediate code 3205 is an intermediate code that branches to the label L.

  The intermediate code 3206 has the label L1 and is an intermediate code for determining whether the variable i is not equal to 2. The intermediate code 3207 is an intermediate code that branches to the label L2 when the determination of the intermediate code 3206 is true, that is, when i is not equal to 2. The intermediate code 3208 is executed when i and 2 are equal, and adds a difference value obtained by subtracting the head address of the function f from the head address of the function g2 and a temporary variable tmp into which the head address of the function f is substituted, This is an intermediate code that assigns the result to the variable fp. The intermediate code 3209 is an intermediate code that branches to the label L.

  The intermediate code 3210 has the label L2 and is an intermediate code for determining whether the variable i is not equal to 3. The intermediate code 3211 is an intermediate code that branches to the label L3 when the determination of the intermediate code 3210 is true, that is, when i is not equal to 3. The intermediate code 3212 is executed when i is equal to 3, and adds a difference value obtained by subtracting the start address of the function f from the start address of the function g3 and a temporary variable tmp into which the start address of the function f is assigned, This is an intermediate code that assigns the result to the variable fp. The intermediate code 3213 is an intermediate code that branches to the label L.

The intermediate code 3214 has a label L3, adds a difference value obtained by subtracting the start address of the function f from the start address of the function g4, and a temporary variable tmp into which the start address of the function f is assigned, and the result is added to the variable fp. This is the intermediate code assigned to. The intermediate code 3215 is an intermediate code having a label L and calling a function indicated by the variable fp.
As described above, the intermediate code shown in FIG. 38 does not assign the absolute addresses of the functions g1, g2, g3, and g4 to the variable fp, but the beginning address of the function f and the beginnings of the functions g1, g2, g3, and g4. The difference value from the address is added to the head address of the function f and substituted into the variable fp (steps S3601 to S3603).

  Next, the PC value addition instruction conversion unit 2904 and the intermediate code are converted into an assembler code. The PC value addition instruction conversion unit 2904 searches for an intermediate code that adds the PC value and the PC relative value, and converts the intermediate code into an assembler code that uses the second lower PC calculator 2800 and the second upper PC calculator 2802. Convert. The instruction conversion unit 2905 converts other intermediate code into assembler code.

  The PC value addition instruction conversion unit 2904 is obtained by transferring the PC value from the operand tmp of the intermediate code 3204 in FIG. 38 using the intermediate code 3201, and the operator + is the PC value and the PC relative value. The intermediate code 3204 is converted into an assembler code addpc for performing addition using the second lower PC calculator 2800 and the second upper PC calculator 2802. The PC value addition instruction conversion unit 2904 similarly converts the intermediate codes 3208, 3212, and 3214 into assembler code addpc. Other intermediate codes in FIG. 38 are converted by the instruction conversion unit 2905.

  FIG. 39 shows an assembler code obtained by converting the intermediate code shown in FIG. In the figure, an assembler code 3301 is an instruction having a label f at the head of the function and transferring the PC value to the register r1. The assembler code 3302 is an instruction for determining whether the value of the constant 1 and the register r0 are not equal. The assembler code 3303 is an instruction that branches to the label L1 when the determination by the instruction 3302 is true. The assembler code 3304 displays a PC relative value that is a difference value between the start address of the function g1 and the start address of the function f and a PC value that is the start address of f stored in the register r1 as a second lower-order PC computing unit 2800. Are added by the second higher-order PC computing unit 2802 and the result is transferred to the register r1. The assembler code 3305 is an instruction that branches to the label L.

  The assembler code 3306 is an instruction having a label L1 and determining whether the value of the constant 2 and the register r0 are not equal. The assembler code 3307 is an instruction that branches to the label L2 when the determination of the instruction 3306 is true. The assembler code 3308 is a second lower-order PC computing unit that calculates the PC relative value, which is the difference between the start address of the function g2 and the start address of the function f, and the PC value, which is the start address of f stored in the register r1. This is an instruction to add 2800 and the second upper PC calculator 2802 and transfer the result to the register r1. The assembler code 3309 is an instruction that branches to the label L.

  The assembler code 3310 is an instruction having a label L2 and determining whether the value of the constant 3 and the register r0 are not equal. The assembler code 3311 is an instruction that branches to the label L3 when the determination of the instruction 3310 is true. The assembler code 3312 is a second lower-order PC computing unit that calculates the PC relative value that is the difference between the start address of the function g3 and the start address of the function f and the PC value that is the start address of f stored in the register r1. This is an instruction to add 2800 and the second upper PC calculator 2802 and transfer the result to the register r1. The assembler code 3313 is an instruction that branches to the label L.

  The assembler code 3314 has a label L3, and stores the PC relative value, which is the difference between the start address of the function g4 and the start address of the function f, and the PC value, which is the start address of f stored in the register r1. This instruction is added by the second lower PC calculator 2800 and the second upper PC calculator 2802 and the result is transferred to the register r1. The assembler code 3315 has a label L and is an instruction for calling a function indicated by r1. Assembler code 3316 is an instruction to end the function.

  As described above, the compiler apparatus according to the present embodiment transfers the address to the external function g to the register r1 when there is source code for substituting the pointer to the external function g into the pointer variable in the function f. Rather than generating the instruction (movr1, g), the difference value (g−f) between the address of the function f and the address of the external function g is added to the address of the function f stored in the register r1, An instruction (addPC g-f r1) for transferring the result to the register r1 is generated. Since the PC relative value g−f is smaller than the absolute address g1, the code size can be reduced by using the addpc instruction. Further, in the PIC code in which the address on the memory of the program is determined at the time of execution, a code expression that avoids the absolute address is required, and an arithmetic instruction using this PC relative value is indispensable.

  The assembler code output by the compiler apparatus according to the present embodiment is converted into object code executed by the processor by the optimization apparatus 303, the assembler apparatus 305, and the linker apparatus 307, as in the first embodiment. The processor executes the PC addition instruction addPC g-f r1 included in the generated object code by the second lower PC calculator 2800 and the second upper PC calculator 2802. That is, the second lower PC calculator 2800 adds the lower 3 bits of the constant value g−f and the lower 3 bits of the numerical value stored in the register r1, and if there is a carry, the carry number is calculated by the second upper PC calculation. Send to vessel 2802. The second upper PC calculator 2802 adds the upper 29 bits of the constant value g−f and the upper 29 bits of the numerical value stored in the register r1, and if there is a carry from the second lower PC calculator 2800, the digit. Also add the number of uplinks. The value obtained by setting the addition result by the second lower PC calculator 2800 as the lower 3 bits and the addition result by the second upper PC calculator 2802 as the upper 29 bits is stored in the register r1.

The instruction shown in FIG. 35 is addition / subtraction between a constant value and a register. However, the present invention is not limited to this, and addition / subtraction between registers and addition / subtraction between PCs and registers can also be performed.
The calculation method of the second lower PC calculator 2800 and the second upper PC calculator 2802 is not limited to the carry method of the first embodiment, and the optimization device 303 and the assembler device that generate the object code If the processor adopts the same method as that used in 305 and the linker device 307, any one of the no carry method, the linear method, and the absolute value method may be used. (Eighth embodiment)
The eighth embodiment relates to a debugger device and a disassembler device.

FIG. 40 is a block diagram showing the configuration of the debugger device and the disassembler device according to this embodiment.
The input control unit 4000 receives an input from the operator and controls other components according to the input content.
The packet address specifying unit 4001 calculates the upper 29 bits of the address of the input instruction.

The in-packet address specifying unit 4002 calculates the lower 3 bits of the address of the input instruction.
The instruction memory 4004 holds instructions to be debugged and disassembled. The instruction address is the same as in the first embodiment, and is a 32-bit value in which the packet address is the upper 29 bits and the in-packet address is the lower 3 bits. FIG. 40 shows a state in which the instruction shown in FIG. 24 is stored.

The instruction reading unit 4003 reads an instruction packet specified by the packet address specified by the packet address specifying unit 4001 from the instruction memory 4004.
The instruction buffer 4005 stores the instruction packet read from the instruction memory 4004 by the instruction reading unit 4004.
The instruction decoding unit 4006 takes out the unit having the in-packet address specified by the in-packet address specifying unit 4002 from the instruction buffer 4005, and decodes the extracted unit. If the unit is a branch instruction, the instruction decoding unit 4006 sends the PC relative value 4007 to the lower PC calculator 4008 and the upper PC calculator 4009.

The label table 4011 is a table that holds a correspondence between a label name and an instruction address of the label. The label table 4011 is created by extracting from the optimized code when the assembler apparatus described in the first embodiment generates a machine language code.
In FIG. 40, it is shown that the address 32′h00000000 corresponds to the label name f, the address 32′h00000008 corresponds to the label name L1, and the address 32′h1345680 corresponds to the label name L2.

The display unit 4012 displays the result of disassembling instructions.
The instruction replacement unit 4013 writes the input instruction after replacement into the unit specified by the in-packet address specified by the in-packet address specifying unit 4002 in the instruction buffer 4005.
The instruction writing unit 4014 rewrites the instruction packet having the packet address specified by the packet address specifying unit 4001 in the instruction memory 4004 to the replaced instruction packet in the instruction buffer 4005.

The upper PC calculator 4009 calculates the upper 29 bits of the address of the instruction specified by the packet address specifying unit 4001 and the upper 29 bits of the PC relative value 4007.
The lower PC calculator 4008 calculates the lower 3 bits of the address of the instruction specified by the in-packet address specifying unit 4002 and the lower 3 bits of the PC relative value 4007. The calculation method of these PC calculators is the same as the method adopted in the object code generation process.

Next, the operation of the disassembler apparatus according to the present embodiment will be described using a specific example.
FIG. 41 is a flowchart showing the operation procedure of the disassembler apparatus.
First, the input control unit 4000 receives an input of a command for instructing disassembly and an address of an instruction to be disassembled. In a specific example, it is assumed that 32'h0000001a is input as an instruction address. (Step S4100).

  Next, the packet address specifying unit 4001 specifies the packet address from the upper 29 bits of the instruction address. Then, the instruction reading unit 4003 takes out an instruction packet having the specified packet address from the instruction memory 4004 and stores it in the instruction buffer 4005. In the specific example, 29′h00000003 is specified as the packet address, and an instruction packet including an instruction sequence of ld (r2), r0 || bra13′h1fec || add r2, r3 is stored in the instruction buffer 4005 (step S4101). .

  The in-packet address specifying unit 4003 specifies the in-packet address from the lower 3 bits of the instruction address, and notifies the instruction decoding unit 4006 of the unit having the specified in-packet address. The instruction decoding unit 4006 takes out the notified unit from the instruction buffer 4005. In the specific example, 3′b010 is specified as the in-packet address, and bra13′h1fec, which is the instruction of the second unit in the instruction buffer 4005, is input to the instruction decoding unit 4006 (step S4102).

The instruction decoding unit 4006 determines whether the fetched instruction is a branch instruction. In the specific example, the fetched instruction bra13′h1fec is a branch instruction (step S4103).
If it is a branch instruction, the PC relative value 4007 specified in the instruction and the address value of the input instruction are calculated. That is, the low-order PC computing unit 4008 adds or subtracts the in-packet address value of the input instruction and the low-order 3 bits of the PC relative value 4007, and sends the calculation result to the label search unit 4010. The upper PC calculator 4008 adds the packet address value of the input instruction, the upper 29 bits of the PC relative value 4007, and the number of carry or borrow from the lower PC calculator 4008 as the case may be. Alternatively, subtraction is performed, and the calculation result is sent to the label search unit 4010. The label search unit 4010 specifies the label address from the lower bit operation result and the upper bit operation result. In the specific example, the label address is specified as 32′h00000008 by the calculation of the input instruction address 32′h0000001a and the PC relative value 13′h1fec (steps S4103 and S4104).

Next, the label search unit 4010 searches the label name having the specified address with reference to the label table 4011. In the specific example, it is searched that the label name corresponding to the address 32′h00000008 is L1 (step S4107).
The display unit 4012 displays the assembler name of the branch instruction and the searched label name. In the specific example, bra, which is the assembler name of the branch instruction, and L1, which is the searched label name, are displayed (step S4108).

If the fetched instruction is not a branch instruction, the instruction decoding unit 4006 instructs the display unit 4012 to display the assembler name (step S4109).
Next, the operation of the debugger apparatus according to the present embodiment will be described using a specific example.
FIG. 42 is a flowchart showing the operation procedure of the debugger apparatus.
First, the input control unit 4000 receives an address of an instruction to be replaced with a command instructing debugging and an input of the instruction after replacement. In a specific example, it is assumed that 32′h0000001a is input as the address of the instruction to be replaced, and subtraction instructions subr0, r1 are input as the instruction after replacement (step S4200).

  Next, the packet address specifying unit 4001 specifies the packet address from the upper 29 bits of the address of the instruction to be replaced. Then, the instruction reading unit 4003 takes out an instruction packet having the specified packet address from the instruction memory 4004 and stores it in the instruction buffer 4005. In the specific example, 29′h00000003 is specified as the packet address, and an instruction packet including an instruction sequence of ld (r2), r0 || bra13′h1fec || add r2, r3 is stored in the instruction buffer 4005 (step S4201). .

Next, the in-packet address specifying unit 4002 specifies the in-packet address from the lower 3 bits of the address of the instruction to be replaced. In the specific example, 3′b010 is specified as the in-packet address (step S4202).
Next, if the specified in-packet address is 3′b000, the instruction replacement unit 4013 replaces the first unit of the instruction packet in the instruction buffer with the input instruction after replacement, and the specified in-packet address is If 3′b010, the second unit of the instruction packet in the instruction buffer is replaced with the input instruction after replacement. If the specified in-packet address is 3′b100, the third unit of the instruction packet in the instruction buffer is replaced. Replace with the replaced instruction entered. In the specific example, since the specified in-packet address is 3′b010, the instruction bra13′h1fec of the second unit is replaced with the replaced instructions subr0 and r1. As a result, the instruction packet in the instruction buffer 4005 becomes ld (r2), r0 || subr0, r1 || add r2, r3 (steps S4203 to S4207).

Then, the instruction writing unit 4014 replaces the instruction packet specified by the packet address in the instruction memory 4004 with the instruction packet stored in the instruction buffer 4005.
In the specific example, the instruction packet ld (r2), r0 || bra13'h1fec || add r2, r3 specified by the packet address 29'h00000003 in the instruction memory 4004 is the instruction packet ld (r2), r0 || subr0, r1 || add is replaced by r2, r3.

  As described above, the disassembler apparatus according to the present embodiment can disassemble instructions executed by the processor according to the first embodiment. Also, when the instruction to be disassembled is a branch instruction, the PC relative value is not displayed as it is, but the address where the label is placed is calculated by the upper PC calculator and the lower PC calculator, and the label is calculated from the address. By referring to the table, the appropriate label name can be displayed.

In addition, the debugger apparatus according to the present embodiment reads an instruction from the memory into the instruction buffer in units of byte-aligned instruction packets, rewrites the instruction in the instruction buffer, and writes the instruction into the memory in units of instruction packet. Suitable for debugging byte-aligned instructions.
Note that the calculation method of the upper PC calculator and the lower PC calculator in this embodiment is not limited to the carry method in the first embodiment, and any one of a separation method, an absolute value method, and a linear method is used. May be.

  The embodiments of the compiler device, the optimization device, the assembler device, the linker device, the processor, the disassembler device, and the debugger device according to the first to eighth embodiments have been described above, but the present invention is not limited to these embodiments. Of course, it is not limited to. (1) In the first to sixth embodiments, the assembler code 302, the optimization code 304, the relocatable code 306, and the object code 308 are a semiconductor integrated memory such as a mask ROM and a flash memory, a floppy (registered trademark) disk, a hard disk It is also possible to record on a magnetic recording medium such as CD-ROM or DVD. (2) In the seventh embodiment, the assembler code 2906 includes a semiconductor integrated memory such as a mask ROM and a flash memory, a magnetic recording medium such as a floppy (registered trademark) disk and a hard disk, and an optical disk such as a CD-ROM and DVD. Can also be recorded.

(Summary)
As is apparent from the above description, the present invention reads out an instruction based on the value of a program counter from a memory that stores an instruction using 1-byte data as one unit of data in the memory, and executes the instruction in one unit of the memory. A first program counter that holds a value that specifies a storage position in the memory of one unit data of the processor constituted by data or one unit data of a plurality of memories, and a processor included in the one unit data of the processor And a second program counter for holding a value for designating a position of one unit instruction of the processor indicating one operation to be executed.

  As a result, the first program counter designates the storage position in the memory of one unit data of the processor having a length in bytes, and the instruction is read from the memory based on the value. Further, the second program counter can designate the position of any one unit instruction of any processor included in one unit data of the processor read into the processor from the memory. That is, the instruction execution unit can be arbitrarily set regardless of the read unit. Therefore, even when the unit to be read from the memory to the processor must be a byte unit, an instruction whose instruction word length is not a byte unit can be executed.

  Here, the processor further includes a first program counter update unit and a second program counter update unit, and the second program counter update unit sets the value of the second program counter to one. Incremented by the number of instructions executed in the previous cycle, and if there is a carry, the number of carry is sent to the first program counter update means, and the first program counter update means May be added by the carry number sent from the second program counter updating means.

As a result, the value of the program counter can be incremented by the number of instructions executed by the processor, so that the program counter can be shifted to the head position of the instruction to be executed in the next cycle.
Here, in the processor, when the execution instruction is an instruction including a program counter relative value based on the address of the first instruction executed in the same cycle as the instruction, the program counter relative value is Program counter relative value extracting means for extracting, the value of the first program counter, the value of the second program counter, and the value of the program counter relative value are added, and the operation result is the value of the first program counter. And an arithmetic means for setting the value of the second program counter.

As a result, when the processor executes the branch instruction, the value of the program counter is added to the program counter relative value that is the difference between the program counter value when the branch instruction is executed and the address of the branch destination instruction. Since the program counter is updated to the addition result, the program counter can be shifted to the address of the branch destination instruction.
Here, the calculation means includes a first calculation unit and a second calculation unit, and the second calculation unit adds the value of the second program counter and the lower bits of the program counter relative value. The result of the addition is set as the value of the second program counter, and when there is a carry, the carry number is sent to the first arithmetic unit. When the first arithmetic unit adds the value of the first program counter and the upper bit of the relative value of the program counter, and further receives the carry number from the second arithmetic unit In the case where the carry number is added or the borrow number is received from the second calculation unit, the borrow number is subtracted and the result of the calculation is used as the value of the first program counter. Also features to set There.

As a result, when the processor executes a branch instruction, in the calculation of the program counter and the program counter relative value, the carry number or the borrow number generated in the lower bit calculation is considered in the upper bit calculation. It is possible to perform an address operation with continuity between the upper bit operation and the lower bit operation.
Here, the calculation means includes a first calculation unit and a second calculation unit, and the second calculation unit carries the value of the second program counter and the lower bits of the program counter relative value. Or adding without causing borrowing, and setting the result of the addition as the value of the second program counter, and the first operation unit calculates the value of the first program counter and the relative value of the program counter. The high-order bits may be added and the addition result set as the value of the first program counter.

  Thus, when the processor executes a branch instruction, the second program counter value and the lower bit of the program counter relative value are calculated from the second program counter value and the program counter relative value. Since the carry number or the borrow number is not sent to the first arithmetic unit that calculates the upper bits of the value, the second arithmetic unit and the first arithmetic unit need only operate independently from each other. Hardware can be used.

Here, the computing means adds the value of the first program counter and the upper bits of the program counter relative value, sets the addition result as the value of the first program counter, and sets the program counter relative The lower bits of the value may be set as the value of the second program counter.
As a result, when the processor executes the branch instruction, the operation of the value of the second program counter and the lower bits of the program counter relative value is not required, so that the execution speed of the branch instruction of the processor is increased.

  Here, the arithmetic means adds a value having the value of the first program counter as an upper bit, a value having the value of the second program counter as a lower bit, and the relative value of the program counter. The upper bit may be set as the value of the first program counter, and the lower bit of the addition result may be set as the value of the second program counter.

As a result, when the processor executes the branch instruction, the operation of the program counter value and the program counter relative value can be executed using a normal arithmetic unit, so that the configuration of the processor can be simplified.
Here, in the processor, when the execution instruction is an instruction including a program counter relative value based on the address of the instruction, a program counter relative value extraction unit that extracts the program counter relative value; Program counter correction means for correcting the value of the first program counter and the value of the second program counter so as to specify the address of the execution instruction, and the corrected value of the first program counter and the value of the first program counter And a calculation means for adding the value of the program counter of 2 and the relative value of the program counter and setting the addition result as the value of the first program counter and the value of the second program counter. It may be a feature.

As a result, the program counter relative value is expressed by the difference value between the branch instruction address and the branch destination instruction. Is no longer necessary.
Here, the processor decodes an add instruction for adding or subtracting a program counter relative value and a register counter or the value of the program counter stored in the first program counter and the second program counter. Program counter relative value calculation instruction decoding means, calculation means for adding or subtracting the program counter value and the program counter relative value to calculate the calculation result, a register or a first program counter in the calculation result, Program counter value updating means for updating the second program counter may be further provided.

  Thereby, instead of using an instruction for storing the absolute address of a function in a register, an instruction using an operation of a program counter and a program counter relative value can be used. Accordingly, since the program counter relative value can be expressed by a bit length shorter than the absolute address of the instruction, the code size of the program can be reduced. In addition, since an absolute address cannot be used in a PIC code in which an address on a memory of a program is determined for the first time at the time of execution, an operation instruction using this program counter and a program counter relative value is indispensable.

Here, when the length of one unit data of the processor is n bytes, the first program counter is one of the processors whose address is a value obtained by bit-shifting the value of the first program counter to the left by log2n. A memory address that is a storage position of the unit data in the memory may be specified.
As a result, when one address is assigned to each byte in the memory, the value of the first program counter and the unit data of each processor stored in the memory correspond one-to-one. Therefore, it is easy to specify one unit data of the processor.

Here, the processor is not limited to one unit data of the processor according to the instruction buffer for temporarily storing the instruction and the empty state of the instruction buffer, but the unit unit data of the memory is not limited to the unit data of the processor. It is also possible to further include an instruction reading means for reading out to the instruction buffer using the minimum unit as a minimum unit.
As a result, the read unit of the instruction read from the memory into the processor can be arbitrarily set, so that the mechanism for reading the instruction of the processor can be made flexible.

  In order to achieve the above object, the present invention provides an instruction sequence optimization device for generating an optimization code from an instruction sequence, predicting the size of each instruction in the instruction sequence, and for each instruction The upper bit designates a memory address in which one unit data of a processor composed of one unit data of a memory having a length of 1 byte or one unit data of a plurality of memories is stored. Address giving means for assigning an address for designating the position of one unit instruction of the processor indicating one operation executed by the processor included in one unit data, and the address of the specific instruction should be resolved from the instruction sequence The label is detected to obtain the address of the instruction, and the label to be resolved to the difference between the addresses of the two specific instructions is detected. When a label to be resolved and a label to be resolved by the difference between the addresses of the two specific instructions are detected, the address of the other instruction is determined from the address of one instruction of the specific two instructions. The program counter relative value calculating means for subtracting and calculating the program counter relative value, and the instruction having the label to be resolved to the address of the specific one instruction, the size of the address of the specific one instruction For an instruction having a label that should be resolved to the difference between the addresses of the two specific instructions, the instruction size corresponding to the magnitude of the program counter relative value. Conversion means for converting to the size of the instruction, and an optimization code for generating an optimized code by converting the address of each instruction according to the size of the converted instruction Characterized by comprising a code generating means.

Thus, it is possible to realize an optimization device that generates a program for a processor that executes a branch instruction.
Here, the program counter relative value calculating means includes an upper bit subtracting section and a lower bit subtracting section, and the lower bit subtracting section uses the lower bit of the address of one instruction of the specific two instructions to the other. Subtract the lower bit of the address of the instruction, set the subtraction result as the lower bit of the relative value of the program counter, and if there is a borrow, send the borrow number to the upper bit subtracting unit, The subtracting unit subtracts the high order bit of the address of the other instruction from the high order bit of the address of one of the specific two instructions, and further receives the borrowing number from the low order bit subtracting unit, The borrowing number may be subtracted, and the subtraction result may be set as the upper bits of the program counter relative value.

As a result, it is possible to realize an optimization device that generates a program targeted for a processor that calculates the address of a branch destination instruction by an address operation using a carry method when executing a branch instruction.
Here, the program counter relative value calculating means includes an upper bit subtracting section and a lower bit subtracting section, and the lower bit subtracting section uses the lower bit of the address of one instruction of the specific two instructions to the other. Subtracting the lower bit of the address of the instruction without causing borrowing, setting the subtraction result as the lower bit of the program counter relative value, and the upper bit subtracting unit is one of the two specific instructions The high order bit of the instruction address may be subtracted from the high order bit of the other instruction address, and the subtraction result may be set as the high order bit of the program counter relative value.

As a result, it is possible to realize an optimization device that generates a program for a processor that calculates an address of a branch destination instruction by an address operation using a no carry method when a branch instruction is executed.
Here, the program counter relative value calculation means subtracts the upper bit of the address of the other instruction from the upper bit of the address of the other instruction from the upper bit of the address of the one instruction of the specific two instructions. It may be set as an upper bit, and a lower bit of the address of one of the two specific instructions may be set as a lower bit of the program counter relative value.

As a result, it is possible to realize an optimization device that generates a program for a processor that calculates the address of a branch destination instruction by an address operation using an absolute value method when executing a branch instruction.
In order to achieve the above object, the present invention provides an assembler device for generating a relocatable code from an instruction sequence, wherein the upper bits are 1 unit data of a memory having a length of 1 byte or 1 unit data of a plurality of memories. The memory address where 1 unit data of the processor configured is stored is specified, and the lower bit specifies the position of the 1 unit instruction of the processor indicating one operation executed by the processor included in the 1 unit data of the processor An instruction sequence acquisition means for acquiring an instruction sequence including an instruction to which an address to be assigned is detected, a label to be resolved to a difference between addresses of two specific instructions in the instruction sequence, and an address of the two instructions Subtract the address of the other instruction from the address of one of the two specific instructions and the label detection means to obtain A program counter relative value calculating means for calculating a gram counter relative value, characterized in that a replacement means for replacing the label on the calculated program counter relative value.

Thus, it is possible to realize an assembler device that generates a program for a processor that executes a branch instruction.
Here, the program counter relative value calculating means includes an upper bit subtracting section and a lower bit subtracting section, and the lower bit subtracting section uses the lower bit of the address of one instruction of the specific two instructions to the other. Subtract the lower bit of the address of the instruction, set the subtraction result as the lower bit of the relative value of the program counter, and if there is a borrow, send the borrow number to the upper bit subtracting unit, The subtracting unit subtracts the high order bit of the address of the other instruction from the high order bit of the address of one of the specific two instructions, and further receives the borrowing number from the low order bit subtracting unit, The borrowing number may be subtracted, and the subtraction result may be set as the upper bits of the program counter relative value.

As a result, it is possible to realize an assembler device that generates a program for a processor that calculates the address of a branch destination instruction by an address operation using a carry method when a branch instruction is executed.
Here, the program counter relative value calculating means includes an upper bit subtracting section and a lower bit subtracting section, and the lower bit subtracting section uses the lower bit of the address of one instruction of the specific two instructions to the other. Subtracting the lower bit of the address of the instruction without causing borrowing, setting the subtraction result as the lower bit of the program counter relative value, and the upper bit subtracting unit is one of the two specific instructions The high order bit of the instruction address may be subtracted from the high order bit of the other instruction address, and the subtraction result may be set as the high order bit of the program counter relative value.

Thus, it is possible to realize an assembler device that generates a program for a processor that calculates an address of a branch destination instruction by an address operation using a no carry method when a branch instruction is executed.
Here, the program counter relative value calculation means subtracts the upper bit of the address of the other instruction from the upper bit of the address of the other instruction from the upper bit of the address of the one instruction of the specific two instructions. It may be set as an upper bit, and a lower bit of the address of one of the two specific instructions may be set as a lower bit of the program counter relative value.

Thus, it is possible to realize an assembler device that generates a program intended for a processor that calculates the address of a branch destination instruction by an address operation using an absolute value method when executing a branch instruction.
In order to achieve the above object, the present invention is a linker device that generates an object code by combining relocatable codes, and the upper bit is one unit data or a plurality of data in a memory having a length of 1 byte. A memory address in which 1 unit data of the processor configured by 1 unit data of the memory is stored is specified, and the lower bit indicates one unit of the processor indicating one operation executed by the processor included in the 1 unit data of the processor A relocatable code acquisition means for acquiring a relocatable code including an instruction to which an address for specifying an instruction is assigned, and a label to be resolved into a difference between addresses of two specific instructions from the relocatable code. A rearrangement information detecting means for acquiring an address of an instruction; A program counter relative value calculating means for calculating the program counter relative value by subtracting the address of the other instruction from the address of one instruction of the instruction, and a replacing means for replacing the label with the calculated program counter relative value. It is characterized by having.

As a result, a linker device that generates a program for a processor that executes a branch instruction can be realized.
Here, the program counter relative value calculating means includes an upper bit subtracting section and a lower bit subtracting section, and the lower bit subtracting section uses the lower bit of the address of one instruction of the specific two instructions to the other. Subtract the lower bit of the address of the instruction, set the subtraction result as the lower bit of the relative value of the program counter, and if there is a borrow, send the borrow number to the upper bit subtracting unit, The subtracting unit subtracts the high order bit of the address of the other instruction from the high order bit of the address of one of the specific two instructions, and further receives the borrowing number from the low order bit subtracting unit, The borrowing number may be subtracted, and the subtraction result may be set as the upper bits of the program counter relative value.

Thus, it is possible to realize a linker device that generates a program for a processor that calculates an address of a branch destination instruction by an address operation using a carry method when executing a branch instruction.
Here, the program counter relative value calculating means includes an upper bit subtracting section and a lower bit subtracting section, and the lower bit subtracting section uses the lower bit of the address of one instruction of the specific two instructions to the other. Subtracting the lower bit of the address of the instruction without causing borrowing, setting the subtraction result as the lower bit of the program counter relative value, and the upper bit subtracting unit is one of the two specific instructions The high order bit of the instruction address may be subtracted from the high order bit of the other instruction address, and the subtraction result may be set as the high order bit of the program counter relative value.

Accordingly, it is possible to realize a linker device that generates a program targeted for a processor that calculates the address of a branch destination instruction by an address operation using a no carry method when a branch instruction is executed.
Here, the program counter relative value calculation means subtracts the upper bit of the address of the other instruction from the upper bit of the address of the other instruction from the upper bit of the address of the one instruction of the specific two instructions. It may be set as a bit, and the lower bit of the address of one of the specific two instructions may be set as the lower bit of the program counter relative value.

Thus, it is possible to realize a linker device that generates a program targeted for a processor that calculates an address of a branch destination instruction by an address operation using an absolute value method when executing a branch instruction.
In order to achieve the above object, the present invention provides a disassembler device for designating an address of an instruction in an object code and outputting an assembler name of the instruction specified by the address, A memory address in which one unit data of a processor composed of one unit data of a memory having a length of 1 byte or one unit data of a plurality of memories is specified, and a lower bit is included in the one unit data of the processor Object code acquisition means for acquiring an object code composed of an instruction to which an address specifying the position of one unit instruction of the processor indicating one operation executed by the processor is provided, and the specified instruction includes a program counter relative value If it is an instruction, the program counter relative value is selected from the specified instructions. The program counter relative value extracting means to be output, the storage means for storing the label address indicating the label position and the label name in association with each other, adding the address of the designated instruction and the program counter relative value, and adding the result A label address calculating means for making a label address, and a searching means for searching for a label name corresponding to the calculated label address with reference to the storage means are provided.

  As a result, the program including the branch instruction can be disassembled. In other words, even when the instruction to be disassembled is a branch instruction, the address of the branch destination instruction is calculated from the program counter relative value, and the label name can be obtained by referring to the label table from the address. The branch destination can be presented to the user by a label name in a format that is easier to understand.

  Here, the label address calculation means includes an upper bit subtraction unit and a lower bit subtraction unit, and the lower bit subtraction unit includes a lower bit of the address of the designated instruction and a lower bit of the relative value of the program counter. The addition result is set as the lower bit of the label address, and when there is a carry, the carry number is sent to the upper bit calculation unit, and when there is a carry, the borrow number is set to the upper bit. When the upper bit subtraction unit adds the upper bit of the address of the designated instruction and the upper bit of the relative value of the program counter, and when the carry number is received from the lower bit calculation unit Adds the carry number or, when the borrowed number is received from the lower bit calculation unit, subtracts the borrowed number, and calculates the result of the calculation It may be characterized in that the upper bits of the bell address.

Thus, it is possible to realize a disassembler device for disassembling a program intended for a processor that calculates the address of a branch destination instruction by an address operation using a carry method when executing a branch instruction.
Here, the label address calculation means includes an upper bit subtraction unit and a lower bit subtraction unit, and the lower bit subtraction unit includes a lower bit of the address of the designated instruction and a lower bit of the relative value of the program counter. Are added without causing a carry or a borrow, and the addition result is used as the lower bits of the label address. Bits may be added, and the addition result may be the upper bits of the label address.

Accordingly, it is possible to realize a disassembler device that disassembles a program intended for a processor that calculates the address of a branch destination instruction by an address operation using a no carry method when executing a branch instruction.
Here, the label address calculation means adds the upper bit of the address of the designated instruction and the upper bit of the program counter relative value, and sets the addition result as the upper bit of the label address. The lower bit may be a lower bit of the label address.

Thus, it is possible to realize a disassembler device that disassembles a program intended for a processor that calculates the address of a branch destination instruction by an address operation using an absolute value method when executing a branch instruction.
In order to achieve the above object, the present invention provides a debugger device for designating an instruction address and a conversion instruction in an object code and replacing an instruction specified by the address with a conversion instruction. Designates a memory address where 1 unit data of a processor composed of 1 unit data of a memory having a length of 1 byte or 1 unit data of a plurality of memories is stored, and a lower bit indicates 1 unit data of the processor An object code acquisition means for acquiring an object code consisting of an instruction to which an address specifying the position of one unit instruction of the processor indicating one operation executed by the included processor is provided, and an upper bit of the address of the specified instruction 1 unit data of specified processor is read from memory and written to instruction buffer 1 unit data reading means of a processor, instruction writing means for writing the conversion instruction at a position of an instruction specified by a lower bit of an address of the designated instruction included in 1 unit data of the processor in the instruction buffer, 1 unit data writing means for the processor for returning 1 unit data of the processor in the instruction buffer after the instruction is written to the memory.

As a result, an instruction is read from the memory to the instruction buffer in units of 1-unit data of the processor, which has a length in bytes, and the instruction is rewritten in the instruction buffer, and the instruction is written to the memory in units of instruction packets. A debugger device that can debug even an instruction that is not unit length can be realized.
In order to achieve the above object, the present invention is a compiler apparatus for generating an instruction sequence from source code, wherein the upper bits are 1 unit data of a memory having a length of 1 byte or 1 unit data of a plurality of memories. The memory address where the 1 unit data of the processor configured is stored is specified, and the lower bit specifies the position of the 1 unit instruction of the processor indicating one operation executed by the processor included in the 1 unit data of the processor The program counter relative value calculation instruction is generated by adding or subtracting the program counter value and the program counter relative value to cause the processor to execute an instruction having the calculation result as the program counter value.

Thus, it is possible to realize a compiler device that generates a program for a processor that executes a program counter relative value calculation instruction.
Here, the program counter relative value calculation instruction adds or subtracts the lower bit of the program counter value and the lower bit of the program counter relative value, sets the calculation result as the lower bit of the program counter value, and carries a carry. In some cases, the number of carry is sent to the upper bit operation unit, and when there is a borrow, the lower bit operation unit that sends the number of borrowing to the upper bit operation unit is executed by the lower bit operation unit of the processor, and the program Add or subtract the upper bit of the counter value and the upper bit of the program counter relative value, and if the carry number is received from the lower bit calculation unit, add the carry number or the lower bit When the borrowing number is received from the calculation unit, the borrowing number is subtracted and the result of the calculation is displayed as the upper bit of the program counter value. It may be characterized in that to execute the high-order bit operation and bets the upper bit arithmetic unit of the processor.

As a result, when executing the program counter relative value calculation instruction, it is possible to realize a compiler device that generates a program for a processor that calculates the value of the program counter and the program counter relative value by the carry method.
Here, the program counter relative value calculation instruction adds or subtracts the lower bit of the value of the program counter and the lower bit of the program counter relative value without causing a borrow, and programs the calculation result. The lower bit operation part of the processor executes the lower bit operation to be the lower bit of the counter value, and adds or subtracts the upper bit of the program counter value and the upper bit of the program counter relative value, and the operation result is the program counter. It is also possible to cause the high-order bit calculation unit of the processor to execute high-order bit calculation that uses the high-order bit of the value of.

Thus, it is possible to realize a compiler device that generates a program for a processor that calculates the value of the program counter and the program counter relative value by the no carry method when executing the program counter relative value calculation instruction.
Here, the program counter relative value calculation instruction adds or subtracts the high order bit of the program counter value and the high order bit of the program counter relative value, and uses the calculation result as the high order bit of the program counter value. May be executed by an upper bit arithmetic unit of the processor, and the lower bit of the program counter relative value may be used as the lower bit of the value of the program counter.

  Thus, it is possible to realize a compiler device that generates a program for a processor that calculates the value of the program counter and the program counter relative value by the absolute value method when executing the program counter relative value calculation instruction.

  The processor according to the present invention can be used in a compiler device, an optimization device, an assembler device, and the like as a processor with improved instruction execution speed.

FIG. 1A shows the format of instructions executed by the processor of the first embodiment. FIG. 1B shows a format of instructions executed by the processor of the first embodiment. FIG. 1C shows the format of instructions executed by the processor of the first embodiment. FIG. 1D shows the format of instructions executed by the processor of the first embodiment.

FIG. 1E shows a format of instructions executed by the processor of the first embodiment.
FIG. 2A is a diagram illustrating an instruction packet which is a unit for storing and reading instructions. FIG. 2B is a diagram showing the order of reading instructions. FIG. 2C is a diagram showing the order of instruction execution. It is a figure which shows the example of the storing and reading method of an instruction | indication in the case of executing the instruction | command which is not byte-aligned in a normal processor. It is a figure which shows the process in which the object code which a processor performs is produced by a compiler apparatus, an optimization apparatus, an assembler apparatus, and a linker apparatus. It is a block diagram which shows the detail of the processor 309 and external memory. It is an increment table which shows the rule of the increment of the address in a packet. FIG. 7A is an addition table showing an addition rule between the lower 3 bits of the branch instruction address and the lower 3 bits of the PC relative value.

FIG. 7B is a subtraction table showing a subtraction rule between the lower 3 bits of the branch destination instruction address and the lower 3 bits of the branch instruction address.
It is a block diagram which shows the component of the optimization apparatus 303, and input-output data. 4 is a flowchart showing an operation procedure of the optimization device 303. A part of the optimization processing code 903 generated by the code optimization unit 902 is shown. An address assignment code 916 generated from the optimization processing code of FIG. 10 is shown. 12 shows label information 906 generated from the address assignment code of FIG. 12 shows an optimization code 915 generated from the address assignment code of FIG. It is a block diagram which shows the structure of the assembler apparatus 305, and related input / output data. 4 is a flowchart illustrating an operation procedure of an assembler device 305. FIG. 14 shows a machine language code 803 generated from the optimized code of FIG. The label information created from the machine language code of FIG. 16 is shown. FIG. 17 shows a relocatable code generated from the machine language code 803 of FIG. 16. FIG. It is a block diagram which shows the structure of the linker apparatus 307, and related input-output data. It is a flowchart which shows the operation | movement procedure of the linker apparatus 307. Indicates a relocatable code. The relocatable code | cord | chord 306 shown in FIG. 18 and the state couple | bonded with the relocatable code | cord | chord shown in FIG. 21 produced | generated separately are shown. A connection code 703 is shown. The label information created from the combined code of FIG. 23 is shown. 24 shows an object code generated from the combined code of FIG. The object code which concerns on 2nd Embodiment is shown. FIG. 27A shows a configuration of an instruction packet according to the third embodiment.

FIG. 27B shows the types of instructions.
FIG. 27C shows the relationship between the in-packet address and the unit in the packet specified by the in-packet address.
FIG. 28A is an addition table showing an addition rule between the lower 3 bits of the address of the branch instruction and the lower 3 bits of the PC relative value by the address operation of the no carry method according to the fourth embodiment.

FIG. 28B is a subtraction table showing a subtraction rule between the lower 3 bits of the address of the branch destination instruction and the lower 3 bits of the address of the branch instruction by the address operation of the no carry method according to the fourth embodiment. .
It is a specific example of the object code produced | generated using the address calculation of the no carry method based on 4th Embodiment. FIG. 30A is an addition table showing an addition rule for the lower 3 bits of the address of the branch instruction and the lower 3 bits of the PC relative value by the absolute value type address operation according to the fifth embodiment.

FIG. 30B is a subtraction table showing a subtraction rule between the lower 3 bits of the address of the branch destination instruction and the lower 3 bits of the address of the branch instruction by the absolute value type address operation according to the fifth embodiment.
It is a specific example of the object code produced | generated using the address calculation of the absolute value system which concerns on 5th Embodiment. The object code produced | generated using the linear type address calculation which concerns on 6th Embodiment is shown. It is a block diagram of the processor which concerns on 7th Embodiment. FIG. 34 (a) shows the correspondence between mnemonics of PC addition instructions and operations.

FIG. 34 (b) shows the correspondence between mnemonics of PC subtraction instructions and operations.
It is a block diagram of the compiler apparatus which concerns on 8th Embodiment. It is a flowchart which shows the operation | movement procedure of a compiler apparatus. The source code described in C language is shown. The intermediate code into which the source program of FIG. 37 was converted is shown. FIG. 40 shows an assembler code obtained by converting the intermediate code of FIG. It is a block diagram which shows the structure of the debugger apparatus and disassembler apparatus which concern on 8th Embodiment. It is a flowchart which shows the operation | movement procedure of a disassembler apparatus. It is a flowchart which shows the operation | movement procedure of a debugger apparatus. It is a block diagram which shows the basic composition of the conventional processor.

Explanation of symbols

100 Parallel execution boundary information 101 Bit format information 300 Source code 301 Compiler device 302 Assembler code 303 Optimization device 304 Optimization code 305 Assembler device 306 Relocatable code 307 Linker device 308 Object code 309 Processor 401a to 401c Operation unit 402 General-purpose register 403 High-order PC
404 Subordinate PC
405 Lower PC calculator 406 Data memory 407 Instruction memory 408 Instruction buffer 409a to 409c Instruction decoder 410 Upper fetch counter 411 Upper PC calculator 412 INC
413 Prefetch lower counter 420 PC relative value selector 421 Immediate value selector 422 Operand address buffer 423 Operand data buffer 424a-c Control signal 702 Code combining means 703 Combined code 704 Relocation information detecting means 705 Relocation information 706 Lower address subtracting means 707 Digit borrowing Number 708 Lower subtraction result 709 Upper address subtraction means 710 Upper subtraction result 711 Address difference calculation means 712 Address difference 713 Relocation information resolution means 802 Machine language code generation means 803 Machine language code 804 Label detection means 805 Label information 806 Lower address subtraction means 807 Number of digits borrowed 808 Lower subtraction result 809 Upper address subtraction means 810 Upper subtraction result 811 Address difference calculation means 812 Address difference 813 Information information resolution means 902 code optimization means 903 optimization processing code 904 address assignment means 905 label detection means 906 label information 907 lower address subtraction means 908 number of borrows 909 lower subtraction result 910 upper address subtraction means 911 upper subtraction result 912 address difference Calculation means 913 Address difference 914 Label information resolution means 916 Address assignment code 2800 Second lower PC calculator 2801a to 2801c Instruction decoder 2802 Second upper PC calculator 2901 Source code 2902 Intermediate code conversion unit 2903 Intermediate code 2904 PC value addition instruction conversion Part 2905 Instruction conversion part 2906 Assembler code 4000 Input control part 4001 Packet address specifying part 4002 In-packet address specifying part 4003 In-packet address Identification unit 4004 Instruction memory 4005 Instruction buffer 4006 Instruction decoding unit 4007 PC relative value 4008 Lower PC computing unit 4009 Upper PC computing unit 4010 Label search unit 4011 Label table 4012 Display unit 4013 Instruction replacement unit 4300 Program counter 4301 Instruction memory 4302 Instruction reading unit 4303 Instruction execution unit

Claims (1)

In a processor that reads instructions from memory,
One unit data of at least one memory consisting of a natural number of bytes is read from the memory. The one unit data of the memory includes one unit instruction of the processor indicating one operation, and the one unit data of each memory is executed by the processor. The number included in one unit data of the memory of one unit instruction of the processor indicating the one operation is a natural number excluding the power of 2,
The first program counter indicates a storage position in the memory of one unit data of the memory,
The second program counter makes a round with the number of stored one unit instructions of the processor indicating one operation included in one unit data of the memory, and one unit of the processor indicating the one operation in one unit data of the memory Indicates the instruction storage location,
After the second program counter makes a round of storage locations, the first program counter indicates the next storage location of one unit of data in the memory in the memory.

Images