JP4323174B2 - Memory control apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a memory control device used in an image encoding device or the like that performs processing of inputting an image frame, dividing it into macroblocks, encoding the macroblocks as processing units, and outputting a bitstream, and the like In particular, buffer overflow and underflow required for input / outputOccurrence ofTheDrasticallyThe present invention relates to a memory control device and a method thereof that can reduce the capacity of the buffers by enabling the avoidance.
[0002]
[Prior art]
Since a moving image encoding apparatus such as MPEG2 uses information in the spatial direction and the temporal direction in order to realize high compression, it is necessary to handle a large amount of data such as image data. In particular, in real-time encoding of HDTV images, it is important to ensure a large memory and a large memory bandwidth (bandwidth for accessing the memory) in order to encode a large amount of image data in real time. It is.
[0003]
For this reason, in the conventional memory control method used in the moving picture coding apparatus, in order to ensure the bandwidth of data transfer with the memory, it is realized by scheduling the data transfer order in advance at the time of design.
[0004]
FIG. 12 illustrates a device configuration of the moving image encoding device.
[0005]
As shown in this figure, the moving picture coding apparatus operates with (1) an image input unit for inputting an image frame from the outside in an interlaced or progressive manner, and (2) a macroblock divided from the image frame as a processing unit. And M (M ≧ 1) macroblock synchronous transfer units, and (3) an encoding process in units of macroblocks after input of divided frames obtained by dividing an image frame into N (N ≧ 1) N coding core units operating in parallel for outputting a divided bit stream, (4) a bit stream output unit for outputting a bit stream to the outside, (5) a memory, (6) a memory and an image input unit / The memory control unit that controls data transfer between the macroblock synchronous transfer unit / encoding core unit / bitstream output unit is employed.
[0006]
Here, in FIG. 12, it is assumed that one filter unit is provided as the M macroblock synchronous transfer units. The image input unit and the bit stream output unit have a small-capacity buffer. Also, the input image, the bit stream, and the data for macroblock processing are stored in a common memory.
[0007]
In the moving image encoding apparatus configured as described above, data transfer of the image input unit and the bit stream output unit occurs regardless of internal processing.
[0008]
From now on, according to the conventional memory control method in which the order of data transfer is scheduled in advance, the buffer held by the image input unit and the bit stream output unit is increased in order to prevent buffer overflow and underflow. Alternatively, the number of data transfers between the image input unit or bit stream output unit and the memory must be increased.
[0009]
In this case, there is a problem that increasing the size of the buffer increases the memory capacity of the buffer. On the other hand, increasing the number of data transfers increases the overhead, and the data transfer cycle to the encoding core unit is sufficient. Therefore, there is a problem that the image quality is liable to be deteriorated.
[0010]
As prior art related to the present invention, (a) the following Patent Document 1 discloses a technique for efficiently transferring data between an image memory and a buffer. Patent Document 2 discloses a technique for preventing overflow in a buffer memory by controlling the amount of encoded data. (C) Patent Document 3 below describes each process of an image encoding device. A technology is disclosed in which processing contention is resolved by determining processing of each part by scheduling.
[0011]
[Patent Document 1]
Japanese Patent Laid-Open No. 8-9381
[Patent Document 2]
JP-A-6-233272
[Patent Document 3]
JP-A-10-108199
[0012]
[Problems to be solved by the invention]
In the conventional memory control system, the following problems occur when data transfer with the memory is performed.
[0013]
(1) The processing cycle of the macroblock increases / decreases depending on the nature of the image and the encoding method. As shown in FIG. 13, the data transfer interval between the image input unit or the bit stream output unit and the memory fluctuates in the data transfer scheduled in advance due to increase / decrease in the processing cycle of the macroblock.
[0014]
In order to prevent the buffer of the image input unit that is input at a constant rate and the buffer of the bit stream output unit that is pulled out at a constant rate due to the fluctuation of the data transfer interval, the buffer amount is increased. A method of increasing the number of data transfers (increasing overhead) is used.
[0015]
(2) Data transfer that occurs between the image input unit and the memory and data transfer that occurs between the bit stream output unit and the memory occur regardless of the macroblock processing. On the other hand, when the transfer sequence is determined at the time of design, data transfer occurs only in the transfer sequence order. From this, the buffer of the image input unit may overflow, or the buffer of the bit stream output unit may underflow.
[0016]
(3) In the memory control method in which N times are designated as the transfer sequence between the N coding core units and the memory, the N-times transfer sequence must be specified in spite of the similar transfer sequence.
[0017]
(4) The waiting state for executing the transfer sequence between the M macroblock synchronous transfer units and the memory and the waiting state for executing the transfer sequence between the N coding core units and the memory Data transfer efficiency may be reduced.
[0018]
As described above, according to the prior art, the buffers of the image input unit and the bit stream output unit may become large, and those buffers may overflow or underflow, and the transfer sequence may be reduced. There is a problem that the amount of memory to be specified is large and wasteful overhead is generated in the waiting state of the transfer sequence.
[0019]
Such a problem is not limited to the moving picture coding apparatus, but is an input unit that inputs processing data and writes it to the memory, a processing unit that performs predetermined processing on the processing data stored in the memory, and a memory that stores the processing data. This is a problem that generally occurs in a processing apparatus that includes an output unit that outputs processed data to be processed.
[0020]
  The present invention has been made in view of such circumstances. An input unit that inputs processing data and writes the processing data in a memory, a processing unit that performs predetermined processing on the processing data stored in the memory, and the memory is stored in the memory. Used in a processing device including an output unit that outputs processed data and controls the data transfer between each unit and the memory. Required buffer overflow or underflowOccurrence ofTheDrasticallyIt is an object of the present invention to provide a new memory control technique that can reduce the capacity of these buffers by making it possible to avoid them.
[0021]
In addition to this, the present invention provides a new memory control technique that makes it possible to reduce the amount of memory that designates a transfer sequence and to reduce unnecessary overhead caused by a waiting state of the transfer sequence. With the goal.
[0022]
[Means for Solving the Problems]
  In order to achieve this object, a memory control device according to the present invention includes an input unit that inputs processing data and writes the processing data in the memory, and one or more processing units that perform predetermined processing on the processing data stored in the memory. Used in a processing apparatus including an output unit that outputs processed data stored in a memory and controls the data transfer between each unit and the memory. ,
  (1) Issuing means for issuing a series of data processing data transfer instructions generated between the memory and the processing unit in a prescribed order;
  (2) An input side maximum value that is a maximum value of a data transfer interval generated between the input unit and the memory limited by the buffer capacity of the input unit, and an output unit limited by the buffer capacity of the output unit First storage means for storing an output side maximum value that is a maximum value of a data transfer interval generated between the memory and the memory;
  (3) Between the input unit and the memoryOccurs in external interactionThe number of elapsed cycles on the input side, which is the number of cycles that have elapsed since the end of the data transfer instruction for data input that controls data transfer, and between the output unit and the memoryOccurs in external interactionCounting means for counting the number of output-side elapsed cycles, which is the number of elapsed cycles from the end of the data output data transfer instruction that controls data transfer;
  (4) For each data processing data transfer instructionOf a fixed value set in advanceSecond storage means for storing the number of execution cycles;
  (5) Obtain the number of execution cycles of the data processing data transfer instruction issued by the issuing means from the second storage means, calculate the added value of the obtained number of execution cycles and the number of input side elapsed cycles, It is determined whether or not the added value exceeds the maximum value on the input side. If so, the data transfer command for data input is determined as the next data transfer command to be executed. Calculate the added value of the acquired number of execution cycles and the number of output-side elapsed cycles, determine whether the added value exceeds the maximum value on the output side, and if so, execute the data transfer command for data output. A data transfer instruction to be executed, and if not exceeding, a determination means for determining the data transfer instruction for data processing issued by the issuing means as a data transfer instruction to be executed next;
  (6) When the data transfer command for data processing issued by the issuing means is determined as the data transfer command to be executed next, and the data transfer command for data processing is in a waiting state, The data transfer instruction or the data output instruction for data output is finally determined as a data transfer instruction to be executed next.
[0024]
  In the memory control device of the present invention configured as described above,IssueMeans are a series of generated between the memory and the processing unit.For data processingIssue data transfer instructions in a prescribed order. For example,For data processingBy referring to the memory area that holds the transfer sequence of the data transfer instruction, a series of data generated between the memory and the processing unitFor data processingData transfer instructions are issued in a prescribed order.
[0025]
  At this time, multipleFor data processingWhen a combination of data transfer instructions is issued repeatedly, to reduce the number of instructions in the transfer sequence,For data processingBy cyclically referencing the memory area holding the transfer sequence of data transfer instructions,For data processingIt is preferable to repeatedly issue a data transfer instruction.
[0026]
  thisFor data processingIn response to the issuance of data transfer instructions,DecisionMeansFirst memoryMeans storage dataToTherefore, the maximum value of the two data transfer intervals(Input side maximum value, output side maximum value)And getCountingCounting meansTwoNumber of elapsed cycles(Number of input side elapsed cycles, number of output side elapsed cycles)Get furtherSecond memoryMeans storage dataToTherefore,IssueIssued by meansFor data processingNecessary for data transfer indicated by data transfer instructionExecutionGet the number of cycles.
[0027]
  continue,DecisionMeans required for the transfer of the acquired dataExecutionAn addition value between the number of cycles and the acquired elapsed cycle number is calculated, and it is determined whether the addition value exceeds the acquired maximum value, thereby determining a data transfer instruction to be executed next.
[0028]
  That is, the added value isFirst memoryNote of meansRememberIf the maximum value exceedsIssueIssued by meansFor data processingWhen the data transfer instruction is executed next, the buffer of the input unit overflows or the buffer of the output unit underflows. Therefore, to avoid such inconvenience, the added value becomes the maximum value. If exceeded, the data transfer instruction associated with the maximum value exceeded(Data transfer instruction for data input or data transfer instruction for data output)Is determined as the next data transfer instruction to be executed, and if the added value does not exceed the maximum value,IssueIssued by meansFor data processingThe data transfer instruction is determined as the next data transfer instruction to be executed.
[0029]
  At this time, it manages the data transfer between the input unit and the memory.For data entryData transfer instructions are responsible for data transfer between the output and memoryFor data outputConsidering that the urgency is higher than the data transfer command, first, the added value is related to the input unit.Input sideJudges whether or not the maximum value is exceeded, and if so, manages the data transfer between the input unit and the memoryFor data entryThe data transfer instruction is determined as the next data transfer instruction to be executed, and if not exceeded, the added value is related to the output unit.Output sideJudges whether or not the maximum value is exceeded, and if so, manages the data transfer between the output unit and the memoryFor data outputIf the data transfer instruction is determined as the next data transfer instruction to be executed and does not exceed,IssueIssued by meansFor data processingDetermine the data transfer instruction as the next data transfer instruction to be executedThe
[0030]
  DecisionWhen the means determines the data transfer instruction to be executed next,final decisionThe means manages data transfer between the processing unit and the memory.For data processingConsidering that a wait state occurs in the data transfer instruction,IssueIssued by meansFor data processingIf the data transfer instruction is determined as the next data transfer instruction to be executed,For data processingCheck if the data transfer instruction is in the wait state andFor data processingControls data transfer between the input unit and memory when a data transfer command is in a wait stateFor data entryControls data transfer instructions or data transfer between output section and memoryFor data outputThe data transfer instruction is processed so as to be finally determined as a data transfer instruction to be executed next.
  For example, (i) when the data transfer instruction for data input is finally determined as the data transfer instruction to be executed next, the data transfer instruction for data output is finally determined as the data transfer instruction to be executed next, On the other hand, when the data transfer instruction for data output was finally determined as the data transfer instruction to be executed next, the data input transfer instruction is finally determined as the data transfer instruction to be executed next, or (ii) The difference value between the input side maximum value and the input side elapsed cycle number and the difference value between the output side maximum value and the output side elapsed cycle number were obtained, and the difference value indicating the smaller value was specified and specified. If the difference value is the difference value between the maximum value on the input side and the number of elapsed cycles on the input side, the data transfer instruction for data input is finally determined as the data transfer instruction to be executed next, while the specified difference Value if the difference value of the output-side maximum value and the output-side elapsed cycles is finalized as a data transfer instruction to be executed next data output for data transfer instruction.
[0031]
  As described above, according to the present invention, the input unit that inputs the processing data and writes the processing data to the memory, the processing unit that performs the predetermined processing on the processing data stored in the memory, and the processing stored in the memory are performed. Used in a processing apparatus having an output unit for outputting processed data and controlling the data transfer between each unit and the memory, and overflowing the buffer of the input unitOccurrence ofTheDrasticallyIt can be avoided and the buffer underflow of the output partOccurrence ofTheDrasticallyAs a result, it is not necessary to give the buffer capacity more than necessary, so that the buffer capacity can be reduced.
[0032]
According to the present invention, data transfer is executed with priority given to a data transfer instruction that controls data transfer between the processing unit and the memory, so that the buffer of the input unit is stored in the buffer until immediately before the buffer overflows. Processing data is input and processing data is output from the buffer until the buffer of the output unit immediately underflows, so that the number of data transfers between the input unit and the memory can be reduced. In addition, the number of data transfers between the output unit and the memory can be reduced.
[0033]
According to the present invention, when a data transfer instruction that controls data transfer between the processing unit and the memory is repeatedly issued, it is possible to reduce the amount of memory that specifies the transfer sequence.
[0034]
According to the present invention, it is possible to reduce useless overhead that occurs due to a wait state of a data transfer instruction that controls data transfer between the processing unit and the memory.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail according to an embodiment applied to a moving image encoding apparatus.
[0036]
FIG. 1 shows an embodiment of a moving picture encoding apparatus comprising the present invention.
[0037]
In the figure, 1 is an image input unit for inputting an image frame from the outside, 10 is a buffer provided in the image input unit 1, 2 is a filter unit, and synchronous transfer of macroblocks divided from the image frame 3-i (i = 1 to N) are N coding core units that perform the filtering process for the image, and operate in parallel, with the divided frames obtained by dividing the image frame into N as inputs. Outputs each divided bit stream after encoding in units of macroblocks, 4 indicates a bit stream output unit, and outputs the bit stream output from the encoding core unit 3-i to the outside, Reference numeral 40 denotes a buffer included in the bit stream output unit 4, 5 denotes a memory, and 6 denotes a memory control unit including the present invention.
[0038]
The image input unit 1 performs a process of inputting image data from the outside and writing it into the memory 5 via the memory control unit 6. The filter unit 2 reads out image data from the memory 5 through the memory control unit 6, performs a filtering process, and performs a process of writing into the memory 5 through the memory control unit 6. The encoding core unit 3-i reads out image data from the memory 5 through the memory control unit 6, performs encoding processing, and performs processing of writing into the memory 5 through the memory control unit 6. The bit stream output unit 4 reads out the encoded image data from the memory 5 via the memory control unit 6 and performs processing to output it to the outside.
[0039]
The memory control unit 6 including the present invention is configured by pipeline-structured hardware, and a processing unit that generates data transfer by interaction with the outside, such as the image input unit 1 and the bitstream output unit 4, A process of providing efficient data transfer is performed on a processing unit that generates data transfer in synchronization with the processing of the macroblock, such as the filter unit 2 and the encoding core unit 3-i.
[0040]
In order to realize this processing, the memory control unit 6 including the present invention includes a data transfer instruction issuing unit 60 including a transfer sequence holding register 61, an execution cycle number managing unit 62, and an input / output execution interval maximum value management. Means 63, input / output elapsed cycle number counting means 64, execution instruction determination means 65, address calculation means 66, and data transfer means 67 are provided.
[0041]
As shown in FIG. 2, the transfer sequence holding register 61 includes a data transfer command (Trans1) that controls data transfer between the filter unit 2 and the memory 5, and each encoding core unit 3-i and the memory 5. Data transfer command for managing data transfer between the coding core unit 3-1, Trans2, Trans3, Trans4,..., Coding core unit 3-N, Transz-2, Transz-1, Transz) And enumeration data (which will constitute a transfer sequence).
[0042]
As shown in FIG. 3, the data transfer command issuing means 60 sends data between the filter unit 2 and the memory 5 to the execution command determining means 65 in accordance with the transfer sequence held in the transfer sequence holding register 61. The memory 5 and the filter unit 2 are issued by sequentially issuing a data transfer command that controls the transfer and a data transfer command that controls the data transfer between each encoding core unit 3-i and the memory 5 according to a cyclic format. / A series of data transfer instructions for N macroblock processing generated between the encoding core unit 3-i is issued.
[0043]
  As shown in FIG. 2, the execution cycle number management means 62 associates each data transfer instruction held in the transfer sequence holding register 61 with the number of execution cycles of the data transfer instruction.(Fixed value set in advance)Manage.
[0044]
The input / output execution interval maximum value management means 63 determines how many cycles the maximum value of the data transfer interval generated between the image input unit 1 and the memory 5 limited by the capacity of the buffer 10 of the image input unit 1 is. And information on how many cycles the maximum value of the data transfer interval generated between the bit stream output unit 4 and the memory 5 limited by the capacity of the buffer 40 of the bit stream output unit 4 is managed. To do.
[0045]
That is, with respect to a data transfer command (TransIn) that controls data transfer between the image input unit 1 and the memory 5, in order to prevent the buffer 10 of the image input unit 1 from overflowing, for example, it does not exceed 100 cycles. When the condition that it must be executed is imposed, as shown in FIG. 2, it is managed that the maximum value of the data transfer interval generated between the image input unit 1 and the memory 5 is 100 cycles. is there.
[0046]
For the data transfer instruction (TransBs) that controls data transfer between the bit stream output unit 4 and the memory 5, for example, the buffer 40 of the bit stream output unit 4 does not underflow, for example, exceeds 500 cycles. When the condition that it must be executed in such a way is imposed, the maximum value of the data transfer interval generated between the bit stream output unit 4 and the memory 5 is 500 cycles as shown in FIG. Is managed.
[0047]
The input / output elapsed cycle number counting means 64 counts the number of elapsed cycles since the end of each data transfer of the image input unit 1 / bitstream output unit 4 that performs data transfer not synchronized with the macroblock, The number of cycles (RTransIn) that have elapsed since the end of the data transfer instruction (TransIn) that controls data transfer between the image input unit 1 and the memory 5 is counted and held, and the bitstream output unit 4 and the memory 5 Count the number of cycles (RTransBs) that have elapsed since the end of the data transfer instruction (TransBs) that controls data transfer to and hold it.
[0048]
That is, the input / output elapsed cycle number counting means 64, as shown in FIG. 4, is the number of elapsed cycles (RTransIn) from the end of the data transfer instruction (TransIn) that controls data transfer between the image input unit 1 and the memory 5. When the data transfer instruction starts execution, the value of the counter 640 is reset. When the data transfer instruction finishes execution, the counter 640 is incremented by one every time one cycle elapses. By incrementing, the number of elapsed cycles (RTransIn) from the end of the data transfer instruction is counted.
[0049]
Then, as shown in FIG. 4, the input / output elapsed cycle number counting means 64 counts the number of elapsed cycles (RTransBs) from the end of the data transfer instruction (TransBs) that controls data transfer between the bit stream output unit 4 and the memory 5. ) Is counted, and when the execution of the data transfer instruction starts, the value of the counter 641 is reset. When the execution of the data transfer instruction ends, the value of the counter 641 is set to 1 every time one cycle elapses. By incrementing it, the number of elapsed cycles (RTransBs) from the end of the data transfer instruction is counted.
[0050]
The execution instruction determination unit 65 includes a data transfer instruction issued by the data transfer instruction issue unit 60, the number of execution cycles of the data transfer instruction acquired from the execution cycle number management unit 62, and an input / output execution interval maximum value management unit 63. The data transfer instruction to be executed next is determined using the maximum value of the data transfer interval acquired from the above and the elapsed cycle number counted by the input / output elapsed cycle number counting means 64 as inputs.
[0051]
The address calculation means 66 receives the data transfer instruction determined by the execution instruction determination means 65 as input, performs address calculation designated by the data transfer instruction, and inputs the address to the memory 5.
[0052]
The data transfer means 67 executes data transfer between the image input unit 1 / filter unit 2 / encoding core unit 3-i / bitstream output unit 4 and the memory 5 in synchronization with the address input to the memory 5. To do.
[0053]
Next, a process executed by the memory control unit 6 having the present invention configured as described above will be described in detail with reference to FIG.
[0054]
Upon receiving the data transfer instruction (Transp (p = 1 to z)) issued by the data transfer instruction issuing means 60, the execution instruction determining means 65 receives the data from the execution cycle number management means 62 as shown in FIG. The number of execution cycles (Sp) of the transfer instruction (Transp) is acquired.
[0055]
At this time, the execution instruction determination unit 65 further obtains the maximum value (MaxIn) / maximum value (MaxBs) of the data transfer interval from the input / output execution interval maximum value management unit 63 and also counts the number of input / output elapsed cycles. From 64, the number of elapsed cycles (RTransIn) / the number of elapsed cycles (RTransBs) is acquired.
[0056]
Subsequently, the execution instruction determination means 65 firstly
RTransIn + Sp> MaxIn
If this condition is satisfied and it is determined that this condition is satisfied, data transfer between the image input unit 1 and the memory 5 is governed as a data transfer command to be executed next. Determine the data transfer instruction (TransIn).
[0057]
That is, when the data transfer instruction (Transp) issued by the data transfer instruction issuing means 60 is selected as the next data transfer instruction to be executed, the number of elapsed cycles (RTransIn) exceeds the maximum value (MaxIn) of the data transfer interval. In this case, a data transfer instruction (TransIn) that controls data transfer between the image input unit 1 and the memory 5 is selected as a data transfer instruction to be executed next.
[0058]
At this time, since the data transfer instruction (Transp) issued by the data transfer instruction issuing means 60 is put on hold, the data transfer instruction issuing means 60 is not notified that the data transfer instruction has been accepted. The instruction issuing means 60 enters a waiting state for issuing the next data transfer instruction.
[0059]
On the other hand, the execution instruction determination means 65
RTransIn + Sp> MaxIn
If it is determined that the above condition does not hold,
RTransBs + Sp> MaxBs
If this condition is satisfied and it is determined that this condition is satisfied, data transfer between the bit stream output unit 4 and the memory 5 is performed as a data transfer instruction to be executed next. Determine the data transfer command (TransBs) to be controlled.
[0060]
That is, when the data transfer instruction (Transp) issued by the data transfer instruction issuing means 60 is selected as the next data transfer instruction to be executed, the number of elapsed cycles (RTransBs) exceeds the maximum value (MaxBs) of the data transfer interval. In this case, a data transfer instruction (TransBs) that controls data transfer between the bit stream output unit 4 and the memory 5 is selected as a data transfer instruction to be executed next.
[0061]
At this time, since the data transfer instruction (Transp) issued by the data transfer instruction issuing means 60 is put on hold, the data transfer instruction issuing means 60 is not notified that the data transfer instruction has been accepted. The instruction issuing means 60 enters a waiting state for issuing the next data transfer instruction.
[0062]
On the other hand, the execution instruction determination means 65
RTransBs + Sp> MaxBs
When it is determined that the above condition is not satisfied, the data transfer instruction (Transp) issued by the data transfer instruction issuing means 60 is determined as the data transfer instruction to be executed next.
[0063]
At this time, the data transfer command issuing unit 60 is notified that the data transfer command has been accepted, and the data transfer command issuing unit 60 issues the next data transfer command.
[0064]
In this way, the execution instruction determination means 65 gives the data transfer instruction (Transp) issued by the data transfer instruction issue means 60 while efficiently advancing the macroblock processing by giving priority to data transfer for macroblock processing. If the buffer 10 of the image input unit 1 overflows when selected, a data transfer command (TransIn) that controls data transfer between the image input unit 1 and the memory 5 is selected. When the data transfer instruction (Transp) issued by the issuing means 60 is selected, when the buffer 40 of the bitstream output unit 4 underflows, the data that controls the data transfer between the bitstream output unit 4 and the memory 5 Processing is performed to select a transfer command (TransBs).
[0065]
Here, the determination of “RTransIn + Sp> MaxIn” is given priority over the determination of “RTransBs + Sp> MaxBs” because the buffer 10 of the image input unit 1 overflows and the input image is lost, which directly leads to image quality degradation. On the other hand, even if there is no bit stream that can be output when the buffer 40 of the bit stream output unit 4 underflows, it can be avoided to some extent by inserting null packets.
[0066]
From this, the execution instruction determination means 65 first determines “RTransIn + Sp> MaxIn” and then determines “RTransBs + Sp> MaxBs” to determine the data transfer instruction to be executed next. .
[0067]
When the execution instruction determination unit 65 determines the data transfer instruction to be executed next, the address calculation unit 66 receives the data transfer instruction determined by the execution instruction determination unit 65 and performs address calculation designated by the data transfer instruction. The address is input to the memory 5, and in response to this, the data transfer means 67 is connected between the image input unit 1 / filter unit 2 / encoding core unit 3 -i / bitstream output unit 4 and the memory 5. Execute data transfer.
[0068]
Thus, according to the memory control unit 6 having the present invention, it is possible to avoid overflow of the buffer 10 of the image input unit 1 and to avoid underflow of the buffer 40 of the bitstream output unit 4. As a result, the capacity of the buffers 10 and 40 need not be given more than necessary, so that the capacity of the buffers 10 and 40 can be reduced.
[0069]
Then, according to the memory control unit 6 including the present invention, the data transfer is executed in the form of giving priority to the instruction that controls the data transfer between the filter unit 2 / encoding core unit 3-i and the memory 5. Thus, it becomes possible to efficiently process the macroblock.
[0070]
According to the memory control unit 6 including the present invention, the image data is input to the buffer 10 until the buffer 10 of the image input unit 1 overflows, and the buffer 40 of the bit stream output unit 4 Since processing is performed such that image data is output from the buffer 40 until immediately before an underflow occurs, the number of data transfers between the image input unit 1 and the memory 5 can be reduced, and the bit stream output unit 4 And the number of data transfers between the memory 5 can be reduced.
[0071]
As described above, the image input unit 1 performs processing to input image data given from the outside. In addition, for example, reduced image data of the input image data is created and stored in the memory 5. A process such as Further, when inputting a color image, a process of inputting image data relating to brightness and image data relating to luminance separately to the memory 5 is performed.
[0072]
From now on, there are a plurality of types of data transfer commands such as a data transfer command (TransIn ') and a data transfer command (TransIn' ') as data transfer commands for controlling data transfer between the image input unit 1 and the memory 5. There are things to do. In such a case, separate buffers 10 are prepared.
[0073]
In such a case, as shown in FIG. 6, the execution instruction determination means 65 executes the execution process 1 for executing the same procedure as that shown in FIG. 5 (so that no overflow or underflow occurs in all buffers). When selecting a data transfer instruction that controls data transfer between the image input unit 1 and the memory 5 in accordance with a process of selecting a data transfer instruction in a form that gives priority to a data transfer instruction related to macroblock processing) As shown in the execution process 2, the plurality of types of data transfer instructions (TransIn ′ and TransIn ″) are processed in order.
[0074]
Here, in such a case, as shown in FIG. 6, the maximum value of each data transfer interval is managed by the input / output execution interval maximum value managing means 63 and the input / output elapsed cycle is managed. The number counting means 64 counts the number of elapsed cycles from the end of each data transfer instruction.
[0075]
In FIG. 2, for the sake of general explanation, it has been described that the data transfer command of each encoding core unit 3-i is different, but in reality, each encoding core unit 3-i is the same. As shown in FIG. 7, the data transfer instruction of the encoding core unit 3-1 is also Trans2, Trans3, Trans4, and the data transfer instruction of the encoding core unit 3-2 is also Trans2, Trans3, as shown in FIG. , Trans4,..., And the data transfer command of each encoding core unit 3-i is the same as the data transfer command of the encoding core unit 3-N is also Trans2, Trans3, Trans4. It becomes.
[0076]
In this case, the transfer sequence holding register 61, as shown in FIG. 7, has a data transfer instruction (Trans1) that controls data transfer between the filter unit 2 and the memory 5, and a common data transfer instruction (Trans2). , Trans3, Trans4), it is sufficient to hold the list data.
[0077]
That is, as shown in FIG. 8, the data transfer command issuing means 60 issues a data transfer command (Trans1) and then transfers the data transfer commands (Trans2, Trans3, Trans4) in the order of “Trans2 → Trans3 → Trans4”. The transfer sequence holding register 61 “Trans1, Trans2, Trans3, Trans4” is issued by repeating the process of repeatedly issuing the data transfer instruction (Trans1) N times and then issuing the data transfer instruction (Trans1) again. This is because it will be sufficient to hold a small number of data transfer instructions.
[0078]
According to this configuration, there is an advantage that the transfer sequence holding register 61 can be made small.
[0079]
When the data transfer instruction issuing means 60 uses such a data transfer instruction issuing form, the address calculating means 66 determines the slice number and macroblock for each data transfer according to the number of repetitions in the data transfer instruction issuing means 60. The address is calculated by changing the number.
[0080]
FIG. 9 shows another embodiment of the moving picture encoding apparatus provided with the present invention.
[0081]
In this embodiment, when the execution instruction determining means 65 determines the data transfer instruction (Transp) issued by the data transfer instruction issuing means 60 as the data transfer instruction to be executed next, the data transfer instruction (Transp) In view of the fact that the system is in a waiting state, the purpose is to reduce the useless overhead caused by such a waiting state.
[0082]
In the case of this embodiment, the memory control unit 6 includes an execution instruction final determination unit 68 that performs a process of finally determining a data transfer instruction to be executed next with the data transfer instruction determined by the execution instruction determination unit 65 as an input. The structure is taken.
[0083]
The execution instruction final decision means 68 is used when the execution instruction decision means 65 decides the data transfer instruction (Transp) issued by the data transfer instruction issue means 60 as the data transfer instruction to be executed next. When (Transp) is in a waiting state, a data transfer command (TransIn) that controls data transfer between the image input unit 1 and the memory 5 or data that controls data transfer between the bitstream output unit 4 and the memory 5 One of the transfer instructions (TransBs) is finally determined as a data transfer instruction to be executed next and inputted to the address calculating means 66.
[0084]
For example, as shown in FIG. 10, when the data transfer command (TransIn) that controls data transfer between the image input unit 1 and the memory 5 is finally determined as the data transfer command to be executed next, as shown in FIG. The data transfer instruction (TransBs) that controls the data transfer between the bit stream output unit 4 and the memory 5 is finally determined as the data transfer instruction to be executed next, and conversely, the bit stream output unit 4 and the memory 5 If the data transfer command (TransBs) that controls the data transfer between the image input unit 1 and the memory 5 is determined this time as the data transfer command to be executed next, the data transfer command that controls the data transfer between the image input unit 1 and the memory 5 this time (TransIn) is finally determined as a data transfer instruction to be executed next.
[0085]
Alternatively, as shown in FIG. 11, “MaxIn−RTransIn” is calculated for the data transfer instruction (TransIn) that controls data transfer between the image input unit 1 and the memory 5, and the bitstream output unit 4 and the memory 5 By calculating “MaxBs − RTransBs” for the data transfer instruction (TransBs) that controls the data transfer between and The data transfer instruction to be executed next is finally determined.
[0086]
By providing the execution instruction final decision means 68, it is possible to reduce useless overhead caused by the waiting state of the transfer sequence.
[0087]
Although the present invention has been described according to the illustrated embodiment, the present invention is not limited to this. For example, in the embodiment, the present invention has been described according to the embodiment applied to the moving image encoding apparatus, but the present invention is not limited to the moving image encoding apparatus.
[0088]
【The invention's effect】
  As described above, according to the present invention, the input unit that inputs processing data and writes it to the memory, the processing unit that performs predetermined processing on the processing data stored in the memory, and the processing that is stored in the memory. Used in a processing apparatus having an output unit for outputting processed data and controlling the data transfer between each unit and the memory, and overflowing the buffer of the input unitOccurrence ofTheDrasticallyIt can be avoided and the buffer underflow of the output partOccurrence ofTheDrasticallyAs a result, it is not necessary to give the buffer capacity more than necessary, so that the buffer capacity can be reduced.
[0089]
According to the present invention, data transfer is executed with priority given to a data transfer instruction that controls data transfer between the processing unit and the memory, so that the buffer of the input unit is stored in the buffer until immediately before the buffer overflows. Processing data is input and processing data is output from the buffer until the buffer of the output unit immediately underflows, so that the number of data transfers between the input unit and the memory can be reduced. In addition, the number of data transfers between the output unit and the memory can be reduced.
[0090]
According to the present invention, when a data transfer instruction that controls data transfer between the processing unit and the memory is repeatedly issued, it is possible to reduce the amount of memory that specifies the transfer sequence.
[0091]
According to the present invention, it is possible to reduce useless overhead that occurs due to a wait state of a data transfer instruction that controls data transfer between the processing unit and the memory.
[Brief description of the drawings]
FIG. 1 is an example of an embodiment of a moving image encoding apparatus provided with the present invention.
FIG. 2 is an explanatory diagram of a transfer sequence held by a transfer sequence holding register.
FIG. 3 is an explanatory diagram of an execution process of a data transfer instruction issuing unit.
FIG. 4 is an explanatory diagram of an execution process of an input / output elapsed cycle number counting unit.
FIG. 5 is an explanatory diagram of an execution process of an execution instruction determination unit.
FIG. 6 is an explanatory diagram of an execution process of an execution instruction determination unit.
FIG. 7 is an explanatory diagram of a data transfer instruction of an encoding core unit.
FIG. 8 is an explanatory diagram of an execution process of a data transfer instruction issuing unit.
[Fig. 9] Fig. 9 is another example of a moving image encoding apparatus according to the present invention.
FIG. 10 is an explanatory diagram of an execution process of an execution instruction final determination unit.
FIG. 11 is an explanatory diagram of an execution process of an execution instruction final determination unit.
FIG. 12 is an explanatory diagram of a device configuration of a video encoding device.
FIG. 13 is an explanatory diagram of processing of a conventional video encoding device.
[Explanation of symbols]
1 Image input section
2 Filter section
3 Coding core part
4-bit stream output section
5 memory
6 Memory controller
10 buffers
40 buffers
60 Data transfer command issuing means
61 Transfer sequence holding register
62 Execution cycle number management means
63 I / O execution interval maximum value management means
64 I / O elapsed cycle number counting means
65 Execution instruction determination means
66 Address calculation means
67 Data transfer means

Claims (8)

An input unit that inputs processing data and writes it to the memory, one or a plurality of processing units that perform predetermined processing on the processing data stored in the memory, and processed data that has been subjected to processing stored in the memory A memory control device used in a processing device including an output unit for outputting and controlling data transfer between each of the units and the memory,
Issuing means for issuing a series of data processing data transfer instructions generated between the memory and the processing unit according to a prescribed order;
The input side maximum value which is the maximum value of the data transfer interval generated between the input unit and the memory limited by the buffer capacity of the input unit, and the output limited by the buffer capacity of the output unit A first storage means for storing an output side maximum value, which is a maximum value of a data transfer interval generated between the storage unit and the memory,
An input side elapsed cycle number that is an elapsed cycle number from the end of a data transfer instruction for data input that controls data transfer generated by an external interaction between the input unit and the memory; the output unit and the memory; Counting means for counting the number of output-side elapsed cycles, which is the number of elapsed cycles from the end of the data transfer instruction for data output that governs the data transfer that occurs in the interaction with the outside between,
For each of the data processing data transfer instruction, a second storage means for storing the number of execution cycles of preset by a fixed value,
Obtaining the number of execution cycles of the data processing data transfer instruction issued by the issuing means from the second storage means, calculating the added value of the number of execution cycles acquired and the number of input side elapsed cycles, It is determined whether or not the added value exceeds the maximum value on the input side. If it exceeds, the data transfer instruction for data input is determined as a data transfer instruction to be executed next. , Calculate the added value of the obtained number of execution cycles and the output side elapsed cycle number, determine whether the added value exceeds the output side maximum value, and if so, for the data output The data transfer instruction is determined as the next data transfer instruction to be executed. If not exceeded, the data processing data transfer instruction issued by the issuing means is determined as the next data transfer instruction to be executed. And means,
When the data transfer command for data processing issued by the issuing means is determined as a data transfer command to be executed next and the data transfer data transfer command is in a wait state, the data input data Including a transfer instruction or a final determination means for finally determining the data output instruction for data output as a data transfer instruction to be executed next .
A memory control device. The memory control device according to claim 1.
The issuing means, when repeatedly issuing a combination of a plurality of data processing data transfer instructions, cyclically refers to the memory area holding the transfer sequence of the data processing data transfer instructions of the combination, Issuing repeated data transfer instructions for combined data processing,
A memory control device. The memory control device according to claim 1 .
If the data input instruction for data input is finally determined as the next data transfer instruction to be executed next, the final determining means finally determines the data transfer instruction for data output as the data transfer instruction to be executed next. On the other hand, if the data output instruction for data output is finally determined as the next data transfer instruction to be executed last time, the data input transfer instruction is finally determined as the data transfer instruction to be executed next time. That
A memory control device. The memory control device according to claim 1 .
The final determining means obtains a difference value between the input side maximum value and the input side elapsed cycle number and a difference value between the output side maximum value and the output side elapsed cycle number, and indicates a smaller value. If the difference value is the difference value between the maximum value on the input side and the number of elapsed cycles on the input side, a data transfer instruction for executing the data transfer instruction for data input next On the other hand, if the specified difference value is a difference value between the output side maximum value and the output side elapsed cycle number, the data transfer instruction for executing the data output data transfer instruction next is executed. As the final decision,
A memory control device. An input unit that inputs processing data and writes it to the memory, one or a plurality of processing units that perform predetermined processing on the processing data stored in the memory, and processed data that has been subjected to processing stored in the memory A memory control method for controlling data transfer between each of the units and the memory used in a processing device including an output unit for outputting,
A first process of issuing a series of data processing data transfer instructions generated between the memory and the processing unit in a prescribed order;
The input side maximum value which is the maximum value of the data transfer interval generated between the input unit and the memory limited by the buffer capacity of the input unit, and the output limited by the buffer capacity of the output unit A second storage unit for acquiring the input-side maximum value and the output-side maximum value from a first storage unit that stores an output-side maximum value that is a maximum value of a data transfer interval that occurs between the memory and the memory. Process,
An input side elapsed cycle number that is an elapsed cycle number from the end of a data transfer instruction for data input that controls data transfer generated by an external interaction between the input unit and the memory; the output unit and the memory; A third step of counting the number of output-side elapsed cycles, which is the number of cycles elapsed since the end of the data transfer instruction for data output, which controls data transfer generated by external interaction between
For each of the data processing data transfer instruction from the second storage means for storing the number of execution cycles The preset fixed value, the fourth to get the number of execution cycles the issued data processing data transfer instruction And the process
If the sum of the number of execution cycles acquired from the second storage means and the number of elapsed cycles on the input side is calculated, it is determined whether or not the sum exceeds the maximum value on the input side. The data input instruction for data input is determined as a data transfer instruction to be executed next, and if it does not exceed, subsequently, an addition value between the acquired execution cycle number and the output side elapsed cycle number is calculated, It is determined whether or not the added value exceeds the maximum value on the output side, and if it exceeds, the data output instruction for data output is determined as a data transfer instruction to be executed next. A fifth step of determining the issued data transfer command for data processing as a data transfer command to be executed next ;
If the issued data processing data transfer instruction is determined as a data transfer instruction to be executed next, and the data processing data transfer instruction is in a wait state, the data input data transfer instruction, Or a sixth step of finally determining the data transfer instruction for data output as a data transfer instruction to be executed next .
A memory control method. The memory control method according to claim 5 ,
In the first process, when a combination of a plurality of data processing data transfer instructions is repeatedly issued, the memory area holding the transfer sequence of the data processing data transfer instructions of the combination is cyclically referenced. , Repeatedly issuing data transfer data processing instructions for that combination,
A memory control method. The memory control method according to claim 5 ,
In the sixth process, when the data transfer instruction for data input is finally determined as the next data transfer instruction to be executed last time, the data transfer instruction for data output is set as the data transfer instruction to be executed next time this time. On the other hand, if the data transfer instruction for data output is finally determined as the data transfer instruction to be executed next, the data transfer instruction for data input is finally determined as the data transfer instruction to be executed next time. To do the
A memory control method. The memory control method according to claim 5 ,
In the sixth process, a difference value between the input side maximum value and the input side elapsed cycle number and a difference value between the output side maximum value and the output side elapsed cycle number are obtained, and a small value is indicated. If the difference value is the difference value between the maximum value on the input side and the number of elapsed cycles on the input side, the data transfer to execute the data transfer instruction for data input next is performed. Data transfer that is finally determined as an instruction, and on the other hand, if the specified difference value is a difference value between the output side maximum value and the output side elapsed cycle number, the data output data transfer instruction is executed next. The final decision as an order,
A memory control method.

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