JP4320779B2 - Line status detection circuit - Google Patents

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JP4320779B2
JP4320779B2 JP2004318332A JP2004318332A JP4320779B2 JP 4320779 B2 JP4320779 B2 JP 4320779B2 JP 2004318332 A JP2004318332 A JP 2004318332A JP 2004318332 A JP2004318332 A JP 2004318332A JP 4320779 B2 JP4320779 B2 JP 4320779B2
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昭彦 北嶋
靖之 水
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Murata Manufacturing Co Ltd
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この発明は、２つの加入者回線電圧から回線状態を検出する回線状態検出回路、特に、加入者回線の極性、接続状態を検出する回線状態検出回路に関するものである。   The present invention relates to a line state detection circuit for detecting a line state from two subscriber line voltages, and more particularly to a line state detection circuit for detecting the polarity and connection state of a subscriber line.

一般電話の加入者回線は基本的には２線式（Ｌ１，Ｌ２）であり、この加入者回線に接続する通信機器（電話機、モデム等）はこれらＬ１ライン，Ｌ２ラインに接続する２つの端子を備えている。そして、通信機器では、加入者回線に発生している電圧の極性、すなわち、前記２つの端子に入力される電圧の大小関係を検出する必要がある。   The subscriber line of a general telephone is basically a two-wire system (L1, L2), and communication equipment (telephone, modem, etc.) connected to this subscriber line has two terminals connected to these L1 line and L2 line. It has. In the communication device, it is necessary to detect the polarity of the voltage generated in the subscriber line, that is, the magnitude relationship between the voltages input to the two terminals.

このような通信機器として、特許文献１には、２つの端子に入力される大きな回線電圧を抵抗分圧することで低電圧化し、設定された基準電圧と比較することで、極性を判別する回線電圧判別回路が開示されている。
登録実用新案第３００１７０３号公報 As such a communication device, Patent Document 1 discloses a line voltage for determining a polarity by reducing a voltage by resistance-dividing a large line voltage input to two terminals and comparing it with a set reference voltage. A discrimination circuit is disclosed.
Registered Utility Model No. 3001703

ところが、特許文献１に記載の回路電圧判別回路では、低電圧化された回線電圧を基準電圧と比較するため、元々電圧値の低い通話中の回線電圧の場合、２つの端子に入力される回線電圧間で基準電圧との差が小さく、比較結果が同じになるので極性を検出することができない。   However, in the circuit voltage discriminating circuit described in Patent Document 1, in order to compare the reduced line voltage with the reference voltage, in the case of a line voltage during a call originally having a low voltage value, a line input to two terminals is used. Since the difference between the voltages and the reference voltage is small and the comparison results are the same, the polarity cannot be detected.

また、無接続状態では回線電圧はオープン状態となることで、回路電圧判別回路にとっては低電圧状態になり、前記通話状態と無接続状態との判別もできない。   Further, since the line voltage is in an open state in the non-connected state, the circuit voltage determining circuit is in a low voltage state, and the call state and the non-connected state cannot be determined.

したがって、本発明の目的は、回線状態によることなく、加入者回線に接続する２つの端子間の電圧極性および接続状態を検出できる回線状態検出回路を提供することにある。   Therefore, an object of the present invention is to provide a line state detection circuit capable of detecting the voltage polarity and connection state between two terminals connected to a subscriber line without depending on the line state.

この発明の回線状態検出回路は、２つの加入者回線電圧の一方を分圧して出力する第１分圧回路と、加入者回線電圧の他方を分圧して、値の異なる２つの分圧電圧を出力する第２分圧回路と、第１分圧回路の分圧電圧出力と第２分圧回路の一方の分圧電圧出力とを比較する第１比較器と、第１分圧回路の分圧電圧出力と第２分圧回路の他方の分圧電圧出力とを第１比較器とは逆の論理で比較する第２比較器とを備え第１分圧回路の分圧電圧出力と第２分圧回路の分圧電圧出力とを比較する比較手段と、第１比較器と第２比較器との入力端子にそれぞれプルアップ電圧を印加するプルアップ電圧印加手段と、を備える。そして、２つの加入者回線電圧が印加されていない時に、第１分圧回路の分圧電圧出力が入力される入力端子に印加される電圧が、第２分圧回路の分圧電圧出力の一方が入力される入力端子に印加される電圧よりも低く、第２分圧回路の分圧電圧出力の他方が入力される入力端子に印加される電圧よりも高くなるように第１分圧回路、第２分圧回路およびプルアップ電圧印加手段が構成されている。 The line status detection circuit of the present invention divides one of two subscriber line voltages and outputs the divided voltage, and the other of the subscriber line voltages is divided into two divided voltages having different values. A second voltage dividing circuit to output, a first comparator for comparing the divided voltage output of the first voltage dividing circuit with one of the divided voltage outputs of the second voltage dividing circuit, and the voltage dividing of the first voltage dividing circuit A second comparator for comparing the voltage output and the other divided voltage output of the second voltage dividing circuit with a logic opposite to that of the first comparator, and the divided voltage output and the second divided voltage of the first voltage dividing circuit; Comparing means for comparing the divided voltage output of the voltage circuit, and pull-up voltage applying means for applying a pull-up voltage to the input terminals of the first comparator and the second comparator, respectively. When the two subscriber line voltages are not applied, the voltage applied to the input terminal to which the divided voltage output of the first voltage dividing circuit is input is one of the divided voltage outputs of the second voltage dividing circuit. The first voltage dividing circuit is lower than the voltage applied to the input terminal to be input and higher than the voltage applied to the input terminal to which the other divided voltage output of the second voltage dividing circuit is input, A second voltage dividing circuit and a pull-up voltage applying unit are configured .

この構成では、第１分圧回路から出力される加入者回線電圧の一方（例えば、Ｌ１ライン）の分圧電圧と、第２分圧回路から出力される加入者回線電圧の他方（例えば、Ｌ２ライン）の分圧電圧とを比較手段により直接比較する。例えば、比較手段の非反転入力端子に第１分圧回路からの分圧電圧出力を入力させ、反転入力端子に第２分圧回路からの分圧電圧出力を入力させる。比較手段はこれら入力された電圧の大小により検出データを出力する。具体的には、第１分圧回路からの電圧が高ければＨｉ状態の検出データを出力し、第２分圧回路からの電圧が高ければＬｏｗ状態の判定信号を出力する。すなわち、２つ分圧回路の分圧電圧出力の大小関係により異なる検出データが出力されて、加入者回線の極性が検出される。   In this configuration, one of the subscriber line voltages (for example, L1 line) output from the first voltage divider circuit and the other of the subscriber line voltages (for example, L2) output from the second voltage divider circuit. The divided voltage of the line) is directly compared by the comparison means. For example, the divided voltage output from the first voltage dividing circuit is input to the non-inverting input terminal of the comparison means, and the divided voltage output from the second voltage dividing circuit is input to the inverting input terminal. The comparison means outputs detection data according to the magnitude of these input voltages. Specifically, if the voltage from the first voltage dividing circuit is high, the detection data in the Hi state is output, and if the voltage from the second voltage dividing circuit is high, the determination signal in the Low state is output. That is, different detection data is output according to the magnitude relationship between the divided voltage outputs of the two voltage dividing circuits, and the polarity of the subscriber line is detected.

これらの構成では、第１分圧回路から出力される分圧電圧と、第２分圧回路から出力される分圧電圧の一方とを比較手段の第１比較器で直接比較し、第１分圧回路から出力される分圧電圧と、第２分圧回路から出力される分圧電圧の他方とを比較手段の第２比較器で直接比較する。例えば、第１比較器の非反転入力端子に第１分圧回路の分圧電圧出力を入力させ、反転入力端子に第２分圧回路の分圧電圧出力の一方を入力させる。第１比較器はこれら入力された電圧の大小により第１の検出データを出力する。具体的には、第１分圧回路からの分圧電圧が高ければＨｉ状態の第１の検出データを出力し、第２分圧回路からの分圧電圧が高ければＬｏｗ状態の第１の検出データを出力する。また、第２比較器の非反転入力端子に第２分圧回路からの分圧電圧出力の他方を入力させ、反転入力端子に第１分圧回路からの分圧電圧出力を入力させる。第２比較器はこれら入力された電圧の大小により第２の検出データを出力する。具体的には、第２分圧回路からの分圧電圧が高ければＨｉ状態の第１の検出データを出力し、第１分圧回路からの分圧電圧が高ければＬｏｗ状態の第２の検出データを出力する。すなわち、２つ分圧回路の分圧電圧の大小関係により異なる検出データ（第１の検出データと第２の検出データ）の組み合わせが得られる。これにより、加入者回線の極性が検出される。   In these configurations, the divided voltage output from the first voltage dividing circuit and one of the divided voltages output from the second voltage dividing circuit are directly compared by the first comparator of the comparing means, and the first divided voltage is compared. The divided voltage output from the voltage dividing circuit and the other divided voltage output from the second voltage dividing circuit are directly compared by the second comparator of the comparing means. For example, the divided voltage output of the first voltage dividing circuit is input to the non-inverting input terminal of the first comparator, and one of the divided voltage outputs of the second voltage dividing circuit is input to the inverting input terminal. The first comparator outputs first detection data according to the magnitude of these input voltages. Specifically, if the divided voltage from the first voltage dividing circuit is high, the first detection data in the Hi state is output, and if the divided voltage from the second voltage dividing circuit is high, the first detection in the Low state is output. Output data. Further, the other of the divided voltage output from the second voltage dividing circuit is input to the non-inverting input terminal of the second comparator, and the divided voltage output from the first voltage dividing circuit is input to the inverting input terminal. The second comparator outputs second detection data according to the magnitude of these input voltages. Specifically, if the divided voltage from the second voltage dividing circuit is high, the first detection data in the Hi state is output, and if the divided voltage from the first voltage dividing circuit is high, the second detection in the Low state is output. Output data. That is, a combination of different detection data (first detection data and second detection data) is obtained depending on the magnitude relationship between the divided voltages of the two voltage dividing circuits. Thereby, the polarity of the subscriber line is detected.

この構成では、加入者回線に接続する２つの端子が無接続状態ならば、比較手段の第１比較器、第２比較器にそれぞれ所定電圧値のプルアップ電圧が印加される。この際、各入力端子に供給される電圧（それぞれプルアップ電圧印加手段によりプルアップされた電圧）の電圧値が前述の関係であることから、第１比較器、第２比較器からは同じ状態の検出データが出力される。これにより、加入者回線の無接続状態が検出される。   In this configuration, if the two terminals connected to the subscriber line are not connected, a pull-up voltage having a predetermined voltage value is applied to the first comparator and the second comparator of the comparison means. At this time, since the voltage values of the voltages supplied to the input terminals (respectively pulled up by the pull-up voltage applying means) are in the above-described relationship, the first comparator and the second comparator are in the same state. Detection data is output. Thereby, the unconnected state of the subscriber line is detected.

この発明によれば、通話状態等の加入者回線電圧が低い状態でも、回線の極性を検出することができる。すなわち、加入者回線の接続状態によらず、回線の極性を検出する回線状態検出回路を構成することができる。さらに、無接続状態を検出する回線状態検出回路を構成することができる。   According to the present invention, the polarity of the line can be detected even when the subscriber line voltage is low, such as a call state. That is, it is possible to configure a line state detection circuit that detects the polarity of the line regardless of the connection state of the subscriber line. Furthermore, it is possible to configure a line state detection circuit that detects a non-connection state.

本発明の第１の実施形態に係る回線状態検出回路について図１を参照して説明する。
図１は本実施形態の回線状態検出回路の概略構成を示すブロック図である。
本実施形態の回線状態検出回路は、加入者回線の２線（Ｌ１ライン、Ｌ２ライン）にそれぞれ接続する入力端子１，２と、第１、第２分圧回路１１，１２と、比較器３とを備える。
第１分圧回路１１は、直列接続された抵抗Ｒ１と抵抗Ｒ１１とからなり、Ｌ１ラインに接続する入力端子１に抵抗Ｒ１側の端部を接続し、抵抗Ｒ１１側の端部をグランドに接続し、抵抗Ｒ１，Ｒ１１の接続点、すなわち分圧点を比較器３の非反転入力端子に接続している。 A line state detection circuit according to a first embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a block diagram showing a schematic configuration of a line state detection circuit according to the present embodiment.
The line state detection circuit of this embodiment includes input terminals 1 and 2 connected to two subscriber lines (L1 line and L2 line), first and second voltage dividing circuits 11 and 12, and a comparator 3 respectively. With.
The first voltage dividing circuit 11 includes a resistor R1 and a resistor R11 connected in series. The end of the resistor R1 is connected to the input terminal 1 connected to the L1 line, and the end of the resistor R11 is connected to the ground. The connection point of the resistors R1 and R11, that is, the voltage dividing point is connected to the non-inverting input terminal of the comparator 3.

第２分圧回路１２は、直列接続された抵抗Ｒ２と抵抗Ｒ２１とからなり、Ｌ２ラインに接続する入力端子２に抵抗Ｒ２側の端部を接続し、抵抗Ｒ２１側の端部をグランドに接続し、抵抗Ｒ２，Ｒ２１の接続点、すなわち分圧点を比較器３の反転入力端子に接続している。   The second voltage dividing circuit 12 includes a resistor R2 and a resistor R21 connected in series. The end of the resistor R2 is connected to the input terminal 2 connected to the L2 line, and the end of the resistor R21 is connected to the ground. The connection point of the resistors R2 and R21, that is, the voltage dividing point is connected to the inverting input terminal of the comparator 3.

比較器３は、第１分圧回路１１に接続する非反転入力端子と、第２分圧回路１２に接続する反転入力端子と、これらの端子に入力される電圧に基づく検出データを出力する出力端子と、を備える。   The comparator 3 is a non-inverting input terminal connected to the first voltage dividing circuit 11, an inverting input terminal connected to the second voltage dividing circuit 12, and an output for outputting detection data based on voltages input to these terminals. A terminal.

このような回線状態検出回路は次に示すように動作する。   Such a line state detection circuit operates as follows.

Ｌ１，Ｌ２ラインを介して２つの加入者回線電圧が入力されると、第１分圧回路１１はＬ１ラインから入力される加入者回線電圧をグランドとの間で分圧する。すなわち、Ｌ１ラインに入力される加入者回線電圧のＲ１１／（Ｒ１＋Ｒ１１）倍の第１分圧電圧を比較器３の非反転入力端子に出力する。また、第２分圧回路１２はＬ２ラインから入力される加入者回線電圧をグランドとの間で分圧する。すなわち、Ｌ２ラインに入力される加入者回線電圧のＲ２１／（Ｒ２＋Ｒ２１）倍の第２分圧電圧を比較器３の反転入力端子に出力する。ここで、第１分圧回路１１の分圧比と第２分圧回路１２の分圧比とは略同じに設定されている。   When two subscriber line voltages are input via the L1 and L2 lines, the first voltage dividing circuit 11 divides the subscriber line voltage input from the L1 line with the ground. That is, a first divided voltage that is R11 / (R1 + R11) times the subscriber line voltage input to the L1 line is output to the non-inverting input terminal of the comparator 3. The second voltage dividing circuit 12 divides the subscriber line voltage input from the L2 line with the ground. That is, a second divided voltage that is R21 / (R2 + R21) times the subscriber line voltage input to the L2 line is output to the inverting input terminal of the comparator 3. Here, the voltage dividing ratio of the first voltage dividing circuit 11 and the voltage dividing ratio of the second voltage dividing circuit 12 are set to be substantially the same.

比較器３は、非反転入力端子に入力された第１分圧電圧と、反転入力端子に入力された第２分圧電圧とを比較して、第１分圧電圧が第２分圧電圧よりも大きければＨｉ状態の検出データを出力する。一方、第１分圧電圧が第２分圧電圧よりも小さければＬｏｗ状態の検出データを出力する。   The comparator 3 compares the first divided voltage input to the non-inverting input terminal with the second divided voltage input to the inverting input terminal, and the first divided voltage is greater than the second divided voltage. If it is larger, the detection data of Hi state is output. On the other hand, if the first divided voltage is smaller than the second divided voltage, detection data in the low state is output.

このような構成とすることで、第１分圧電圧と第２分圧電圧、すなわち、２つの加入者回線電圧の大小関係により比較器３から異なる状態の検出データが出力される。具体的には、表１に示すように、検出データのＨｉ状態／Ｌｏｗ状態に応じて加入者回線の極性が決まっているので、検出データのＨｉ／Ｌｏｗに応じて極性が検出される。   With such a configuration, detection data in different states is output from the comparator 3 according to the magnitude relationship between the first divided voltage and the second divided voltage, that is, the two subscriber line voltages. Specifically, as shown in Table 1, since the polarity of the subscriber line is determined according to the Hi state / Low state of the detected data, the polarity is detected according to the Hi / Low of the detected data.

Figure 0004320779
Figure 0004320779

このような構成とすることで、通話時、非通話時を問わず、１つ（１ｂｉｔ）の検出データで加入者回線の極性を検出することができる。   With such a configuration, the polarity of the subscriber line can be detected with one (1 bit) detection data regardless of whether the call is in progress or not.

次に、第２の実施形態に係る回線状態検出回路について図２を参照して説明する。
図２は本実施形態の回線状態検出回路の概略構成を示すブロック図である。
本実施形態の回線状態検出回路は、加入者回線の２線（Ｌ１ライン、Ｌ２ライン）にそれぞれ接続する入力端子１，２と、第１、第２分圧回路１１，１２と、比較器３，４とを備える。なお、第１の実施形態と同じ部分については、同じ記号を付しており、説明は省略する。 Next, a line state detection circuit according to the second embodiment will be described with reference to FIG.
FIG. 2 is a block diagram showing a schematic configuration of the line state detection circuit of the present embodiment.
The line state detection circuit of this embodiment includes input terminals 1 and 2 connected to two subscriber lines (L1 line and L2 line), first and second voltage dividing circuits 11 and 12, and a comparator 3 respectively. , 4. Note that the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

本実施形態に示す第１分圧回路１１は、第１の実施形態に示した第１分圧回路１１と同じ構成であるが、分圧点が比較器３の非反転入力端子に接続するとともに、比較器４の反転入力端子に接続している。   The first voltage dividing circuit 11 shown in the present embodiment has the same configuration as the first voltage dividing circuit 11 shown in the first embodiment, but the voltage dividing point is connected to the non-inverting input terminal of the comparator 3. Are connected to the inverting input terminal of the comparator 4.

入力端子２に接続する第２分圧回路１２は第１局部分圧回路１２１と第２局部分圧回路１２２とからなる。
第１局部分圧回路１２１は、直列接続された抵抗Ｒ２と抵抗Ｒ２１とからなり、Ｌ２ラインに接続する入力端子２に抵抗Ｒ２側の端部を接続し、抵抗Ｒ２１側の端部をグランドに接続し、抵抗Ｒ２，Ｒ２１の接続点、すなわち分圧点を比較器３の反転入力端子に接続している。 The second voltage dividing circuit 12 connected to the input terminal 2 includes a first local partial pressure circuit 121 and a second local partial pressure circuit 122.
The first local partial pressure circuit 121 includes a resistor R2 and a resistor R21 connected in series. The end of the resistor R2 side is connected to the input terminal 2 connected to the L2 line, and the end of the resistor R21 side is grounded. The connection point of the resistors R2 and R21, that is, the voltage dividing point is connected to the inverting input terminal of the comparator 3.

第２局部分圧回路１２２は、直列接続された抵抗Ｒ３と抵抗Ｒ３１とからなり、Ｌ２ラインに接続する入力端子２に抵抗Ｒ３側の端部を接続し、抵抗Ｒ３１側の端部をグランドに接続し、抵抗Ｒ３，Ｒ３１の接続点、すなわち分圧点を比較器４の非反転入力端子に接続している。   The second local partial pressure circuit 122 includes a resistor R3 and a resistor R31 connected in series. An end of the resistor R3 is connected to the input terminal 2 connected to the L2 line, and an end of the resistor R31 is grounded. The connection point of the resistors R3 and R31, that is, the voltage dividing point is connected to the non-inverting input terminal of the comparator 4.

比較器３は、第１分圧回路１１に接続する非反転入力端子と、第２分圧回路１２の第１局部分圧回路１２１に接続する反転入力端子と、これらの端子に入力される電圧に基づく検出データ（第１検出データ）を出力する出力端子とを備える。比較器４は、第２分圧回路１２の第２局部分圧回路１２２に接続する非反転入力端子と、第１分圧回路１１に接続する反転入力端子と、これらの端子に入力される電圧に基づく検出データ（第２検出データ）を出力する出力端子とを備える。なお、これら比較器３と比較器４とがそれぞれ本発明の「第１比較器」と「第２比較器」とに相当する。   The comparator 3 includes a non-inverting input terminal connected to the first voltage dividing circuit 11, an inverting input terminal connected to the first local partial pressure circuit 121 of the second voltage dividing circuit 12, and voltages input to these terminals. And an output terminal for outputting detection data (first detection data) based on. The comparator 4 includes a non-inverting input terminal connected to the second local partial pressure circuit 122 of the second voltage dividing circuit 12, an inverting input terminal connected to the first voltage dividing circuit 11, and voltages input to these terminals. And an output terminal for outputting detection data (second detection data) based on. The comparator 3 and the comparator 4 correspond to the “first comparator” and the “second comparator” of the present invention, respectively.

このような回線状態検出回路は次に示すように動作する。   Such a line state detection circuit operates as follows.

Ｌ１，Ｌ２ラインを介して２つの加入者回線電圧が入力されると、第１分圧回路１１はＬ１ラインから入力される加入者回線電圧とグランドとにより生じる電圧を分圧する。すなわち、Ｌ１ラインに入力される加入者回線電圧のＲ１１／（Ｒ１＋Ｒ１１）倍の第１分圧電圧を比較器３の非反転入力端子に出力する。また、第２分圧回路１２の第１局部分圧回路１２１はＬ２ラインから入力される加入者回線電圧とグランドとによる電圧を分圧する。すなわち、Ｌ２ラインに入力される加入者回線電圧のＲ２１／（Ｒ２＋Ｒ２１）倍の第２分圧電圧（１個目の第２分圧電圧）を比較器３の反転入力端子に出力する。また、第２分圧回路１２の第２局部分圧回路１２２は、Ｌ２ラインから入力される加入者回線電圧とグランドとにより生じる電圧を分圧する。すなわち、Ｌ２ラインに入力される加入者回線電圧のＲ３１／（Ｒ３＋Ｒ３１）倍の第３分圧電圧（２個目の第２分圧電圧）を比較器４の非反転入力端子に出力する。   When two subscriber line voltages are input via the L1 and L2 lines, the first voltage dividing circuit 11 divides the voltage generated by the subscriber line voltage input from the L1 line and the ground. That is, a first divided voltage that is R11 / (R1 + R11) times the subscriber line voltage input to the L1 line is output to the non-inverting input terminal of the comparator 3. Further, the first local partial pressure circuit 121 of the second voltage dividing circuit 12 divides the voltage due to the subscriber line voltage inputted from the L2 line and the ground. That is, a second divided voltage (first second divided voltage) that is R21 / (R2 + R21) times the subscriber line voltage input to the L2 line is output to the inverting input terminal of the comparator 3. The second local partial pressure circuit 122 of the second voltage dividing circuit 12 divides the voltage generated by the subscriber line voltage input from the L2 line and the ground. That is, a third divided voltage (second second divided voltage) times R31 / (R3 + R31) times the subscriber line voltage input to the L2 line is output to the non-inverting input terminal of the comparator 4.

ここで、第１分圧回路１１の分圧比と、第２分圧回路１２の第１局部分圧回路１２１の分圧比と、第２分圧回路１２の第２局部分圧回路１２２の分圧比とは略同じに設定されている。なお、第１局部分圧回路１２１と第２局部分圧回路１２２との分圧比を全く同じにする場合は、第２局部分圧回路１２２を省略して、第１局部分圧回路１２１の分圧電圧を比較器４の非反転入力端子に入力させてもよい。   Here, the voltage dividing ratio of the first voltage dividing circuit 11, the voltage dividing ratio of the first local partial pressure circuit 121 of the second voltage dividing circuit 12, and the voltage dividing ratio of the second local partial pressure circuit 122 of the second voltage dividing circuit 12. Is set to be substantially the same. When the partial pressure ratio between the first local partial pressure circuit 121 and the second local partial pressure circuit 122 is exactly the same, the second local partial pressure circuit 122 is omitted, and the first local partial pressure circuit 121 is divided. The voltage may be input to the non-inverting input terminal of the comparator 4.

比較器３は、非反転入力端子に入力された第１分圧電圧と、反転入力端子に入力された第２分圧電圧とを比較して、第１分圧電圧が第２分圧電圧よりも大きければＨｉ状態の第１検出データを出力する。一方、第１分圧電圧が第２分圧電圧よりも小さければＬｏｗ状態の第１検出データを出力する。比較器４は、非反転入力端子に入力された第３分圧電圧と、反転入力端子に入力された第１分圧電圧とを比較して、第３分圧電圧が第１分圧電圧よりも大きければＨｉ状態の第２検出データを出力する。一方、第３分圧電圧が第１分圧電圧よりも小さければＬｏｗ状態の第２検出データを出力する。すなわち、比較器４は比較器３とは逆の論理で２つの分圧電圧を比較する。   The comparator 3 compares the first divided voltage input to the non-inverting input terminal with the second divided voltage input to the inverting input terminal, and the first divided voltage is greater than the second divided voltage. If it is larger, the first detection data in the Hi state is output. On the other hand, if the first divided voltage is smaller than the second divided voltage, the first detection data in the low state is output. The comparator 4 compares the third divided voltage input to the non-inverting input terminal with the first divided voltage input to the inverting input terminal, and the third divided voltage is greater than the first divided voltage. If it is larger, the second detection data in the Hi state is output. On the other hand, if the third divided voltage is smaller than the first divided voltage, the second detection data in the low state is output. That is, the comparator 4 compares the two divided voltages with a logic opposite to that of the comparator 3.

このような構成とすることで、比較器３から出力される第１検出データと比較器４から出力された第２検出データとの組み合わせに応じて加入者回線の極性が検出される。具体的には、表２に示すように、第１検出データ、第２検出データのＨｉ状態／Ｌｏｗ状態の組み合わせに対して加入者回線の極性が決まっているので、検出データの組み合わせに応じて極性が検出される。   With this configuration, the polarity of the subscriber line is detected according to the combination of the first detection data output from the comparator 3 and the second detection data output from the comparator 4. Specifically, as shown in Table 2, since the polarity of the subscriber line is determined with respect to the combination of the Hi state / Low state of the first detection data and the second detection data, depending on the combination of the detection data Polarity is detected.

Figure 0004320779
Figure 0004320779

この表２に示すように、第１検出データがＨｉ状態であり、第２検出データがＬｏｗ状態である場合には、第１分圧電圧が第２分圧電圧および第３分圧電圧よりも大きくなる、すなわち、Ｌ１ラインの加入者回線電圧がＬ２ラインの加入者回線電圧よりも大きくなるので、極性はＬ１＞Ｌ２と検出される。一方、第１検出データがＬｏｗ状態であり、第２検出データがＨｉ状態である場合には、第１分圧電圧が第２分圧電圧および第３分圧電圧よりも小さくなる、すなわち、Ｌ１ラインの加入者回線電圧がＬ２ラインの加入者回線電圧よりも小さくなるので、極性はＬ１＜Ｌ２と検出される。
このような構成とすることで、２つ（２ｂｉｔ）の検出データによって、第１の実施形態と同様に加入者回線の極性を検出することができる。 As shown in Table 2, when the first detection data is in the Hi state and the second detection data is in the Low state, the first divided voltage is higher than the second divided voltage and the third divided voltage. Since the subscriber line voltage of the L1 line becomes larger than the subscriber line voltage of the L2 line, the polarity is detected as L1> L2. On the other hand, when the first detection data is in the Low state and the second detection data is in the Hi state, the first divided voltage is smaller than the second divided voltage and the third divided voltage, that is, L1 Since the subscriber line voltage of the line is smaller than the subscriber line voltage of the L2 line, the polarity is detected as L1 <L2.
With such a configuration, the polarity of the subscriber line can be detected by using two (2 bits) detection data as in the first embodiment.

次に、第３の実施形態に係る回線状態検出回路について図３を参照して説明する。
図３は本実施形態の回線状態検出回路の概略構成を示すブロック図である。
第１分圧回路１４は、直列接続された抵抗Ｒ４１と抵抗Ｒ４２とからなり、Ｌ１ラインに接続する入力端子１に抵抗Ｒ４１側の端部を接続し、抵抗Ｒ４２側の端部をグランドに接続し、抵抗Ｒ４１，Ｒ４２の接続点、すなわち分圧点を比較器３１（オペアンプ１０１）の非反転入力端子および比較器３２（オペアンプ１０２）の反転入力端子に接続している。第１プルアップ回路４１は、直列接続された抵抗Ｒ４３と抵抗Ｒ４２（第１分圧回路１４が兼用）とからなり、Ｖｃｃ入力端子６ａに抵抗Ｒ４３側の端部を接続し、抵抗Ｒ４２側の端部をグランドに接続し、抵抗Ｒ４３，Ｒ４２の接続点、すなわち外部印加電圧Ｖｃｃの抵抗Ｒ４３，Ｒ４２の分圧点を比較器３１（オペアンプ１０１）の非反転入力端子および比較器３２（オペアンプ１０２）の反転入力端子に接続している。すなわち、第１分圧回路１４の分圧点と第１プルアップ回路４１の分圧点とが接続している。 Next, a line state detection circuit according to the third embodiment will be described with reference to FIG.
FIG. 3 is a block diagram showing a schematic configuration of the line state detection circuit of the present embodiment.
The first voltage dividing circuit 14 includes a resistor R41 and a resistor R42 connected in series. The end of the resistor R41 is connected to the input terminal 1 connected to the L1 line, and the end of the resistor R42 is connected to the ground. The connection point of the resistors R41 and R42, that is, the voltage dividing point, is connected to the non-inverting input terminal of the comparator 31 (the operational amplifier 101) and the inverting input terminal of the comparator 32 (the operational amplifier 102). The first pull-up circuit 41 includes a resistor R43 and a resistor R42 (also used as the first voltage dividing circuit 14) connected in series. The end of the resistor R43 side is connected to the Vcc input terminal 6a, and the resistor R42 side is connected. The end is connected to the ground, and the connection point of the resistors R43 and R42, that is, the voltage dividing point of the resistors R43 and R42 of the externally applied voltage Vcc is used as the non-inverting input terminal of the comparator 31 (the operational amplifier 101) and the comparator 32 (the operational amplifier 102). ) Input terminal. That is, the voltage dividing point of the first voltage dividing circuit 14 and the voltage dividing point of the first pull-up circuit 41 are connected.

入力端子２に接続する第２分圧回路１７は第１局部分圧回路１５と第２局部分圧回路１６とからなる。
第１局部分圧回路１５は、直列接続された抵抗Ｒ５１と抵抗Ｒ５２とからなり、Ｌ２ラインに接続する入力端子２に抵抗Ｒ５１側の端部を接続し、抵抗Ｒ５２側の端部をグランドに接続し、抵抗Ｒ５１，Ｒ５２の接続点、すなわち分圧点を比較器３１（オペアンプ１０１）の反転入力端子に接続している。 The second voltage dividing circuit 17 connected to the input terminal 2 includes a first local partial pressure circuit 15 and a second local partial pressure circuit 16.
The first local partial pressure circuit 15 comprises a resistor R51 and a resistor R52 connected in series. The end of the resistor R51 is connected to the input terminal 2 connected to the L2 line, and the end of the resistor R52 is grounded. The connection point of the resistors R51 and R52, that is, the voltage dividing point is connected to the inverting input terminal of the comparator 31 (the operational amplifier 101).

第２局部分圧回路１６は、直列接続された抵抗Ｒ６１と抵抗Ｒ６２とからなり、Ｌ２ラインに接続する入力端子２に抵抗Ｒ６１側の端部を接続し、抵抗Ｒ６２側の端部をグランドに接続し、抵抗Ｒ６１，Ｒ６２の接続点、すなわち分圧点を比較器３２（オペアンプ１０２）の非反転入力端子に接続している。   The second local partial pressure circuit 16 includes a resistor R61 and a resistor R62 connected in series. The end of the resistor R61 is connected to the input terminal 2 connected to the L2 line, and the end of the resistor R62 is grounded. The connection point of the resistors R61 and R62, that is, the voltage dividing point is connected to the non-inverting input terminal of the comparator 32 (the operational amplifier 102).

第２プルアップ回路５１は、直列接続された抵抗Ｒ５３と抵抗Ｒ５２（第２分圧回路１７の第１局部分圧回路１５が兼用）とからなり、Ｖｃｃ入力端子６ｂに抵抗Ｒ５３側の端部を接続し、抵抗Ｒ５２側の端部をグランドに接続し、抵抗Ｒ５３，Ｒ５２の接続点、すなわち外部印加電圧Ｖｃｃの抵抗Ｒ５３，Ｒ５２の分圧点を比較器３１（オペアンプ１０１）の反転入力端子に接続している。すなわち、第２分圧回路１７の第１局部分圧回路１５の分圧点と第２プルアップ回路５１の分圧点とが接続している。   The second pull-up circuit 51 includes a resistor R53 and a resistor R52 connected in series (also used as the first local partial voltage circuit 15 of the second voltage dividing circuit 17), and the Vcc input terminal 6b has an end portion on the resistor R53 side. Is connected to the ground, and the connection point of the resistors R53 and R52, that is, the voltage dividing point of the resistors R53 and R52 of the externally applied voltage Vcc, is the inverting input terminal of the comparator 31 (the operational amplifier 101). Connected to. That is, the voltage dividing point of the first local partial pressure circuit 15 of the second voltage dividing circuit 17 and the voltage dividing point of the second pull-up circuit 51 are connected.

第３プルアップ回路６１は、直列接続された抵抗Ｒ６３と抵抗Ｒ６２（第２分圧回路１７の第２局部分圧回路１６が兼用）とからなり、Ｖｃｃ入力端子６ｃに抵抗Ｒ６３側の端部を接続し、抵抗Ｒ６２側の端部をグランドに接続し、抵抗Ｒ６３，Ｒ６２の接続点、すなわち外部印加電圧Ｖｃｃの抵抗Ｒ６３，Ｒ６２の分圧点を比較器３２（オペアンプ１０２）の非反転入力端子に接続している。すなわち、第２分圧回路１７の第２局部分圧回路１６の分圧点と第３プルアップ回路６１の分圧点とが接続している。   The third pull-up circuit 61 is composed of a resistor R63 and a resistor R62 (also used as the second local partial voltage circuit 16 of the second voltage dividing circuit 17) connected in series, and the Vcc input terminal 6c has an end portion on the resistor R63 side. Is connected to the ground, and the connection point of the resistors R63 and R62, that is, the voltage dividing point of the resistors R63 and R62 of the externally applied voltage Vcc is the non-inverting input of the comparator 32 (the operational amplifier 102). Connected to the terminal. That is, the voltage dividing point of the second local partial pressure circuit 16 of the second voltage dividing circuit 17 and the voltage dividing point of the third pull-up circuit 61 are connected.

比較器３１は、オペアンプ１０１と抵抗Ｒ１０１とを備える。オペアンプ１０１の非反転入力端子は比較器３１の非反転入力端子に相当し、第１プルアップ回路４１の抵抗Ｒ４２，Ｒ４３の接続点を介して抵抗Ｒ４１に接続している。オペアンプ１０１の反転入力端子は比較器３１の反転入力端子に相当し、第２プルアップ回路５１の抵抗Ｒ５２，Ｒ５３の接続点を介して抵抗Ｒ５１に接続している。オペアンプ１０１の接地端子は接地しており、駆動電圧入力端子はＶｃｃ入力端子７に接続するとともに、抵抗Ｒ１０１を介して出力端子に接続している。   The comparator 31 includes an operational amplifier 101 and a resistor R101. The non-inverting input terminal of the operational amplifier 101 corresponds to the non-inverting input terminal of the comparator 31, and is connected to the resistor R 41 through a connection point between the resistors R 42 and R 43 of the first pull-up circuit 41. The inverting input terminal of the operational amplifier 101 corresponds to the inverting input terminal of the comparator 31, and is connected to the resistor R 51 through a connection point between the resistors R 52 and R 53 of the second pull-up circuit 51. The ground terminal of the operational amplifier 101 is grounded, and the drive voltage input terminal is connected to the Vcc input terminal 7 and is also connected to the output terminal via the resistor R101.

比較器３２は、オペアンプ１０２と抵抗Ｒ１０２とを備える。オペアンプ１０２の非反転入力端子は比較器３２の非反転入力端子に相当し、第３プルアップ回路６１の抵抗Ｒ６２，Ｒ６３の接続点を介して抵抗Ｒ６１に接続している。オペアンプ１０２の反転入力端子は比較器３２の反転入力端子に相当し、抵抗Ｒ４１に接続している。オペアンプ１０２の接地端子は接地しており、駆動電圧入力端子はＶｃｃ入力端子８に接続するとともに、抵抗Ｒ１０２を介して出力端子に接続している。
このような回線状態検出回路は次に示すように動作する。 The comparator 32 includes an operational amplifier 102 and a resistor R102. The non-inverting input terminal of the operational amplifier 102 corresponds to the non-inverting input terminal of the comparator 32, and is connected to the resistor R 61 through a connection point between the resistors R 62 and R 63 of the third pull-up circuit 61. The inverting input terminal of the operational amplifier 102 corresponds to the inverting input terminal of the comparator 32 and is connected to the resistor R41. The ground terminal of the operational amplifier 102 is grounded, and the drive voltage input terminal is connected to the Vcc input terminal 8 and is connected to the output terminal via the resistor R102.
Such a line state detection circuit operates as follows.

入力端子１にＬ１ラインの加入者回線電圧が入力されると、抵抗Ｒ４１と抵抗Ｒ４２とからなる第１分圧回路１４にＬ１ラインの加入者回線電圧が供給されて分圧される。この第１分圧電圧は第１プルアップ回路４１を介してオペアンプ１０１の非反転入力端子およびオペアンプ１０２の反転入力端子に供給される。同時に、入力端子２にＬ２ラインの加入者回線電圧が入力されると、抵抗Ｒ５１と抵抗Ｒ５２とからなる第２分圧回路１７の第１局部分圧回路１５にＬ２ラインの加入者回線電圧が供給されて分圧される。この第２分圧電圧は第２プルアップ回路５１を介してオペアンプ１０１の反転入力端子に供給される。また、入力端子２にＬ２ラインの加入者回線電圧が入力されると、抵抗Ｒ６１とＲ６２とからなる第２分圧回路１７の第２局部分圧回路１６にＬ２ラインの加入者回線電圧が供給されて分圧される。この第３分圧電圧は第３プルアップ回路６１を介してオペアンプ１０２の非反転入力端子に供給される。ここで、抵抗Ｒ４１，Ｒ４２による分圧比（第１分圧回路の分圧比）と、抵抗Ｒ５１，Ｒ５２による分圧比（第１局部分圧回路の分圧比）と、抵抗Ｒ６１，Ｒ６２による分圧比（第２局部分圧回路の分圧比）は略同じに設定されている。   When the subscriber line voltage of the L1 line is input to the input terminal 1, the subscriber line voltage of the L1 line is supplied to the first voltage dividing circuit 14 composed of the resistors R41 and R42 and divided. The first divided voltage is supplied to the non-inverting input terminal of the operational amplifier 101 and the inverting input terminal of the operational amplifier 102 via the first pull-up circuit 41. At the same time, when the subscriber line voltage of the L2 line is input to the input terminal 2, the subscriber line voltage of the L2 line is applied to the first local partial pressure circuit 15 of the second voltage dividing circuit 17 composed of the resistors R51 and R52. Supplied and divided. This second divided voltage is supplied to the inverting input terminal of the operational amplifier 101 via the second pull-up circuit 51. When the L2 line subscriber line voltage is input to the input terminal 2, the L2 line subscriber line voltage is supplied to the second local partial circuit 16 of the second voltage dividing circuit 17 composed of resistors R61 and R62. And is divided. This third divided voltage is supplied to the non-inverting input terminal of the operational amplifier 102 via the third pull-up circuit 61. Here, the voltage dividing ratio by the resistors R41 and R42 (the voltage dividing ratio of the first voltage dividing circuit), the voltage dividing ratio by the resistors R51 and R52 (the voltage dividing ratio of the first local partial pressure circuit), and the voltage dividing ratio by the resistors R61 and R62 ( The voltage division ratio of the second local partial pressure circuit is set to be substantially the same.

ここで、第１プルアップ回路４１の抵抗Ｒ４２，Ｒ４３の接続点がオペアンプ１０１の非反転入力端子とオペアンプ１０２の反転入力端子とに接続しているので、無接続状態のようにＬ１ライン、Ｌ２ラインが開放であった場合に、これらの端子にはＶｃｃ電圧をグランドとの間において抵抗Ｒ４２，Ｒ４３で分圧した電圧がプルアップ電圧として入力される。また、抵抗Ｒ５２，Ｒ５３の接続点がオペアンプ１０１の反転入力端子に接続しているので、この端子にはＶｃｃ電圧をグランドとの間において抵抗Ｒ５２，Ｒ５３で分圧した電圧がプルアップ電圧として入力される。また、抵抗Ｒ６２，Ｒ６３の接続点がオペアンプ１０２の非反転入力端子に接続しているので、この端子にはＶｃｃ電圧をグランドとの間において抵抗Ｒ６２，Ｒ６３で分圧した電圧がプルアップ電圧として入力される。この際、抵抗Ｒ４３，Ｒ４２でのＶｃｃの分圧電圧は、抵抗Ｒ５３，Ｒ５２でのＶｃｃの分圧電圧よりも小さく、抵抗Ｒ６３，Ｒ６２での分圧電圧よりも大きく設定されている。   Here, since the connection point of the resistors R42 and R43 of the first pull-up circuit 41 is connected to the non-inverting input terminal of the operational amplifier 101 and the inverting input terminal of the operational amplifier 102, the L1 line, L2 When the line is open, a voltage obtained by dividing the Vcc voltage with the resistors R42 and R43 with respect to the ground is input to these terminals as a pull-up voltage. Since the connection point of the resistors R52 and R53 is connected to the inverting input terminal of the operational amplifier 101, a voltage obtained by dividing the Vcc voltage with the resistors R52 and R53 between the ground and the ground is input to this terminal as a pull-up voltage. Is done. Since the connection point of the resistors R62 and R63 is connected to the non-inverting input terminal of the operational amplifier 102, a voltage obtained by dividing the Vcc voltage with the resistors R62 and R63 between the ground and the ground is used as the pull-up voltage. Entered. At this time, the divided voltage of Vcc at the resistors R43 and R42 is set smaller than the divided voltage of Vcc at the resistors R53 and R52 and larger than the divided voltage at the resistors R63 and R62.

前述の各抵抗値の設定としては、例えば、抵抗Ｒ４１を５．６ＭΩ、抵抗Ｒ４２，Ｒ４３を１１０ｋΩ、抵抗Ｒ５１，Ｒ６１を１０ＭΩ、抵抗Ｒ５２，Ｒ６３を１９９．５５ｋΩ、抵抗Ｒ５３，Ｒ６２を１９３．４ｋΩとすればよい。   As the setting of each of the above resistance values, for example, the resistor R41 is 5.6 MΩ, the resistors R42 and R43 are 110 kΩ, the resistors R51 and R61 are 10 MΩ, the resistors R52 and R63 are 199.55 kΩ, and the resistors R53 and R62 are 193.4 kΩ. And it is sufficient.

このような構成とすることで、オペアンプ１０１の非反転入力端子およびオペアンプ１０２の反転入力端子に第１プルアップ回路４１からのプルアップ電圧が供給され、オペアンプ１０１の反転入力端子に第２プルアップ回路５１からのプルアップ電圧が供給され、オペアンプ１０２の非反転入力端子に第３プルアップ回路６１からのプルアップ電圧が供給される。これにより、無接続時には、オペアンプ１０１，１０２ともに非反転入力端子に入力される電圧が反転入力端子に入力される電圧よりも低くなる。   With such a configuration, the pull-up voltage from the first pull-up circuit 41 is supplied to the non-inverting input terminal of the operational amplifier 101 and the inverting input terminal of the operational amplifier 102, and the second pull-up voltage is applied to the inverting input terminal of the operational amplifier 101. The pull-up voltage from the circuit 51 is supplied, and the pull-up voltage from the third pull-up circuit 61 is supplied to the non-inverting input terminal of the operational amplifier 102. Thus, when there is no connection, the voltage input to the non-inverting input terminal of both the operational amplifiers 101 and 102 is lower than the voltage input to the inverting input terminal.

オペアンプ１０１は抵抗Ｒ１０１とともにコンパレータとして機能し、非反転入力端子に入力される第１プルアップ回路４１の出力電圧（第１分圧電圧をプルアップした電圧）と、反転入力端子に入力される第２プルアップ回路５１の出力電圧（第２分圧電圧をプルアップした電圧）とを比較する。そして、第１プルアップ回路４１の出力電圧が第２プルアップ回路５１の出力電圧よりも大きければ、オペアンプ１０１はＨｉ状態（３．３Ｖ）の第１検出データを出力する。一方、第１プルアップ回路４１の出力電圧が第２プルアップ回路５１の出力電圧よりも小さければ、オペアンプ１０１はＬｏｗ状態（０Ｖ）の第１検出データを出力する。また、前述のような無接続状態の場合、非反転入力端子に入力される電圧が反転入力端子に入力される電圧よりも低くなるので、オペアンプ１０１はＬｏｗ状態（０Ｖ）の第１検出データを出力する。   The operational amplifier 101 functions as a comparator together with the resistor R101, the output voltage of the first pull-up circuit 41 (voltage obtained by pulling up the first divided voltage) input to the non-inverting input terminal, and the first input to the inverting input terminal. 2 The output voltage of the pull-up circuit 51 (voltage obtained by pulling up the second divided voltage) is compared. If the output voltage of the first pull-up circuit 41 is larger than the output voltage of the second pull-up circuit 51, the operational amplifier 101 outputs the first detection data in the Hi state (3.3 V). On the other hand, if the output voltage of the first pull-up circuit 41 is smaller than the output voltage of the second pull-up circuit 51, the operational amplifier 101 outputs the first detection data in the low state (0 V). In the non-connection state as described above, since the voltage input to the non-inverting input terminal is lower than the voltage input to the inverting input terminal, the operational amplifier 101 receives the first detection data in the low state (0 V). Output.

オペアンプ１０２は抵抗Ｒ１０２とともにコンパレータとして機能し、反転入力端子に入力される第１プルアップ回路４１の出力電圧（第１分圧電圧をプルアップした電圧）と、非反転入力端子に入力される第３プルアップ回路６１の出力電圧（第３分圧電圧をプルアップした電圧）とを比較する。そして、第３プルアップ回路６１の出力電圧が第１プルアップ回路４１の出力電圧よりも大きければ、オペアンプ１０２はＨｉ状態（３．３Ｖ）の第２検出データを出力する。一方、第３プルアップ回路６１の出力電圧が第１プルアップ回路４１の出力電圧よりも小さければ、オペアンプ１０２はＬｏｗ状態（０Ｖ）の第２検出データを出力する。また、前述のような無接続状態の場合、非反転入力端子に入力される電圧が反転入力端子に入力される電圧よりも低くなるので、オペアンプ１０２はＬｏｗ状態（０Ｖ）の第２検出データを出力する。   The operational amplifier 102 functions as a comparator together with the resistor R102, and the output voltage of the first pull-up circuit 41 (voltage obtained by pulling up the first divided voltage) input to the inverting input terminal and the first input input to the non-inverting input terminal. The output voltage of the 3 pull-up circuit 61 (voltage obtained by pulling up the third divided voltage) is compared. If the output voltage of the third pull-up circuit 61 is larger than the output voltage of the first pull-up circuit 41, the operational amplifier 102 outputs the second detection data in the Hi state (3.3V). On the other hand, if the output voltage of the third pull-up circuit 61 is smaller than the output voltage of the first pull-up circuit 41, the operational amplifier 102 outputs the second detection data in the low state (0 V). In the non-connection state as described above, since the voltage input to the non-inverting input terminal is lower than the voltage input to the inverting input terminal, the operational amplifier 102 receives the second detection data in the low state (0 V). Output.

このような構成では、オペアンプ１０１から出力される第１検出データとオペアンプ１０２から出力された第２検出データとの組み合わせに応じて加入者回線の極性が検出される。具体的には、表３に示すように、第１検出データ、第２検出データのＨｉ状態／Ｌｏｗ状態の組み合わせに対して加入者回線の極性および接続状態が決まっており、検出した組み合わせに応じて極性および接続状態が検出する。   In such a configuration, the polarity of the subscriber line is detected according to the combination of the first detection data output from the operational amplifier 101 and the second detection data output from the operational amplifier 102. Specifically, as shown in Table 3, the polarity and connection state of the subscriber line are determined for the combination of the Hi state / Low state of the first detection data and the second detection data, and depending on the detected combination Polarity and connection status are detected.

Figure 0004320779
Figure 0004320779

この表３に示すように、第１検出データがＨｉ状態であり、第２検出データがＬｏｗ状態である場合には、第１分圧電圧が第２分圧電圧および第３分圧電圧よりも大きくなる、すなわち、Ｌ１ラインの加入者回線電圧がＬ２ラインの加入者回線電圧よりも大きくなるので、極性はＬ１＞Ｌ２と検出される。一方、第１検出データがＬｏｗ状態であり、第２検出データがＨｉ状態である場合には、第１分圧電圧が第２分圧電圧および第３分圧電圧よりも大きくなる、すなわち、Ｌ１ラインの加入者回線電圧がＬ２ラインの加入者回線電圧よりも小さくなるので、極性はＬ１＜Ｌ２と検出される。   As shown in Table 3, when the first detection data is in the Hi state and the second detection data is in the Low state, the first divided voltage is higher than the second divided voltage and the third divided voltage. Since the subscriber line voltage of the L1 line becomes larger than the subscriber line voltage of the L2 line, the polarity is detected as L1> L2. On the other hand, when the first detection data is in the Low state and the second detection data is in the Hi state, the first divided voltage is larger than the second divided voltage and the third divided voltage, that is, L1 Since the subscriber line voltage of the line is smaller than the subscriber line voltage of the L2 line, the polarity is detected as L1 <L2.

さらに、第１分圧電圧、第２分圧電圧、第３分圧電圧がＶｃｃによりプルアップされた電圧のみからなる場合、第１検出データと第２検出データとがともにＬｏｗ状態になるので、無接続状態が検出される。   Furthermore, when the first divided voltage, the second divided voltage, and the third divided voltage are composed of only the voltage pulled up by Vcc, the first detection data and the second detection data are both in the low state. A disconnected state is detected.

このような構成とすることで、２つ（２ｂｉｔ）の検出データによって、前述のように通話状態によらず極性を検出するとともに、無接続状態を検出する回線状態検出回路を実現することができる。   By adopting such a configuration, it is possible to realize a line state detection circuit that detects a polarity and detects a non-connection state by using two (2 bits) detection data, as described above, regardless of the call state. .

第１の実施形態に係る回線状態検出回路のブロック図Block diagram of a line state detection circuit according to the first embodiment 第２の実施形態に係る回線状態検出回路のブロック図Block diagram of a line state detection circuit according to the second embodiment 第３の実施形態に係る回線状態検出回路のブロック図Block diagram of a line state detection circuit according to the third embodiment

符号の説明Explanation of symbols

１，２−入力端子
３，４，３１，３２−比較器
１１，１２，１４，１５，１６−分圧回路
１２１，１２２−局部分圧回路
４１，５１，６１−プルアップ回路
６ａ〜６ｃ，７，８−Ｖｃｃ入力端子
１０１，１０２−オペアンプ 1, 2-input terminals 3, 4, 31, 32-comparators 11, 12, 14, 15, 16-voltage dividing circuits 121, 122-local partial pressure circuits 41, 51, 61-pull-up circuits 6a to 6c, 7,8-Vcc input terminals 101, 102-operational amplifier

Claims (1)

２つの加入者回線電圧の一方を分圧して出力する第１分圧回路と、
前記加入者回線電圧の他方を分圧して、値の異なる２つの分圧電圧を出力する第２分圧回路と、
前記第１分圧回路の分圧電圧出力と前記第２分圧回路の一方の分圧電圧出力とを比較する第１比較器と、前記第１分圧回路の分圧電圧出力と前記第２分圧回路の他方の分圧電圧出力とを前記第１比較器とは逆の論理で比較する第２比較器とを備え、前記第１分圧回路の分圧電圧出力と前記第２分圧回路の分圧電圧出力とを比較する比較手段と、
前記第１比較器と前記第２比較器との入力端子にそれぞれプルアップ電圧を印加するプルアップ電圧印加手段と、を備え、
前記２つの加入者回線電圧が印加されていない時に、前記第１分圧回路の分圧電圧出力が入力される前記入力端子に印加される電圧が、前記第２分圧回路の分圧電圧出力の一方が入力される前記入力端子に印加される電圧よりも低く、前記第２分圧回路の分圧電圧出力の他方が入力される前記入力端子に印加される電圧よりも高くなるように前記第１分圧回路、前記第２分圧回路および前記プルアップ電圧印加手段が構成されていることを特徴とする回線状態検出回路。 A first voltage dividing circuit for dividing and outputting one of the two subscriber line voltages;
A second voltage dividing circuit that divides the other of the subscriber line voltages and outputs two divided voltages having different values ;
A first comparator for comparing the divided voltage output of the first voltage dividing circuit with one of the divided voltage outputs of the second voltage dividing circuit; the divided voltage output of the first voltage dividing circuit; A second comparator for comparing the other divided voltage output of the voltage dividing circuit with a logic opposite to that of the first comparator, and the divided voltage output of the first voltage dividing circuit and the second divided voltage A comparison means for comparing the divided voltage output of the circuit;
Pull-up voltage applying means for applying a pull-up voltage to the input terminals of the first comparator and the second comparator, respectively,
The voltage applied to the input terminal to which the divided voltage output of the first voltage dividing circuit is input when the two subscriber line voltages are not applied is the divided voltage output of the second voltage dividing circuit. The voltage is lower than the voltage applied to the input terminal to which one of the two is input, and higher than the voltage applied to the input terminal to which the other divided voltage output of the second voltage dividing circuit is input. A line state detection circuit comprising a first voltage dividing circuit, the second voltage dividing circuit, and the pull-up voltage applying means .
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