JP4318900B2 - Game machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gaming machine having a plurality of light emitting elements as display means for displaying game contents and lighting means for effects.
[0002]
[Prior art]
In gaming machines such as pachinko machines and slot machines, a large number of LEDs are arranged on the front of the machine body in order to display information related to game contents and to produce effects by electrical decoration.
In general, in this type of gaming machine, LED lighting control is performed by dynamic drive control in a sub-control unit that is independent from a main control unit that performs main control of the game. For example, in Patent Document 1 below, a wiring board on which a plurality of matrix-connected LEDs are mounted is connected to a CPU via an I / O port, and a drive signal from the CPU is sent to each common signal line and segment signal line. Are sequentially switched so that the lighting operation of each LED is switched at high speed.
[0003]
[Patent Document 1]
JP 2001-327661 A (pages 11 to 14, FIGS. 4 and 9)
[0004]
Also, in conventional pachinko machines and slot machines, when the brightness is changed by the LED to be controlled, such as lighting with different brightness depending on the location, the pulse width of the LED is changed by changing the pulse width of the drive signal for the common side. The lighting time is changed. Since the lighting control for each LED can be switched at high speed, if the lighting time for a given LED group is different from the other LED groups, the LED group has a different brightness from the other LED groups due to the effect of the afterimage phenomenon. It appears to emit light.
[0005]
[Problems to be solved by the invention]
In the control as described in Patent Document 1, the CPU applies a driving voltage to a predetermined common signal line, and a control signal that instructs each LED connected to the common signal line to light or not (this specification). Then, the process of outputting the “lighting control signal” is executed alternately. However, such control increases the burden on the CPU and increases the capacity of the program. In particular, if the number of LEDs introduced is increased in order to increase the illumination effect, an excessive burden is placed on the CPU and it may be difficult to switch the lighting state of each LED at high speed. In order to solve this problem, if a high-performance CPU or a large-capacity memory is used, there is a problem that the cost is increased.
[0006]
In addition, when adjusting the apparent brightness by controlling the lighting time of the LED, the CPU needs to switch the voltage application time when the drive target is switched. In this way, when the voltage application time is managed in the CPU, it is necessary to execute a plurality of steps such as a process for counting elapsed time and a process for determining whether or not the time is up. There arises a problem that the control burden and program capacity of the system become large. In addition, if the drive voltage supply time is set to be long in order to light the LED brightly, the time required for lighting control becomes long, and it becomes difficult to switch the lighting state of the LED at high speed.
[0007]
The present invention has been made paying attention to the above problems, and performs a process of performing dynamic lighting control on a large number of light emitting elements and a process of adjusting the brightness of a light emitter without increasing the burden on the CPU and software. The purpose is to make it possible.
[0008]
[Means for Solving the Problems]
  A gaming machine according to one configuration of the present invention includes a plurality of light-emitting elements connected in a matrix.A control unit that is individually connected to each segment signal line and outputs a lighting control signal for each segment signal line in parallel, and a plurality of switch units that individually connect each common signal line in the connection circuit to a drive power source, A shift register for controlling opening and closing of each switch unit, and a frequency dividing circuit for generating and outputting a drive clock for operating the shift register by inputting and dividing the internal clock signal of the control unit It comprises.
  The shift register includes more output terminals than the number of the switch units, an input terminal for inputting the drive clock, and a clear terminal, and the same number of output terminals as the switch units are provided on a one-to-one basis for each switch unit. In addition, one output terminal lower than the output terminal connected to the switch unit and an input path for an external reset signal are connected to the clear terminal. The output path of the drive clock from the frequency divider circuit is divided into two parts, one connected to the input terminal of the shift register and the other connected to the input terminal of the control unit. Each switch unit closes in response to a drive pulse from a corresponding output terminal of the shift register.
  Further, the shift register switches the output terminal that outputs the drive pulse one by one in order from the higher order, and each time the drive clock from the frequency divider circuit is input, the shift register outputs the drive pulse from the switched output terminal. Operates to output. Further, the control unit recognizes the timing at which the switching of each switch unit is switched based on the input of the driving clock from the frequency divider circuit, and outputs an hourly lighting control signal in accordance with the recognized timing.
[0009]
  In the above gaming machine, the light emitting element is, for example, an LED, and a predetermined number of LEDs are used as one unit, and one electrode of each LED is commonly connected for each unit. The other electrode of each LED is connected in series for each LED of the common segment, and is connected to the control unit side. The control unit is a microcomputer including a CPU.AndOutput ports that output lighting control signals for each light emitting elementIt has.
[0010]
  In addition,Each switch unit can be integrated as an IC having a number of semiconductor switches corresponding to the number of common signal lines.
[0011]
  According to the gaming machine configured as described above,The switch unit to be closed is sequentially switched by the drive pulse from the shift register that operates based on the drive clock generated by dividing the internal clock signal of the control unit, thereby switching the common signal line to which the voltage is applied. be able to. In addition, the shift register is reset by an external reset signal or a drive pulse output from its own circuit after the output of the drive pulse to each switch unit is completed, so that the voltage application to each common signal line is switched. Control can be executed repeatedly. In addition, since the control unit outputs the lighting control signal in accordance with the switching timing described above, it is possible to control the lighting operation of each light emitting element for each one connected to the same common signal line. Therefore,Control which switches lighting operation of each light emitting element at high speed can be implement | achieved significantly reducing the burden of a control part. Moreover, since the algorithm for controlling the common side is not required, the capacity of the program can be reduced, and the lighting operation of a large number of light emitting elements can be easily controlled using a control unit having the same performance as the conventional one. Is possible.
[0012]
  In a preferred aspect of the gaming machine having the above configuration,The shift register is provided with a second input terminal for inputting a signal for validating or invalidating the input of the driving clock. The output line from the control unit includes a signal line connected to each segment signal line and a signal line connected to the second input terminal of the shift register. Further, the control unit sets a signal for the second input terminal of the shift register to a state in which the input of the driving clock is made valid while continuing to output the lighting control signal, and outputs the lighting control signal. In response to the stop or end, the signal to the second input terminal of the shift register is set to a state in which the input of the drive clock becomes invalid.
  According to the above aspect, when the control unit stops or ends the output of the lighting control, the switching control of the switch unit by the shift register can be stopped accordingly.
[0013]
  Next, a gaming machine according to another configuration of the present invention comprises a predetermined number of light emitters and a constant voltage circuit for generating a drive voltage for the light emitters.A control unit that outputs a lighting control signal to the light emitter connected to the plurality of switches, a plurality of switch units that individually connect a plurality of resistance circuits having different resistance values as detection resistors to the constant voltage circuit, and A shift register for controlling opening and closing; and a frequency dividing circuit for generating and outputting a drive clock for operating the shift register by inputting and dividing the internal clock signal of the control unit. The shift register includes more output terminals than the number of the switch units, an input terminal for inputting the drive clock, and a clear terminal, and the same number of output terminals as the switch units are provided on a one-to-one basis for each switch unit. In addition, one output terminal lower than the output terminal connected to the switch unit and an input path for an external reset signal are connected to the clear terminal. Further, the output path of the drive clock from the frequency divider circuit is divided into two parts, one being connected to the input terminal of the shift register and the other being connected to the input terminal of the control unit. Each of the switch sections closes in response to a drive pulse from a corresponding output terminal of the shift register.
  Further, the shift register switches the output terminal that outputs the drive pulse one by one in order from the highest one, and outputs the drive pulse from the switched output terminal each time the drive clock from the frequency divider is input. To work. Further, the control unit recognizes the timing at which the switching of each switch unit is switched based on the input of the drive clock from the frequency divider circuit, and recognizes the lighting control signal to the light emitter connected to the constant voltage circuit. According to the output.
[0014]
  Each light emitter may be a single light emitting element, but a plurality of light emitting elements may be connected in common. The constant voltage circuit is, for example, an output voltage variable regulator IC,By changing the resistance value of the detection resistor by switching the open / close state of the switchThe magnitude of the output voltage can be changed.
[0015]
  In addition,The switch unit can be configured by a semiconductor switch such as a transistor or FET.
[0016]
  The control unit is a microcomputer having a CPU and a memory, like the gaming machine having the above configuration.It is. Also,When one light emitter is constituted by a plurality of light emitting elements, the control unitA process of switching the light emitter connected to the constant voltage circuit and a process of outputting a lighting control signal to the light emitter connected to the constant voltage circuit are executed in accordance with the timing at which the switching state of the switch unit is switched.
[0017]
  Of the above configurationAccording to the gaming machine,The switch unit is sequentially switched by the drive pulse from the shift register that operates based on the drive clock generated by dividing the internal clock signal of the control unit, thereby switching the detection resistor of the constant voltage circuit and switching the output voltage. . The shift register is reset by a reset signal from the outside or a drive pulse output from its own circuit after the output of the drive pulse to each switch unit, so it repeatedly executes control to switch the output voltage of the constant voltage circuit can do. Also, according to this switching, a lighting control signal is output from the control unit to the light emitters connected to the constant voltage circuit, so that the brightness of the light emitters can be changed in stages or the plurality of light emitters can be different from each other. It becomes possible to light up with brightness.
[0018]
  Preferred embodiment of the gaming machineThe shift register is provided with a second input terminal for inputting a signal for enabling or disabling the input of the drive clock. The output line from the control unit includes a signal line connected to each segment signal line and a signal line connected to the second input terminal of the shift register. Further, the control unit sets a signal for the second input terminal of the shift register to a state in which the input of the driving clock is made valid while continuing to output the lighting control signal, and outputs the lighting control signal. In response to the stop or end, the signal for the second input terminal of the shift register is set to a state in which the input of the drive clock is invalidated.
  According to the above aspect, when the control unit stops or ends the lighting of the light emitter, it is possible to end the control for switching the output voltage of the constant voltage circuit accordingly.
[0019]
In addition, the light emitter used in the gaming machine according to the present invention is not limited to an LED, and an EL (Electro Luminescence) can also be used. In addition, the present invention can be applied to display control of an LCD in a gaming machine using an LCD (liquid crystal display).
[0020]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a configuration of a lighting control device in a gaming machine (pachinko machine, slot machine, etc.) to which the present invention is applied. This lighting control device 20 is for controlling the lighting operation of the LED 7 for lighting provided on the front surface of the aircraft based on a command from a main control device (not shown). The CPU 1, the frequency dividing circuit 2, the shift register 3 , Common drive circuit 4, data output port 5, segment drive circuit 6 and the like are mounted. Although not shown here, the CPU 1 is connected to a memory such as a ROM or a RAM. The illumination control device 20 is also provided with a power supply circuit (a regulator 11 according to a second embodiment described later corresponds to this) that serves as a drive source for the LED 7.
[0021]
The lighting control device 20 controls an anode common type LED 7 connected in an n × m matrix (in this embodiment, for convenience of illustration and description, three on the common side and four on the segment side). It is assumed that the LED 7 is connected.) The common signal lines C0, C1, C2, and C3 are connected to the common drive circuit 4, and the segment signal lines S0, S1, and S2 are connected to the segment drive circuit 6, respectively.
[0022]
The frequency dividing circuit 2 takes in an internal clock signal of the CPU 1 and divides it to generate a clock signal for driving the shift register 3 (hereinafter referred to as “drive clock”). By the shift operation of the shift register 3 according to the drive clock, the common signal lines C0 to C3 to be driven by the common drive circuit 4 are sequentially switched, and the common signal line to be driven is required for driving the LED 7. A voltage (hereinafter referred to as “driving voltage”) is applied.
[0023]
On the other hand, the segment drive circuit 6 is connected to the CPU 1 via the data output port 5. The driving clock from the frequency dividing circuit 2 is also input to the CPU 1, and the CPU 1 outputs the lighting control signals for the segment signal lines S0 to S2 in parallel according to the timing of the driving clock. Therefore, the lighting control signal is given to each LED group (hereinafter simply referred to as “LED group”) that is connected to the same common signal line and receives voltage application at the same time. A turn-off instruction is given.
[0024]
Since the switching process by the shift register 3 is performed at a high speed, the lighting of each LED group is switched at an extremely short time interval if any lighting control signal for each segment indicates “lighting”. Therefore, any LED 7 can appear to be continuously lit.
[0025]
In the conventional lighting control based on the dynamic drive method, the control on both the common side and the segment side is performed by the CPU, so that there is a problem that the control burden on the CPU becomes large and the program capacity increases. In contrast, in this embodiment, since the switching process for the common side is controlled by the shift register 3, the CPU 1 only has to perform the lighting control for the segment side in accordance with the switching timing. Control burden and program capacity can be reduced. Even if the number of LEDs 7 to be controlled increases and the number of commons increases, an increase in the processing time of the CPU 1 can be suppressed, so that it is possible to cope without increasing the performance of the CPU 1.
[0026]
FIG. 2 shows a specific circuit configuration of the illumination control device 20. Note that each electronic component in the figure corresponds to 8 bits, but here, it is limited to the configuration necessary for executing the control on the matrix of 3 columns × 4 rows, and is not related to the processing. The signal lines and signal lines are not shown except for some parts. In the figure, the reset signal at the left end is supplied from a power supply device (not shown), and is switched from a low level to a high level when a predetermined time elapses after the power is turned on.
[0027]
The frequency divider 2 and the shift register 3 of this embodiment are reset according to the timing when the input to the clear terminal CLR falls from the high level to the low level. In the illustrated circuit, the reset signal is input to the clear terminal CLR of the frequency divider 2 or the shift register 3 via the NOT circuit 8 in accordance with this characteristic.
[0028]
As described above, the frequency dividing circuit 2 generates a drive clock by dividing the internal clock signal input from the CPU 1. The frequency dividing ratio of the frequency dividing circuit 2 is set so that the driving clock is output at a timing corresponding to the time length necessary for generating the lighting control signal for each LED group on the CPU 1 side. The generated drive clock is supplied to the shift register 3 and the CPU 1.
[0029]
The shift register 3 inputs the drive clock to the input terminal CK, and sequentially outputs a drive pulse signal having a predetermined width from each output terminal in accordance with the drive clock. In this shift register 3, up to five output terminals Q0 to Q4 are used, but the common drive circuit 4 is connected to Q0 to Q3 corresponding to the common signal lines C0 to C3. The fifth output terminal Q4, which is each output terminal, is connected to the clear terminal CLR of its own circuit via the OR circuit 10. When the clear signal is input, the shift register 3 is cleared, so that the output is started again from the first output terminal Q0 by the next drive clock. Therefore, in the shift register 3, the drive pulses corresponding to the common signal lines C0 to C3 are repeatedly output with five drive clocks as one cycle. An inverted reset signal from the NOT circuit 8 is input to the other input terminal of the OR circuit 10.
[0030]
The common drive circuit 4 is an IC incorporating a transistor array having a size corresponding to the number of sets of input / output terminals, and its power supply terminal is connected to a 12V DC power supply for LED driving. Input terminals T0 to T3 of the common drive circuit 4 are connected to output terminals Q0 to Q3 of the shift register 3, and output terminals U0 to U3 are connected to the common signal lines C0 to C3, respectively. In the common drive circuit 4, when a drive pulse from the shift register 3 is given to any one of the input terminals T0 to T3, transistors between the input terminals T0 to T3 and the corresponding output terminals U0 to U3 are turned on. The 12V direct current flows to the output terminals U0 to U3.
[0031]
Next, the data output port 5 is set so as to relay a 4-bit signal line among the 8-bit signal lines of the CPU 1. Among these signal lines, the upper 3 bit signal lines (outputs from the terminals D0 to D2 of the CPU 1) serve as the transmission path of the lighting control signal. These lighting control signals are input to the segment drive circuit 6 via the data output port 5. On the other hand, the fourth bit signal line (output from the terminal D3 of the CPU 1) is input to the input terminal CE of the shift register 3 via the NOT circuit 9.
[0032]
Similar to the common drive circuit 4, the segment drive circuit 6 is an IC containing a transistor array having a size corresponding to the number of sets of input / output terminals. The segment drive circuit 6 receives a DC power supply (not shown) and receives the data output port 5 The lighting control signal from is relayed in a non-inverted state. The lighting control signal output terminals H0 to H3 have resistances R, respectively._A, R_B, R_CAre connected to the segment signal lines S0 to S3.
[0033]
The lighting control signal of this embodiment is normally at a high level, and is set as a signal that becomes a low level when instructing “lighting”. Therefore, if the lighting control signal for a predetermined segment is at a low level, the LED 7 corresponding to the lighting control signal at the low level in the LED group to which the voltage is applied by the common drive circuit 4 is turned on and turned on. Become.
[0034]
Note that the shift register 3 actually performs a shift operation based on the logical product of the input from the input terminal CK and the inverted signal of the input from the input terminal CE. As described above, an inverted signal of the output from the output terminal D3 of the CPU 1 is input to the input terminal CE. However, the output from the output terminal D3 is normally at a high level as in the case of the lighting control signal. It is set to be. Therefore, the normal input level to the input terminal CE becomes a low level, and the shift operation can proceed according to the inverted signal and the drive clock from the input terminal CK.
[0035]
In the above configuration, the shift register 3 sequentially outputs drive pulses to the input terminals T0 to T3 of the common drive circuit 4 at a timing according to the drive clock from the frequency divider circuit 2. Based on this drive pulse, the internal transistors of the common drive circuit 4 are sequentially turned on, so that a drive voltage of DC 12 V is sequentially applied to the common signal lines C0 to C3.
[0036]
On the other hand, the CPU 1 recognizes the timing at which the LED group to be driven is switched based on the drive clock from the frequency dividing circuit 2, and outputs a lighting control signal for the LED group to be driven in accordance with this timing. This lighting control signal is given to the segment signal lines S0 to S3 via the data output port 5 and the segment drive circuit 6, and the lighting operation of the LED group is controlled.
[0037]
Even when the CPU 1 stops or ends the output of the lighting control signal, the common-side switching control by the shift register 3 and the common drive circuit 4 is continuously performed. When it is necessary to stop the switching control, the CPU 1 switches the output from the output terminal D3 from the high level to the low level. As a result, the input of the drive clock to the shift register 3 is invalidated, and the switching control for the common side is stopped.
[0038]
FIG. 3 shows a configuration of the illumination control device 21 according to the second embodiment.
The illumination control device 21 of this embodiment is configured to sequentially switch the lighting operation of each light emitter in accordance with the supply timing while supplying different driving voltages to two light emitters (not shown). . Each light emitter is an aggregate of a plurality of LEDs, and each LED is commonly connected to each light emitter. Further, the CPU 1 of this embodiment is set so as to alternately execute the switching control on the common side and the lighting control on the segment side as in the prior art.
[0039]
In this embodiment, a variable output voltage type three-terminal regulator 11 is used as a power supply circuit for generating a driving voltage for each light emitter, and a detection resistor for defining the output voltage of the regulator 11 is used as the first resistor. The frequency switching circuit 2 and the shift register 3 which are the same as those in the first embodiment are sequentially switched. In addition, detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol as FIG.1, 2 to the electronic component similar to a 1st Example.
[0040]
Input voltage terminal V of the regulator 11_inIs supplied with a predetermined level of direct current DC1 from the power supply device (not shown). Output voltage terminal V_outIs connected to a resistor R1, and a second resistor R2 is connected in series to the resistor R1. A third resistor R3 is connected to the set voltage control terminal ADJ, and a signal line branched from the connection between the resistors R1 and R2 is connected to a connection path between the terminal ADJ and the resistor R3.
[0041]
As the resistors R2 and R3, resistors having different resistance values are used. These resistors R2 and R3 are connected to the ground via NPN transistors TR1 and TR2, respectively. As a result, when the transistor TR1 becomes conductive, the resistors R1 and R2 function as detection resistors of the regulator 11. On the other hand, when the transistor TR2 becomes conductive, the resistors R1 and R3 serve as detection resistors of the regulator 11. Will work.
In FIG. 3, reference numerals 12 and 14 are polar smoothing capacitors, and reference numerals 13 and 15 are bypass capacitors.
[0042]
In the shift register 3 of this embodiment, the upper three output terminals Q0 to Q2 are used for the control of the regulator 11. The first output terminal Q0 is connected to the base of the transistor TR2 through a resistor R4, and the second output terminal Q1 is connected to the base of the transistor TR1 through a resistor R5. The third output terminal Q2 is connected to the clear terminal CLR of the shift register 3 via the OR circuit 10.
[0043]
In the above configuration, the frequency dividing circuit 2 generates a drive clock from the internal clock of the CPU 1 and outputs it to the shift register 3 and the CPU 1 as in the first embodiment. In the frequency dividing circuit 2 of this embodiment, the time required for the process of applying a voltage to the common side of one light emitter and the process of outputting the lighting control signal to the segment side of the light emitter is determined. The frequency division ratio is set so that the drive clock is output at the timing.
[0044]
The shift register 3 repeatedly executes a process of outputting drive pulses in order from the output terminals Q0 and Q1 according to the drive clock. Thereby, the on and off states of the transistors TR1 and TR2 are sequentially switched, and the detection resistance of the regulator 11 is switched in accordance with the switching, so that the voltage output terminal V_outThe output potential DC2 from is switched.
[0045]
The CPU 1 recognizes the switching timing of the output voltage DC2 of the regulator 11 based on the driving clock, switches the supply destination of the driving voltage according to this timing, and outputs a lighting control signal for the light emitting body that is the power supply destination. As a result, the two light emitters are turned on under the supply of drive voltages of different levels, and a brightness difference corresponding to the difference of the drive voltages appears between the light emitters. It becomes like this.
[0046]
In this embodiment, the output from the first output terminal D0 of the CPU 1 is input to the input terminal CE of the shift register 3 via the NOT circuit 9. Similar to the first embodiment, this signal is used for stopping the shift operation of the shift register 3 at an arbitrary timing, and is normally set to a high level.
[0047]
In the above embodiment, the two light emitters emit light with different brightnesses. However, the present invention is not limited to this, and brightness of up to 7 levels is set according to the number of terminals of the shift register 3. Can do. If the output interval of the drive clock is set large, a plurality of light emitters can be turned on by the output voltage at each stage.
[0048]
In this way, even when several types of light emitters have different brightness, the CPU 1 can execute the same control on each light emitter, reducing the burden on the CPU 1, An increase in program capacity can be avoided. Also, even if the brightness is increased, the time required for lighting control of individual light emitters does not fluctuate. Therefore, even when the number of light emitters to be controlled increases, the influence on the control for switching the lighting operation should be reduced. Can do.
[0049]
Further, the configuration of FIG. 3 is not limited to the purpose of causing a plurality of light emitters to emit light with different brightnesses. For example, while driving a predetermined number of light emitters at the same level voltage, the drive voltage is increased stepwise. It can also be applied to control that brightens the illumination.
[0050]
【The invention's effect】
  According to the present invention, the matrix connectionIt is possible to reduce the burden on the control unit required for the control of lighting operations of a plurality of light emitting elements and the control of changing the brightness of the light emitter, and to perform these controls at high speed.Further, even if the number of light-emitting elements and light-emitting bodies to be controlled increases, it can be sufficiently coped with by the control unit having the same performance as the conventional one.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a lighting control device in a gaming machine to which the present invention is applied.
FIG. 2 is a circuit diagram showing a specific configuration of the illumination control device of FIG. 1;
FIG. 3 is a circuit diagram showing a configuration of an illumination control apparatus according to a second embodiment.
[Explanation of symbols]
1 CPU
Divide-by-2 circuit
3 Shift register
4 Common drive circuit
5 Data output port
6 segment drive circuit
7 LED
11 Regulator
C0, C1, C2, C3 Common signal line
S0, S1, S2 Segment signal line
R1, R2, R3 resistance
TR1, TR2 transistors

Claims (4)

In a gaming machine having a plurality of light emitting elements connected in a matrix,
A control unit which is individually connected to each segment signal line in the connection circuit of the light emitting element and outputs a lighting control signal for each segment signal line in parallel, and each common signal line in the connection circuit is individually used as a drive power source. A plurality of switch units connected to each other, a shift register for controlling opening and closing of each switch unit, and a drive clock for operating the shift register by inputting and dividing the internal clock signal of the control unit A frequency dividing circuit for generating and outputting,
The shift register includes more output terminals than the number of the switch units, an input terminal for inputting the drive clock, and a clear terminal, and the same number of output terminals as the switch units are provided on a one-to-one basis for each switch unit. The output terminal connected to the switch unit and the output path of the reset signal from the outside are connected to the clear terminal.
The drive clock output path from the frequency divider circuit is divided into two, one connected to the input terminal of the shift register and the other to the input terminal of the control unit,
Each of the switch units closes in response to a drive pulse from a corresponding output terminal of the shift register,
The shift register switches the output terminal for outputting the drive pulse one by one in order from the higher one, and outputs the drive pulse from the switched output terminal each time the drive clock from the frequency divider circuit is input. Works to
The control unit recognizes a timing when switching of each switch unit is switched based on an input of a driving clock from the frequency divider circuit, and outputs an hourly lighting control signal in accordance with the recognized timing. A featured gaming machine. The shift register is provided with a second input terminal for inputting a signal for enabling or disabling the input of the drive clock,
The output line from the control unit includes a signal line connected to each segment signal line and a signal line connected to the second input terminal of the shift register,
The control unit sets a signal for the second input terminal of the shift register to a state in which the input of the driving clock is made valid while continuing to output the lighting control signal, and outputs the lighting control signal. In response to the stop or end, a signal for the second input terminal of the shift register is set to a state where the input of the drive clock is invalidated.
The gaming machine according to claim 1. In a gaming machine comprising a predetermined number of light emitters and a constant voltage circuit for generating a drive voltage for these light emitters,
A control unit that outputs a lighting control signal to the light emitter connected to the constant voltage circuit, a plurality of switch units that individually connect a plurality of resistance circuits having different resistance values to the constant voltage circuit as detection resistors, and A shift register for controlling opening and closing of each switch unit; and a frequency dividing circuit for generating and outputting a drive clock for operating the shift register by inputting and dividing the internal clock signal of the control unit; Comprising
The shift register includes more output terminals than the number of the switch units, an input terminal for inputting the drive clock, and a clear terminal, and the same number of output terminals as the switch units are provided on a one-to-one basis for each switch unit. The output terminal connected to the switch unit and the output path of the reset signal from the outside are connected to the clear terminal.
The drive clock output path from the frequency divider circuit is divided into two, one connected to the input terminal of the shift register and the other to the input terminal of the control unit,
Each of the switch units closes in response to a drive pulse from a corresponding output terminal of the shift register,
The shift register switches the output terminal for outputting the drive pulse one by one in order from the higher one, and outputs the drive pulse from the switched output terminal each time the drive clock from the frequency divider circuit is input. Works to
The control unit recognizes a timing when switching of each switch unit is switched based on an input of a drive clock from the frequency divider circuit, and outputs a lighting control signal to a light emitter connected to the constant voltage circuit. Output according to the recognized timing,
A gaming machine characterized by that . The shift register is provided with a second input terminal for inputting a signal for enabling or disabling the input of the drive clock,
The output line from the control unit includes a signal line connected to each segment signal line and a signal line connected to the second input terminal of the shift register,
The control unit sets a signal for the second input terminal of the shift register to a state in which the input of the driving clock is made valid while continuing to output the lighting control signal, and outputs the lighting control signal. In response to the stop or end, a signal for the second input terminal of the shift register is set to a state where the input of the drive clock is invalidated.
A gaming machine according to claim 3.

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