JP4316158B2 - Formal verification method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a formal verification method for verifying the function of a logic circuit.
[0002]
[Prior art]
Semiconductor integrated circuits such as system LSIs have high functionality and a large logical scale. Accordingly, logic verification of semiconductor integrated circuits tends to become longer and longer in both verification scale and verification time.
Recently, formal verification has attracted attention as one of logic verification techniques. Formal verification, for example, converts a logic circuit modeled by RTL description into a finite element machine and mathematically proves that the specification to be verified is satisfied. Formal verification is superior in terms of completeness compared to conventional simulation methods that consider only input patterns. Therefore, it is possible to detect errors that are difficult to find in simulation.
[0003]
[Problems to be solved by the invention]
However, formal verification is computationally intensive compared to logic simulation. For this reason, if a circuit model with a large number of states is handled, the memory capacity of the workstation that executes the verification program may be insufficient, and verification may become impossible. When verification becomes impossible due to memory shortage, the verification program is forcibly terminated, and there is a problem that no verification result remains. That is, when the verification program is forcibly terminated, there is a problem that it is impossible to confirm how far the verification program has been verified. Formal verification can take up to a week to complete. For this reason, the time loss and the cost loss upon forced termination are very large.
[0004]
The scale of a circuit model that can be handled by formal verification largely depends on the number of flip-flops included in the model. Theoretically, the number of states in the circuit model is twice the increment of the flip-flop, and the memory capacity required for verification is also doubled accordingly. On the other hand, since formal verification is characterized by the completeness of input patterns as described above, it is difficult to correctly estimate the memory capacity and verification time required for verification. For this reason, the formal verification is not always correctly performed only by adding the memory of the workstation.
[0005]
As described above, formal verification is very useful for verification of logic circuits, but no consideration is given to forced termination due to a relatively short memory shortage.
An object of the present invention is to improve the verification efficiency by leaving the verification result so far when the formal verification is forcibly terminated.
[0006]
[Means for Solving the Problems]
In the formal verification method of the present invention , the order of the degree of influence on the operation of the logic circuit when these input signals change is given to the input signals input to the logic circuit to be verified. Then, verification is executed by giving free patterns, which are all possible input patterns, in order from the input signal having the highest influence level. That is, the input pattern is sequentially generated according to a preset condition (influence degree). Therefore, even when formal verification is forcibly terminated midway due to a memory shortage of the verification device, it is possible to leave a verification result up to the middle based on the above-described influence degree. As a result, the cause of forced termination can be easily analyzed, and verification efficiency can be improved. Since the input pattern that has been verified and the input pattern that could not be verified become clear, the time required to complete all verifications and the memory capacity of the verification device required for verification can be estimated.
[0007]
In the formal verification method of the present invention , verification is performed by giving a free pattern to each of the input signals, and then performing verification by giving a free pattern in order from a plurality of input signals having a high influence. In this way, by gradually giving complex input patterns, for example, when the memory capacity of the verification device is the same, it is possible to verify more combinations of input patterns. As a result, more types of verification histories can be left.
[0008]
In the formal verification method of the present invention , verification is executed by giving either “0 fixed” or “1 fixed” to an input signal to which no free pattern is given. That is, “0 fixed” or “1 fixed” is preferentially given to an input signal having a low influence on the logic circuit operation. Since the relationship between the preset condition (influence degree) and the generated input pattern becomes easy to understand, the cause of the forced termination can be easily analyzed, and the verification efficiency can be improved.
[0009]
In the formal verification method of the present invention , an input pattern is described by a regular expression for an input signal whose input pattern is determined in the verification of the logic circuit. For this reason, the number of signals to be ranked can be reduced, and the verification time can be shortened. Moreover, an input pattern can be easily generated.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 5 show a first embodiment of the formal verification method of the present invention .
FIG. 1 shows an example of a logic circuit (verification target) that performs formal verification. This logic circuit is formed in a semiconductor integrated circuit such as a system LSI, for example. The specification of the logic circuit is determined so that the output signals OUT-1 and OUT-2 do not simultaneously become "1" when the input signals IN-A, IN-B, and IN-C are given. For this reason, the formal verification proves mathematically that the output signals OUT-1 and OUT-2 are not simultaneously "1". Formal verification is performed, for example, by a workstation verification program.
[0011]
FIG. 2 shows a signal name list corresponding to the input signals IN-A, IN-B, and IN-C. The signal name list ranks the degree of influence of the input signals IN-A, IN-B, and IN-C on the operation of the logic circuit when these input signals change. The signal name list is created by a designer or verifier who is familiar with the logic circuit to be verified.
[0012]
For example, an input signal whose logic value may be fixed, such as an operation mode signal for setting the operation mode (normal operation mode, standby mode, test mode, etc.) of the system LSI, is lowered in rank. A signal whose significance of verification becomes low when the input level is fixed is given higher rank. An example of a signal for increasing the priority is an interrupt signal. However, when the operation mode switching operation is intended for verification, the order of the operation mode signals becomes higher.
[0013]
Signals that do not make sense when verified are excluded from the signal name list. For example, when verifying only the normal operation mode, the reset signal is excluded from the signal name list. Similarly, when verifying the normal operation by disabling the input of the interrupt signal, the interrupt signal is excluded from the signal name list.
[0014]
As described above, in the operation of the logic circuit, in the operation of interest (the operation to be verified), an input signal whose logic level changes frequently or an input signal whose logic level changes irregularly has a higher rank. On the other hand, in an operation of interest (operation to be verified), an input signal whose logic level does not change much or an input signal that does not significantly influence the operation of the logic circuit is lowered in rank.
[0015]
The created signal name list is input to a workstation that performs verification. The verification program executed by the workstation sequentially generates input patterns while referring to the order of the signal name list, and executes verification.
FIG. 3 shows an example of combinations of input patterns generated by the verification program. The verification program first gives "0 fixed (0 display in the figure)" and "1 fixed (1 display in the figure)" ((combinations (1)-(8 )).
[0016]
Next, the verification program gives “free pattern (?? display in the figure)” in order from the input signal having the highest degree of influence, and gives “0 fixed” and “1 fixed” to the remaining input signals (( Combinations (9) to (12), (13) to (16), and (17) to (20)) Here, “free patterns” are all patterns that can be input comprehensively.
[0017]
Next, the verification program gives “free pattern” in order from the two input signals having the highest degree of influence, and gives “fixed 0” and “fixed 1” to the remaining input signals ((combinations (21) to 21)). (22), (23) to (24), (25) to (26)) In this way, the verification program gives a “free pattern” according to the condition (influence) set in the signal name list in advance. The input program is generated while gradually increasing the number of input signals, and the verification program gives “free patterns” to all the input signals (combination (27)).
[0018]
The combination of input patterns is 3 to the nth power, where n is the number of input signals to be verified. In this example, since the number of input signals is “3”, there are 27 combinations (1) to (27). In addition, combination (1)-(8), combination (9)-(12), combination (13)-(16), combination (17)-(20), combination (21)-(22), combination (23 ) To (24) and the seven groups consisting of the combinations (25) to (26), the order of the combinations in each group need not be limited to FIG. For example, verification may be performed in the order of (16) to (13) in the group of combinations (13) to (16).
[0019]
The combination (27) that gives free patterns to all input signals corresponds to the input pattern used in the conventional formal verification. As described above, according to the present invention, the logic verification, which has been conventionally performed in a batch, is executed by being divided into a plurality of combinations of input patterns according to the degree of influence of the input signal on the circuit. For this reason, the verifier / designer can confirm to which combination the verification is completed even when the verification program is forcibly terminated due to the memory shortage of the workstation.
[0020]
FIG. 4 shows a verification flow executed by the workstation (verification program). The verification is executed in the order of combinations (1) to (27) shown in FIG. 3 until a memory shortage occurs.
First, in step S1, “0 fixed” or “1 fixed” is sequentially given to all the input signals IN-A, IN-B, and IN-C, and verification is performed. Step S1 corresponds to the combinations (1) to (8) shown in FIG.
[0021]
Next, in step S2, “free pattern” is given to one input signal in descending order of influence, “0 fixed” or “1 fixed” is given to the remaining input signals, and verification is performed. Step S2 corresponds to the combinations (9) to (20) shown in FIG.
Next, in step S3, “free pattern” is given to the two input signals in descending order of influence, “0 fixed” or “1 fixed” is given to the remaining input signals, and verification is performed. Step S3 corresponds to the combinations (21) to (26) shown in FIG. In this way, by gradually giving complex input patterns, it is possible to verify more combinations of input patterns.
[0022]
Finally, in step S4, “free pattern” is given to all the input signals IN-A, IN-B, and IN-C, and verification is performed. Step S4 corresponds to the combination (27) shown in FIG.
When the number of input signals is greater than “3”, “free pattern” is sequentially given to a plurality of highly influenced input signals after step S3, and “0 fixed” or “1 fixed” is applied to the remaining input signals. "Is given and verification is performed.
[0023]
FIG. 5 shows a part of the waveforms of the input signals IN-A, IN-B, and IN-C generated in the workstation at the time of verification and the verification results. In this example, the memory capacity of the workstation becomes insufficient during the verification of the combination (25), and the subsequent verification cannot be executed. However, since combinations of input patterns are determined based on a signal name list created in advance by a designer or the like, it can be seen that the verification of the combinations (1) to (24) has been completed without any problems at this point. Since the input patterns (1) to (24) for which the verification has been completed and the input patterns (25) to (27) that have not been verified become clear, it is necessary to complete the verification and the time required for the verification. The memory capacity can be easily estimated.
[0024]
FIG. 6 shows an example of the verification result output from the workstation after the verification is interrupted due to insufficient memory capacity. “OK” in the verification result column indicates that the verification has been completed without any problem. “NG” in the verification result column represents that the verification is interrupted due to a shortage of memory during verification with this input pattern (combination (25)). “-” In the verification result column indicates that verification with this pattern (combination (26), (27)) could not be executed.
[0025]
When the formal verification is forcibly terminated in the middle, the designers, based on the execution results of the formal verification shown in FIG. Consider whether it can be verified by simulation. In addition, the capacity of the insufficient memory is predicted from the combination that has been verified, and expansion of the memory is considered as necessary.
[0026]
As described above, in the present embodiment, the input pattern is sequentially generated according to the preset condition (influence degree). Therefore, even when formal verification is forcibly terminated due to a lack of memory in the workstation, the influence degree is also increased. Based on the above, it is possible to leave the verification result up to the middle. That is, it is possible to leave as a history what combination of input signals has been verified. As a result, when the verification result is “NG”, the cause can be easily analyzed, and the verification efficiency can be improved.
[0027]
Since input patterns that have been verified (for example, combinations (1) to (24)) and input patterns that could not be verified (for example, combinations (25) to (27)) are clear, all verifications are completed. It is possible to estimate the memory time required for verification and the time until
After performing verification by giving a free pattern to each of the input signals IN-A, IN-B, and IN-C, verification was performed by giving free patterns in order from a plurality of input signals having high influence. In this way, by gradually giving complex input patterns, it is possible to verify more combinations of input patterns when the memory capacity of the workstation is the same. As a result, more types of verification histories can be left.
[0028]
Verification was performed by preferentially giving either “0 fixed” or “1 fixed” to an input signal to which a free pattern is not given, that is, an input signal having a low influence on the logic circuit operation. Since the relationship between the preset condition (influence degree) and the generated input pattern becomes easy to understand, the cause of the forced termination can be easily analyzed, and the verification efficiency can be improved.
[0029]
7 and 8 show a second embodiment of the formal verification method of the present invention . The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. A logic circuit (verification target) for performing formal verification is formed in a semiconductor integrated circuit such as a system LSI, for example.
[0030]
FIG. 7 shows a signal name list of input signals IN-A, IN-B, IN-C, RESET, and CLK2 input to the logic circuit. That is, in this embodiment, the reset signal RESET and the clock signal CLK2 are added to the signal name list of the first embodiment. The reset signal RESET and the clock signal CLK2 are signals whose input patterns are determined in the verification of the logic circuit of this embodiment. That is, the reset signal RESET and the clock signal CLK2 must always have waveforms with predetermined timings in order to operate the logic circuit normally. In the signal name list, the input signals IN-A, IN-B, and IN-C are ranked in the degree of influence on the operation of the logic circuit when the input signal changes, as in the first embodiment. Is.
[0031]
As for the reset signal RESET and the clock signal CLK2, the input pattern of these signals is described by regular expressions. The symbol “[]” represents a logic level in one cycle. The symbol “{}” represents the number of repetitions. The symbol “*” represents that the immediately preceding description continues indefinitely.
[0032]
In this way, in the verification of the logic circuit, for a signal whose input pattern is always determined, the input pattern is described by a regular expression. In other words, the number of signals to be ranked can be reduced and the verification time can be shortened by describing in regular expressions the signals that have no meaning of verification unless they change to a certain logic level. The signal name list is created by a designer or verifier who is familiar with the logic circuit to be verified, as in the first embodiment.
[0033]
FIG. 8 shows an actual input pattern of the reset signal RESET and the clock signal CLK2 which are regularly expressed in the signal name list of FIG. The input pattern of the reset signal RESET and the clock signal CLK2 may be such that the designer or the like inputs the waveform shown in FIG. 8 into the workstation, and the workstation program may convert these waveforms into regular expressions. May be input to the workstation as an input pattern described by a regular expression. That is, for a signal whose input pattern is always determined, the input pattern is easily generated.
[0034]
Also in this embodiment, the same effect as that of the first embodiment described above can be obtained. Further, in this embodiment, since the input pattern is described with a regular expression for a signal whose input pattern is always determined, the number of signals to be ranked can be reduced, and the verification time can be shortened. Moreover, an input pattern can be easily generated.
[0035]
In the above-described embodiment, the example in which the verification program is executed on the workstation has been described. The present invention is not limited to such an embodiment. For example, the verification program may be executed on a personal computer.
As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.
[0036]
【The invention's effect】
In the formal verification method of the present invention , even if the formal verification is forcibly terminated due to a memory shortage of the verification device or the like, it is possible to leave a verification result up to the middle based on the degree of influence. As a result, the cause of forced termination can be easily analyzed, and verification efficiency can be improved. The time required to complete all verifications and the memory capacity of the verification device required for verification can be estimated.
In the formal verification method of the present invention , it is possible to verify more combinations of input patterns, and it is possible to leave more types of verification histories.
[0037]
In the formal verification method of the present invention , since the relationship between preset conditions (influence levels) and generated input patterns is easy to understand, the cause of forced termination can be easily analyzed, and verification efficiency can be improved.
In the formal verification method of the present invention , the number of signals to be ranked can be reduced, and the verification time can be shortened. Moreover, an input pattern can be easily generated.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an example of a logic circuit that performs formal verification in a first embodiment.
FIG. 2 is a signal name list of input signals indicating the ranking of the degree of influence on the operation of the logic circuit in the first embodiment.
FIG. 3 is an explanatory diagram illustrating an example of combinations of input patterns generated by a verification program according to the first embodiment.
FIG. 4 is a flowchart illustrating a verification procedure executed by a verification program according to the first embodiment.
FIG. 5 is an explanatory diagram showing a part of a waveform of an input signal generated in the workstation and a verification result in the first embodiment.
FIG. 6 is an explanatory diagram illustrating an example of a verification result output from the workstation according to the first embodiment.
FIG. 7 is a signal name list of input signals indicating the ranking of the degree of influence on the operation of the logic circuit in the second embodiment.
8 is a waveform diagram showing actual input patterns of the reset signal and clock signal of FIG. 7. FIG.
[Explanation of symbols]
CLK2 clock signal
IN-A, IN-B, IN-C input signal
OUT-1, OUT-2 output signal
RESET Reset signal

Claims (5)

A plurality of input signals input to the logic circuit to be verified are ranked in advance, and the order is an input signal whose logic level changes frequently during operation of the logic circuit or an input whose logic level changes irregularly. Using a signal name list that is higher for signals, the computer sequentially gives all input patterns that can be input to each input terminal in the descending order, and performs verification using each input pattern;
And a computer outputting a verification result obtained by the verification ,
A formal verification method characterized in that, for the input signal whose input pattern is determined in the verification of the logic circuit, a computer converts the input pattern input to a regular expression . The formal verification method according to claim 1, wherein:
The computer performs verification by giving an input pattern of “0 fixed” or “1 fixed” to an input signal other than the input signal to which all input patterns that can be input are given. Formal verification method to do. The formal verification method according to claim 1, wherein:
After the computer performs verification by giving all input patterns that can be input to each of the input signals,
A formal verification method, wherein a computer executes verification by giving all the input patterns that can be input in order from the combination having the highest order among a plurality of combinations of the input signals. The formal verification method according to claim 3,
The computer performs verification by giving an input pattern of “0 fixed” or “1 fixed” to an input signal other than the input signal to which all input patterns that can be input are given. Formal verification method to do. The formal verification method according to claim 1, wherein:
A formal verification method characterized in that when a computer becomes unable to perform verification due to a memory shortage, an input pattern that has been verified is distinguished from an input pattern that has not been verified and is output.

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