JP4315104B2 - Signal processing circuit and optical disc recording / reproducing apparatus - Google Patents

Description

  The present invention relates to a gain control amplifier (GCA), a single-to-differential conversion circuit, and an offset cancellation circuit, and particularly to a reproduction signal from a photodiode (PD) in processing of a reproduction signal from an optical disc recording medium. Gain control amplifier (GCA circuit), single-to-differential conversion circuit, and offset cancellation until sending to bit reproduction system, tracking error (TE) signal generation system, focus error (FE) signal reproduction system, wobble signal reproduction system, etc. The configuration of the circuit.

In optical discs ranging from compact discs (CDs) to DVDs and Blu-rays, the read-only type is physical uneven pits by laser cutting and stamping, and the write-once type melts and decomposes organic dyes with a recording laser, for example. The rewritable type has different recording principles, such as the generation of recording mark rows having different reflectivities by phase transition of the crystal structure of the recording film with pulsed light.
However, as a reproduction system of an optical disk, a disk medium is used in that a recorded data bit is reproduced by applying a light spot from a laser diode (LD) to the disk surface and detecting the intensity of the reflected light by a photodiode (PD). Regardless, the data bits are reproduced on the same principle.
Therefore, from the viewpoint of reducing the size and cost of the playback apparatus, it is desirable that the playback signal processing system is configured with a common circuit regardless of the type of media. At this time, the problem is that the reflected light intensity differs greatly between the read-only disc, the write once disc, and the rewritable disc.
That is, the photocurrent from the PD or the pick-up signal level obtained by current-voltage conversion (IV conversion) is strongly dependent on the difference in reflectivity of the disk media. For this reason, it is necessary for the GCA circuit to absorb a signal level difference of about 20 dB in the previous stage of the reproduction signal processing, together with compensation for fluctuations in the reproduction signal level due to aging of the laser light intensity. Otherwise, the entire processing circuit in the subsequent stage must have a wide dynamic range, which makes designing very difficult. In other words, it results in sacrificing other performance such as increased current consumption and bandwidth.

In addition, from the reproduction signal, not only the data bit string but also servo system signals such as tracking error (TE) information and focus error (FE) information, or in the additional recording and rewriting media, address information or a reference for writing clock generation It is necessary to extract the wobble signal. For this reason, PDs are usually composed of multi-division photodiodes, such as 4-division or 8-division photodiodes, instead of single photodiodes. By appropriately adding and subtracting signals from each photodiode, the TE information, FE information is obtained, and laser spot tracking servo and focus servo are applied based on this information.
For example, the optical pickup shown in FIG. 6 uses the DPP (Differential Push-Pull) method for tracking servo and the astigmatism (astigma) method for focus servo, and the signal level from each photodiode. This is a configuration method conventionally used for obtaining TE information, FE information, and the like by using. Here, although there are some variations in the number of divisions of PD, each is composed of multi-division PDs and signal paths, which are disclosed in, for example, Japanese Patent Laid-Open Nos. 2003-257034 and 2004-192729. ing.

In FIG. 6, the optical pickup is composed of an 8-division photodiode (PD) and an RF circuit composed of an addition / subtraction circuit using, for example, an operational amplifier, a tracking error (TE) circuit, and a focus error (FE) circuit. Has been.
As for the RF signal, the optical signals detected by the photodiodes A, B, C, and D are added by C + D by the operational amplifier 201, A + B is added by the operational amplifier 206, and these outputs are added by the operational amplifier 212 to obtain an RF signal of A + B + C + D. It is done.
In the focus error (FE), the operational amplifier 204 obtains an A + C addition signal, and the operational amplifier 205 obtains a B + D addition signal. Then, the operational amplifier 210 calculates the difference between the output signal of the operational amplifier 204 and the output signal of the operational amplifier 205 to obtain a focus error signal of (A + C) − (B + D).
Regarding the tracking error (TE), the optical signal detected by the photodetectors E and F is obtained by the operational amplifier 202 as a difference signal (E−F), and the optical signal detected by the photodetectors G and H is obtained by the operational amplifier 203 as a difference signal (G After obtaining -F), the operational amplifier 207 adds both signals to obtain a signal of (E−F + G−H).
On the other hand, the operational amplifier 208 obtains a difference signal (A + B) − (C + D) between the output signal A + B from the operational amplifier 206 and the output signal C + D from the operational amplifier 210. When the difference between the output signal from the operational amplifier 207 and the output signal from the operational amplifier 208 is obtained by the operational amplifier 211, a tracking error signal of (A + B) − (C + D) − (EF−G−H) is obtained.

FIG. 7 shows a block diagram of a front end signal processing circuit 250 of a general optical disk reproducing apparatus. The output of the photodetector 251 is connected to an IV (current-voltage) conversion circuit 255, and the photodetection signal of the photodetector A (E) is output to the GCA 259 as a voltage. Similarly, the photodetectors 252, 253, and 254 convert the light detection signals (currents) into voltages by the IV conversion circuits 256, 257, and 258, and output the output signals of B (F), C (G), and D (H). It supplies to GCA260,261,262, respectively.
Output signals output from the photodetectors output from the GCA 259, 260, 261, and 262 are added and subtracted by the arithmetic circuit 263, and the above-described RF signal, tracking signal, and focus signal are output.
Since the output method of the arithmetic circuit 263 is a single-ended output, it is connected to the single-differential conversion circuit 254 in the next stage and converted to a differential output. A VGA 255 is connected to the output of the single-to-differential conversion circuit 254, and the gain is adjusted by the amplitude detection signal to make the output level constant. Since the VGA 255 has an offset, the VGA 255 is connected to a next-stage circuit 258 such as a filter through a coupling capacitor constituting an offset cancel circuit / high-pass (HP) circuit 256.

  In this way, FIG. 7 shows an example in which the light reception level signals from four systems of PDs are handled. First, since the output from the PD is a single-ended signal, it is converted into a differential signal to match the circuit configuration of the subsequent stage. There is a need to. The necessity of making the differential is well known, such as improvement of S / N, improvement of external noise resistance of power supply, substrate and the like.

  Next, VGA (Variable Gain Amplifiers) 255 for configuring an automatic gain adjustment circuit AGC (Automatic Gain Control) is placed. While the GCA (259, 260, 261, 262) adjusts the level difference mainly caused by the media in stages, the AGC loop detects the signal amplitude in the subsequent circuit during playback signal processing, Feedback is applied to the VGA 255 to make the desired amplitude. As a result, the signal level during reproduction is always kept constant at the signal amplitude detection point. This AGC loop is set to an optimal loop constant so that the gain setting by the VGA 255 does not change unnecessarily sensitively when the signal level fluctuates greatly due to scratches, dust, etc. on the disk surface. It also contributes to improving total playability.

In addition to these, the front end signal processing circuit 250 further includes an offset cancel circuit. This is to remove the DC offset amplified by the gain stage and to relax the necessary dynamic range in the subsequent circuit. Therefore, as schematically shown in FIG. The DC offset at the output unit is compressed by negatively feeding back the DC component of the unit to the input stage of the gain stage (resulting in a high-pass circuit).
JP 2003-257034 A JP 2004-192729 A

As described above, the front-end signal processing circuit that handles the photoelectric conversion signal from the PD includes five components, that is, the GCA for the number of PD divisions, the addition circuit, the single-differential conversion circuit, the VGA, and the offset cancellation circuit. Circuit blocks are necessary, and these are necessary for each application such as a tracking servo system, a focus servo system, and an RF signal system.
Therefore, the conventional method for simply cascade-connecting these configurations increases the total circuit scale or power consumption, and a circuit configuration method that can realize the above five functions in a compact manner is desired. .

  The signal processing circuit of the present invention includes one or more single-ended signal input terminals, a plurality of input resistors in which one end of the single-ended signal input terminal is connected to one end of a resistor, and the other ends of the plurality of input resistors. A first feedback resistor having one end connected to a commonly connected node, a common connection node of the plurality of input resistors, and the other end of the first feedback resistor are connected to a low impedance input terminal and a high impedance output terminal, respectively. A connection node of the current follower, the first feedback resistor and the high impedance output terminal of the current follower is connected to one input terminal, and the plurality of input resistors, the first feedback resistor, and the low impedance input of the current follower A single-to-differential converter circuit in which a terminal connection node is connected to the other input terminal and an output of the single-to-differential converter circuit are connected A variable offset amplifier connected between the output of the variable gain amplifier and the single-to-differential converter circuit to detect a differential offset, and a differential offset canceling current is detected according to the detected differential offset. And a differential node configured to flow between a connection node of one feedback resistor and a high impedance output terminal of the current follower, and a connection node of the plurality of input resistors, the first feedback resistor and a low impedance input terminal of the current follower. And an operational transconductance amplifier.

  The optical disk recording / reproducing apparatus of the present invention detects the amount of light reflected from a disk by a plurality of photo detectors of an optical pickup, converts the detected photocurrent signal into a voltage, and then converts the detected light into a voltage in a signal processing circuit. The signal is calculated, the converted signal is converted into a differential signal, amplified, and output with a constant amplitude level, and the signal recorded on the disk is reproduced using the signal output from the signal processing circuit. An optical disk recording / reproducing apparatus, wherein the signal processing circuit includes one or more single-ended signal input terminals, a plurality of input resistors connected to one end of the single-ended signal input terminals, and the plurality of input resistors. A feedback resistor having one end connected to a node commonly connected to the other end, a common connection node of the plurality of input resistors, and the other end of the feedback resistor each having a low impedance A current follower connected to the input terminal and the high impedance output terminal, and a connection node between the feedback resistor and the high impedance output terminal of the current follower are connected to one input terminal, and the plurality of input resistors, feedback resistors and current A single-to-differential conversion circuit in which a connection node of a low-impedance input terminal of the follower is connected to the other input terminal, a variable gain amplifier to which an output of the single-to-differential conversion circuit is connected, and an output of the variable gain amplifier Is connected between the single-differential conversion circuit and a differential offset is detected, and a differential offset canceling current is connected to the feedback resistor and a high impedance output terminal of the current follower according to the detected differential offset And a plurality of input resistors, feedback resistors and a low impedance of a current follower. And a differential Oh Bae relational transconductance amplifier to flow between a connection node of the input terminal.

  Five circuit functional blocks, which are indispensable for the playback system front-end signal processing of an optical disk recording / playback apparatus, are a gain control amplifier (GCA circuit), an adder circuit, a single-to-differential converter circuit, an automatic gain adjustment circuit (AGC), and an offset cancel circuit. Can be realized with an organic combination of general and general-purpose circuit components, has a high degree of design freedom for common-mode voltage, and the bias state does not change even during offset cancellation. can get.

FIG. 1 shows an embodiment of a signal processing circuit (front end signal processing circuit) 50 used in the optical disc recording / reproducing apparatus of the present invention.
Here, Ain to Din indicate received light (level) signals obtained by IV conversion of the photocurrent from the PD. Although an example of four inputs is shown here, it should be clearly not limited to this.
A circuit configuration of a signal processing circuit (front end signal processing circuit) 50 will be described with reference to FIG. A terminal to which a light reception signal Ain detected by the photodetector (PD) A is supplied is connected to one terminal of the capacitor C1, and the other terminal is connected to one terminal of the variable resistor R1. The other terminal of the variable resistor R1 is connected to one terminal of the variable resistor R5 and an input terminal having a low input impedance of the current follower (circuit).
In the example of FIG. 1, the resistance values of the input resistance group (plurality of input resistances) and the feedback resistance R5 composed of the variable resistances R1, R2, R3, and R4 are variable by switching means, and the input resistance group and the feedback resistance The current follower functions as an adder and a gain control amplifier.
Further, the terminal to which the light reception signal Bin of the photodetector (PD) B is supplied is connected to one terminal of the capacitor C2, and the other terminal is connected to one terminal of the variable resistor R2. The other terminal of the variable resistor R2 is connected to one terminal of the variable resistor R5 and the input terminal of the current follower.
A terminal to which the light reception signal Cin of the photodetector (PD) C is supplied is connected to one terminal of the capacitor C3, and the other terminal is connected to one terminal of the variable resistor R3. The other terminal of the variable resistor R3 is connected to one terminal of the variable resistor R5 and the input terminal of the current follower.
Further, the terminal to which the light receiving signal Din of the photodetector (PD) D is supplied is connected to one terminal of the capacitor C4, and the other terminal is connected to one terminal of the variable resistor R4. The other terminal of the variable resistor R4 is connected to one terminal of the variable resistor R5 and the input terminal of the current follower.
The input terminal of the current follower is also connected to one terminal of the (input) resistor R12, and the other terminal is connected to the inverting input terminal of the operational amplifier 31.

The other terminal of the variable resistor R5 is connected to the output terminal of the current follower and also connected to one terminal of the (input) resistor R10 of the operational amplifier 31 of the single-differential conversion circuit. The other terminal of the input resistor R10 is connected to the non-inverting input terminal of the operational amplifier 31.
The non-inverting output terminal of the operational amplifier 31 is connected to one terminal of the feedback resistor R11, and the other terminal of the feedback resistor R11 is connected to the inverting input terminal of the operational amplifier 31. The inverting output terminal of the operational amplifier 31 is connected to one terminal of the feedback resistor R13, and the other terminal of the feedback resistor R13 is connected to the non-inverting input terminal of the operational amplifier 31.

The non-inverting output and the inverting output of the operational amplifier 31 are connected to the VGA 41, and the output of the VGA 41 is connected to the input of the OTA 33. The VGA 41 is supplied with an amplitude detection signal control signal so that the level of the output signal is constant.
A capacitor 35 is connected between the two outputs (differential outputs) of the OTA 33 and functions as a band limiting filter. This output is connected to the next-stage (differential) transconductance 32 where it is converted into a current corresponding to the input voltage. One output terminal of the transconductance 32 is connected to one terminal of the input resistor R12, the input terminal of the current follower, and one terminal of the variable resistor R5.
The other output terminal of the transconductance 32 is connected to one terminal of the input resistor R10, the other terminal of the variable resistor R5, and the output terminal of the current follower.

Next, the operation of the signal processing circuit 50 will be described with reference to FIGS.
The input signal is input to a voltage amplifier composed of a current follower, its input, and a feedback resistor. As is well known, the gain of the voltage amplifier can be set by the ratio of the input resistance (R1, R2, R3, R4) and the feedback resistance (R5). Therefore, by switching each resistance value with a MOS switch or the like, the GCA (gain (Control amplifier) 20 can be configured, and at the same time, the input voltage (signal) of Ain to Din is added as an inflow current to the low impedance input node (node) of the current follower, so that the GCA (circuit) 20 functions as an adder circuit. Have both. The signal after gain control and addition by the GCA 20 is input to a subsequent single-differential conversion circuit.

After the light-receiving current output from each photodetector (PD) is IV-converted, the current converted by the capacitors C1 to C4 and the variable resistors R1 to R4 is added to the input and output terminals of the current follower. Are respectively supplied as the same amount of input current Iin, so that a voltage of R15 * Iin is generated between both terminals of the variable resistor R5 as a feedback resistor, and the voltage generated in the variable resistor R15 is used as a differential voltage. It is input to the input resistors (R10, R12) of the operational amplifier 31 of the single-differential conversion circuit constituting the differential circuit. That is, the single-ended signal is converted into a differential signal using the feedback resistor R15 and the current Iin flowing through the input / output terminals of the current follower.
The differential output signal amplified by the single-to-differential conversion circuit is subjected to AGC control by the subsequent VGA 41 to become a differential signal having a constant amplitude, and further transferred to a post-processing signal processing circuit.

In the present invention, the configuration of the single-differential conversion circuit is specifically realized by a differential resistance feedback amplifier (operational amplifier 31, R10, R11, R12, R13) having a simple differential configuration.
As described above, the output terminal of the single-ended GCA 20 is connected to one input terminal of the differential resistance feedback amplifier constituting the single-to-differential conversion circuit, and the other input terminal of the differential resistance feedback amplifier is connected to the GCA 20. Connected to the low-impedance input terminal of the current follower.
By adopting this configuration, the input common-mode voltage of the differential resistance feedback amplifier is determined by the input DC of the current follower, and the output common-mode voltage has a degree of freedom by a common-mode feedback circuit provided at the output stage of the operational amplifier. You can set it.
That is, the DC current resulting from the input / output common mode voltage difference of the differential resistance feedback amplifier flows as a DC current component to the input / output terminal of the current follower via the feedback resistance and the input resistance.

Since the (differential) input resistors (R10, R12) and (differential) feedback (feedback) resistors (R11, R13) of the differential resistance feedback amplifier can be set as large as several tens of KΩ, the DC current due to the input / output common mode potential difference The difference between the input DC that is optimal for the current follower (circuit) to be used and the common mode potential that is optimal for the output of the operational amplifier 31 or the input of the VGA 41 in the next stage is small, with little increase in power consumption. It can be absorbed by a resistance feedback amplifier.
At this time, as shown in FIG. 2, the common mode current a (Icm / 2) output from one output terminal of the operational amplifier 31 is passed through the (differential) feedback resistor R11 and the (differential) input resistor R12. It flows to the input terminal of the current follower. The common mode current b (Icm / 2) output from the other output terminal of the operational amplifier 31 flows to the output terminal of the current follower via the (differential) feedback resistor R13 and the (differential) input resistor R10.

  In this way, the common mode current (Icm) flows equally into the input / output terminals of the current follower and does not flow into the feedback resistor R5 of the GCA 20 (see FIG. 2). For this reason, problems such as induction of secondary offset due to the common mode current do not occur, and the steady current caused by such a common mode potential difference can be accurately estimated at the time of circuit design. It is only necessary to design the DC bias in the follower (circuit), and it is possible to design a circuit that allows easy estimation of design margin and the like.

  In addition, as described above, the single-to-differential converter circuit is realized by a differential resistance feedback amplifier having a simple differential configuration. Therefore, a specific circuit such as an operational amplifier used here is a general differential operational amplifier. The design risk can be minimized because the circuit configuration of the existing library that can be used and is reliable in the design environment can be used as it is.

Next, the signal flow and operation after the single-to-differential conversion circuit will be described.
The output signal differentiated by the single-to-differential conversion circuit is input to the VGA 41 having a differential configuration. The VGA 41 constitutes an AGC loop together with an amplitude detection circuit at the subsequent stage. Although offset cancellation is required at the output stage of the VGA 41, in the present invention, first, a differential DC offset at the output of the VGA 41 is detected and amplified by an OTA (Operational Transconductance Amplifier) 33, and after the OTA 33. The offset differential current is converted by the connected differential transconductance 32.
Here, the OTA 33 and the subsequent differential transconductance 32 may be of a general differential configuration. Here, as a feature of the present invention, as described above, one output terminal of the differential transconductance 32 is an input terminal of the current follower, and the other output terminal of the differential transconductance 32 is an output of the current follower. Each terminal is connected. By adopting this configuration, the differential output current of the differential transconductance 32 works to cancel the offset at the VGA 41 output terminal.
At this time, all of the offset cancellation current d (Ios) output from the differential transconductance 32 flows to the feedback resistor R5 of the GCA 20 and does not flow into the current follower (circuit) (see FIG. 3).
For this reason, the DC bias of the current follower does not fluctuate due to the offset cancellation current, and it becomes possible to design a circuit that can easily estimate the design margin and the like.
Further, since the differential transconductance 32 is connected to the low impedance node of the current follower directly or via the feedback resistor R5, its output common mode potential is determined automatically, and a common mode feedback circuit or the like is added to the output section. There is no need to do. This suppresses the number of parasitic elements added to the original signal path, and offset cancellation can be realized without impairing the signal band.

  Since the offset cancellation loop is essentially a high-pass filter, it is desirable to reduce the bandwidth of the feedback loop as much as possible so as not to impair the main line signal bandwidth. In this method, since the output impedance of the OTA 33 can be easily increased, a very narrow band feedback loop can be realized even in combination with a relatively small band limiting capacity.

  FIG. 4 shows a circuit diagram of a signal processing circuit (front-end signal processing circuit) 100 according to an embodiment of the present invention including an example of a current follower (circuit). The configuration of the signal processing circuit 100 in FIG. 4 will be described. Since the block configuration of FIG. 1 is the same except for the current follower constituting the GCA 20, its detailed description is omitted. Note that the numbers of the same circuit blocks and circuit elements are the same as those in FIG.

  Photocurrents are detected by the photodiodes A, B, C, and D, and light-receiving level signals Ain, Bin, Cin, and Din that have undergone IV conversion are generated. An input terminal to which the light receiving level signal is supplied is connected to variable resistors R1, R2, R3, and R4 via capacitors C1, C2, C3, and C4, and output terminals of these variable resistors R1, R2, R3, and R4 are common. Connected to the variable resistor R5, one terminal of the input resistor R12 of the operational amplifier 31, and further to the drain of the PMOS transistor M1 (or the source of the NMOS transistor M2) which is the input terminal of the current follower. The output terminal of the variable resistor R5 is connected to one terminal of the input resistor R10 of the operational amplifier 31 and the output terminal of the drain of the PMOS transistor M3 constituting the current follower.

In the current follower, one terminal of the constant current source I14 is connected to the power supply Vcc, and the other terminal is connected to the drain of the NMOS transistor M2. The bias potential _{V B} is connected to the gate of the NMOS transistors M2, and the source is connected to the ground via a constant current source I11 and I12.
The source of the PMOS transistor M1 is connected to the power supply Vcc, the gate is connected to the drain of the NMOS transistor M2, the drain is the source of the NMOS transistor M2, the input terminal of the variable resistor R5 and the constant current sources I11 and I12. It is connected to the.
The source of the PMOS transistor M3 is connected to the power supply Vcc, the gate is connected to the gate of the NMOS transistor M1, the drain is an output terminal, the output side terminal of the variable resistor R5, the output terminal of the transconductance 32, and the constant current source I13. It is connected to the.

Thereafter, as described with reference to FIG. 1, the signal differentiated by the single-to-differential conversion circuit is input to the differential VGA 41, and this VGA 41 constitutes an AGC loop together with the subsequent amplitude detection circuit. Although offset cancellation is required at the output stage of the VGA 41, in the present invention, the differential DC offset at the output of the VGA 41 is first detected and amplified by the OTA 33, and converted to an offset compensation current by the differential transconductance 32 subsequent to the OTA 33. To do.
One output terminal of the differential transconductance 32 is connected to the input terminal of the current follower, and the other output terminal of the differential transconductance 32 is connected to the output terminal of the current follower. By adopting this configuration, as described above, the differential output current of the differential transconductance 32 works in a direction to cancel the offset at the VGA 41 output terminal.

Next, the operation of the signal processing circuit (front end signal processing circuit) 100 shown in FIG. 4 will be described. However, the overall operation is the same as that described with reference to FIG. 1, and detailed description thereof will be omitted. Here, the operation of the current follower that mainly constitutes a part of the GCA 20 will be described.
In FIG. 4, the currents output from the variable resistors R1, R2, R3, and R4 are added and supplied to the drain of the PMOS transistor M1 that is the input terminal and the common connection terminal of the constant current sources I11 and I12. Since the currents of the constant current sources I11 and I12 are constant, when the input current Iin is input, the current flowing through the source of the NMOS transistor M2 decreases, and the gate-source voltage Vgs decreases. As a result, since the drain current becomes small, the current flowing from the constant current source I14 is constant. Therefore, the difference between the current flowing from the constant current source I14 and the current flowing to the drain of the NMOS transistor M2 is different between the PMOS transistor M1 and the PMOS transistor M3. It flows (charges) at each gate.

  Then, the gate potentials of the PMOS transistor M1 and the PMOS transistor M3 rise, the Vgs of the PMOS transistor M1 (and M3) decreases, and the drain current of the PMOS transistor M1 (and M3) decreases. As a result, the currents flowing through the constant current sources I11 and I12 are compensated and become constant. That is, the current follower circuit compensates so that the current supplied to the current sources I11 and I12 is made constant by increasing / decreasing the current in the direction opposite to the increase (or decrease) of the input current Iin supplied to the input terminal. .

  On the other hand, since the PMOS transistor M1 and the PMOS transistor M3 have a current mirror configuration, the drain current flowing to the output of the PMOS transistor M1 and the drain current flowing to the PMOS transistor M3 are the same when both transistor sizes are the same. The same current as the (input) current Iin flowing in the terminal flows into the output terminal.

  The output signal of the GCA 20 is supplied to the non-inverting input terminal and the inverting input terminal of the operational amplifier 31 via (differential) input resistors R10 and R12 configured in a single-to-differential conversion circuit, respectively. A differential signal is output from. This output signal is negatively fed back to the input of the op-amp 31 using (differential) feedback resistors (R11, R13).

The differential output signal of the operational amplifier 31 is output to the VGA 41 in the subsequent stage, where gain control (AGC) is performed by the amplitude detection signal to make the amplitude of the output signal constant.
The output signal of the VGA 41 is fed back to the input of the single-to-differential conversion circuit via the OTA 33, the capacitor 35 constituting the filter, and the differential transconductance 32 so as to cancel the offset current related to the VGA 41.

  That is, in the current follower described above, the source of the common-gate NMOS transistor M2 serves as an input terminal, and the potential change at the input terminal is fed back in the direction canceled by the transconductances of M2 and M1, resulting in a low input impedance. The inflow current Iin to the input terminal is mirrored (arbitrarily multiplied) to the output terminal by M1 and M3 current mirrors.

Also in the signal processing circuit 50 of FIG. 4, as shown in FIG. 2, the common mode current at the output terminal of the single-to-differential conversion circuit is input to the current follower via the feedback resistors R11 and R13 and the input resistors R10 and R12. Since the same amount of current flows through the terminal and the output terminal, and no other flows at all, cancellation can be made by increasing I11 and I13 by the same amount. Therefore, the operation of the current follower is not affected by the above-described path through which the common mode current flows.
In this way, when the current setting obtained by matching I13 with the current obtained by adding I11 and I12 without compromising the circuit balance of the current follower and compensating for the change due to the common mode current, the common mode current and the offset current are applied to the circuit. The input and output voltages of the single-to-differential conversion circuit can be set to optimum voltages without adversely affecting them.
In FIG. 4, the voltage at the low impedance input terminal of the current follower is fixed. With this fixed voltage, the setting of the input common-mode voltage of the differential operational amplifier 31 constituting the single-to-differential conversion circuit is determined, and as described above, the output common-mode voltage of the single-to-differential conversion circuit is the input to the VGA 41. A value suitable for the voltage can be determined, and the degree of freedom in design can be increased.

  In FIG. 4, the current follower is configured by a MOS transistor, but a circuit configuration in which a PMOS transistor and an NMOS transistor are interchanged may of course be used.

FIG. 5 shows an equivalent input impedance circuit of the current follower (circuit) described above. Here, for example _{, go, M1} indicate the drain conductance of the MOS transistor M1, go _{, M1} indicate the transconductance of the MOS transistor M1, and go _{, I1} , go _{, I2} , go _{, I3} , go _{, I4} are The conductances of the current sources I11, I12, I13, and I14 are shown, respectively.
The impedance Zi when viewing the input terminal of the current follower circuit, that is, the drain of the PMOS transistor M1 and the source of the NMOS transistor M2, can be regarded as equivalent to a configuration in which three resistors RA, RB, RC are connected in parallel. Here, equations for RA, RB, and RC are shown in FIG.
As can be seen from FIG. 5, the input impedance Zi is mainly determined by the smallest resistance among the three resistances (RA, RB, RC). In the example shown in FIG. The input impedance of the current follower can be made as small as the drain conductance divided by the square of the transconductance. As a result, the input impedance Zi is several Ω.
Therefore, it can be seen that the input impedance Zi of the current follower is very low in the specific circuit configuration of FIG.

  The above signal processing circuit (front-end signal processing circuit) can be used for data reading of a CD, CD-R, CD-RW, DVD-R, DVD-RW, DVD-RAM device, etc. Increased high performance devices can be realized.

  As described above, the gain control amplifier (GCA), the addition circuit, the single-differential conversion circuit, the automatic gain adjustment circuit (AGC), which are indispensable for the optical signal processing (front-end signal processing) of the reproduction system of the optical disk recording / reproducing apparatus. ), 5 circuit functional blocks of the offset cancel circuit can be realized by organic combination of general and general circuit components, and the design freedom of common mode voltage is high, and the bias state does not change even during offset cancel. As a result, it is possible to realize a configuration in which a design margin can be easily taken.

It is a figure which shows the block configuration of the signal processing circuit used for the optical disk recording / reproducing apparatus of this invention. It is a circuit diagram for demonstrating operation | movement of the common mode electric current of the signal processing circuit shown in FIG. FIG. 2 is a circuit diagram for explaining an operation of an offset cancel current of the signal processing circuit shown in FIG. 1. It is the figure which showed the circuit structure of the current follower of the embodiment of the signal processing circuit shown in FIG. FIG. 5 is an equivalent circuit diagram illustrating input impedance of the current follower illustrated in FIG. 4. It is a circuit diagram which shows the circuit structure of the conventional optical pick-up. It is a circuit diagram which shows the structure of the front end signal processing circuit containing the conventional optical pick-up.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20,259-262 ... GCA (Gain Control Amplifier; Gain control amplifier), 30 ... Offset cancellation circuit, 31,201-212 ... Operational amplifier, 32 ... Differential transconductance, 33 ... OTA (Operational Transformance Amplifier), 35,256 , 257, C1 to C4, capacitors, 40, AGC (Automatic Gain Control) circuit, 41, 255, VGA (Variable Gain Amplifier), 50, 100, signal processing circuit (front-end signal processing circuit), 200, optical pickup circuit 251 to 254 ... photo detectors 255 to 258 ... IV (current-voltage) conversion circuit 263 ... addition / subtraction circuit 254 ... single Differential conversion circuit, 258... Next stage circuit, R1 to R5... Variable resistance, R10 to R13, RA, RB, RC, RD... Resistor, M1, M3 ... PMOS transistor, M2 ... NMOS transistor, I1, I11 to I14. Constant current source, Zi: Input impedance.

Claims (12)

One or more single-ended signal input terminals;
A plurality of input resistors in which one end of the single-ended signal input terminal is connected to one end of the resistor;
A first feedback resistor having one end connected to a node commonly connected to the other ends of the plurality of input resistors;
A current follower in which a common connection node of the plurality of input resistors and the other end of the first feedback resistor are respectively connected to a low impedance input terminal and a high impedance output terminal;
A connection node of the first feedback resistor and the high impedance output terminal of the current follower is connected to one input terminal, and a connection node of the plurality of input resistors, the first feedback resistor and the low impedance input terminal of the current follower is A single-to-differential conversion circuit connected to the other input terminal;
A variable gain amplifier to which an output of the single-to-differential conversion circuit is connected;
A differential offset is detected by being connected between the output of the variable gain amplifier and the single-to-differential conversion circuit, and a differential offset cancellation current is applied to the first feedback resistor and the current according to the detected differential offset. A differential operational transconductance amplifier configured to flow between a connection node of a high impedance output terminal of a follower and a connection node of the plurality of input resistors, the first feedback resistor, and a low impedance input terminal of a current follower And a signal processing circuit. The resistance values of the plurality of input resistors and the first feedback resistor are varied by switching means, and the plurality of input resistors, the first feedback resistor, and the current follower have functions of an adder and a gain control amplifier. 1. The signal processing circuit according to 1. The single-to-differential conversion circuit includes first and second input resistors, second and third feedback resistors, and a differential operational amplifier, and the differential input of the single-to-differential conversion circuit The terminal is connected to the first and second input resistors, and the other end of the resistor is connected to the differential input terminal of the differential operational amplifier, and the second and third feedback resistors are The signal processing circuit according to claim 1, further comprising a negative feedback circuit connected between the differential output terminal and the differential input terminal of a differential operational amplifier. The signal processing circuit according to claim 1, wherein the signal processing circuit further includes a filter circuit that limits a signal band of a differential offset cancellation path together with an output impedance between differential outputs of the differential operational transconductance amplifier. . The signal processing circuit further includes a differential transconductor circuit at an output of the operational transconductance amplifier, and the differential offset canceling current is connected to a connection node between the first feedback resistor and an output terminal of a current follower. 5. The signal processing circuit according to claim 4, wherein the signal processing circuit is caused to flow between the plurality of input resistors, the first feedback resistor, and a connection node of an input terminal of the current follower. The current follower has the low impedance input terminal connected to the drain terminal of the first field effect transistor, the first and second constant current sources, and the source terminal of the second field effect transistor, and the second field effect transistor. The drain terminal of the first and third field effect transistors is connected to the fourth constant current source, and the current follower has the high impedance output terminal connected to the third field effect transistor. A drain terminal and a third constant current source are connected, source terminals of the first and third field effect transistors are connected to a power supply line, and an arbitrary bias potential is applied to a gate terminal of the second field effect transistor. And the low impedance input terminal is connected to the second and first field effect transistors. And a current mirror having the first and third field effect transistors allows an inflow current to the low impedance input terminal to be arbitrarily multiplied by the high impedance output terminal. Item 2. A signal processing circuit according to Item 1. After detecting the amount of light reflected from the disk by a plurality of photodetectors of the optical pickup and converting the detected photocurrent signal into voltage, the signal processing circuit calculates the optical signal converted into voltage, and the calculated signal is An optical disk recording / reproducing apparatus that reproduces a signal recorded on the disk using a signal output from the signal processing circuit, outputting the signal with a constant amplitude level after being converted into a differential signal and amplified,
The signal processing circuit includes:
One or more single-ended signal input terminals;
A plurality of input resistors in which one end of the single-ended signal input terminal is connected to one end of the resistor;
A first feedback resistor having one end connected to a node commonly connected to the other ends of the plurality of input resistors;
A current follower in which a common connection node of the plurality of input resistors and the other end of the first feedback resistor are respectively connected to a low impedance input terminal and a high impedance output terminal;
A connection node of the first feedback resistor and the high impedance output terminal of the current follower is connected to one input terminal, and a connection node of the plurality of input resistors, the first feedback resistor and the low impedance input terminal of the current follower is A single-to-differential conversion circuit connected to the other input terminal;
A variable gain amplifier to which an output of the single-to-differential conversion circuit is connected;
A differential offset is detected by being connected between the output of the variable gain amplifier and the single-to-differential conversion circuit, and a differential offset cancellation current is applied to the first feedback resistor and the current according to the detected differential offset. A differential operational transconductance amplifier configured to flow between a connection node of a high impedance output terminal of a follower and a connection node of the plurality of input resistors, the first feedback resistor, and a low impedance input terminal of a current follower An optical disc recording / reproducing apparatus comprising: 8. The optical disk recording / reproducing apparatus according to claim 7, wherein resistance values of the plurality of input resistors and feedback resistors are varied by switching means, and the input resistor group, the first feedback resistor, and the current follower are used as an adder and a gain control amplifier. apparatus. The single-to-differential conversion circuit includes first and second input resistors, second and third feedback resistors, and a differential operational amplifier, and the differential input of the single-to-differential conversion circuit The terminal is connected to the first and second input resistors, and the other end of the resistor is connected to the differential input terminal of the differential operational amplifier, and the second and third feedback resistors are The optical disk recording / reproducing apparatus according to claim 7, further comprising a negative feedback circuit connected between the differential output terminal and the differential input terminal of a differential operational amplifier. 8. The optical disk recording / reproducing apparatus according to claim 7, wherein the signal processing circuit further includes a filter circuit for limiting a signal band of a differential offset cancellation path together with an output impedance between differential outputs of the differential operational transconductance amplifier. apparatus. The signal processing circuit further includes a differential transconductor circuit at an output of the operational transconductance amplifier, and the differential offset canceling current is connected to a connection node between the first feedback resistor and an output terminal of a current follower. The optical disk recording / reproducing apparatus according to claim 10, wherein a current flows between the plurality of input resistors, the first feedback resistor, and a connection node of an input terminal of a current follower. The current follower has the low impedance input terminal connected to the drain terminal of the first field effect transistor, the first and second constant current sources, and the source terminal of the second field effect transistor, and the second field effect transistor. A drain terminal of the first field effect transistor and a gate terminal of the third field effect transistor are connected to a fourth constant current source, and the current follower has the high impedance output terminal connected to the third constant current source. The drain terminal of the field effect transistor and a third constant current source are connected, the source terminal of the first and third field effect transistors is connected to a power supply line, and the gate terminal of the second field effect transistor is Arbitrary bias potential is supplied, and the low impedance input terminal is the second and The impedance is reduced by a negative feedback loop through one field effect transistor, and current flowing into the low impedance input terminal is arbitrarily applied to the high impedance output terminal by a current mirror having the first and third field effect transistors. The optical disk recording / reproducing apparatus according to claim 7.

Images