JP4314759B2 - Bus system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technology for signal transmission between elements such as a multiprocessor and a memory in an information processing apparatus (for example, between digital circuits configured by CMOS or the like or between functional blocks thereof). The present invention relates to a technology for speeding up bus transmission that is connected to a transmission line and performs data transfer. In particular, the present invention relates to a bus connecting a plurality of memory modules and a memory controller and a system using the bus.
[0002]
[Prior art]
As a bus system for connecting a large number of nodes and transferring data at high speed, there has been a non-contact bus wiring disclosed in JP-A-7-141079. The basic method is shown in FIG. In this case, data transfer between two nodes is performed using a crosstalk generator having a length L, that is, a directional coupler. That is, transfer between the bus master 10-1 and the slaves 10-2 to 10-3 is transferred between two lines, that is, using crosstalk between the terminated wiring 1-1 and the terminated wiring 1-2 to 1-3. Technology. This is suitable for one-to-many transfer between the bus master 10-1 and the slaves 10-2 to 10-3, that is, suitable for data transfer between the memory and the memory controller.
[0003]
[Problems to be solved by the invention]
However, in Japanese Patent Application Laid-Open No. 7-141079 of the prior art, the wiring length L occupied by the directional coupler determines the interval between the bus slaves 10-2, 10-3. In FIG. 2, the wiring length occupied by the two bus slaves DRAMs 10-1 and 10-2 is at least 2L, and the interval between the DRAMs 10-1 and 10-2 is L.
[0004]
In order to increase the density of the system, that is, to reduce the space between the DRAMs, it is easy to shorten the wiring length L of the directional coupler, but this causes a reduction in transmission efficiency, that is, the degree of coupling. I could not.
[0005]
A first problem of the present invention is to narrow the interval between DRAMs and to perform high-density mounting of a memory system.
[0006]
As a second problem, in a memory module system using a DQS signal for latching the DQ signal, for example, a DDR-SDRAM (Double Data Rate Synchronous DRAM), there is a problem that the latency of write data is long.
[0007]
The SSTL (Stub Series Terminated Logic) interface employed in the DDR-SDRAM has the same Hiz state as the termination voltage Vtt, and the receiver reference voltage Vref is substantially the same as the termination voltage Vtt. Here, the Hiz state means a state when the driver of the interface is not outputting data, that is, a high impedance state. For this reason, the transition from Hiz to L state or Hiz to H state cannot be recognized. For this reason, prior to data transfer, the strobe signal is once shifted from the HiZ state to the L state, and then data transfer is performed. This part is particularly called a preamble, and the presence of this preamble lengthens the write access time.
[0008]
In the case of a bus using a directional coupler using an SSTL driver, that is, when the main line and the sub-coupling wiring as shown in FIG. 2 are terminated, the amplitude of the preamble portion is half that of the data transfer. It is. In other words, the transition of the drive amplitude from the HiZ state to the L state or from the HiZ state to the H state is about half the signal amplitude compared to the transition from the L state to the H state and vice versa. For this reason, the amplitude of the write data and the read data input to the receiver is half of the data portion in the preamble portion, and the receiver sensitivity is insufficient, and it is necessary to ensure the signal amplitude.
[0009]
For this reason, when the SSTL driver is used, it is necessary to transition the strobe signal from the Hiz state to the L state once to ensure the signal amplitude. As a result, the access time is extended by the memory write.
[0010]
[Means for Solving the Problems]
As means for solving the first problem, a signal transmission driver of the memory controller 10-1 (MC) is set to have the same impedance as the characteristic impedance Zo of the wiring (main line) 1-1 connected thereto. And re-reflecting with this driver. The far end of the main line is an open end, and the signal is totally reflected at this portion. As the name suggests, a directional coupler composed of two wires (for example, parallel wires) has a signal discrimination characteristic with respect to the direction of signal transmission. In other words, the signal propagating in the main line is induced in the other wiring (sub-coupling wiring) of the directional coupler by a traveling wave traveling in a direction away from the main line as viewed from the MC 10-1. On the other hand, a signal is induced on the near end side and a reflected wave returning in the approaching direction is induced on the far end side.
[0011]
The directional coupler can separately extract the crosstalk caused by the traveling wave and the reflected wave of the signal propagating through the main line from both ends of the sub-coupled line. For this reason, two memory modules can be connected to one coupler. For this reason, since two memories can be connected within the line length of the directional coupler, the mounting density can be doubled.
[0012]
Further, by forming the main line as a folded directional coupler with different layers, the directional coupler can be overlapped, so that the memory interval can be further halved. For this reason, since the interval between the memory modules can be significantly reduced as compared with the conventional example, the mounting area can be reduced.
[0013]
As a means for solving the second problem, the memory controller uses a binary signal for data transfer, and the impedance of the memory controller is the same as the characteristic impedance of the wiring on the memory controller side. That is, the HiZ state and H state when data is not transferred are set to the same potential and driven with the same impedance as the characteristic impedance of the wiring. That is, the input impedance becomes equal to the characteristic impedance. When the data is in the L state, the L signal is driven with the same impedance as the characteristic impedance. By doing so, the reflected wave can be absorbed.
[0014]
When the signal is driven from the Hiz state to the L state and when the signal is driven from the H state to the L state, the signal has the same amplitude, so that the signal passing through the coupler has the same amplitude in the two transfers. This eliminates the need for a preamble because the signal amplitude is the same for any signal transition. Since the preamble is unnecessary, the memory access time is shortened, the bus use efficiency is increased, and the system performance is improved.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment will be described with reference to FIG.
10-1 is an LSI chip (hereinafter referred to as MC) having a memory controller control mechanism, and 10-2 to 10-5 are memory chips (hereinafter referred to as DRAM).
[0016]
The MC 10-1 performs data read / write (read / write) operations on the DRAMs 10-2 to 10-5. The data transfer wirings for reading and writing are 1-1 to 1-3, and among these, the wiring 1-1 connected to the MC 10-1 is called a main line. Further, the wiring 1-2 is composed of three parts, and a sub-coupling line (Sub Coupling Line) portion having a length L constituting a directional coupler by wiring in parallel with the main line 1-1 and its sub-coupling. Two stub wiring (stub) portions physically (substantially) vertically drawn from both ends of the line portion. In FIG. 1, the sub-coupling line portion having the length L and the main line 1-1 in the wirings 1-2 and 1-3 form directional couplers C1 and C2, respectively. For this reason, the directional couplers C1 and C2 do not include the drawer stub wiring.
[0017]
Data signal propagation between the MC 10-1 and the DRAMs 10-2 to 10-5 is performed by C1 and C2 directional couplers represented by inverted symbols "C". This directional coupler is equivalent to that described in JP-A-7-141079. That is, in this case, data transfer between two nodes is performed using crosstalk which is a coupling between two parallel wirings (directional coupler). That is, transfer between the MC (bus master) 10-1 and the memory chip (bus slave) 10-2 to 10-5 is performed between two lines, that is, crosstalk between the main line 1-1 and the wirings 1-2 and 1-3. Use to transfer.
[0018]
Termination resistors are built in the I / O circuits of the DRAMs 10-2 to 10-5. That is, the I / O circuits of the DRAMs 10-2 to 10-5 have the same input impedance as the characteristic impedance of the wirings 1-2 to 1-3 connected thereto. For this reason, there is no reflection at this I / O circuit section. With this configuration, the signals generated by the directional couplers C1 and C2 propagate to the stub wiring, but are not re-reflected at the input ends of the DRAMs 10-2 to 10-5. This termination may be constituted by a MOS transistor in the DRAM 10-2 or may be constituted by an external resistor.
[0019]
The main line 1-1 is terminated with an impedance that is far greater than the characteristic impedance of the main line 1-1 when viewed from the MC 10-1. In the case of FIG. 1, it is opened (OPEN-END). The reflection coefficient at the main line 1-1 is almost 1, and the voltage is totally reflected.
[0020]
Further, the driver of the I / O circuit of the MC 10-1 has the same impedance as the characteristic impedance of the main line 1-1, and there is no re-reflection at this portion. In FIG. 1, there are four DRAMs, 10-2 to 10-5, but there is no difference in the effect of the present invention with more or less DRAMs.
[0021]
Next, the signal propagation operation between the MC 10-1 and the DRAMs 10-2 to 10-5 in FIG. 1 will be described with reference to FIGS.
3 and FIG. 4, the same symbols as those in FIG. 1 are the same as those in FIG.
[0022]
In the main line 1-1, it can be functionally distinguished into a part (main coupling line) constituting the couplers C1 and C2 and a wiring connecting them. The main coupling line is a portion in the main line 1-1 that is wired in parallel to the sub coupling lines in the wirings 1-2 and 1-3 in the directional couplers C1 and C2. . The signal propagation delay time from the MC 10-1 to the far end of the main line 1-1 is represented by T1. Further, the propagation delay time of the main coupled line portion of the coupled lines C1 and C2 is represented by T2. Here, although there is a part of the wiring that does not constitute the directional coupler on the main line 1-1, it is assumed that the propagation delay time is negligibly short for simplicity. That is, description will be made assuming that T1 = 2 * T2.
[0023]
Let both ends of the main line 1-1 be terminals (A) and (B). (A) is the MC 10-1 side, and (B) is a distant open end of the main line 1-1. Similarly, both ends of the wiring 1-2 are (C) and (D), and both ends of the wiring 1-3 are (E) and (F). FIGS. 4, 5, and 6 schematically show voltage waveforms at these points (A) to (F).
[0024]
4 shows a signal state in which a data signal is transmitted (written) from MC 10-1, FIG. 5 shows a signal state in which a memory read signal is transmitted from DRAM 10-2 to MC 10-1, and FIG. A signal state in which a memory read signal is transmitted to the MC 10-1 is shown. The horizontal axis direction represents time, and vertical dotted lines are drawn at intervals of T2. The vertical axis indicates the signal voltage.
[0025]
In FIG. 4, waveform (A) is an output waveform of the driver of MC 10-1 and transitions from the L state to the H state. The driver of the MC 10-1 has the same output impedance as that of the main line 1-1. Such a driver is particularly called a Source Impedance Matching Driver. The drive waveform that has transitioned from the L state to the H state is divided by the impedance of the driver and the impedance of the main line 1-1, and is therefore output at half the drive voltage. The drive signal propagates on the main line 1-1 in the right hand direction of the drawing for a time T1, and then reaches the far end (B). Since the voltage at this time is the open end of (B), total reflection occurs and the traveling wave and reflected wave are superimposed. (A) Twice the “half drive voltage” at the end Voltage.
[0026]
After a time T1 from the time of driving, the reflected wave propagates on the main line 1-1 in the left-hand direction and reaches the end (A) again. This time is 2 * T1 after driving. The voltage at this time is a superposition of traveling wave and reflected wave. Because there is It becomes equal to the drive voltage of MC10-1. Further, since this driver is Source Impedance Matching, there is no re-reflection at this point, and the signal does not repeat re-reflection and is stabilized in the H state.
[0027]
Next, each point of the wiring 1-2 and 1-3 will be examined. A signal is generated backward in the coupler C1 by the traveling wave flowing through the main line 1-1. Here, the backward direction is the direction opposite to the traveling wave direction, and is the terminal (C) side in FIG. This is backward crosstalk. The signal generated in the direction of the terminal (C) is absorbed in the DRAM 10-2 in FIG. 3 and is not reflected. This is because the DRAM 10-2 is terminated with the same impedance as the characteristic impedance Zo of the wiring 1-2.
[0028]
When the coupler is composed of a strip line, which is a wiring surrounded by a metal plane, the induced voltage due to the inductance between the two wires and the induced voltage due to the capacitance cancel each other in the forward direction on the terminal (D) side. Thus, no signal is generated. So-called forward crosstalk does not occur. That is, in the directional coupler C1 of FIG. 4, backward crosstalk due to traveling waves of the main line 1-1 is generated on the terminal (C) side, but no forward crosstalk is generated on the terminal (D). The backward crosstalk generated by the coupler C1 has a length of round trip time of the coupler C1 (= 2 * T2).
[0029]
The reason for this pulse width is as follows.
Backward crosstalk is generated at the front of the traveling wave, and is induced in the sub-coupled line until the traveling wave is input to the coupler and then output. A traveling wave propagates from the input to the exit of the main coupler at time T2, and since a signal generated near the exit of the main coupling line takes T2 to propagate through the sub-coupler, a total of 2T2 signals are induced. Because.
[0030]
After T2 from the drive time, the traveling wave traveling on the main line 1-1 reaches the coupler C2, and then the coupler C2 also moves in the same manner as the coupler C1. As a result, a signal similar to the waveform (C) is induced at the terminal (E) of the DRAM 10-3. Of course, there is no reflection here. Like the terminal (D), the traveling wave propagating through the coupler C2 does not induce any voltage at the terminal (F).
[0031]
After time T1, when a reflected wave is generated at the open end (B) of the main line 1-1, the reverse process occurs. Since (B) is an open end, the reflected wave is totally reflected, the voltage amplitude of the reflected wave is the same as the traveling wave, and the traveling direction is opposite. When the reflected wave returns along the main line 1-1 toward the MC 10-1, first, backward crosstalk is induced by the coupler C2. This induces a signal on the terminal (F) side that is behind the reflected wave of the main line 1-1. Therefore, if there is no wiring resistance and the waveform traveling on the main line 1-1 is not distorted, the reflected wave of the main line 1-1 induces the same waveform as (C) at the terminal (F). This timing is after the time T1 when the reflected wave is generated as measured from the time when the MC 10-1 starts transmitting the signal. The pulse width of the waveform (F) is T2 which is twice. Naturally, this reflected wave does not induce anything on the front terminal (E) side in the coupler C2.
[0032]
After time T1 + T2, when the reflected wave of the main line 1-1 enters the coupler C1, a backward crosstalk is induced on the terminal (D) side in the same manner. This pulse width is also twice T2.
[0033]
As described above, the signal traveling on the main line 1-1 from the MC 10-1 generates backward crosstalk in the couplers C1 and C2 by the traveling wave and the reflected wave at the end (B). The devices C1 and C2 are selective in signal generation with respect to the direction of the traveling wave / reflected wave, and do not overlap each other and do not become noise. Therefore, at the terminals (C) to (F) of the DRAMs 10-2 to 10-5, pulses having a width of T2 that is twice the propagation delay time of the round trip of the couplers C1 and C2 are generated. This is the same as Kaihei 7-141079 and indicates that it has the same signal waveform quality. The order of signal generation was waveform (C) → (E) → (F) → (D). This means that the DRAM 10-2 (C) is closest to the MC 10-1 in terms of time, and the second DRAM 10-3 (D) is the farthest from the MC 10-1. Signal propagation delay times from the MC 10-1 to the DRAMs 10-2 to 10-5 are respectively expressed by the following (Equation 1) to (Equation 4).
Signal propagation delay time from MC 10-1 to DRAM 10-2 (C) = 0 (Expression 1)
Signal propagation delay time from MC 10-1 to DRAM 10-3 (D) = T1 + T2 (Equation 2)
Signal propagation delay time from MC 10-1 to DRAM 10-4 (E) = T2 (Equation 3)
Signal propagation delay time from MC 10-1 to DRAM 10-5 (F) = T1 (Equation 4)
Therefore, in each case, the signal arrives after the delay time indicated by (Expression 1) to (Expression 4).
[0034]
As shown in FIGS. 1 and 3, two terminated DRAMs 10-2 to 10-3 and 10-4 to 10-5 are connected to both ends of the directional couplers C1 and C2, respectively. It can be seen that signal transmission can be performed to -2 to 10-5.
[0035]
Next, with reference to FIGS. 5 and 6, signal transmission from the DRAM 10-2 to 10-5, which is the memory read direction, to the MC 10-1 will be considered. FIG. 5 shows waveforms at various points related to transfer from the DRAM 10-2 to the MC 10-1, and FIG. 6 shows waveforms at transfer from the DRAM 10-3 to the MC 10-1. Waveforms of transfer from the DRAMs 10-4 and 10-5 to the MC 10-1 are the same as those in FIGS.
[0036]
In FIG. 5, first, a pulse is output from the L state to the H state from the DRAM 10-2 (C). After that time T2, the signal reaches the terminal (D). Since the input impedance of the DRAM 10-3 (D) is the same as the characteristic impedance of the wiring, there is no reflection. The coupler C1 induces backward crosstalk in the main line 1-1. This pulse time is the round-trip propagation delay time (= 2 * T2) of the same coupler as in FIG. Crosstalk is not generated in front of the main line 1-1. Therefore, no signal is induced at the end (B). For this reason, if a pulse signal is driven from the DRAM 10-2, even if the end (B) of the main line 1-1 is open, crosstalk is generated in the MC 10-1. This has the same pulse width as that of the prior art JP-A-7-141079.
[0037]
Transfer from the DRAM 10-3 (D) to the MC 10-1 (A) in FIG. 6 is a generation process in the reverse direction to that in FIG. The pulse from the DRAM 10-3 (D) reaches the terminal (C) after time T2. In the coupler C1, backward crosstalk is induced and propagates in the end (B) direction on the main line 1-1. After a time T2 from the time of driving from (D), the rear crosstalk generated by the coupler C1 reaches the end (B). Here, the light is totally reflected and travels back along the main line 1-1. Then, MC10-1 is reached after time T2 + T1 after driving. Also in FIG. 6, the width of the pulse reaching MC10-1 (A) is T2 which is twice the same as that in FIG.
[0038]
The signal propagation delay time from the DRAMs 10-2 to 10-5 for read operation to the MC 10-1 is the same as that in FIG. That is, it is shown by the following (Equation 5) to (Equation 8).
Signal propagation delay time from DRAM 10-2 (C) to MC 10-1 = 0 (Equation 5)
Signal propagation delay time from DRAM 10-3 (D) to MC 10-1 = T2 + T1 (Equation 6)
Signal propagation delay time from DRAM 10-4 (E) to MC 10-1 = T2 (Equation 7)
Signal propagation delay time from DRAM 10-5 (F) to MC 10-1 = T1 (Equation 8)
In each case, the signal arrives after the delay time indicated by the above equation. These (Equation 5) to (Equation 8) are the same as (Equation 1) to (Equation 4), and the propagation delay time between the MC 10-1 and the DRAMs 10-2 to 10-5 is the same for both the write operation and the read operation. I understand that. This is the same as the case of using the prior art, and is an important characteristic when performing timing design in a memory system. That is, it means that the same timing design method as in the past can be followed as it is. This leads to a reduction in development man-hours.
[0039]
In this way, it can be seen that the bus can be configured with only two couplers in order to connect the four DRAMs 10-2 to 10-5 with the bus and perform signal transmission in both directions. As a result, the mounting area of the DRAM can be reduced to half that of the prior art shown in FIG. 2, which enables high-density mounting. That is, in Japanese Patent Application Laid-Open No. 7-141079, which is a conventional technique, the distance (pitch) between the DRAMs 10-2 to 10-5 is continuously arranged as shown in FIG. However, the main line is open as shown in FIG. 1 or 3, the MC 10-1 driver is set to Source Impedance Matching, and the terminated DRAM 10-2˜ By using 10-5, it is possible to connect double DRAMs with the same wiring length to the same main line, and high-density mounting is possible as a system.
[0040]
Next, this signal transmission was confirmed by simulation. This is shown in FIGS.
FIG. 7 shows a cross-sectional shape of the directional coupler. The shape of the coupler can be considered in various ways depending on the requirements of the system, but the wiring width (W = 154 μm) wiring pitch (W = 154 μm) used in a PC or PC server using FR-4, which is a general printed board material. S = 216.7 μm). As a result of electromagnetic field analysis, the electrical characteristics between the wirings were as follows.
[0041]
Capacitance matrix between two lines
CMATRIX (F / um) =
1.446e-16 -6.644e-17
-6.644e-17 1.446e-16 (Equation 9)
Inductance matrix between two lines
LMATRIX (H / um) =
4.487e-13 2.062e-13
2. 062e-13 4. 487e-13 (Equation 10)
Characteristic impedance matrix
Real part =
6.272e + 01 2.882e + 01
2. 882e + 01 6. 272e + 01 (Equation 11)
Imaginary part =
-3.336e-01 -1.694e-02
-1.694e-02 -3.336e-01 (Equation 12) Therefore, the effective impedance Zeff of the two lines was 55Ω. Here, e represents a power with 10 as the base.
[0042]
[0043]
The backward crosstalk coefficient is
Real part =
1.000e + 00 2.433e-01
2. 433e-01 1. 000e + 00 (Equation 13)
Imaginary part =
0.000e + 00 1.441e-03
It was 1.441e-03 0.000e + 00 (Equation 14). That is, it can be seen that a rear crosstalk of 0.2433V is induced when a 1V signal is incident.
[0044]
Using this coupler, the write data waveform from the MC 10-1 to the DRAM 10-2 to 10-5 in FIG. 3 was simulated by the equivalent circuit shown in FIG. The simulator used is SPICE (Simulation Program for Integrated Circuit Emphasis) for circuit analysis. As an equivalent circuit of the driver of MC10-1, a pulse voltage source and a resistor rs are used. As an equivalent circuit of the main line 1-1, a known transmission line model T1, T3, T5 and a known loss coupling line model Y2, Y4 as a directional coupler are connected, and one terminal S6 of the transmission line T5 is set high. Terminated with a resistance rk. Since rk has a high resistance of 100 kΩ, it can be regarded as an open end. Terminals (A) and (B) in FIG. 3 correspond to S1 and S6 in FIG.
[0045]
DRAMs 10-2 to 10-5 are represented by parallel connection of termination resistors rk1, rk2, rj1, and rj2 and input capacitances ck1, ck2, cj1, and cj2. 3 correspond to K1 and K4 in FIG. 8, and terminals (E) and (F) in FIG. 3 correspond to J1 and J4 in FIG. The terminal potential is represented by Vtt. These constants are shown below.
VPULSE: Amplitude = 1. 8V Rise time = 0. 1ns ... (Equation 15)
rs = 55Ω (Equation 16)
t1, t3, t5, t6, t8, t9, t10: Characteristic impedance z0 = 55Ω td = 1, 0ns (Equation 17)
Y2, Y4: Wiring length = 40mm (Equation 18)
rk = 100KΩ (Equation 19)
rk1, rk2, rj1, rj4 = 55Ω (Equation 20)
Vtt = 0. 9V (Equation 21)
ck1, ck2, ck3, ck4 = 0. 1pF (Equation 22)
This simulation waveform is shown in FIG. This is an example of VTT = 0.9V. As in FIG. 4, clean rectangular pulses are generated at the terminals K1, K4, J1, and J4 corresponding to the DRAMs 10-2 to 10-5, and it can be seen that there is no significant disturbance. In addition, the amplitude of the crosstalk is 108 mV to 220 mV with respect to the amplitude of the drive pulse of 0.9 V, and the amplitudes of K1, J1, J4, and K4 are sequentially decreased due to the wiring resistance of the main line 1-1. However, the signal of about 100 mV is a voltage level that can be sufficiently identified even in a semiconductor using a C-MOS. The time order also appears in the order of K1, J1, J4, and K4, and it can be seen that it is the same as FIG.
[0046]
Next, signal transmission (read) waveforms from the DRAM 10-2 to the MC 10-1 will be described with reference to FIGS. FIG. 10 is the same as FIG. 8 and is an equivalent circuit. A voltage source as a read waveform is connected to a point K0 corresponding to the DRAM 10-2 in FIG. The impedance of the driver of the DRAM 10-2 is represented by rk1, and in this simulation is 10Ω, which is smaller than the wiring impedance Zo (= 55Ω). The purpose of this is to increase the signal amplitude of the pulse.
[0047]
Further, a resistor rs (= 55Ω) having the same resistance value as the characteristic impedance Zo of the wiring is connected to the point S1 corresponding to the MC 10-1 of the main line. Other circuit constants are the same as in FIG. A waveform obtained by the circuit analysis is shown in FIG. A pulse of 368 mV has reached the S1 point of MC10-1, and there is almost no waveform distortion that causes noise at other points. This waveform is approximately the same as FIG.
[0048]
Next, FIG. 12 shows signal waveforms from the DRAM 10-3 to the MC 10-1. In the equivalent circuit, the pulse voltage source is connected to rk2 as compared with the case of FIG. 10, and rk1 is connected to the termination power source VTT with characteristic impedance as shown in FIG. rk2 has a low impedance of 10Ω as with rk1 in FIG. The waveform of this is shown in FIG.
[0049]
In FIG. 12, the drive pulse from K4 represented by the dotted line passes through the coupler Y2 in FIG. 10, thereby generating crosstalk on the main line. This pulse travels on the main line and is reflected at the terminal S6. . Since this reflection is total reflection, the amplitude is doubled. This reaches S1 and results in a pulse with an amplitude of 302 mV. The arrival time is later than that in FIG. 11 and is the same as the delay time from S1 to K4 in FIG. In this waveform, noise of about 80 mV is on J4, but this is not a problem. This is because this transfer is a read transfer from the DRAM 10-3 to the MC 10-1, and the DRAM 10-5 does not use this signal.
[0050]
Similarly from DRAM 10-4, 10-5. The mechanism of the lead waveform is the same. For this reason, read data can be transferred to the MC 10-1. It can also be seen that the propagation delay time at this time is the same as in FIG.
[0051]
Next, the I / O circuits of the MC 10-1 and the DRAMs 10-2 to 10-5 in FIG. 1 will be described with reference to FIGS.
[0052]
FIG. 13 is an I / O circuit of the MC 10-1. Reference numeral 51 denotes a driver of the MC 10-1, and reference numeral 52 denotes a receiver, which is connected to the same potential together with an input / output terminal (I / O PAD). The driver 51 is Source Impedance Matching and has an impedance equal to the characteristic impedance of the wiring connected to this when the data is not transmitted and when it is transmitted. The final stage transistors of the driver 51 are denoted as M1 and M2. The transistors M1 and M2 are connected to a totem pole, and M1 is a P-MOS transistor connected to the output terminal (I / O PAD) and the power supply VDDQ. M2 is an N-MOS transistor connected to the output terminal and the ground (VSS). Since the impedance of the two transistors M1 and M2 can be changed by changing the gate width of the transistor, the characteristics of the main line 1-1 can be adjusted by adjusting the gate width of the transistor using an impedance adjustment circuit not shown in FIG. Can be matched to impedance.
[0053]
The MC 10-1 controls M1 and M2 according to the data to be output. When the output data is DATA and the output enable signal is OE, the characteristics of the driver that the MC 10-1 of FIG. 1 should have are as shown in the table of FIG. That is, only when DATA = L (logical low) and OE = L, M2 is turned on and the L signal is transmitted. In other states, the M1 transistor is on. For this reason, the impedance of the driver matches the characteristic impedance of the main line whether data is transmitted or received. The main line connected to the driver 51 is an open-ended main line. With this configuration, no current is consumed unless the L signal is driven.
[0054]
Next, the receiver 52 has a hysteresis characteristic in order to discriminate the signal generated by the directional coupler. That is, when the signal incident on the directional coupler transitions from L (logical low) to H (logical high), a positive pulse is generated here, and when the signal transitions from H to L, the negative polarity is generated. A pulse is generated. For this reason, one method for discriminating these two signals having different polarities is a hysteresis characteristic.
[0055]
When the driver of the MC 10-1 of FIG. 13 is connected to the bus of FIG. 1, the read data read by the MC 10-1 generates a positive / negative pulse with respect to the potential in the H state. This is because the directional coupler has no direct current (DC) coupling between the two lines, so that an alternating current (AC) pulse is generated with respect to the potential of the main coupling wiring regardless of the DC value of the drive voltage. This is because, of course, data is not output from the driver during reading, and the potential of the main line is equal to VDDQ in the H state.
[0056]
Therefore, in the receiver 52, the signal from the I / O PAD is compared with the H potential of the driver 51, that is, with respect to VDDQ. For this reason, the receiver 52 operates as a circuit that receives a signal by VDD higher than VDDQ. For example, when VDDQ = 1.8V, VDD = 2.5V, the receiver 52 can be configured without any problem even with C-MOS.
[0057]
As described above, the MC 10-1 in FIG. 1 has the I / O circuit as shown in FIG. 13 so that signals can be transmitted and received stably.
[0058]
Next, an example of the I / O circuit of the DRAMs 10-2 to 10-5 is shown in FIG.
The I / O circuits of the DRAMs 10-2 to 10-5 are almost the same as the I / O circuit of the MC 10-1 in FIG. 13, and the difference is in the driver 51 '. The transistor M2 has a value lower than the impedance of the wiring. Others are the same as the structure of FIG.
[0059]
This is due to the following reason. The wiring on the DRAM side is terminated at both ends when inputting data. Also, when data is output, the other DRAM has a matching termination condition. That is, the reflected wave from the far end does not return. This is different from the condition that the end of the main line connected to the MC 10-1 is an open end, and it is not necessary to terminate the driver 51 '. That is, the driver 51 ′ does not need to perform source impedance matching. For this reason, in order to increase the signal generated by the coupler, the drive pulse may be increased. Therefore, a larger amplitude can be secured by lowering the impedance of M2. Of course, the output impedance of the driver 51 'may be matched with the characteristic impedance of the wiring. In this case, the signal amplitude of the drive pulse is reduced, but there is no problem if the MC 10-1 receiver can identify the data. The configuration of the I / O circuit in this case is the same as in FIG.
[0060]
When receiving data, the driver outputs an H state so that its impedance matches the characteristic impedance of the main line. For this reason, the drivers 51 'of the two DRAMs 10-2 and 10-3 connected to the same wiring output H from each other. However, since these potentials are equal to VDDQ, current consumption does not flow in this state. That is, current consumption does not flow when the H drive or data is in the HiZ state. With this configuration, there is no current consumption unless the L signal is driven, and the same power saving effect as that of the main line in FIG. 13 is obtained.
[0061]
As shown in FIGS. 13 and 14, even if the potential of the main line at the time of reception is VDDQ, the signal amplitude generated by the directional coupler does not change. For this reason, even if the MC10-1 is in the H state, L state, or HiZ state, the binary signal is output in a state where the output impedance matches the impedance of the wiring. It is possible to output drive pulses with less distortion. Further, the signal amplitude can be ensured and the waveform is not distorted by making the driver 51 'of the DRAM 10-2 to 10-5 low impedance only in the L state. For this reason, data can be transmitted and received stably at high speed.
[0062]
Next, with reference to FIG. 15, a wiring mode when mounted on a printed circuit board will be described. Reference numerals 2-2 to 2-7 denote memory modules on which the DRAMs 10-2 to 10-7 are mounted. Reference numeral 1 denotes a motherboard on which the MC 10-1 and the memory modules 2-2 to 2-7 are mounted. The memory modules 2-2 to 2-7 are connected to the motherboard 1 by connectors. A solid line in the mother board 1 is a wiring layer for mounting components, and dotted lines m1 and x1 represent inner signal line layers.
[0063]
The main line 1-1 from the MC 10-1 is wired on the inner wiring layer m1 in a straight line from right to left in FIG. If it is necessary to bypass the VIA hole for the connector lead-out wiring and power supply pin, it may be bent. The main line 1-1 forms couplers C1 to C3 with a part of the lines 1-2 to 1-7 arranged in parallel with the main line 1-1. Stub lines to the DRAM are drawn at both ends of the sub-couplers of the couplers C1 to C3. The couplers C1 to C3 are arranged continuously with respect to the main line 1-1 so as not to overlap. By wiring in this way, it is possible to wire all the memory modules 2-2 to 2-7 with the same wiring density. The main line 1-1 is an open end at the right end (distant end) in FIG.
[0064]
Data transmission / reception between the MC 10-1 and the DRAMs 10-2 to 10-7 is performed with respect to the DRAMs 10-2, 10-4, and 10-6. For the DRAMs 10-3, 10-5, and 10-7, the talk is performed by using the reflected wave at the far end and the rear crosstalk signal.
[0065]
With this configuration, it is possible to connect twice as many memory modules 2-2 to 2-7 with the same main line 1-1 length as compared with the conventional system shown in FIG. In FIG. 15, the directional coupler is configured by using two inner layers, but the effect is the same even if it is configured by two adjacent wirings in one layer. In this case, the inner layer constituting the coupler can be reduced from two layers to one layer, but the wiring density per layer is doubled, so it may be selected according to the requirements of the system.
[0066]
Further, in FIG. 15, among the memory modules 2-2 to 2-7 to be mounted, a certain memory module may not be mounted depending on the system configuration. In this case, since reflection occurs in the vacant memory module, in order to suppress this, it is necessary to insert a termination module equipped with a resistor for matching and terminating the wiring to the termination power source. This termination power supply has the same potential as the memory modules 2-2 to 2-7, and the termination resistance value is also the same as the impedance value of the DRAM 10-2 to 10-7. Of course, the characteristic impedance of the wiring in the termination module is also made equal to that of the memory module. By configuring the termination module in this way and inserting it into the connector of the vacant memory module, the reflection noise of the wiring is eliminated and the bus operation can be performed stably.
[0067]
A second embodiment will be described with reference to FIG.
The purpose of this embodiment is to mount memory modules at a higher density than in the first embodiment. In Mother Board 1, the interval (pitch) between the memory modules 2-2 to 2-9 mounted on the Mother Board 1 is the length of this coupler since directional couplers are continuously arranged in JP-A-7-141079. There was a problem that could not be done below.
[0068]
In contrast to FIG. 15, in the configuration of this embodiment, the wiring of the main line 1-1 is drawn in the right hand direction of the signal layer m1 as viewed from the MC 10-1, and the layer is connected to the signal line layer m2 at the right end by a VIA hole. Changed to the left hand direction. And it is opened at the farthest end.
[0069]
The main line 1-1 of the signal layer m1 includes couplers C1 and C3 by the wiring 1-2 between the DRAMs 10-2 and 10-4 and the wiring 1-4 between the DRAMs 10-6 and 10-8. The main line 1-1 of the folded signal layer m2 is a coupler C4 to the wiring 1-5 between the DRAMs 10-7 and 10-9, and a coupler to the wiring 1-3 between the DRAMs 10-3 and 10-5. Configure C2.
[0070]
The wirings 1-2 and 1-4 constitute a signal line layer x1, and the wirings 1-3 and 1-5 constitute a sub-coupling line portion with the signal line layer x2. Therefore, the couplers C1 and C3 are composed of wiring layers x1 and m1, and the couplers C2 and C4 are composed of wiring layers m2 and x2. For this reason, the couplers C1 and C3 are referred to as upper layers, and C2 and C4 are referred to as lower layers.
[0071]
The couplers C1 to C4 are continuously arranged so that the characteristic impedance of the wiring is constant with respect to the main line 1-1. The data transfer between the MC 10-1 and the DRAMs 10-2 to 10-9 is arranged and wired so that rear crosstalk is performed in any coupler. That is, the DRAMs 10-2 and 10-6 connected to the couplers C2 and C4 in the upper layer are connected to the couplers C4 and C2 in the lower layer by a traveling wave flowing through the main line 1-1 in the m1 layer. Therefore, in -9 and 10-5, backward crosstalk is induced by a traveling wave flowing through the main line 1-1 of the m2 layer. The DRAMs 10-3 and 10-7 connected to the couplers C2 and C4 in the lower layer are reflected by the reflected wave flowing through the main line 1-1 of the m2 layer, and the DRAMs 10-8 and 10-4 are the couplers in the upper layer. Back crosstalk is induced by the reflected wave of the main line 1-1 of the m1 layer by C4 and C2. Thus, the rear crosstalk is arranged in any transfer.
[0072]
Since the main line 1-1, which is the main coupling wiring constituting the coupler, is folded once from one layer to the other layer, a directional coupler can be configured in each layer, so that the memory modules 2-2 and 2 The interval of −9 can be made about half the wiring length of the couplers of the directional couplers C1 to C4. For this reason, it becomes possible to mount the memory modules on one Mother Board 1 with high density. The high-density mounting can be performed twice as much as FIG. 15 of the first embodiment and four times as high as that of FIG. 2 of the conventional example. Even in such a case, the coupling length necessary for coupling is the same, and the coupling amount necessary for signal propagation is the same as that of Japanese Patent Laid-Open No. 7-141079 in FIG. 2 and has the same signal waveform quality. Become.
[0073]
That is, in Japanese Patent Application Laid-Open No. 7-141079, which is a conventional technique, the interval (pitch) between the memory modules 2-2 to 2-4 mounted on the mother board 1 as shown in FIG. However, there is a problem that it cannot be made shorter than the length of the coupler because of the arrangement, but by folding the main line as shown in FIG. 16, the memory modules 2-2 to 2- The interval (pitch) of 9 can be reduced to ¼ of the length of the coupler, enabling high-density mounting as a system.
[0074]
In addition, in FIG. 16, as in the first embodiment, among the memory modules 2-2 to 2-9 to be mounted, a memory module may not be mounted depending on the system configuration. In this case, since reflection occurs in the vacant memory module, in order to suppress this, it is necessary to insert a termination module equipped with a resistor for matching and terminating the wiring to the termination power source. This termination power supply has the same potential as the memory modules 2-2 to 2-9, and the termination resistance value is also the same as the impedance value of the DRAM 10-2 to 10-9. Of course, the characteristic impedance of the wiring in the termination module is also made equal to that of the memory module. By configuring the termination module in this way and inserting it into the connector of the vacant memory module, the reflection noise of the wiring is eliminated and the bus operation can be performed stably.
[0075]
Next, FIG. 17 shows an example of the layer configuration of the mother board 1 corresponding to FIG. FIG. 17 is a cross section in a direction perpendicular to the main line 1-1 of the mother board 1 of FIG. From the upper layer, CAP1 layer, power supply layer (V1), ground layer (G1), signal layer (m1), signal layer (x1), ground layer (G2), power supply layer (V2), signal layer (m2), signal layer ( x2), a ground layer (G3), a power supply layer (V3), and a CAP2 layer. In general, a printed wiring board is formed by bonding a copper-clad plate covered with copper on both sides with a prepreg, and this prepreg is represented by two wavy lines.
[0076]
The directional coupler comprises a coupler C1 in FIG. 16 by parallel wirings 1-1 and 1-2 arranged in the upper and lower layers of the m1 layer and the x1 layer. Similarly, the coupler C2 in FIG. 16 is constituted by the parallel wirings 1-1 and 1-3 arranged in the upper and lower layers of the m2 layer and the x2 layer. Here, the main line 1-1 of the signal layer m1 and the main line 1-1 of the signal layer m2 are the same folded wiring in FIG.
[0077]
A ground layer or a power supply layer is located between the couplers of the m1, x1, m2, and x2 layers, and functions to prevent noise between signals that is a coupling between the directional couplers C1 and C2. ing. With this configuration, signal coupling between couplers, that is, crosstalk noise is small and high-speed data transfer is possible.
[0078]
Further, as shown in FIG. 18, the coupler may be configured so as to be arranged in a transverse direction with respect to the cross section and coupled. Here, the lateral direction means that a coupler is configured using the same layer. For example, the coupler C1a surrounded by an ellipse is composed of a main line 1-1a and a wiring 1-2a, and the folded main line 1-1a forms a wiring 1-3a and a coupler C2a in the m2 layer. Similarly, the main line 1-1b having different signal bits is combined with the wiring 1-2b in the m1 layer to form the coupler C1b, and the folded main line 1-1b forms the wiring 1-3b and the coupler C2b. To do. In order to reduce the amount of noise that is the coupling between the respective couplers C1a, C1b, C2a, C2b, a planar power supply layer is inserted between the layers, and the distance between the signal lines 1-1a, 1-1b is increased. . With such a configuration, there is an effect that the number of layers for configuring the coupler is small compared to FIG.
[0079]
A third embodiment will be described with reference to FIG.
This embodiment is a configuration example in which the far end of the main line 1-1 is short-circuited with respect to FIG.
[0080]
The short circuit means that the connection is made with a very low impedance compared to the impedance of the wiring. In FIG. 19, the short circuit is connected to a power source having zero internal impedance. By connecting in this way, total reflection occurs at the far end. In this case, the reflection coefficient is −1, so that the polarity is different from the traveling wave. For this reason, the sign of the backward crosstalk generated in the DRAMs 10-5 and 10-3 using the reflected wave is also opposite to that in FIG. 1, and becomes negative logic with respect to the DRAMs 10-2 and 10-3. That is, the receivers of the DRAMs 10-3 and 10-5 have negative logic compared to the DRAMs 10-2 and 10-4. Similarly, the DRAMs 10-3 and 10-5 have negative logic.
[0081]
Here, the power supply to be short-circuited may be ground or VDDQ. The output impedance of the driver in the MC 10-1 is the same as the characteristic impedance of the wiring as in the driver of the first embodiment (FIG. 1), but the short-circuit potential and the output potential in a state where no data is output in the HiZ state are aligned. Needless to say. The reason is that if this is not done, current flows from the driver and power consumption increases even when data transfer is not performed.
[0082]
With this configuration, it is possible to use a mixture of positive and negative logic signals. Although the DRAMs 10-2 to 10-5 have the same configuration, there are cases where it is desired to change the polarity of signals on the system with respect to even-numbered and odd-numbered DRAMs. For example, this corresponds to the case where it is desired to use the rising edge and the case where the falling edge is desired to be used in the clock signal input to the DRAM. Looking at several connected DRAMs from the MC in time order, the DRAM behind the half becomes negative logic, so the clock phase can be changed between the front half and the rear half. This can be used for time phase adjustment when the clock cycle is shorter than the propagation delay time of the main line.
[0083]
15 and 16, even when the same module is used depending on whether a signal wiring on the motherboard is an open end or a short end, the even-numbered module can be selectively made negative logic. Become. For example, by sharing the chip select signal from the MC 10-1 with the DRAMs 10-2 and 10-3, the DRAMs 10-2 and 10-3 can be exclusively selected with one signal, so that the chip select signal can be reduced. .
[0084]
In addition, since the electromagnetic field is blocked compared to the case where the far end of the main line 1-1 is an open end, the electromagnetic wave confined in the space and radiated to the free space is reduced. That is, there is an effect that electromagnetic radiation noise can be reduced.
[0085]
A fourth embodiment will be described with reference to FIG.
In this embodiment, the embodiment of FIG. 19 is applied to a differential signal. The main line 1-1 from the differential driver in the MC 10-1 matched in source impedance constitutes a ring. DRAMs 10-2 to 10-5 are connected to the main line 1-1 of the ring so as to constitute couplers C1 to C4. The differential I / O circuits in the DRAMs 10-2 and 10-4 are connected to the positive logic terminal for the couplers C1 and C3, and the negative logic terminal is connected to the couplers C2 and C4. On the other hand, in the DRAMs 10-3 and 10-5, the couplers C2 and C4 are connected to the positive logic terminal, and the couplers C1 and C3 are connected to the negative logic terminal. Moreover, the wiring length from MC10-1 of coupler C1, C2 is the same clockwise and counterclockwise, and a pulse arrives at the same time. The same applies to the couplers C3 and C4.
[0086]
The ring-shaped main line 1-1 is folded at the right end portion of FIG. 20, and pulses of the same potential with different signs, which are differential pulses from the MC 10-1, are overlapped in this portion, resulting in FIG. It behaves the same as when short-circuited. That is, in FIG. 20, the drive pulse from the positive logic side of MC10-1 propagates from the left to the right and travels in the positive polarity and reaches the folded portion. The traveling wave of the negative electrode proceeds. This is because this waveform is the same as the state in which the far end from the MC 10-1 is short-circuited.
[0087]
With this configuration, even-numbered DRAMs can be selectively set to negative logic even for differential signals.
Further, a differential line may be configured as shown in FIG.
[0088]
The main lines 1-1a and 1-1b, which are differential signal wirings from the MC 10-1 matched in source impedance, are configured by wirings having two open ends. Since a positive total reflection wave is generated at the open end, the inputs of the receivers of the DRAMs 10-3 and 10-5 are opposite to those in FIG. That is, the DRAMs 10-2 and 10-3 connected to the coupler C1 are connected to positive logic terminals, and the DRAMs 10-2 and 10-3 connected to the coupler C2 are connected to negative logic terminals. By doing in this way, it is possible to transmit all positive logic differential signals.
[0089]
Further, by combining FIG. 20 and FIG. 21, the even-numbered DRAM is selectively positive logic depending on whether the main line is configured in a ring shape or two open-ends for the same DRAM connected by bus. Appear in negative logic. In FIGS. 15 and 16, only the wiring of the motherboard is short-circuited or opened, and no other components are required. This increases the degree of freedom in system design.
[0090]
In a memory module system using a DQS (data strobe) signal for latching a DQ (data) signal, for example, a DDR-SDRAM (Double Data Rate Synchronous DRAM), there is a problem that the latency of write data is long. This will be described with reference to FIG.
[0091]
The SSTL (Stub Series Terminated Logic) interface adopted in the DDR-SDRAM has the same Hiz state as the termination voltage Vtt, and the receiver reference voltage Vref is almost the same as the termination voltage Vtt. There was a problem that the transition to the H state could not be detected.
[0092]
In FIG. 22, a command is issued and data is transmitted based on the clock CK. For example, a write command is issued in stage 1, and write data (DA0) is transmitted from stage 2. The strobe signal DQS is once dropped from the Hiz state to L in the stage 1 and the strobe signal for latching data is driven in the stage 2, and as a result, one cycle wait is included in the data signal.
[0093]
This is because the DQS cannot detect the transition from the Hiz to the L state, and the DQS transition can be identified only after the DQS changes from L to H. For this reason, a wait, which is a preamble for one stage, is included for recognition of DQS transition.
[0094]
On the other hand, when the directional coupler of the first embodiment is used, data can be issued in synchronization with the command as shown in FIG. Here, DQTx is a data signal waveform transmitted from the MC 10-1, and DQRx is a backward crosstalk induced by a directional coupler, and is a data signal waveform input to a DRAM receiver. Similarly, for the strobe, DQSTx and DQSRx are the output signal of MC and the input signal of DRAM, respectively.
[0095]
As can be seen from FIG. 23, the MC can issue a write command and data DQTx at the same time, and can also drive the strobe signal DQSTx in stage 1. That is, when DQSTx changes from Hiz to L, a pulse is generated in the DQSRx signal, and this pulse can be identified in the DRAM. As a result, the DQS does not require a preamble, and a write command and write data can be issued simultaneously. As a result, the memory write access latency can be shortened by one stage. As a result, the system performance is improved because the memory access latency is improved.
[0096]
In the case of a bus using a directional coupler using an SSTL driver, that is, when the main line and the sub-coupling wiring as shown in FIG. 2 are terminated, the amplitude of the preamble portion is compared with the amplitude of data transfer. It is half. That is, the drive amplitude changes from the HiZ state to the L state or from the HiZ state to the H state from the L state to the H state and vice versa. For this reason, the amplitude input to the receiver is halved, and the receiver sensitivity is insufficient, and it is necessary to ensure the amplitude. For this reason, when the SSTL driver is used, it is necessary to change the strobe signal from the Hiz to the L state once to ensure the signal amplitude, and as a result, the access time is extended by the memory write.
[0097]
The memory controller uses a binary signal for data transfer, and the impedance of the memory controller is the same as the characteristic impedance of the wiring on the memory controller side. That is, the HiZ state and H state when data is not transferred are set to the same potential and driven with the same impedance as the characteristic impedance of the wiring. When the data is in the L state, the L signal is driven with the same impedance as the characteristic impedance. By doing so, the reflected wave can be absorbed.
[0098]
When the signal is driven from the Hiz state to the L state and when it is driven from the H state to the L state, the signal has the same amplitude, so that the signal passing through the coupler has the same amplitude in the two transfers. This eliminates the need for a preamble because any signal transition has the same signal amplitude. Since the preamble is unnecessary, the memory access time is shortened, the bus use efficiency is increased, and the system performance is improved.
[0099]
Next, a method for increasing the signal amplitude of the memory write data will be described with reference to FIGS.
[0100]
As shown in FIG. 14, the input impedance of the DRAM also matches the impedance of the wiring. For this reason, the data signal of the memory write is inputted with a signal having the same amplitude as the signal generated by the directional coupler. By configuring this as shown in FIG. 24, the signal amplitude can be increased.
[0101]
Reference numeral 51a denotes a driver of this embodiment. The receiver 52 has the same configuration as in FIG. The driver 51a has an increased control signal (WRITE) compared to FIG. The operation is shown in the table in FIG. That is, when the WRITE signal is H, the operation is the same as in FIG. 14, but when the WRITE signal is L, both the transistors M1 and M2 become HiZ, and as a result, the input impedance of the DRAM becomes HiZ. That is, the input impedance of the DRAM driver 51a to which the L WRITE signal is input becomes HiZ, and the signal from the wiring is totally reflected. For this reason, the signal amplitude from the wiring is doubled and input to the receiver 52. For this reason, the sensitivity of the receiver 52 does not have to be higher than that of FIG. 14, and the noise margin increases, so that the noise resistance can be increased.
[0102]
As shown in FIG. 1, the DRAM having this circuit is connected one-to-one with a DRAM or a termination module having the same impedance as that of the wiring through a directional coupler. Therefore, even if the DRAM having the I / O circuit of FIG. 24 becomes HiZ and the signal from the directional coupler causes total reflection, if the WRITE signal of the other DRAM is H or the termination module is connected. This reflected wave is absorbed. For this reason, even if the driver 51a becomes HiZ, the signal on the wiring 1-2 connecting the DRAM is not disturbed and stable operation is possible.
[0103]
Next, the output timing of the WRITE signal will be described with reference to FIG.
FIG. 25 shows an example in which there is one stage available from when the WRITE command is issued until write data is output, as in FIG. The write command reaches the DRAM after the propagation delay time of the wiring after being output from the MC. This signal reaching the DRAM was denoted as COMMANDRx. In addition to the WRITE command, the DRAM can identify the DRAM to be written by a chip select signal or other control signal.
[0104]
DQTX and DQSTx are output one stage after issuing the WRITE command and reach the DRAM after the same wiring delay time. This was designated as DQRx and DQSRx. The negative logic WRITE signal is an internal signal of the DRAM, but is output L after receiving the command WRITE signal. The L period has a length approximately equal to or longer than the burst length of data. For this reason, since the input impedance of the write target DRAM is HiZ during this period, the signal amplitude is doubled only during the period of receiving the write data. For this reason, the noise margin of the receiver can be ensured and the waveform distortion is small, so that stable operation is possible.
[0105]
Next, FIG. 26 shows an embodiment in which a memory bus system using the directional coupler of the present invention is applied.
[0106]
In FIG. 26, four CPUs and a chip set 300 are interconnected by a processor bus 201. A chip set 300 including a memory controller that controls the DRAM is interconnected by a memory bus 202. Further, an I / O LSI for connecting peripheral devices such as PCI (Personal Connect Interface) and the chip set 300 are interconnected by an I / O bus 203. Further, as a graphic port, the chip set 300 and the graphic control LSI are connected via the graphic bus 204.
[0107]
These buses 201 to 204 are connected to the chip set 300. The chip set 300 manages data transmission / reception between the buses 201 to 204.
[0108]
Here, data transfer is performed using a coupler for the memory bus 202. As a result, the memory access can be performed at high speed, the throughput is improved, and the latency is shortened, so that the system performance is improved.
[0109]
In addition, the same effect can be obtained when applied to the cache memory bus 410 in the processor module 400 as shown in FIG. In this case, the coupler is configured in a processor module. For example, if a technique for mounting a large number of semiconductor elements in one package such as MCM (Multi Chip Module) is used, a processor including a cache controller and a cache memory are connected. They can be coupled by a coupler configured in the package, thereby enabling high-speed data transfer.
[0110]
A fifth embodiment will be described with reference to FIG.
In this embodiment, a 1-bit signal of a bus that is originally composed of multiple bits is extracted. In this embodiment, data transfer is performed between one MC and two DRAMs using one directional coupler, and the amount of signal generated is increased.
[0111]
In the bus of this embodiment, the MC 10-1, the DRAM 10-2, and the DRAM 10-3 are connected, and the internal impedance viewed from the pins of the MC 10-1 and the DRAM 10-3 is the same as the characteristic impedance of the line. Source impedance matching has been made. However, the input impedance of the DRAM 10-2 is HiZ. Here, of the ends of the directional coupler C1, the end of the wiring 1-2 on the MC10-1 side is connected to the DRAM 10-2, but this wiring length is extremely short. For example, the wiring length can be minimized by directly attaching the DRAM 10-2 directly below the coupler C1 of the motherboard on which the MC 10-1 is mounted.
[0112]
Note that the wiring from the other end of the coupler C1 to the end (D) of the DRAM 10-3 may have a certain length as in a module configuration, for example. However, the wiring is drawn out from the end of the sub-coupling line portion constituting the coupler of the wiring 1-2 on the DRAM 10-3 side perpendicularly to the end (B) of the main coupling line 1-1. The main coupled line is not necessarily longer or shorter than the sub coupled line.
[0113]
The waveform at the memory write operation in the case of the wiring configuration of FIG. 28 will be described with reference to FIG. In the figure, it is assumed that the wiring length from the MC 10-1 to the coupler and the wiring length from the sub coupler to the DRAM 10-3 are negligibly short.
[0114]
FIG. 29 shows the waveform of the memory write data from MC10-1. Since the waveform of (A) is a source impedance matched waveform, a voltage (V1) that is approximately half of the drive voltage continues for the period of the round-trip propagation delay time T2 of the directional coupler as in the waveform (A) of FIG. After that, the reflected wave returns and rises to (2 * V1). At the end (B) on the opposite side of the MC 10-1 of the wiring 1-1, after the delay time T2, the reflected wave is generated at the same time as the traveling wave arrives and overlaps, so the voltage is (2 * V1). .
[0115]
A backward crosstalk signal (Kb * V1) generated when a traveling wave from the end (A) to the end (B) propagates through the coupler C1 is transmitted to the end of the wiring 1-2 (C). Since this (C) end is HiZ, this rear crosstalk signal is totally reflected and doubled, so the signal voltage at (C) end is (2 * Kb * V1).
[0116]
Further, the same voltage (2 * Kb * V1) is also propagated to the end of the wiring 1-2 (D). This is the result of overlapping two rear crosstalks.
[0117]
In the first rear crosstalk, the signal generated by the traveling wave of the coupler C1 on the end (C) side is reflected by (C) of the wiring 1-2 and propagates to the end (D) side of the wiring 1-2. Signal. This propagated signal is Kb * V1. Second, the traveling wave propagating through the coupler C1 is reflected at the end of the wiring 1-1 (B), and this reflected wave is reflected to the end of the wiring 1-2 (D) by the coupler C1. Kb * V1) is generated. The phases of the two rear crosstalk signals are the same, and the signals overlap with each other in the same phase, that is, (2 * Kb * V1). Since the input impedance of the DRAM 10-3 matches the characteristic impedance of the wiring, it is absorbed without re-reflection at the end of the DRAM 10-3. This is because the signal amplitude is doubled compared to FIG.
[0118]
That is, in the operation of the memory write, since the reflection is used at the end (C) and the end (D), the signal amplitude is doubled. This means that the noise resistance of the DRAMs 10-2 and 10-3 is increased, and data transfer can be realized stably and at high speed.
[0119]
Waveforms during the memory read operation in the case of the wiring configuration of FIG. 28 will be described with reference to FIG.
FIG. 30 shows a waveform of memory read data from the DRAM 10-2. Since the driver of the DRAM 10-2 is driven with an impedance lower than the characteristic impedance of the line, the waveform of the end (C) has a substantially full amplitude (2 * V1). The driven signal is absorbed at the end (D) after a delay time T2. This is because the matching termination is performed by the source impedance matching function of the DRAM 10-3. The signal from the DRAM 10-2 that transmits the wiring 1-2 generates backward crosstalk, and the voltage generated at the end (A) is 2 * V1 * Kb. In addition, since the source impedance matching is also performed at the end (A), there is no reflection at this end.
[0120]
FIG. 31 shows a memory read data waveform from the DRAM 10-3.
The output from the DRAM 10-3 having the source impedance matching driver has an amplitude (V1) that is half of the power supply voltage, and becomes full amplitude due to the reflected wave after (2 * T2) as in FIG. The drive signal voltage traveling from the end (D) side to the end (C) side of the sub-coupled line generates a rear crosstalk voltage (V1 * Kb) on the end (B) side, but immediately reflects at the end (B). Head to end (A). Further, the signal totally reflected at the end (C) of the sub-coupled line returns to the end (D) side this time. Also at this time, the rear crosstalk signal (V1 * Kb) is generated on the end (A) side of the main coupling line. These two signals on the main coupling line have the same phase and become a double signal at the overlapping end (A). For this reason, the memory read data from the DRAM 10-3 is also (2 * V1 * Kb), and the signal amount is doubled.
[0121]
As described above, it is understood that the signal amount is (2 * V1 * Kb) for the memory read data from the DRAM 10-2 and the DRAM 10-3.
[0122]
In this way, in both the memory write and memory read operations, the data signal is (2 * V1 * Kb) and the signal amplitude is doubled in any case, so the MC 10-1, DRAM 10-2, 10-3. In the data transfer in between, the noise resistance is increased, and the data transfer can be realized stably and at high speed.
[0123]
As shown in FIGS. 32 and 33, the above memory access behavior was confirmed by simulation.
[0124]
FIG. 32 shows a data waveform of the memory write output from the MC 10-1. The coupling line has the wiring cross-sectional dimension of FIG. 7, and the wiring length of the coupler is the same as 40 mm as in FIG. In FIGS. 32 and 33, as in the previous description, the length of the lead wire from the MC 10-1 to the coupler in the wire 1-1 and the length of the wire from the sub-coupler to the DRAM 10-3 in the wire 1-2 are negligibly short. Is assumed.
[0125]
As a result of the simulation, the memory write data waveform of FIG. 32 has an end (C) and end (D) signal of about 390 mV, which is about 1.8 times the 220 mV of end K1 and end J1 of FIG. I understand that. This is because the crosstalk and the reflected wave are superimposed in the same phase as described above.
[0126]
FIG. 33 shows data waveforms at the time of memory read from the DRAM 10-2. Since the output impedance of the DRAM 10-2 connected to the end (C) is 10Ω, which is lower than the characteristic impedance of the wiring, it is driven at almost full amplitude. This is driven by the directional coupler C1 in FIG. That is, the data is propagated to the MC 10-1. The signal amplitude at this time is also about 320 mV, and it can be seen that the signal amplitude is almost the same as in FIG. Also, as can be seen from FIGS. 32 and 33, the time width of the generated signal is equal to 0. 48 ns of the round trip propagation delay time (2 * T2) of the coupler, which is the rear cross in FIGS. It is the same as the talk pulse width.
[0127]
The data transmission waveform from the DRAM 10-3 to the MC 10-1 was almost the same as that shown in FIG. This is because the load condition seen from the DRAM 10-3 is almost the same as the load condition seen from the MC 10-1. The load condition viewed from the DRAM 10-3 continues to the wiring to the coupler and the unterminated directional coupler, and the wiring condition constituting the other coupler is also a condition in which the near end is open and the far end is terminated. It is. The only difference between the load condition of the DRAM 10-3 and the load condition of the MC 10-1 is that the DRAM 10-2 is connected to the DRAM 10-3 side wiring. The input impedance of the DRAM 10-2 is HiZ, Since it can be regarded as an open end, the read data waveform from the DRAM 10-3 is almost the same as in FIG. 32, the dotted line of the waveform (A) is the output waveform from the DRAM 10-3, the waveform (B) is the waveform at the end (C) of the DRAM 10-2, and the waveform (C) is the end (B). The waveform (D) corresponds to the input waveform of MC10-1.
[0128]
As described above, the memory write data signal from MC10-1 and the read data waveform from DRAMs 10-2 and 10-3 in FIG. 28 also have an amplitude of 350 mV or more as shown in FIG. It can be seen that the signal voltage is increased.
[0129]
FIG. 34 and FIG. 35 show cross-sectional views when this is mounted.
[0130]
FIG. 34 is a view seen from the cross-sectional direction of the mother board 1 as in FIGS. 15 and 16. FIG. 34 shows that the DRAM 10-2 having the input impedance of HiZ in FIG. 28 is directly mounted on the mother board 1 and the input impedance matches the source impedance. The DRAM 10-3 is connected to the memory module 2-2 through a connector while being mounted on the memory module 2-2. A directional coupler for connecting the respective chips is configured in the mother board 1, the wiring 1-1 including the main coupling line from the MC 10-1 is on the layer m 1, and the wiring 1-2 including the sub-coupling line is on the layer x 1. Is provided. Note that the main coupling line 1-1 ends at a point opposite to the lead-out point from the sub-coupler of the line 1-2 to the memory module 2-2. As a result, the rear crosstalk and reflection are overlapped in the same phase, and the signal is amplified.
[0131]
Although it has been described that the DRAM 10-3 is terminated (source impedance matching), it is of course possible to use a method in which the input impedance is terminated to a HiZ DRAM with an external resistor. In this case, the same DRAM 10-2 and DRAM 10-3 can be used.
[0132]
FIG. 35 is different from FIG. 34 in that a termination board 2-2 ′ is inserted in the connector instead of the memory module 2-2. This is used when the memory capacity required by the system is minimally satisfied by mounting the DRAM 10-2 due to the system configuration and is shipped in this state. Then, if it is necessary to expand the memory, for example, to improve the system performance, the termination board 2-2 'in FIG. 35 is removed, and the memory module 2-2 having the DRAM 10-3 is inserted as shown in FIG. By doing so, the memory can be expanded. As described above, this embodiment can be said to be a mounting method having system expandability as shown in FIGS.
[0133]
In FIG. 34, even if the DRAM 10-2 is not installed and only the memory module 2-2 is installed, the generated signals are the same, so that data is transferred between the MC 10-1 and the DRAM 10-3. It is also possible. There is an effect that the signal amount can be doubled even when the DRAM 10-2 cannot be mounted, for example, when there are restrictions on mounting.
[0134]
FIG. 36 shows a sixth embodiment.
This is an embodiment in which the capacity of the DRAM that can be mounted is increased with respect to FIG. 28 as the fifth embodiment.
[0135]
In the bus of this embodiment, the MC 10-1 and the DRAMs 10-2 to 10-5 are connected, and the internal impedance of the MC 10-1, the DRAM 10-3, and the DRAM 10-5 as seen from the pins is the same as the characteristic impedance of the line. The source impedance is matched. The input impedance of the DRAMs 10-2 and 10-4 is HiZ. Here, one ends of the sub-coupled lines 1-2a and 1-b constituting the directional coupler C1 are connected to the DRAMs 10-2 and 10-4, respectively. For example, the DRAMs 10-2 and 10-4 can be connected directly below or directly above the coupler C1 of the motherboard on which the MC 10-1 is mounted.
[0136]
Note that the wiring from the other end of the sub-coupling wiring portion of the wiring 1-2a and 1-2b of the coupler C1 to the DRAMs 10-3 and 10-5 has a certain length as in a module configuration as shown in FIG. There may be. However, the end of the sub-coupled line on the DRAM 10-3, 10-5 side is drawn vertically from the position opposite to the end of the main coupled line, and the main coupled line is not necessarily longer or shorter than the sub-coupled line. .
[0137]
In the directional coupler C1, wirings 1-2a and 1-2b are arranged on both sides of the line 1-1 connected to the MC 10-1, but the same is applied to these wirings 1-2a and 1-2b. It is adjusted to have a backward crosstalk coupling coefficient. That is, they are arranged so as to have the same wiring width, the same wiring pitch, and the same wiring length. Since the lines 1-2a and 1-2b are configured in this way, the memory write data signal is the same in the DRAM 10-2 and DRAM 10-4 or in the DRAM 10-3 and DRAM 10-5 as shown in FIG. It becomes a waveform. That is, as described above, the signal amplitudes in the DRAMs 10-2 to 10-5 are twice as large (2 * Kb * V1) as the reflected waves are superimposed.
[0138]
Similarly, the waveform of the memory read data from the DRAM 10-2 or DRAM 10-4 is such that the directional coupler C1 has the same coupling coefficient as that of the line 1-1 connected to the MC 10-1. Since 2a and 1-2b are configured, they have the same size, and are (2 * Kb * V1) as described in FIG. Similarly, the memory read data waveform from the DRAM 10-3 or DRAM 10-5 has the same size (2 * Kb * V1) as in FIG.
[0139]
36, four DRAMs 10-2 to 10-5 can be connected to one MC 10-1, and the memory capacity can be increased compared to the fifth embodiment. There is. Of course, DRAMs 10-3 and 10-5 are mounted on the module. If the system may have a small memory capacity, it is terminated with a termination board. If expansion is required, the memory on which DRAMs 10-3 and 10-5 are mounted. It goes without saying that the system can have memory expandability by replacing it with a module.
[0140]
The seventh embodiment will be described with reference to FIG.
In the present embodiment, the memory mounting amount can be further expanded by connecting the main coupling line 1-1 in FIG. 36 via a connection means such as a MOS switch.
[0141]
Reference numerals 3-1 and 3-2 denote MOS switches, which are controlled by switching means (selector) 4 provided in the MC 10-1. The MOS switches 3-1 and 3-2 are provided in the line 1-1 connected to the MC 10-1, and the wiring 1-1 (A) between the MOS switch 3-1 and the MC 10-1 is the line 1-2 a, The directional coupler C1 is composed of 1-2b. A wiring 1-1 (B) between the MOS switch 3-2 and the MOS switch 3-2 constitutes a directional coupler C2 with the lines 1-3a and 1-3b. A wiring 1-1 (C) from the MOS switch 3-2 to the end forms a directional coupler C3 with the lines 1-4a and 1-4b. DRAMs 10-2 to 10-5 are connected to the coupler C1, DRAMs 10-6 to 10-9 are connected to the coupler C2, and DRAMs 10-10 to 10-13 are connected to the coupler C3. The connection mode of the couplers C1 to C3 and the DRAMs 10-2 to 10-13 is the same as that shown in FIG.
[0142]
When data is transferred between the MC 10-1 and one of the DRAMs 10-2 to 10-5, the MOS switch 3-1 is configured so that the lines 1-1 (A) and 1-1 (B) are disconnected. It is controlled by the switching means 4. For this reason, the signal propagating on the line 1-1 (A) is almost totally reflected at the end of the MOS switch 3-1. For this reason, the MC 10-1 and the DRAMs 10-2 to 10-5 operate in exactly the same way as in FIG.
[0143]
Next, when data is transferred between the MC 10-1 and one of the DRAMs 10-6 to 10-9, the MOS switch 3-1 is electrically connected to the lines 1-1 (A) and 1-1 (B). Thus, the MOS switch 3-2 is controlled by the switching means 4 so that the lines 1-1 (B) and 1-1 (C) are disconnected. For this reason, the signal propagating on the line 1-1 (B) is almost totally reflected at the end of the MOS switch 3-2. For this reason, the MC 10-1 and the DRAMs 10-6 to 10-9 operate in exactly the same way as in FIG. Note that the DRAMs 10-2 to 10-5 and the lines 1-2a and 1-2b are not in contact with the line 1-1 (A) and are characteristic impedances of the lines 1-1 (A) and 1-1 (B). Are the same, it does not give distortion to the signals transmitting 1-1 (A) and 1-1 (B). Of course, it is desirable that the conduction resistance of the MOS 3-1 is very small compared to the line impedance. This has the effect of suppressing waveform distortion due to impedance mismatch.
[0144]
Similarly, when data is transferred between the MC 10-1 and one of the DRAMs 10-10 to 10-13, the MOS switch 3-1 and the MOS switch 3-2 are controlled by the switching means 4 so as to be conductive. The For this reason, the signal propagating on the line 1-1 (C) is almost totally reflected at the far end. For this reason, the MC 10-1 and the DRAMs 10-9 to 10-13 operate in exactly the same way as in FIG.
[0145]
Thus, by making the MOS switches 3-1 and 3-2 nonconductive or conductive, data is selectively transferred between the MC 10-1 and one of the DRAMs 10-2 to 10-3. be able to. That is, the number of DRAMs that can be mounted in the system can be increased as compared with the case of FIG. This switching means may be shared with a signal such as a chip selector used in the DRAM.
[0146]
Whether or not all of the DRAMs 10-2 to 10-13 are to be installed is related to the requirements of the system. At first, a small number of DRAMs may be installed, and DRAMs may be added when function expansion is required. If necessary, a termination board 2-2 ′ as shown in FIG. 35 may be used.
[0147]
The eighth embodiment will be described with reference to FIG.
In FIG. 38, the directional coupler C1 includes a wiring 1-1 as in FIG. 36, and lines 1-2a and 1-2b arranged in parallel and close to the wiring 1-1 on both sides at the same interval. Further, the ends of the wirings 1-2a and 1-2b on the MC10-1 side are connected. Further, the other two ends of the wirings 1-2a and 1-2b are respectively drawn out vertically to the DRAMs 10-2 and 10-3.
[0148]
The input impedance of the DRAMs 10-2 and 10-3 differs depending on whether or not there is access to the memory. If there is a memory access, the input impedance will be HiZ, otherwise it will be in the source impedance matching state. Note that MC 10-1 is constantly in a source impedance matching state. By configuring in this way, the signal amount can be 4 times 4 * Kb * V1.
[0149]
FIG. 39 shows a simulation waveform of data at the time of memory write. The simulation conditions are the same except for the part applied to the wiring. The mechanism is shown below. This figure shows waveforms of data transfer from the MC 10-1 to the DRAM 10-2.
[0150]
The output from the end (A) of the MC 10-1 is stepped because its impedance is the same as the characteristic impedance of the wiring. A signal propagating through the wiring 1-1 at this time is assumed to be V1. This signal generates backward crosstalk in the wirings 1-2a and 1-2b, and the magnitude thereof is Kb * V1. The backward crosstalk generated in the wiring 1-2b propagates to the end (D) through the wiring 1-2a. The signal propagating through the wiring 1-1 is totally reflected at the end (B), and this reflected wave generates back crosstalk again at the wirings 1-2a and 1-2b. The magnitude of the generated rear crosstalk is (Kb * V1), and is superimposed in the same phase as the rear crosstalk generated in the wiring 1-2b by the traveling wave of the wiring 1-1. Therefore, the amplitude of the signal traveling through the wiring 1-2a to the DRAM 10-2 is (2 * Kb * V1). Further, when reaching the end (D) of the DRAM 10-2, the input impedance of the DRAM 10-2 is HiZ, so that it is totally reflected again, resulting in a signal waveform of (4 * Kb * V1). In FIG. 39, it is about 640 mV. The time width of this signal wave is 0.448 ns round-trip propagation delay time of the coupler C1. That is, it can be seen that only the signal amount is increased.
[0151]
Similarly, data transfer from the MC 10-1 to the DRAM 10-3 has the same waveform as FIG. 39 by matching the impedance of the DRAM 10-2 with the characteristic impedance of the wiring and setting the input impedance of the DRAM 10-3 to HiZ. The write data can be transferred with a signal of 4 * Kb * V1).
[0152]
Next, FIG. 40 shows a simulation waveform of memory read data from the DRAM 10-2 to the MC 10-1.
The output impedance of the DRAM 10-2 is lower (10Ω) than the characteristic impedance of the line. Therefore, the drive waveform (D) has a full amplitude of approximately (2 * V1), and with this drive signal, backward crosstalk (2 * Kb * V1) is generated in the end (B) direction on the line 1-1. . Since this is totally reflected at the end (B), this rear crosstalk propagates in the direction of the end (A) as it is. The drive waveform from the DRAM 10-2 is transmitted from the wiring 1-2a to the wiring 1-2b, but the drive waveform transmitted through the wiring 1-2b has a backward crosstalk having an amplitude of (2 * Kb * V1) to the wiring 1-1. Generate. Since this rear crosstalk and the rear crosstalk reflected at the previous end (B) overlap with each other in the same phase, the signal becomes (4 * Kb * V1) and is input to the MC 10-1 and terminated. In FIG. 40, it can be seen that a voltage of approximately 580 mV is input to the end (A). The signal waveform has the same time width as that in FIG.
[0153]
FIG. 41 shows input impedances of the MC 10-1, the DRAM 10-2, and 10-3 for each memory access. MC10-1 is in a source impedance matching state during both memory write and read, and this is indicated by RTT. In the case of a memory write, the target DRAM is HiZ, and the non-target DRAM is in the RTT state. In the case of memory read, the output impedance of the DRAM that outputs the memory read data is low (LOW), and the impedance of the non-target DRAM is RTT. It can be recognized by the chip select (CS) signal whether the DRAMs 10-2 and 10-3 are objects of data transfer.
[0154]
By configuring and operating in this manner, the signal can be increased to about 4 times (4 * Kb * V1). That is, there is an effect that a sufficient signal amount can be obtained even if the drive signal has a small amplitude. Naturally, the number of DRAMs connected to the bus can be increased by configuring MOS switches as shown in FIG. 38 in multiple stages.
[0155]
The ninth embodiment will be described with reference to FIG.
FIG. 42 is a block diagram of an I / O circuit having a DRAM and MC 10-1 driver and receiver or termination means. 53 is a termination means. Reference numeral 51-1 denotes a driver. 52-1 is a receiver having hysteresis characteristics. Reference numeral 52-2 denotes a receiver having no hysteresis characteristic. Reference numeral 73 denotes switching means for switching between the receiver 52-1 and the receiver 52-2. Reference numeral 72 denotes bonding switching means connected when manufacturing a semiconductor element including the I / O circuit, and the connection can be changed to either VDD or GND at the time of manufacturing. In the figure, VDD, that is, a HIGH logic signal is given to the switching means 73. Similarly, 71 can switch whether the termination means 53 is turned ON or OFF at the time of manufacture.
[0156]
For this reason, for example, the DRAM 10-2 and the DRAM 10-3 in FIG. 28 have different input impedances but are manufactured with the same semiconductor mask, and have two functions with one mask by switching the bonding switching means 71 at the time of manufacture. Can be made. Similarly, the manufacturing cost can be reduced by switching a receiver 52-2 such as SSTL which is a conventional DRAM interface and a receiver 52-1 having hysteresis characteristics suitable for a directional coupler at the time of manufacturing using the same semiconductor mask. it can.
[0157]
A tenth embodiment will be described with reference to FIG.
This embodiment is an example in which a part composed of a plurality of chips is mounted on one multichip module like the processor module 400 of FIG. 27, and the previous embodiment, for example, the wiring system of FIG. 28 is applied. The processor (CPU) 31 and the cache memory 32 provided in the multichip module 400 can perform data transfer between them via the wiring system shown in FIG. 28, that is, the directional coupler C1. Therefore, data transfer between the CPU 31 and the cache memory 32 can be performed at high speed. Of course, the multichip module can be handled as one element whose performance is improved by adding not only the function of the CPU 31 but also the function of the cache memory 32. Further, since it is not necessary to provide data transfer between the CPU 31 and the cache memory 32 to the printed board on which the CPU 31 is mounted, there is an effect that the configuration of the printed board is simplified.
[0158]
【The invention's effect】
By making the far end of the main line connected to the MC an open end or a short-circuit end, total reflection occurs, and this reflected wave and traveling wave are used to generate backward crosstalk at both ends of the directional coupler. Data can be transferred between the DRAM and MC connected to both ends of the coupler. By sharing this directional coupler by two DRAMs, the pitch between DRAM modules can be halved.
[0159]
Further, by folding back the opened or short-circuited main line and forming a directional coupler for the folded main line, the interval between the DRAM modules can be reduced to 1/4 of the wiring length of the coupler of the directional coupler. .
[0160]
In addition, since the connected DRAM can be selectively set to positive logic or negative logic depending on whether it is open or short-circuited with respect to the signal of the DRAM, the signal is controlled exclusively like a chip select signal. There is an effect that the number of can be reduced.
[0161]
The memory controller uses a binary signal for data transfer, and the impedance of the memory controller is the same as the characteristic impedance of the wiring on the memory controller side. That is, the HiZ state and H state when data is not transferred are set to the same potential and driven with the same impedance as the characteristic impedance of the wiring. When the data is in the L state, the L signal is driven with the same impedance as the characteristic impedance. By doing so, the reflected wave can be absorbed.
[0162]
When the signal is driven from the Hiz state to the L state and when the signal is driven from the H state to the L state, the signal has the same amplitude, so that the signal passing through the coupler has the same amplitude in the two transfers. This eliminates the need for a preamble because the signal amplitude is the same for any signal transition. Since the preamble is unnecessary, the memory access time is shortened, the bus use efficiency is increased, and the system performance is improved.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a first embodiment;
FIG. 2 is a conventional method.
FIG. 3 is an explanatory diagram of the first embodiment.
FIG. 4 is a write timing from the MC to the DRAM of the first embodiment.
FIG. 5 is a read timing from the DRAM 10-1 of the first embodiment to the MC.
FIG. 6 is a read timing from the DRAM 10-2 of the first embodiment to the MC.
FIG. 7 shows the configuration of the coupler of the first embodiment.
FIG. 8 is an equivalent circuit for writing data from MC to DRAM according to the first embodiment;
FIG. 9 is a write data waveform from MC to DRAM of the first embodiment;
FIG. 10 is a simulation equivalent circuit from the DRAM 10-1 to the MC according to the first embodiment;
FIG. 11 shows a read data waveform from the DRAM 10-1 to the MC according to the first embodiment;
FIG. 12 shows a read data waveform from the DRAM 10-2 to the MC according to the first embodiment;
FIG. 13 is an MC I / O circuit according to the first embodiment;
FIG. 14 is an I / O circuit of the DRAM of the first embodiment.
FIG. 15 is a configuration diagram (cross-sectional view) of a module type substrate according to the first embodiment;
FIG. 16 is a configuration diagram (cross-sectional view) of a module type substrate according to a second embodiment;
FIG. 17 is a cross-sectional view of a substrate according to the second embodiment.
FIG. 18 is a cross-sectional view of a substrate according to the second embodiment.
FIG. 19 is a diagram for explaining a third embodiment;
FIG. 20 shows a ring-type differential wiring system to which the third embodiment is applied.
FIG. 21 shows an open type differential wiring system to which the third embodiment is applied.
FIG. 22 is a timing diagram of memory write in a conventional DDR-SDRAM.
FIG. 23 is a timing diagram of memory write using the first embodiment.
FIG. 24 shows a DRAM interface that can double the input amplitude.
25 is a timing diagram of memory write to the DRAM of FIG. 24. FIG.
FIG. 26 is a system having a memory bus using a main line having an open end and a short-circuit end.
FIG. 27 is a system having a cache memory bus using a main line having an open end and a short-circuit end.
FIG. 28 is a diagram for explaining a fifth embodiment;
FIG. 29 is a diagram showing write timings from MC 10-1 to DRAMs 10-2 and 10-3 according to the fifth embodiment;
FIG. 30 is a diagram showing read timing from the DRAM 10-2 to the MC according to the fifth embodiment;
FIG. 31 is a diagram showing a read timing from the DRAM 10-3 to the MC according to the fifth embodiment;
FIG. 32 is a diagram showing write data waveforms from MC 10-1 to DRAMs 10-2 and 10-3 according to the fifth embodiment;
FIG. 33 is a diagram showing a read data waveform from the DRAM 10-2 to the MC according to the fifth embodiment;
FIG. 34 is a diagram showing a cross-sectional view of the substrate mounting of the fifth embodiment.
FIG. 35 is a cross-sectional view of a substrate mounted in the fifth embodiment (case in which a termination board is mounted).
FIG. 36 is a diagram for explaining a sixth embodiment;
FIG. 37 is a diagram for explaining a seventh embodiment;
FIG. 38 is a diagram for explaining an eighth embodiment;
FIG. 39 shows a simulation waveform (memory write) of the eighth embodiment.
FIG. 40 shows a simulation waveform (memory read) of the eighth embodiment.
FIG. 41 is a diagram showing input impedances of MC10-1 and DRAMs 10-2 and 10-3 according to the eighth embodiment;
FIG. 42 is a diagram for explaining a ninth embodiment (bonding option).
FIG. 43 is a diagram for explaining a tenth embodiment (a diagram in which a directional coupler is applied to a multi-chip module).
[Explanation of symbols]
1 ... Printed circuit board (motherboard)
1-1 ... Main line
1-2 to 1-5 ... Wiring
2-1 to 2-9 ······································ each module board on which semiconductor elements for data transfer are mounted
2-a to 2-d ... Memory subsystem with many memory modules
51, 51 ', 51a ... Driver
10-1 ... Memory controller (part)
10-2 to 10-9... Semiconductor elements that perform data transfer (memory)
30 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Processor (CPU)
40 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Graphic part
50 ... I / O section
60, 61 ... Directional coupling tip
201 ... Processor bus
202 ... Memory bus
203 ... I / O bus
204 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Graphic bus
300 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Chipset
400 ... Processor module
410 ..... Cache memory bus
MC ... Memory controller
m1, m2 ..... Wiring layer in board 1 (main line)
x1, x2 ..... Wiring layer (crosstalk) in substrate 1
C1-C4 ... Directional coupler
Rtt ............ Terminal resistance
Vtt ......... Termination voltage
rs ... Equivalent impedance of driver
L1 to L7 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Wiring
vpulse ………… Driver pulse source
s1, s6, k1, k4, j1, j4... simulation nodes

Claims (8)

A bus system for transferring data between a bus master connected to a bus system for transferring data and a plurality of bus slaves,
A main line for transmitting data between the bus master and the bus slave and a main line drawn from the bus master are arranged in a non-contact and substantially parallel to the main line to form a directional coupler. Connect the bus slaves to both ends of each sub-coupling wiring, including the coupling wiring,
An end of the main line to which the bus master is not connected is terminated so as to cause reflection at the end, and a traveling wave of the main line and a reflected wave from the end are used to connect both ends of the sub-coupling wiring. bus system and performing data transfer in both directions at the inter-connected the bus slave and said bus master. The bus system according to claim 1,
When the end of the main line that is not connected to the bus master is opened, positive total reflection is generated at the end, and the traveling wave of the main line and the reflected wave from the end are used to said bus slave connected to both ends, the bus system and performing at between the bus master data transfer in both directions. The bus system according to claim 1,
By short-circuiting the end of the main line that is not connected to the bus master to the ground or the power source, negative total reflection is generated, and the positive traveling wave of the main line and the negative reflected wave from the shorted end are generated. bus system and the bus slave connected to both ends of the sub coupling line, and performing data transfer in both directions at between the bus master using.   The bus master includes a bus driver that is connected to the main line and transmits data to the main line, and the output impedance of the bus driver is kept equal to the characteristic impedance of the main line connected to the bus driver, and is LOW 2. The bus system according to claim 1, wherein a LOW voltage is output when data is output, a HIGH voltage is output when HIGH data is output, and a HIGH voltage is output when data is not output. The bus system according to claim 1, wherein the plurality of bus slaves are memories. The bus system according to claim 1,
The main line drawn from the bus master is folded at the center, and is drawn from the bus slave to the main line from the bus master to the wiring part from the bus master to the turning point, and to the wiring part after the turning point. A bus system, wherein at least a part of the wiring forms a directional coupler alternately and continuously. A memory system including a node controller that selectively controls access to a plurality of types of memory access node groups, and a plurality of memories for executing at least one of data storage and data reading for processing by the nodes And an information processing apparatus including a bus system using a directional coupler that transfers data between the node controller and the memory system,
The bus system has a main line having one end connected to the node controller, and is close to a predetermined range in a non-contact manner with respect to the main line, and is arranged substantially in parallel to form a directional coupler with the main line. Including multiple sub-coupled wires,
At least one end of the sub-coupled wiring is connected to one of the plurality of memories, and the other end is connected to another memory of the plurality of memories;
The other end of the main line. An information processing apparatus that is terminated so that a signal is reflected at the other end, and performs bidirectional data transfer between the node controller and the memory system using a signal traveling wave of the main line and a reflected wave from the other end. A node for controlling the secondary cache memory access of the processor, a plurality of secondary cache memory groups for executing at least one of storing and reading data for processing by the processor, the node and the secondary A processor module including a bus system using a directional coupler for transferring data between cache memories,
The bus system has a main line having one end connected to the node, and is close to a predetermined range in a non-contact manner with respect to the main line, and is arranged substantially in parallel to form a directional coupler with the main line. A plurality of sub-coupled wires,
One end of the sub-coupled wiring is connected to one of the plurality of secondary cache memories, and the other end is connected to another secondary cache memory among the plurality of secondary cache memories,
The other end of the main line is terminated so that a signal is reflected at the other end, and a signal traveling wave of the main line and a reflected wave from the other end are used to connect the node and the secondary cache memory group. A processor module that performs bidirectional data transfer.

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