JP4313168B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having an upright structure and a method for manufacturing the same.

  A micro optical bench having an upright structure is realized by MEMS (micro electro mechanical system) technology using silicon. Using this MEMS technology, for example, it is reported that a resonant micro scanner for a laser scanning display, a movable micro reflector, a scanning micro mirror for an external resonator of a semiconductor laser, and the like are produced.

  In this conventional MEMS technology, a part of the stacked semiconductor layers is peeled off by etching, and then the peeled part is slid to stand up and joined by a hinge to form an upright structure. Using this standing structure, a mirror standing at a predetermined angle is formed on the substrate. Such mirrors are operated by a comb driver or sliding mechanism.

  However, when an upright structure is made of a semiconductor using conventional MEMS technology, wear occurs when the peeled semiconductor layer is slid. In addition, it is difficult to accurately slide the semiconductor layer to a predetermined position. For this reason, it is difficult to accurately control the angle and position of each member constituting the standing structure, and the workability is poor.

On the other hand, the present inventors have proposed a method of manufacturing a semiconductor device having an upright structure using a stacked structure of a plurality of semiconductor layers having different lattice constants (see Patent Document 1).
JP 2001-260092 A

  According to the semiconductor device and the manufacturing method thereof, the angle and position of each member constituting the standing structure can be accurately controlled.

  Therefore, it is desired to easily manufacture a semiconductor device applicable to various devices such as an optical scanner and an actuator using this method. In particular, it is desirable to easily produce a structure in which a pair of parts can be translated from each other.

  An object of the present invention is to provide a semiconductor device that has a structure in which a pair of parts can move in parallel with each other, can be easily and accurately manufactured, and can be miniaturized, and a method for manufacturing the same.

A semiconductor device according to a first invention includes a substrate and a laminated structure provided on the substrate, and the laminated structure includes a first layer, a second layer, and a third layer in order, and is linear. A first region and a second region adjacent to each other via a first boundary portion, and the second region is further divided into a plurality of regions via a plurality of linear second boundary portions, the second layer, different look including a plurality of semiconductor layers having a lattice constant, the first region and on the second respectively on the regions of the first and second opposing electrodes of the laminated structure are provided, the first the third layer in the peripheral portion surrounding the second region with the exception of the boundary portion, the portion of the second layer and the first layer are removed, portions of the first layer in the second region is selectively removed As a result, the portions of the second layer and the third layer in the second region are separated from the substrate and are caused by the second layer. By the distortion, portions of the second layer in the first boundary portion is folded in a valley shape, by the portion of the second layer in the plurality of the second boundary portion is folded in a valley shape or a mountain shape , in which the first opposing electrode and the second opposing electrode is movably opposed parallel.

In the semiconductor device according to the present invention, the third layer in the peripheral portion surrounding the second region with the exception of the first boundary, a portion of the second layer and the first layer is removed and a second region The portion of the first layer at is selectively removed. Thereby, the portions of the second layer and the third layer in the second region are separated from the substrate. In addition, due to the strain caused by the second layer , the portion of the second layer in the first boundary portion is bent into a valley shape, and the portion of the second layer in the plurality of second boundary portions is valley-shaped or It is bent in a mountain shape. Thereby, the first counter electrode and the second counter electrode face each other so as to be movable in parallel.

  In this case, an electrostatic force acts between the first counter electrode and the second counter electrode by applying a voltage between the first counter electrode and the second counter electrode. Thereby, the first counter electrode and the second counter electrode can be moved in parallel, and each part of the second region can be moved.

In addition, the first boundary portion and the second layer portion in the plurality of second boundary portions are valley-shaped or ridged so as to relieve strain caused by the difference in lattice constant between the plurality of semiconductor layers in the second layer. Therefore, it is possible to easily and accurately manufacture a structure in which the first counter electrode and the second counter electrode can be translated without requiring manual assembly or a complicated assembly mechanism. In addition, the semiconductor device can be miniaturized.

The first boundary portion and the plurality of second boundary portions are provided substantially parallel to each other, and the first counter electrode and the second counter electrode are located with respect to the first boundary portion and the plurality of second boundary portions. And may be provided so as to be movable in a substantially vertical direction.

In this case, a portion of the second layer in the first boundary portion and the plurality of second boundary portions provided substantially in parallel with each other is bent into a valley shape or a mountain shape, so that the first counter electrode and The second counter electrode can be translated in a direction substantially perpendicular to the first boundary portion and the plurality of second boundary portions . Thereby, each part of the second region can be moved linearly.

At least one of the plurality of second boundary portions is provided substantially perpendicular to the first boundary portion , and a part of the second region stands substantially perpendicular to the substrate, and the second boundary portion The counter electrode may be provided so as to be rotatable in a circumferential direction around an axis substantially perpendicular to the substrate and to be movable in parallel with the first counter electrode.

In this case, at least one of the plurality of second boundary portions is provided substantially perpendicular to the first boundary portion , so that a part of the second region stands substantially perpendicular to the substrate. . As a result, the second counter electrode is rotated in the circumferential direction about an axis substantially perpendicular to the substrate and translated with respect to the first counter electrode, so that each part of the second region is circular. It becomes possible to move along the circumferential direction.

By removing at least the portion of the third layer in the first boundary portion and the plurality of second boundary portions , the portion of the second layer in the first boundary portion is bent into a valley shape, and the plurality of second layers The portion of the second layer at the boundary between the two may be bent into a valley shape or a mountain shape.

In this case, when the portion of the third layer in the first boundary portion and the plurality of second boundary portions is removed, the first, second, and third semiconductor layers in the second layer The second layer is bent in a valley shape at the second boundary portion so as to relieve the strain caused by the difference between the second and third lattice constants, and a plurality of second boundary portions The portion of the second layer in is bent into a valley shape or a mountain shape.

The second layer includes a first semiconductor layer having a first lattice constant, and a second semiconductor layer having a second lattice constant smaller than the first lattice constant, the first boundary portion and portion of the third layer may be removed at the first boundary portion and a plurality of second boundary portion as part of the second layer in the plurality of the second boundary portion is folded in a valley shape .

In this case, the first lattice constant of the first semiconductor layer and the second lattice constant of the second semiconductor layer are removed by removing the portion of the third layer in the first boundary portion and the plurality of second boundary portions. portion of the second layer in the first boundary portion and a plurality of second boundary portion is folded in a valley shape so as to relieve the strain caused by the difference between the lattice constant.

The second layer has a first semiconductor layer having a first lattice constant, a second semiconductor layer having a second lattice constant smaller than the first lattice constant, and larger than the second lattice constant. A third semiconductor layer having a third lattice constant, and a portion of the second layer in at least one second boundary portion among the plurality of second boundary portions is bent in a mountain shape a portion of the third layer is removed in at least one second boundary, the portion of the second layer in the second boundary portion of the other of the first boundary portion and a plurality of second boundary valleys The third layer portion and the third semiconductor layer portion in the first boundary portion and the other second boundary portion may be removed so as to be bent in a shape.

In this case, the difference between the first, second, and third lattice constants of the first, second, and third semiconductor layers is removed by removing the portion of the third layer at the at least one second boundary portion. portion of the second layer is folded in a mountain shape in at least one of the second boundary portion so as to relieve the strain caused by the. Further, by the portion and the portion of the third semiconductor layer of the third layer in the second boundary portion of the other of the first boundary portion and a plurality of second boundary portion is removed, the first semiconductor the second layer in the first lattice constant and a first boundary portion and the other of the second boundary portion so as to relieve the strain caused by the difference between the second lattice constant of the second semiconductor layer of the layer The part is bent into a valley shape.

According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device , comprising: forming a stacked structure including a first layer, a second layer, and a third layer in order on a substrate; A first region and a second region adjacent to each other via one boundary portion, and the second region is further divided into a plurality of regions via a plurality of linear second boundary portions; layer comprises the steps of viewing including a plurality of semiconductor layers, providing a first region and on the second respectively on the regions of the first and second opposing electrodes of multilayer structures having different lattice constants, a first boundary the third layer in the peripheral portion surrounding the second region with the exception of parts, removing the portion of the second layer and the first layer, selectively a portion of the first layer in the second region It is separated by removing a portion of the second layer and the third layer in the second region from the substrate , By the distortion caused by the second layer, a portion of the second layer in the first boundary portion is folded in a valley shape, trough or mountain portions of the second layer at a plurality of second boundary by bent Jo, in which further comprising a step of opposing the first opposing electrode and the second opposing electrode movably parallel.

In the method of manufacturing a semiconductor device according to the present invention, the third layer in the peripheral portion surrounding the second region with the exception of the first boundary, a portion of the second layer and the first layer are removed, the The portion of the first layer in the region 2 is selectively removed. Thereby, the portions of the second layer and the third layer in the second region are separated from the substrate. In addition, due to the strain caused by the second layer , the portion of the second layer in the first boundary portion is bent into a valley shape, and the portion of the second layer in the plurality of second boundary portions is valley-shaped or It is bent in a mountain shape. Thereby, the first counter electrode and the second counter electrode face each other so as to be movable in parallel.

  In this case, an electrostatic force acts between the first counter electrode and the second counter electrode by applying a voltage between the first counter electrode and the second counter electrode. Thereby, the first counter electrode and the second counter electrode can be moved in parallel, and each part of the second region can be moved.

In addition, the first boundary portion and the second layer portion in the plurality of second boundary portions are valley-shaped or ridged so as to relieve strain caused by the difference in lattice constant between the plurality of semiconductor layers in the second layer. Therefore, it is possible to easily and accurately manufacture a structure in which the first counter electrode and the second counter electrode can be translated without requiring manual assembly or a complicated assembly mechanism. In addition, the semiconductor device can be miniaturized.

  According to the present invention, it is possible to move the first counter electrode and the second counter electrode in parallel to move each part of the second region. In addition, it is possible to easily and accurately manufacture a structure in which the first counter electrode and the second counter electrode can be translated without requiring manual assembly or a complicated assembly mechanism. Miniaturization is possible.

  FIGS. 1A and 1B are schematic cross-sectional views for explaining the configuration and operation of the semiconductor device according to the first embodiment of the present invention.

  In FIG. 1, a rectangular plate 510 is connected to a plate 500 on the substrate 1 via a hinge 310, a rectangular plate 520 is connected to the plate 510 via a hinge 320, and a rectangular shape is connected to the plate 520 via a hinge 330. A plate 530 is connected.

  A rectangular electrostatic plate 222 is provided on the plate 500, and a rectangular electrostatic plate 122 is provided on the plate 530.

  The hinges 310, 320, and 330 are bent in a valley shape. As a result, the plate 530 and the plate 500 face each other, and the electrostatic plate 122 and the electrostatic plate 222 face each other via the plate 530.

  Usually, as shown to Fig.1 (a), it sets so that the plate 530 and the plate 500 may partially oppose. Thereby, the electrostatic plate 122 and the electrostatic plate 222 partially face each other. As will be described later, when a voltage is applied between the electrostatic plate 122 and the electrostatic plate 222, an electrostatic force acts between the electrostatic plate 122 and the electrostatic plate 222. As a result, as shown in FIG. 1B, the plate 530 is translated with respect to the plate 500 in the direction of the arrow so that the electrostatic plate 122 and the electrostatic plate 222 face each other as a whole.

  2 to 6 are process diagrams showing a method of manufacturing the semiconductor device 100 of FIG. 1, wherein (a) is a schematic plan view and (b) is a schematic cross-sectional view.

  First, as shown in FIG. 2, on a substrate 1 made of GaAs, a buffer layer 2 made of GaAs, a sacrificial layer 3 made of AlGaAs, a strain layer 4 and a component layer (component layer). 5 are grown epitaxially in order. These buffer layer 2, sacrificial layer 3, strained layer 4 and component layer 5 are formed by MBE (molecular beam epitaxial growth), MOCVD (metal organic chemical vapor deposition), CVD (chemical vapor deposition). Method) or the like.

  The strained layer 4 includes a first InGaAs layer 41a having a thickness of several nm to several tens of nm, a GaAs layer 42 having a thickness of several nm to several tens of nm, and a second InGaAs layer 41b having a thickness of several nm to several tens of nm. Composed. In the present embodiment, the lattice constants of the first and second InGaAs layers 41 a and 41 b are larger than the lattice constant of the GaAs layer 42. Therefore, strain due to the difference in lattice constant occurs in the strained layer 4. The function of the strained layer 4 will be described later.

  The component layer 5 is composed of a distributed reflective film (hereinafter referred to as a DBR film). The DBR film has a stacked structure in which a plurality of AlGaAs layers and a plurality of GaAs layers are alternately stacked. The period of the AlGaAs layer and the GaAs layer is, for example, 4 to 20.

  The component layer 5 may be configured by alternately laminating aluminum oxide layers and AlGaAs layers obtained by oxidizing AlAs. Further, the component layer 5 may be made of a GaAs plate.

An etching stop layer made of, for example, Al _0.58 Ga _0.42 As having a thickness of 150 nm may be provided between the strain layer 4 and the component layer 5. Further, a strain compensation layer (strain compensation layer) made of InGaAs having a thickness of 10 nm and a cap layer made of GaAs having a thickness of 10 nm, for example, may be provided on the component layer 5. The strain compensation layer is provided in order to prevent deformation of the component layer 5 peeled off in a later step. The cap layer is provided to prevent evaporation of In in InGaAs during the manufacturing process.

  Next, as shown in FIG. 3, the component layer 5 and the second InGaAs layer 41b are removed by photolithography and etching, and valley grooves 21, 22, and 23 that define hinges 310, 320, and 330 described later are formed. They are formed in parallel with each other at intervals. As the etching, a wet etching method or a dry etching method can be used.

  Next, as shown in FIG. 4, wiring layers 121 and 221 made of metal films are formed on the component layer 5. Further, electrode pads 120 and 220 and electrostatic plates 122 and 222 made of a metal film are formed on the component layer 5. The electrode pad 120 and the electrostatic plate 122 are electrically connected by the wiring layer 121, and the electrode pad 220 and the electrostatic plate 222 are electrically connected by the wiring layer 221.

  Since the wiring layer 121 intersects hinges 310, 320, and 330 described later, the wiring layer 121 has a smaller thickness than the electrode pads 120 and 220 and the electrostatic plates 122 and 222.

  In the semiconductor device 100 of the present embodiment, a voltage is applied between the electrode pads 120 and 220 in order to generate an electrostatic force on the electrostatic plates 122 and 222, but no current flows through the wiring layers 121 and 221. Therefore, by reducing the thickness of the wiring layers 121 and 221, the hinge can be bent and the wiring layers 121 and 221 can be prevented from being cut due to the bending of the hinge. The electrode pads 120 and 220 preferably have a certain large thickness in order to ensure wire bonding.

  For example, the wiring layers 121 and 221 have a laminated structure of 4 nm thick Ti (titanium) and 40 nm thick Au (gold). The electrode pads 120 and 220 and the electrostatic plates 122 and 222 have a laminated structure of Ti having a thickness of 4 nm and Au having a thickness of 200 nm. Therefore, the deposition process of the thin wiring layers 121 and 221 is performed separately from the deposition process of the thick electrode pads 120 and 220 and the electrostatic plates 122 and 222.

  Next, as shown in FIG. 5, the region between the valley fold groove 21 and the valley fold groove 22 excluding the valley fold groove 21, the region between the valley fold groove 22 and the valley fold groove 23, and the electrostatic plate The component layer 5, the strained layer 4, and the sacrificial layer 3 are removed by photolithography and etching so as to surround the region including the region 122, thereby forming the isolation groove 11. Thereby, the component layer 5 surrounded by the separation groove 11 is separated from the surrounding component layer 5. Also in this case, a wet etching method or a dry etching method is used as the etching.

  Thereafter, as shown in FIG. 6, the sacrificial layer 3 under the strained layer 4 in the region surrounded by the separation groove 11 is selectively etched by a wet etching method. As a result, the strained layer 4 becomes the hinges 310, 320, 330 as the valley fold grooves 21, so as to relieve strain caused by the difference in lattice constant between the first InGaAs layer 41a and the GaAs layer 42 constituting the strained layer 4. It curves in a valley shape below 22 and 23. Thereby, the component layer 5 is bent into a valley shape at the valley fold grooves 21, 22, and 23.

  Here, a method of mountain-folding and valley-folding the component layer 5 will be described. FIG. 7 is a schematic cross-sectional view showing the strained layer 4 and the component layer 5, wherein (a) shows an unfolded state, (b) shows a mountain-folded state, and (c) shows a valley fold. Indicates the state that has been performed. The mountain fold of the component layer 5 is used when manufacturing the semiconductor device according to the second embodiment.

  As shown in FIG. 7A, the strained layer 4 has a structure in which a GaAs layer 42 is sandwiched between a first InGaAs layer 41a and a second InGaAs layer 41b. The second InGaAs layer 41b has a larger thickness than the first InGaAs layer 41a. The component layer 5 is formed on the second InGaAs layer 41b.

  In this case, since the first InGaAs layer 41a and the second InGaAs layer 41b have a larger lattice constant than the GaAs layer 42, the first InGaAs layer 41a acts to bend the GaAs layer 42 upward, The second InGaAs layer 41b acts to bend the GaAs layer 42 downward. In this state, since the component layer 5 is formed on the second InGaAs layer 41b, the strained layer 4 is not curved.

  As shown in FIG. 7B, when the component layer 5 is etched until the second InGaAs layer 41b is exposed, the thickness of the first InGaAs layer 41a is smaller than the thickness of the second InGaAs layer 41b. The second InGaAs layer 41b acts to bend the GaAs layer 42 downward. Thereby, the component layer 5 is bent in a mountain shape at the etched portion.

  As shown in FIG. 7C, when the component layer 5 and the second InGaAs layer 41b are etched until the GaAs layer 42 is exposed, the first InGaAs layer 41a acts to bend the GaAs layer 42 upward. To do. Thereby, the component layer 5 is bent into a valley shape at the etched portion.

  Thus, by using the strained layer 4 and adjusting the etching depth, the component layer 5 can be bent into a valley shape and a mountain shape.

  In this case, by selecting optimally the thickness of the first and second InGaAs layers 41a and 41b, the thickness of the GaAs layer 42, and the In composition ratio in the first and second InGaAs layers 41a and 41b, Layer 5 can be folded at a desired angle.

For example, the thickness of the first InGaAs layer 41a is 10 nm, and the thickness of the GaAs layer 42 is 10 nm. Further, when the In composition ratio X in the composition In _x Ga _1-x As of the first InGaAs layer 41a is 0.2, the strained layer 4 is bent vertically.

  Note that by changing the In composition ratio in the first InGaAs layer 41a, the difference in lattice constant between InGaAs and GaAs can be changed to about 7%.

  When the thickness t1 of the first InGaAs layer 41a is equal to the thickness t2 of the GaAs layer 42, the thickness t1 of the first InGaAs layer 41a, the thickness t2 of the GaAs layer 42, and the first InGaAs layer 41a There is the following relationship between the In composition ratio X and the radius of curvature R of the strained layer 4.

R = (a / Δa) · {(t1 + t2) / 2}
Here, a is a lattice constant of GaAs and is 5.6533 Å. Δa is the difference between the lattice constant of In _X Ga _{1 -X} As and the lattice constant of GaAs. The lattice constant of In _0.2 Ga _0.8 As is 5.7343.

  As described above, the semiconductor device 100 of FIG. 1 in which the plate 530 and the plate 500 are opposed to each other so as to be movable in parallel is easily and accurately manufactured.

  In the semiconductor device 100 of FIG. 1, the component layer 5 is bent in a valley shape and is not bent in a mountain shape. Therefore, the second InGaAs layer 41 b may not be provided.

  FIG. 8 is a diagram for explaining the operating principle of the semiconductor device 100 of FIG. As shown in FIG. 8A, in the initial state, the electrostatic plate 122 and the electrostatic plate 222 face each other in a partially overlapping state. When a voltage is applied between the electrostatic plate 122 and the electrostatic plate 222 in this state, an electrostatic force acts between the electrostatic plate 122 and the electrostatic plate 222 as indicated by an arrow F. In this case, the electrostatic plate 122 moves in parallel with respect to the electrostatic plate 222 as indicated by an arrow X by the electrostatic force acting between the end portion of the electrostatic plate 122 and the end portion of the electrostatic plate 222. As shown in FIG. 8B, the electrostatic plate 122 completely overlaps the electrostatic plate 222.

  When the voltage applied between the electrostatic plate 122 and the electrostatic plate 222 is reduced or set to 0, the electrostatic plate 122 moves relative to the electrostatic plate 222 by the elastic force of the hinges 310, 320, and 330 in FIG. And move back in the direction opposite to the arrow X to return to the state shown in FIG.

  In this way, by changing the voltage applied between the electrostatic plate 122 and the electrostatic plate 222, the electrostatic plate 122 and the electrostatic plate 222 are linearly translated from each other, and the plate 530 of FIG. Can be translated relative to the plate 500.

  FIG. 9 is a schematic cross-sectional view showing a first method for improving the slide characteristics between the plate 530 and the plate 500 in the semiconductor device 100 of FIG. FIG. 10 is a schematic cross-sectional view showing a second method for improving the slide characteristics between the plate 530 and the plate 500 in the semiconductor device 100 of FIG.

  In the method of FIG. 9, contact pads 601 made of diamond-like carbon or the like are formed on the electrostatic plate 222 at, for example, four locations. Thereby, friction between the plate 530 and the electrostatic plate 222 is reduced, and adsorption between the plate 530 and the electrostatic plate 222 is prevented. Further, the wear of the plate 530 is prevented, and the distance between the electrostatic plate 122 and the electrostatic plate 222 is kept constant.

  In the method of FIG. 10, the second InGaAs layer 41b of FIG. 7C is not provided, or the first InGaAs layer 41a is formed thicker than the second InGaAs layer 41b. Thereby, the plate 530 is slightly curved. In this case, since the plate 530 contacts the electrostatic plate 222 with a curved surface, friction between the plate 530 and the electrostatic plate 222 is reduced, and adsorption between the plate 530 and the electrostatic plate 222 is prevented. Further, the wear of the plate 530 is prevented, and the distance between the electrostatic plate 122 and the electrostatic plate 222 is kept constant.

  In the method of FIG. 10 as well, a contact pad made of diamond-like carbon or the like may be formed on the electrostatic plate 222 as in the method of FIG.

  Applications of the semiconductor device 100 according to the first embodiment will be described later.

  FIGS. 11A and 11B are schematic cross-sectional views for explaining the configuration and operation of the semiconductor device according to the second embodiment of the present invention.

  In FIG. 11, a rectangular plate 510 is connected to the plate 500 on the substrate 1 via a hinge 310, a rectangular plate 520 is connected to the plate 510 via a hinge 320, and a rectangular shape is connected to the plate 520 via a hinge 340. A plate 530 is connected.

  A rectangular electrostatic plate 222 is provided on the plate 500, and a rectangular electrostatic plate 122 is provided on the plate 530.

  The hinges 310 and 320 are bent in a valley shape, and the hinge 340 is bent in a mountain shape. Thereby, the plate 530 and the plate 500 face each other, and the electrostatic plate 122 and the electrostatic plate 222 face each other. Note that an insulating film (not shown) is formed on the surfaces of the electrostatic plates 122 and 222 so that the electrostatic plate 122 and the electrostatic plate 222 do not come into electrical contact.

  Usually, as shown to Fig.11 (a), it sets so that the plate 530 and the plate 500 may partially oppose. Thereby, the electrostatic plate 122 and the electrostatic plate 222 partially face each other. As described above, when a voltage is applied between the electrostatic plate 122 and the electrostatic plate 222, an electrostatic force acts between the electrostatic plate 122 and the electrostatic plate 222. As a result, as shown in FIG. 11B, the plate 530 is translated in the direction of the arrow so that the electrostatic plate 122 and the electrostatic plate 222 are entirely opposed.

  12 to 16 are process diagrams showing a method of manufacturing the semiconductor device 100 of FIG. 11, wherein (a) is a schematic plan view and (b) is a schematic cross-sectional view.

  First, as shown in FIG. 12, a buffer layer 2 made of GaAs, a sacrificial layer 3 made of AlGaAs, a strained layer 4 and a component layer 5 are formed on a substrate 1 made of GaAs in the same manner as in the first embodiment. Are grown epitaxially in order.

  These buffer layer 2, sacrificial layer 3, strained layer 4 and component layer 5 are formed using an epitaxial growth technique such as MBE, MOCVD, or CVD.

  The strained layer 4 includes a first InGaAs layer 41a having a thickness of several nm to several tens of nm, a GaAs layer 42 having a thickness of several nm to several tens of nm, and a second InGaAs layer 41b having a thickness of several nm to several tens of nm. Composed. In the present embodiment, the lattice constants of the first and second InGaAs layers 41 a and 41 b are larger than the lattice constant of the GaAs layer 42. Therefore, strain due to the difference in lattice constant occurs in the strained layer 4. The function of the strain layer 4 is as described with reference to FIG.

  The component layer 5 is composed of a DBR film. The configuration of the DBR film is the same as the configuration of the DBR film in the first embodiment. Further, the component layer 5 may be made of a GaAs plate.

An etching stop layer made of, for example, Al _0.58 Ga _0.42 As having a thickness of 150 nm may be provided between the strain layer 4 and the component layer 5. Further, a strain compensation layer made of, for example, InGaAs having a thickness of 10 nm and a cap layer made of, for example, GaAs having a thickness of 10 nm may be provided on the component layer 5.

  Next, as shown in FIG. 13, the component layer 5 and the second InGaAs layer 41b are removed by photolithography and etching, and the valley grooves 21 and 22 defining the hinges 310 and 320 described later are spaced apart. They are formed in parallel with each other, the component layer 5 is removed, and the mountain fold grooves 24 are formed in parallel with the valley fold grooves 22 at intervals. As the etching, a wet etching method or a dry etching method can be used.

  Next, as shown in FIG. 14, wiring layers 121 and 221 made of metal films are formed on the component layer 5. Further, electrode pads 120 and 220 and electrostatic plates 122 and 222 made of a metal film are formed on the component layer 5. The electrode pad 120 and the electrostatic plate 122 are electrically connected by the wiring layer 121, and the electrode pad 220 and the electrostatic plate 222 are electrically connected by the wiring layer 221.

  The formation method of the electrode pads 120 and 220, the wiring layers 121 and 221 and the electrostatic plates 122 and 222 is the same as that in the first embodiment. Further, an insulating film (not shown) is formed on the electrostatic plates 122 and 222.

  Next, as shown in FIG. 15, except for the valley fold groove 21, a region between the valley fold groove 21 and the valley fold groove 22, a region between the valley fold groove 22 and the mountain fold groove 24, and the electrostatic plate 122. The component layer 5, the strained layer 4 and the sacrificial layer 3 are removed by photolithography and etching so as to surround the region including the isolation groove 11, thereby forming the isolation groove 11. Thereby, the component layer 5 surrounded by the separation groove 11 is separated from the surrounding component layer 5. Also in this case, a wet etching method or a dry etching method is used as the etching.

  Thereafter, as shown in FIG. 16, the sacrificial layer 3 under the strained layer 4 in the region surrounded by the separation groove 11 is selectively etched by a wet etching method. As a result, the strained layer 4 can be folded as hinges 310 and 320 so as to relieve strain caused by the difference in lattice constant between the first and second InGaAs layers 41a and 41b and the GaAs layer 42 constituting the strained layer 4. The groove is bent in a valley shape below the grooves 21 and 22, and the strained layer 4 is bent in a mountain shape below the fold groove 24 as the hinge 340. Thereby, the component layer 5 is bent into a valley shape at the valley fold grooves 21, 22 and is bent into a mountain shape at the mountain fold groove 24.

  The method for folding and valley-folding the component layer 5 is as described with reference to FIG.

  As described above, the semiconductor device 100 of FIG. 11 in which the plate 530 and the plate 500 are opposed to each other so as to be movable in parallel is manufactured easily and accurately.

  The operation principle of the semiconductor device 100 of FIG. 11 is the same as the operation principle of the semiconductor device 100 of FIG. 1 described with reference to FIG.

  FIG. 17 is a schematic cross-sectional view showing a first method for improving the slide characteristics of the plate 530 and the plate 500 in the semiconductor device 100 of FIG. 18 is a schematic cross-sectional view showing a second method for improving the slide characteristics between the plate 530 and the plate 500 in the semiconductor device 100 of FIG.

  In the method of FIG. 17, contact pads 601 made of diamond-like carbon or the like are formed on the electrostatic plate 122 at, for example, four locations. A contact pad may be formed on the electrostatic plate 222. Thereby, friction between the electrostatic plate 122 and the electrostatic plate 222 is reduced, and adsorption between the electrostatic plate 122 and the electrostatic plate 222 is prevented. Further, the electrostatic plates 122 and 222 are prevented from being worn, and the distance between the electrostatic plate 122 and the electrostatic plate 222 is kept constant.

  In the method of FIG. 18, an InGaAs layer is formed on the surface of the plate 530 on the electrostatic plate 122 side by the MBE method or the like. Thereby, the plate 530 is slightly curved. In this case, since the electrostatic plate 122 contacts the electrostatic plate 222 with a curved surface through an insulating film, friction between the electrostatic plate 122 and the electrostatic plate 222 is reduced, and the electrostatic plate 122 and the electrostatic plate Adsorption with 222 is prevented. Further, the electrostatic plates 122 and 222 are prevented from being worn, and the distance between the electrostatic plate 122 and the electrostatic plate 222 is kept constant.

  In the method of FIG. 18 as well, a contact pad made of diamond-like carbon or the like may be formed on the electrostatic plate 122 or the electrostatic plate 222 as in the method of FIG.

  Next, the use of the semiconductor device 100 according to the first and second embodiments will be described.

  FIG. 19 is a schematic diagram showing an actuator using the semiconductor device 100 of FIG. An actuator is configured using one or more pairs of semiconductor devices 100. The actuator of FIG. 19 conveys the conveyance object 600.

  As illustrated in FIG. 19A, the transfer target object 600 is placed on the front semiconductor device 100 and the rear semiconductor device 100 in the transfer direction. As shown in FIG. 19B, the semiconductor device 100 on the rear side slides in the direction of the arrow X1. Thereby, the conveyance object 600 moves as indicated by the arrow x1. At this time, the conveyance object 600 is supported by the semiconductor device 100 on the rear side.

  Next, as shown in FIG. 19C, the semiconductor device 100 on the front side slides in the direction of the arrow X3. Thereby, the conveyance target 600 is supported by the semiconductor device 100 on the front side and the rear side. Thereafter, as shown in FIG. 19D, the rear semiconductor device 100 slides as indicated by an arrow X4. Thereby, the conveyance target 600 is supported by the semiconductor device 100 on the front side. Further, as shown in FIG. 19E, the semiconductor device 100 on the front side slides as indicated by an arrow X5. Thereby, the conveyance object 600 moves as shown by the arrow x2.

  In this way, the conveyance object 600 can be conveyed by the actuator shown in FIG. A similar actuator can be configured using the semiconductor device 100 of FIG.

  The semiconductor device 100 in FIGS. 1 and 11 can also be used as an optical switch or an optical scanner.

  FIG. 20 is a plan view showing a state before the standing up of the semiconductor device according to the third embodiment of the present invention. FIG. 21 is a plan view showing a state after the standing up of the semiconductor device according to the third embodiment of the present invention.

  20 and FIG. 21 has a stacked structure similar to that of the semiconductor device 100 of FIGS. 1 and 11 on the substrate 1.

  As shown in FIG. 20, a rectangular plate 510 is formed so as to be adjacent to the plate 500 on the substrate 1 via the valley groove 21. A rectangular plate 520 is formed on one side of the plate 510 so as to be adjacent to each other through the valley groove 22. A rectangular plate 530 is formed so as to be adjacent to the plate 520 through the valley groove 23. A plate 540 is formed so as to be adjacent to the other side of the rectangular plate 510 with a valley groove 25 interposed therebetween.

  The separation groove 11 is formed so as to surround the plates 510, 520, 530, and 540 except for the valley fold groove 21.

  An electrostatic plate 222 is formed on the plate 500, and an electrostatic plate 122 is formed on the plate 530. In addition, electrode pads 120 and 220 are formed on the plate 500. The electrode pad 120 and the electrostatic plate 122 are electrically connected by the wiring layer 121, and the electrode pad 220 and the electrostatic plate 222 are electrically connected by the wiring layer 221.

  Similar to the first and second embodiments, when the sacrificial layer below the plates 510, 520, 530, and 540 is removed by etching, the strained layers in the valley grooves 21, 22, 23, and 25 are shown in FIG. The hinges 310, 320, 330 and 350 are curved in a valley shape. Accordingly, as shown in FIG. 21, the plate 510 stands vertically with respect to the plate 500, and the plates 520 and 540 also stand vertically with respect to the plate 500. Further, the plate 530 is bent perpendicular to the plate 520.

  In this way, the plates 520 and 530 are rotatable about the hinge 320 and the plate 530 is opposed to the plate 500 so as to be movable in parallel.

  In the initial state, as shown in FIG. 21, the electrostatic plate 122 and the electrostatic plate 222 face each other in a partially overlapped state. In this state, when a voltage is applied between the electrostatic plate 122 and the electrostatic plate 222 via the electrode pads 120 and 220, an electrostatic force acts between the electrostatic plate 122 and the electrostatic plate 222. In this case, the plate 530 rotates in the circumferential direction indicated by the arrow R around the hinge 320 and moves parallel to the plate 500, so that the electrostatic plate 122 completely overlaps the electrostatic plate 222.

  When the voltage applied between the electrostatic plate 122 and the electrostatic plate 222 is reduced or set to 0, the elastic force of the hinge 320 causes the plate 530 to rotate in the circumferential direction opposite to the arrow R about the hinge 320 as an axis. At the same time, it moves parallel to the plate 500 and returns to the state shown in FIG.

  In this way, by changing the voltage applied between the electrostatic plate 122 and the electrostatic plate 222, the plate 530 is rotated in the circumferential direction around the hinge 320 and is also translated with respect to the plate 500. be able to.

  In this case, the plate 520 rotates in the circumferential direction around the hinge 320 in a state perpendicular to the substrate 1. Accordingly, when the plate 520 is irradiated with the light beam L, the reflection direction of the light beam L can be changed in the horizontal plane by the rotation of the plate 520. Therefore, the semiconductor device 100 of the third embodiment can be used as an optical scanner.

In the first to third embodiments, the sacrificial layer 3 corresponds to the first layer, the strained layer 4 corresponds to the second layer, and the component layer 5 corresponds to the third layer. . The first InGaAs layer 41a corresponds to the first semiconductor layer, the GaAs layer 42 corresponds to the second semiconductor layer, and the second InGaAs layer 41b corresponds to the third semiconductor layer. Further, the region of the plate 500 corresponds to the first region, and the regions of the plates 510, 520, and 530 correspond to a plurality of regions of the second region. The region of the hinge 310 corresponds to the first boundary portion, and the region of the hinges 320, 330, 340, and 350 corresponds to the second boundary portion.

  The semiconductor devices of the first to third embodiments can be easily and inexpensively manufactured by a planar technique such as normal photolithography, etching, epitaxial growth, or the like.

  In the first to third embodiments, the strained layer 4 uses a laminated structure of an InGaAs layer and a GaAs layer. However, the present invention is not limited to this, and a combination of various semiconductor layers having different lattice constants is used. be able to. As the strained layer, a stacked structure of another group III-V compound semiconductor or a stacked structure of group II-VI compound semiconductor may be used. Alternatively, a stacked structure of semiconductor layers containing Si (silicon) and Ge (germanium) may be used as the strained layer.

  In the first to third embodiments, a substrate made of GaAs is used. However, another substrate such as a Si substrate may be used in consideration of the material of the sacrificial layer, the strained layer, and the component layer. Good.

  Further, in the first to third embodiments, AlGaAs is used as the material for the sacrificial layer, but the material is not limited to this, and other materials may be used in consideration of selective etching.

  Further, the material of the component layer is not limited to the above embodiment, and any material can be used.

  The present invention can be used for various devices and elements such as actuators, optical switches, and optical scanners.

It is a typical sectional view for explaining composition and operation of a semiconductor device in a 1st embodiment of the present invention. FIG. 2 is a process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1. FIG. 2 is a process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1. FIG. 2 is a process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1. FIG. 2 is a process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1. FIG. 2 is a process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1. It is typical sectional drawing which shows a distortion layer and a component layer. It is a figure for demonstrating the principle of operation of the semiconductor device of FIG. FIG. 2 is a schematic cross-sectional view showing a first method for improving the slide characteristics of a plate in the semiconductor device of FIG. 1. Also, FIG. 6 is a schematic cross-sectional view showing a second method for improving the slide characteristics of the plate in the semiconductor device of FIG. 1. It is a typical sectional view for explaining composition and operation of a semiconductor device in a 2nd embodiment of the present invention. FIG. 12 is a process diagram illustrating a method of manufacturing the semiconductor device of FIG. 11. FIG. 12 is a process diagram illustrating a method of manufacturing the semiconductor device of FIG. 11. FIG. 12 is a process diagram illustrating a method of manufacturing the semiconductor device of FIG. 11. FIG. 12 is a process diagram illustrating a method of manufacturing the semiconductor device of FIG. 11. FIG. 12 is a process diagram illustrating a method of manufacturing the semiconductor device of FIG. 11. FIG. 12 is a schematic cross-sectional view showing a first method for improving the slide characteristics of the plate in the semiconductor device of FIG. 11. FIG. 12 is a schematic cross-sectional view showing a second method for improving the slide characteristics of the plate in the semiconductor device of FIG. 11. It is a schematic diagram which shows the actuator using the semiconductor device of FIG. It is a top view which shows the state before standing up of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a top view which shows the state after standing up of the semiconductor device which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Sacrificial layer 4 Strain layer 5 Component layer 11 Separation groove 21, 22, 23 Valley fold groove 24 Mountain fold groove 41 a First InGaAs layer 41 b Second InGaAs layer 42 GaAs layer 100, 100 a Semiconductor device 120 , 220 Electrode pad 121, 221 Wiring layer 122, 222 Electrostatic plate 310, 320, 330, 340, 350 Hinge 500, 510, 520, 530, 540 Plate

Claims (7)

A substrate ,
A laminated structure provided on the substrate,
The stacked structure includes a first layer, a second layer, and a third layer in order, and includes first and second regions that are adjacent to each other via a linear first boundary portion;
The second region is further divided into a plurality of regions via a plurality of linear second boundaries,
The second layer, seen including a plurality of semiconductor layers having different lattice constants,
First and second opposing electrodes respectively provided on the first region and the second region of the laminated structure,
The third layer in the peripheral portion surrounding the first boundary portion and the second region with the exception of the portion of the second layer and the first layer are removed, the in the second region the The portion of the first layer is selectively removed, so that the second layer and the third layer in the second region are separated from the substrate;
Due to the strain caused by the second layer, the portion of the second layer in the first boundary portion is bent into a valley shape, and the portion of the second layer in the plurality of second boundary portions is A semiconductor device , wherein the first counter electrode and the second counter electrode face each other so as to be movable in parallel by being bent in a valley shape or a mountain shape . The first boundary portion and the plurality of second boundary portions are provided substantially parallel to each other, and the first counter electrode and the second counter electrode are connected to the first boundary portion and the plurality of second boundary portions . 2. The semiconductor device according to claim 1, wherein the semiconductor device is provided so as to be movable in a direction substantially perpendicular to the boundary between the two. At least one of the plurality of second boundary portions is provided substantially perpendicular to the first boundary portion ,
A part of the second region stands substantially perpendicular to the substrate, and the second counter electrode is rotatable in a circumferential direction about an axis substantially perpendicular to the substrate. 2. The semiconductor device according to claim 1, wherein said semiconductor device is provided so as to be movable in parallel with respect to said first counter electrode. The portion of the second layer in the first boundary portion is bent in a valley shape by removing at least the portion of the third layer in the first boundary portion and the plurality of second boundary portions . is, the semiconductor device according to claim 1, portions of the second layer in the plurality of second boundary portion is characterized in that it is folded in a valley shape or a mountain shape. The second layer includes a first semiconductor layer having a first lattice constant and a second semiconductor layer having a second lattice constant smaller than the first lattice constant,
Wherein in said first boundary portion and the plurality of second boundary portion of the first boundary portion and the plurality as folded in a valley shape of the second layer in the second boundary 5. The semiconductor device according to claim 1, wherein a portion of the third layer is removed. The second layer includes a first semiconductor layer having a first lattice constant, a second semiconductor layer having a second lattice constant smaller than the first lattice constant, and the second lattice constant. A third semiconductor layer having a third lattice constant greater than
Portions of said second layer is a mountain shape bent by said at least one of said third in the second boundary so that in at least one of the second boundary portion of the plurality of second boundary The portion of the layer is removed, and the portion of the second layer in the other second boundary portion of the first boundary portion and the plurality of second boundary portions is bent in a valley shape. 5. The part of the third layer and the part of the third semiconductor layer in the first boundary part and the other second boundary part are removed. 6. Semiconductor device. Forming a stacked structure including a first layer, a second layer, and a third layer in that order on a substrate;
The stacked structure includes first and second regions adjacent to each other via a linear first boundary portion;
The second region is further divided into a plurality of regions via a plurality of linear second boundaries,
The second layer, seen including a plurality of semiconductor layers having different lattice constants,
Providing at said first region and on the second first and respectively on the region of the second opposing electrodes of said laminated structure,
Removing portions of said third layer, said second layer and said first layer in the peripheral portion with the exception of the first boundary surrounds said second region,
Wherein by selectively removing portions of said first layer in the second region, thereby separating the portion of the second layer and the third layer in the second region from said substrate, said first The second layer portion in the first boundary portion is bent into a valley shape due to strain caused by the two layers, and the second layer portion in the plurality of second boundary portions is valley-shaped. Alternatively, the method further includes the step of causing the first counter electrode and the second counter electrode to face each other so as to be parallel-movable by being bent in a mountain shape .

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