JP4301627B2 - False contour correction apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a false contour correction apparatus and method used when a video signal is digitally processed.
[0002]
[Prior art]
In recent years, digital signal processing has been increasingly performed on video signals as image quality and functionality of television receivers and the like have increased. For example, in order to increase the contrast of video, gradation correction by digital signal processing is performed. When such digital signal processing is performed on a quantized digital signal, an unnatural contour line called a false contour may be generated in an image displayed on the screen. On the other hand, for example, Japanese Patent Laid-Open No. 6-62280 discloses a technique for removing false contours generated by digital signal processing.
[0003]
The conventional false contour correction circuit disclosed in Japanese Patent Laid-Open No. 6-62280 will be described below with reference to the drawings. FIG. 9 is a block diagram showing the configuration of this conventional false contour correction circuit. This false contour correction circuit includes a random number generator 5, a discrimination circuit 6, and an addition circuit 7, and receives an n-bit digital video signal A. A signal F consisting of predetermined lower bits among n bits constituting the input digital video signal A is determined. Another It is supplied to the circuit 6. The random number generator 5 outputs a digital random number H having the same bit width as that of the signal F. The discriminating circuit 6 compares the value indicated by the signal F consisting of predetermined low-order bits of the digital video signal A with the digital random number H output from the random number generator 5, and “1” according to the comparison result. Alternatively, a signal indicating “0” is output as the correction signal I. The adder circuit 7 is an adder having the same bit width as the upper bits G of the digital video signal A, and corrects by adding the upper bits G of the digital video signal A and the correction signal I output from the determination circuit 6. An output signal J is generated.
[0004]
According to the false contour correction circuit as described above, since the correction signal I having no regularity is added to the upper bits G of the digital video signal A, it is input to the discrimination circuit 6 among the n bits constituting the digital video signal A. The relationship between the lower-order bit signal F and the correction signal I output from the determination circuit 6 becomes uncorrelated within the accuracy of the random number generator 5. By performing correction that has no correlation in terms of image in this way, when quantizing an image with little change in luminance or hue, the position on the screen where the quantization level changes is dispersed in the front, back, left, and right. Unnatural false contours are reduced. Therefore, with such a corrected digital video signal, it is possible to obtain an image in which a deterioration in image quality due to quantization with a low quantization level is prevented.
[0005]
[Problems to be solved by the invention]
In the above-described conventional false contour correction circuit, in order to make the position on the screen where the quantization level changes uncorrelated with the video signal, there is no fluctuation corresponding to the change of the least significant bit in the digital video signal. The correlation is given. For this reason, even when a signal representing a single luminance level image with no luminance change is input, the image on the screen appears rough due to fluctuations in the video signal corresponding to the change in the least significant bit. Has been obtained.
[0006]
Accordingly, the present invention provides a false contour correction apparatus and method capable of reducing the false contour in an image based on a digital video signal while avoiding a deterioration in image quality due to a side effect associated with the false contour correction that causes the above-described noise. The purpose is to provide.
[0007]
[Means for Solving the Problems and Effects of the Invention]
A first invention is a false contour correction device for reducing false contours in a video based on a digital video signal,
A double bit that detects a signal value change corresponding to twice the minimum quantization unit of the digital video signal as a double bit change in the digital video signal and outputs a signal indicating the detection result as a double bit change detection signal A change detection circuit;
De To reduce false contours for double bit change in digital video signals Further, based on the double bit change detection signal, the double bit change portion in the digital video signal is corrected to a portion where there are two 1-bit changes, which are signal value changes corresponding to the minimum quantization unit. A signal correction circuit.
According to the first invention, the double bit change in the digital video signal is Converts to two 1-bit changes to accommodate twice that change False contour Removed or Reduction The Therefore, it is possible to reduce false contours while avoiding deterioration in image quality due to side effects such as generation of noise in conventional false contour correction.
[0009]
First 2 In the first invention,
It is determined whether or not there is a signal value change more than twice the minimum quantization unit in a predetermined section before and after the double bit change in the digital video signal, and a signal indicating the determination result is output as a flat detection signal. A front / rear flatness detection circuit is further provided,
The signal correction circuit is based on the flatness detection signal, and only when the signal value change more than twice the minimum quantization unit does not exist in a predetermined section before and after the double bit change, the false contour is applied to the double bit change portion. It is characterized by performing correction for reducing the above.
First 2 According to the invention, only when there is no change more than the double bit change in the predetermined section before and after the double bit change in the digital video signal, that is, when the value of the digital video signal becomes substantially constant in the predetermined section. Only the correction for the double bit change is performed. For this reason, it is possible to reliably correct only the false contour, and to prevent an adverse effect on the image due to the false contour correction.
[0010]
First 3 The invention of the 2 In the invention of
The predetermined section is a section corresponding to five adjacent pixels in the digital video signal.
[0011]
First 4 The invention of the 1 In the invention of
It is determined whether or not there is a signal value change more than twice the minimum quantization unit in a predetermined section before and after the double bit change in the digital video signal, and a signal indicating the determination result is output as a flat detection signal. A front / rear flatness detection circuit is further provided,
Based on the flat detection signal, the signal correction circuit performs a correction for reducing the false contour for the double-bit change portion only when there is no signal value change more than twice the minimum quantization unit in a predetermined interval. In the correction, the position of the 1-bit change is determined so that the interval between the two 1-bit changes is shorter than a predetermined interval.
First 4 According to the invention, correction is performed only when there is no other double bit change in a predetermined section before and after the double bit change in the digital video signal, and the interval between two 1-bit changes generated by the correction is performed. Becomes shorter than the predetermined interval. Accordingly, the correction for one of the two double bit changes existing in the digital video signal does not adversely affect the correction for the other, and therefore, a false operation that does not cause a malfunction even for a digital video signal in which the double bit change frequently occurs. Contour correction processing can be performed.
[0012]
First 5 The invention of the 1 In the invention of
A random number generating circuit for generating a random number signal indicating a pseudo random number;
The signal correction circuit is characterized in that the positions of two 1-bit changes to be generated by correcting the double-bit change portion are determined based on a random number signal.
First 5 According to the invention, the positions of the two 1-bit changes generated by the correction for the double-bit change portion in the digital video signal are determined at random based on the random number signal. In the video based on the video signal, it is possible to prevent the phenomenon that the vertical lines are aligned and look like vertical lines.
[0013]
First 6 The invention of the 5 In the invention of
The random number generation circuit receives a horizontal synchronization signal corresponding to a digital video signal, and outputs a signal indicating a value varying according to a horizontal line indicated by the horizontal synchronization signal as a random number signal.
First 6 According to the invention, the positions of the two 1-bit changes generated by correcting the double-bit change portion in the digital video signal are irregularly shifted left and right for each horizontal line based on the random number signal. It is possible to prevent a phenomenon in which bit change portions are aligned vertically in a video based on a digital video signal and look like vertical lines.
[0015]
First 7 The present invention is a false contour correction method for reducing false contour in a video based on a digital video signal,
A double bit change detection step of detecting a portion in which the value of an adjacent pixel is different by twice the minimum quantization unit of the digital video signal as a double bit change portion in the video represented by the digital video signal;
false Reduce contours Therefore, based on the detection result in the detection step, the value of the pixel of the double bit change portion is corrected so that there are two 1-bit change portions where the values of adjacent pixels are different by the minimum quantization unit. A correction step.
[0017]
First 8 The invention of the 7 In the invention of
In a predetermined section before and after the adjacent pixel in the double bit change portion, further comprising a front and back flat detection step for detecting whether or not there is an adjacent pixel having a value that is twice or more the minimum quantization unit,
In the correction step, based on the detection result of the back-and-forth flatness detection step, the value of the pixel of the double bit change portion is corrected only when there is no adjacent pixel having a different value in the predetermined section at least twice the minimum quantization unit It is characterized by that.
[0018]
First 9 The invention of the 7 In the invention of
In a predetermined section before and after the adjacent pixel in the double bit change portion, further comprising a front and back flat detection step for detecting whether or not there is an adjacent pixel having a value that is twice or more the minimum quantization unit,
In the correction step, based on the detection result of the back-and-forth flatness detection step, the pixel value of the double bit change portion is corrected only when there is no signal value change more than twice the minimum quantization unit in the predetermined interval, In the correction, the position of the 1-bit changing portion is determined so that the interval between the two 1-bit changing portions is shorter than a predetermined interval.
[0019]
First 10 The invention of the 7 In the invention of
A random number generating step for generating a pseudo-random number;
The correction step is characterized in that the positions of two 1-bit changing portions to be generated by correcting the double-bit changing portion are determined based on pseudo random numbers.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 4 is a virtual signal waveform diagram showing changes in signal values expressed by the digital video signal. The quantized digital video signal is usually in a state where there is a change of 1 bit or a state where there is no change, as shown in FIG. This 1-bit change is a signal value change corresponding to the minimum quantization unit. When gradation display is performed using 8 bits or more, it corresponds to this 1-bit change in the video displayed on the screen. The level difference is almost invisible to the human eye.
[0022]
However, depending on the contents of the digital signal processing applied to the video signal, the resulting digital video signal A has a change of twice the minimum quantization unit as shown in FIG. Bit change) may occur at once. For example, when gradation correction is performed by digital signal processing to increase the contrast of a video, a double bit change may occur. In such a case, in the video based on the digital video signal, the double bit change appears as an unnatural false contour.
[0023]
Therefore, in each embodiment of the present invention, a double bit change is detected in a digital video signal, and processing for reducing false contours is performed based on the detection result. Hereinafter, details of each of such embodiments will be described.
[0024]
<First Embodiment>
FIG. 1 is a block diagram showing a configuration of a false contour correction apparatus according to the first embodiment of the present invention. This false contour correction device includes a double bit change detection circuit 1 and a signal correction circuit 2a. The digital video signal A input to the false contour correction device is a double bit change detection circuit 1 and a signal correction. It is supplied to the circuit 2a.
[0025]
The double bit change detection circuit 1 has a pixel value difference corresponding to twice the minimum quantization unit (quantization step size) between adjacent pixels in the video represented by the digital video signal A, that is, When there is a difference corresponding to twice the 1-bit change in the values of those adjacent pixels, the difference between these pixel values is detected as “double-bit change”, and the signal indicating the detection result is changed by a 2-bit change. Output as detection signal B. Such a double bit change detection circuit 1 can be realized by the same configuration as the double bit change detection circuit 10 in the false contour correction apparatus shown in FIG. Note that the double bit change may be a double bit change for a pixel adjacent in the horizontal direction in the image represented by the digital video signal A and a double bit change for a pixel adjacent in the vertical direction. In the following description, it is assumed that the double bit change detection circuit 1 detects a double bit change for pixels adjacent in the horizontal direction. However, the double bit change for pixels adjacent in the vertical direction will be described later.
[0026]
The signal correction circuit 2a uses the double bit change detection signal B to correct the double bit change in the digital video signal A into two minimum quantization unit changes (hereinafter referred to as “1 bit change”). The corrected digital video signal is output as a corrected video signal C1. Such a signal correction circuit 2a can be realized by the same configuration as the signal correction circuit 20 in the false contour correction apparatus shown in FIG.
[0027]
The operation of the false contour correcting apparatus of the present embodiment configured as described above will be described with reference to FIG.
[0028]
In the false contour correcting device of this embodiment, when a digital video signal A having a double bit change as shown in FIG. 4B is input, the double bit change detection circuit 1 changes the double bit change. Detected. In the signal correction circuit 2a, the double bit change detection signal B indicating the detection result is used to convert the double bit change portion in the digital video signal A into two 1-bit change portions. That is, for example, as shown in FIG. 4C, a 1-bit change first occurs before the time of the double bit change, and a 1-bit change further occurs after a period of 4 clocks from the time of the 1-bit change. Thus, the digital video signal A is corrected to a signal in which a 1-bit change occurs in two stages. Here, the period of n clocks (n is a natural number) means a period of n cycles, ie, a period of n pixels, in a clock signal composed of pulses corresponding to each pixel.
[0029]
The double bit change detection circuit 1 in the above embodiment does not detect a signal value change larger than the double bit change, that is, a signal value change exceeding twice the minimum quantization unit. It is determined that the portion of the digital video signal A that has a signal value change exceeding a double bit change does not correspond to the false contour but corresponds to the true contour in the image represented by the digital video signal A. Because it is done.
[0030]
As described above, according to the present embodiment, a false contour is detected by detecting a double bit change portion in the digital video signal A, and the double bit change portion is decomposed into two 1-bit changes. As a result, the false contour is removed. Since correction is performed only for the signal portion corresponding to the false contour in this way, the false contour can be reduced while avoiding side effects such as generation of noise in the conventional false contour correction. Further, in this embodiment, a signal value change exceeding a double bit change in the digital video signal A (a signal value change exceeding twice the minimum quantization unit) is not detected. Is avoided. Thereby, it is possible to reliably reduce only the false contour while preventing the blur of the true contour due to the false contour correction.
[0031]
<Second Embodiment>
FIG. 2 is a block diagram showing a configuration of a false contour correction apparatus according to the second embodiment of the present invention. As in the first embodiment, the false contour correction apparatus includes a double bit change detection circuit 1 and a signal correction circuit 2b. In addition to these, the false contour correcting device includes a front / rear flatness detecting circuit 3, which is different from the first embodiment in this respect. In the present embodiment, the digital video signal A input to the false contour correction device is supplied to the double bit change detection circuit 1, the signal correction circuit 2b, and the front / rear flatness detection circuit 3.
[0032]
Since the function and configuration of the double bit change detection circuit 1 in the present embodiment are the same as those of the double bit change detection circuit 1 in the first embodiment, description thereof is omitted.
[0033]
The front and rear flat detection circuit 3 detects whether or not the digital video signal A is flat in a predetermined period before and after the double bit change detected by the double bit change detection circuit 1, and the detection result is used as a flat detection signal D. Output. Here, when the digital video signal A does not include a signal value change greater than or equal to a double bit change in a certain period, that is, when the signal value does not change or changes even when it changes, The digital video signal A is assumed to be flat during that period. Such a front / rear flatness detection circuit 3 can be realized by a configuration similar to that of the front / rear flatness detection circuit 30 in the false contour correction apparatus shown in FIG.
[0034]
The signal correction circuit 2b performs a double bit change in the digital video signal A based on the double bit change detection signal B from the double bit change detection circuit 2 and the flat detection signal D from the front and rear flat detection circuit 3. The bit change is corrected, and the corrected digital video signal is output as a corrected video signal C2. Such a signal correction circuit 2b can also be realized by the same configuration as the signal correction circuit 20 in the false contour correction apparatus shown in FIG.
[0035]
The operation of the false contour correcting apparatus of the present embodiment configured as described above will be described with reference to FIG. FIG. 5 is a virtual signal waveform diagram showing an example of a change in signal value expressed by the digital video signal A.
[0036]
Also in the present embodiment, as shown in FIG. 4C, the signal correction circuit 2b is digitally converted using the double bit change detection signal B from the double bit change detection circuit 1 as in the first embodiment. The double bit change portion in the video signal A is corrected into two 1-bit change portions. The two 1-bit change parts generated in this correction are separated by a period of 4 clocks, but if there are a plurality of double-bit change parts in the digital video signal A, the interval between them is within a period of 4 clocks. In such a case, the correction for one of the two double bit change parts adversely affects the correction for the other. That is, in this case, the false contour cannot be corrected appropriately in the signal correction circuit 2b. In addition, in the digital video signal A, when the double bit change portions are continuously present at short intervals, it is highly likely that these double bit change portions do not correspond to false contours. In the present embodiment, a period of 5 clocks is adopted as a value determined on a trial and error basis on the assumption that the number of effective pixels 720 in the horizontal direction, and when the interval between two double bit changes is shorter than the period of 5 clocks, It is assumed that correction for reducing the false contour is not performed on the two double bit change portions.
[0037]
From the above viewpoint, in this embodiment, the front / rear flat detection circuit 3 determines whether or not the digital video signal A is flat during the period of 5 clocks before and after the double bit change, that is, the double bit change or more as shown in FIG. It is detected whether or not there is a change, and the detection result is output as a flat detection signal D. Then, the signal correction circuit 2b uses the flat detection signal D together with the double bit change detection signal B, and there is a double bit change in the digital video signal A, and the period of 5 clocks before and after the double bit change is When the digital video signal A is flat, the double bit change portion is corrected to two 1-bit change portions.
[0038]
According to the present embodiment as described above, the correction for removing the false contour is performed only when the double bit change is detected in the digital video signal A and the period is flat for 5 clocks before and after the double bit change. If a plurality of double bit changes exist and their interval is equal to or shorter than the period of 4 clocks, no correction for false contour removal is performed. Therefore, it is possible to perform a false contour correction process without malfunction even for a digital video signal in which a double bit change frequently occurs. In addition, the false contour correction process can be performed only on the false contour within a range where no adverse effect is caused by the false contour correction process.
[0039]
<Third Embodiment>
FIG. 3 is a block diagram showing a configuration of a false contour correction apparatus according to the third embodiment of the present invention. As in the second embodiment, the false contour correcting apparatus includes a double bit change detection circuit 1, a signal correction circuit 2c, and a front / rear flatness detection circuit 3. In addition to these, the false contour correcting device includes a random number generation circuit 4 and is different from the second embodiment in this respect. In this embodiment, the digital video signal A input to the false contour correction device is supplied to the double bit change detection circuit 1, the signal correction circuit 2c, and the front / rear flatness detection circuit 3 as in the second embodiment.
[0040]
The functions and configurations of the double bit change detection circuit 1 and the front and rear flat detection circuit 3 in the present embodiment are the same as the functions and configurations of the double bit change detection circuit 1 and the front and rear flat detection circuit 3 in the second embodiment, respectively. Therefore, explanation is omitted.
[0041]
The random number generation circuit 4 generates an uncorrelated random number for the input digital video signal A and the corrected video signal C3 which is an output signal, and outputs a random number signal E indicating the random number.
[0042]
The signal correction circuit 2c is a digital video based on the double bit change detection signal B from the double bit change detection circuit 2, the flat detection signal D from the front and rear flat detection circuit 3, and the random signal E from the random number generation circuit 4. The double bit change in the signal A is corrected to two 1-bit changes, and the digital video signal subjected to such correction is output as a corrected video signal C3. Such a signal correction circuit 2c can also be realized by the same configuration as the signal correction circuit 20 in the false contour correction device shown in FIG.
[0043]
The operation of the false contour correcting apparatus of the present embodiment configured as described above will be described with reference to FIG.
[0044]
Also in this embodiment, as in the second embodiment, the signal correction circuit 2c uses the double bit change detection signal B to cause the double bit change in the digital video signal A as shown in FIG. Is corrected to two 1-bit change portions. When the false contour extends in the vertical direction in the video represented by the digital video signal A, the positions of the two 1-bit changes generated in this correction are always as shown in FIG. 6A in the second embodiment. Are the same. For this reason, depending on the state of the input digital video signal A, the 1-bit changed part after correction may appear as a vertical line aligned vertically in the video displayed on the screen.
[0045]
Therefore, in this embodiment, the position of the 1-bit change generated by correcting the double-bit change portion in the digital video signal A is shown in FIG. 6B using the random number signal E from the random number generation circuit 4. As shown, each line is shifted. As a result, it is possible to prevent a phenomenon in which the 1-bit change portion generated in the false contour correction looks vertically like a vertical line in the video displayed on the screen.
[0046]
FIG. 7 is a detailed block diagram showing an example of the configuration of the false contour correction apparatus according to the present embodiment. Double The bit change detection circuit 1, the signal correction circuit 2c, the front / rear flatness detection circuit 3, and the random number generation circuit 4 are the double bit change detection circuit 10, the signal correction circuit 20, the front / rear flatness detection circuit 30, and the random number generation shown in FIG. These correspond to the circuits 40, respectively.
[0047]
In this configuration example, the double bit change detection circuit 10 includes a 1-clock differentiation circuit 12, a full-wave rectification circuit 14, a level comparator 16, and a delay circuit 18. The 1-clock differentiating circuit 12 generates a signal having a value corresponding to a difference between signal values separated by a period of 1 clock in the digital video signal A, that is, a difference between adjacent pixel values, as a differential signal. A flag signal Flg indicating whether it is negative or negative is output. The full wave rectification circuit 14 converts the differential signal into a signal having only a positive value by inverting the polarity of the negative signal portion of the differential signal from the one clock differentiation circuit 12, and this is subjected to full wave rectification. Output as a signal. The level comparator 16 compares the value of the full-wave rectified signal with a reference value corresponding to a double bit change which is a preset value, and becomes H level only when it is equal to the reference value. A digital signal which becomes L level is output. The delay circuit 18 outputs a signal obtained by delaying the digital signal by a predetermined number of clocks as a double bit change detection signal B.
[0048]
The front / rear flat detection circuit 30 includes a least significant bit truncation circuit 32, a full-wave rectification circuit 34, a delay circuit in which ten 1-clock delay elements T are connected in cascade, and an OR circuit 36. The least significant bit truncation circuit 32 receives the differential signal from the 1-clock differentiation circuit 12 in the double bit change detection circuit 10 and outputs a signal obtained by truncating the least significant bit of the differentiation signal. However, when the differential signal to be input is an analog signal, the least significant bit truncation circuit 32 converts the differentiated signal into a digital signal and truncates the least significant bit of the converted signal. Instead of using the differential signal output from the 1-clock differentiating circuit 12, a 1-clock differentiating circuit is separately provided in the front / rear flatness detecting circuit 30, and the digital video signal A is input to the 1-clock differentiating circuit. A differential signal obtained by the clock differentiation circuit may be input to the least significant bit truncation circuit 32. The signal from the least significant bit truncation circuit 32 passes through a full wave rectifier circuit 34 having the same function as the full wave rectifier circuit 14 in the double bit change detection circuit, and is a delay circuit composed of ten 1-clock delay elements T. Is input. The signal input to the delay circuit is L level when there is no change in the digital video signal A or even if there is a change, and becomes H level when there is a change more than double bit change. . The OR circuit 36 includes an input signal to the delay circuit, an output signal of each delay element T from the first stage to the fourth stage among the ten delay elements T constituting the delay circuit, and the sixth stage. The output signals of the delay elements T up to the tenth stage are input, and a logical sum signal of these signals is output as the flat detection signal D. Therefore, the flat detection signal D becomes L level at each time point in units of clocks when the signal from the full-wave rectifier circuit 34 is L level in the period of 5 clocks before and after that time point, and otherwise. At H level. Therefore, the flat detection signal D is a low active signal, and even if the signal value does not change or changes during the period of 5 clocks before and after the double bit change in the digital video signal A, it changes by 1 bit. It becomes L level at the time of, and becomes H level when there is a change more than double bit change.
[0049]
The random number generation circuit 40 may be realized as a circuit that generates a pseudo-random number using a linear feedback shift register or the like, but in this configuration example, the horizontal synchronization signal Sh is input to the horizontal line indicated by the horizontal synchronization signal. This is realized by a conversion table for outputting as a random number signal E a signal indicating a value that varies accordingly. This conversion table is set so that the position of 1-bit change determined by the random number signal E is pseudo-randomly shifted for each line as shown in FIG. Has been.
[0050]
The signal correction circuit 20 adds and subtracts with the delay circuit 22 vessel 24 and an addition / subtraction control circuit 26. The delay circuit 22 delays the digital video signal A by a predetermined number of clocks and outputs the delayed digital video signal. The addition / subtraction control circuit 26 includes a double bit change detection signal B and a flag signal Flg from the double bit change detection circuit 10, a flat detection signal D from the front and rear flat detection circuit 30, and a random number signal E from the random number generation circuit 40. Based on the above, a control signal Cop composed of the addition instruction signal Cadd and the subtraction instruction signal Csub is generated as a signal for controlling the calculation by the adder / subtractor 24. The adder / subtractor 24 adds or subtracts a predetermined value for a predetermined period to the delayed digital video signal output from the delay circuit 22 in accordance with the control signal Cop, and corrects the calculated digital video signal. Output as video signal C3. The delay circuit 22 in the signal correction circuit 20 and the delay circuit 18 in the double bit change detection circuit 10 are digital video signal A and double bit change detection signal in order to realize the operation shown in FIG. B, introduced to adjust the timing between the flat detection signal D and the like.
[0051]
FIG. 8A is a signal waveform diagram showing an operation example of the signal correction circuit 20. However, this figure shows not a real signal waveform but a virtual signal waveform indicating a change in signal value expressed by the digital signals A and C3 for the digital video signal A and the corrected video signal C3. Yes. As shown in FIG. 8A, when there is a double bit change in the direction in which the signal value increases in the digital video signal A, the double bit change detection signal B indicating the position of the double bit change is 1 A flag signal Flg indicating that the value of the differential signal from the clock differentiation circuit 12 is positive is input to the addition / subtraction control circuit 26. The flag signal Flg indicating “positive” in this way means that the double bit change is a change in the direction in which the value of the digital video signal A increases. In this case, the addition instruction signal Cadd out of the control signal Cop output from the addition / subtraction control circuit 26 is the number of clocks n1 immediately before the point of the double bit change if the flat detection signal D is active (L level). It becomes active (H level) only for a period. On the other hand, if the flat detection signal D is active (L level), the subtraction instruction signal Csub of the control signal Cop is active (H level) for the period of the number of clocks n2 immediately after the double bit change. . Here, the values of the clock numbers n1 and n2 are determined by the random number signal E. While the addition instruction signal Cadd is active, the adder / subtractor 24 adds a value corresponding to the minimum quantization unit (that is, a value corresponding to the magnitude of 1-bit change) to the value of the digital video signal A, and performs a subtraction instruction. While the signal Csub is active, a value corresponding to the minimum quantization unit is subtracted from the value of the digital video signal A. As a result, as shown in FIG. 8A, a digital video signal in which the double bit change portion is corrected to two 1-bit changes is obtained, and this signal is obtained as a corrected video signal C3 from the signal correction circuit 20. Is output. If the flatness detection signal D is inactive, the addition instruction signal Cadd and the subtraction instruction signal Csub are not active. Therefore, if there are other double bit changes or more changes in the period of 5 clocks before and after the above double bit change, the above correction is not performed for the double bit change.
[0052]
FIG. 8B is a signal waveform diagram showing another operation example of the signal correction circuit 20. However, this figure also shows virtual signal waveforms indicating changes in signal values expressed by the digital signals A and C3, not the actual signal waveforms, for the digital video signal A and the corrected video signal C3. Yes. As shown in FIG. 8B, when there is a double bit change in the direction in which the signal value decreases in the digital video signal A, the double bit change detection signal B indicating the position of the double bit change is 1 A flag signal Flg indicating that the value of the differential signal from the clock differentiation circuit 12 is negative is input to the addition / subtraction control circuit 26. The flag signal Flg indicating “negative” in this way means that the double bit change is a change in the direction in which the value of the digital video signal A decreases. In this case, the subtraction instruction signal Csub out of the control signal Cop output from the addition / subtraction control circuit 26 is active only for the period of the number of clocks n1 immediately before the point of the double bit change if the flat detection signal D is active. Become. On the other hand, the addition instruction signal Cadd in the control signal Cop is active only for the period of the number of clocks n2 immediately after the double bit change if the flat detection signal D is active. Based on the subtraction signal Csub and the addition signal Cadd, the adder / subtractor 24 performs subtraction and addition on the digital video signal from the delay circuit 22, thereby changing the double bit change as shown in FIG. A digital video signal whose portion is corrected to two 1-bit changes is obtained, and this signal is output from the signal correction circuit 20 as a corrected video signal C3. Note that the values of the clock numbers n1 and n2 are determined by the random number signal E as described above. In addition, when there are other double bit changes or more changes in the period of 5 clocks before and after the above double bit change, the flat detection signal D becomes inactive. The above correction is not performed.
[0053]
By the above-described operation of the signal correction circuit 20, as shown in FIGS. 8 (a) and 8 (b), the double bit change in the digital video signal A is reduced to two. 1 It is corrected to bit change. That is, the double bit change is decomposed into a 1-bit change at a time point n1 clock before the double bit change time point and a 1-bit change at a time point n2 clocks after the double bit change time point. . However, if there are other double bit changes or more changes in the period of 5 clocks before and after the double bit change, the double bit change is not corrected. Further, since n1 and n2 are determined by the random number signal E, the positions of two 1-bit changes generated in the correction for the double-bit change, that is, the false contour correction, are shown for each line as shown in FIG. It will shift to.
[0054]
According to the present embodiment as described above, the same effect as in the first and second embodiments can be obtained, and the 1-bit change portion generated in the false contour correction is displayed on the screen. It is possible to prevent the phenomenon that the vertical lines are aligned like vertical lines.
[0055]
<Modification>
In each of the embodiments described above, it is assumed that the interval between two 1-bit changes generated by the correction for the double bit change in the digital video signal A is a period of 4 clocks as shown in FIG. However, this interval is not limited to a period of 4 clocks and may be a period of 2 clocks or more.
[0056]
In addition, the front and rear flatness detection circuit 3 used in the second and third embodiments detects whether or not the digital video signal A is flat in a period of 5 clocks before and after the double bit change. The flat period to be detected before and after the double bit change is not limited to a period of 5 clocks. The appropriate length of the flat period depends on how far the interval between two double bit changes existing in the digital video signal should be determined as a false contour. For example, by statistically examining the video represented by the digital video signal, it is possible to determine an appropriate length as the flat period according to the number of horizontal pixels in the video. However, as described above, in order to perform false contour correction without malfunction, the flat period to be detected is set to two 1-bit change intervals generated by correction for double bit change (in each embodiment described above). 4 clock periods).
[0057]
Furthermore, the false contour correction device of each of the above embodiments is used as a device for performing a false contour correction process on a digital video signal sent in real time such as a video signal in a television receiver, for example. However, it can also be used when performing false contour correction processing as image processing for accumulated image data. That is, the image signal obtained by sequentially reading out image data stored in a storage device such as a semiconductor memory or a hard disk device is regarded as the digital video signal A in each of the above embodiments, and the false contour correcting device of each of the above embodiments is used. It is also possible to do.
[0058]
Furthermore, in each of the embodiments described above, a double bit change is detected for pixels adjacent in the horizontal direction. However, in order to remove a false contour extending in the horizontal direction, a double bit for pixels adjacent in the vertical direction is detected. You may make it detect a change. In the case of performing false contour correction by detecting a double bit change for pixels adjacent in the vertical direction, for example, in the false contour correction device shown in FIG. A signal having a value corresponding to a difference between signal values separated by a line period is replaced with a one-line differentiating circuit that generates a differential signal, and each one-clock delay element T in the front and rear flat detection circuit 30 is replaced with a one-line delay element. In addition, the processing in units of clocks in each unit may be changed to be processing in units of one line.
[0059]
In each of the embodiments described above and the modifications thereof, the digital video signal A is doubled on the premise that a portion having a signal value change exceeding a double bit change does not correspond to a false contour. The bit change detection circuit 1 detects only a double bit change in the digital video signal A (or an adjacent pixel whose value is different by twice the minimum quantization unit). However, a signal value change more than three times the minimum quantization unit, that is, a signal change more than three times the bit change has occurred due to the digital signal processing applied to the digital video signal A. When it appears as a false contour in the above display, not only a double bit change but also a signal value change greater than a triple bit change is detected, and a correction for reducing the false contour is performed based on the detection result. It may be. For this purpose, for example, in the false contour correcting device shown in FIG. 7, the level comparator 16 is a digital signal that becomes H level if the value of the full-wave rectified signal is greater than or equal to the reference value, and that is L level otherwise. Can be changed to output. In this case, correction for a change in the signal value that is not equal to the false contour and that is more than a double bit change is avoided by the front-rear flatness detection circuit 30.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a false contour correction apparatus according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a false contour correction apparatus according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a false contour correction apparatus according to a third embodiment of the present invention.
FIG. 4 is a virtual signal waveform diagram for explaining the operation of the false contour correcting apparatus according to the first embodiment.
FIG. 5 is a virtual signal waveform diagram for explaining the operation of the false contour correcting apparatus according to the second embodiment.
FIG. 6 is a view for explaining the operation of a false contour correction apparatus according to a third embodiment.
FIG. 7 is a block diagram showing a detailed configuration of a false contour correction apparatus according to a third embodiment.
FIG. 8 is a virtual signal waveform diagram for explaining the operation of the false contour correcting apparatus shown in FIG. 7;
FIG. 9 is a block diagram showing a configuration of a conventional false contour correction circuit.
[Explanation of symbols]
1, 10 ... double bit change detection circuit
2a, 2b, 2c, 20... Signal correction circuit
3, 30 ... Front and rear flatness detection circuit
4, 40 ... random number generation circuit
A: Digital video signal
B: Double bit change detection signal
C1, C2, C3... Corrected video signal
D: Flatness detection signal
E ... Random number signal

Claims (10)

A false contour correction device for reducing false contour in video based on a digital video signal,
In the digital video signal, a signal value change corresponding to twice the minimum quantization unit of the digital video signal is detected as a double bit change, and a signal indicating the detection result is output as a double bit change detection signal 2 A double bit change detection circuit;
To reduce the false contour to the portion of the double bit change in the previous SL digital video signal, on the basis of the double bit change detection signal, a portion of said double bit change in said digital video signal, said minimum A false contour correction apparatus comprising: a signal correction circuit that corrects a portion in which two 1-bit changes, which are signal value changes corresponding to quantization units, exist . It is determined whether there is a signal value change more than twice the minimum quantization unit in a predetermined section before and after the double bit change in the digital video signal, and a signal indicating the result of the determination is a flat detection signal Further comprising a front and rear flat detection circuit that outputs as
The signal correction circuit, based on the flatness detection signal, changes the double bit change only when there is no signal value change more than twice the minimum quantization unit in the predetermined section before and after the double bit change. The false contour correction apparatus according to claim 1, wherein the correction for reducing the false contour is performed on a portion of the false contour. The false contour correction apparatus according to claim 2 , wherein the predetermined section is a section corresponding to five adjacent pixels in the digital video signal. It is determined whether there is a signal value change more than twice the minimum quantization unit in a predetermined section before and after the double bit change in the digital video signal, and a signal indicating the result of the determination is a flat detection signal Further comprising a front and rear flat detection circuit that outputs as
Based on the flatness detection signal, the signal correction circuit applies the false contour to the double bit change portion only when there is no signal value change more than twice the minimum quantization unit in the predetermined interval. performs correction for reducing, the interval between two of said 1 bit change to determine the position of the 1 bit change to be shorter than the predetermined interval in the correction, the false contour correcting apparatus according to claim 1. A random number generating circuit for generating a random number signal indicating a pseudo random number;
2. The false contour correction device according to claim 1 , wherein the signal correction circuit determines two positions of the 1-bit change to be generated by correction for the double-bit change portion based on the random number signal. The random number generation circuit receives a horizontal synchronizing signal corresponding to the digital video signal, and outputs the signal as the random number signal indicating a value that varies in accordance with the horizontal line indicated by the horizontal synchronization signals, according to claim 5 False contour correction device. A false contour correction method for reducing false contour in video based on a digital video signal,
A double bit change detection step of detecting a portion in which the value of an adjacent pixel is different from the minimum quantization unit of the digital video signal by twice as a double bit change portion in the video represented by the digital video signal;
To reduce the pre-Symbol false contour, based on said detection result in the detecting step, wherein the value of a pixel of double bit change portion, one bit changes the value of the adjacent pixels are only different portions said minimum quantization unit A false contour correction method comprising: a correction step of correcting so that there are two portions . A flat front and back detection step for detecting whether or not there is an adjacent pixel having a value different from that of the minimum quantization unit in a predetermined section before and after the adjacent pixel in the double bit change portion;
In the correction step, based on the detection result of the back-and-forth flatness detection step, the pixel of the double bit change portion is only when there is no adjacent pixel having a different value in the predetermined section at least twice the minimum quantization unit. The false contour correcting method according to claim 7 , wherein the value of is corrected. A flat front and back detection step for detecting whether or not there is an adjacent pixel having a value different from that of the minimum quantization unit in a predetermined section before and after the adjacent pixel in the double bit change portion;
In the correction step, based on the detection result of the back-and-forth flatness detection step, the value of the pixel of the double bit change portion is obtained only when there is no signal value change more than twice the minimum quantization unit in the predetermined section. The false contour correction method according to claim 7 , wherein the position of the 1-bit changing portion is determined such that an interval between the two 1-bit changing portions is shorter than the predetermined interval in the correction. A random number generation step for generating a pseudo-random number, wherein in the correction step, the positions of the two 1-bit change portions to be generated by the correction for the double-bit change portion are based on the pseudo-random numbers. The false contour correction method according to claim 7 , which is determined.

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