JP4294888B2 - Transmission system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for distributing high bit rate digital data to a plurality of systems and digitally transmitting the data through a plurality of transmission paths.
[0002]
[Prior art]
Nowadays, a stable video signal with little deterioration can be transmitted by compressing the video signal by the MPEG-2 system by digital signal processing, and performing digital modulation and demodulation.
In current television broadcast road race relay and the like, for example, an 800 MHz band Orthogonal Frequency Division Multiplex (OFDM) digital FPU (Field Pick-up Unit) is used. Here, the digital FPU can stably transmit a video signal (up to 8 Mbit / s digital data) captured by a TV camera mounted on a mobile relay vehicle up to a reception point.
However, at this bit rate, only a standard television system (hereinafter referred to as SDTV) video signal such as NTSC can be transmitted. Recently, a video signal of a high-definition television system (hereinafter referred to as HDTV) that has been awaited has about six times the number of pixels as that of an SDTV, and a transmission path of about 22 Mbit / s is required.
[0003]
[Problems to be solved by the invention]
As described above, the above-mentioned conventional digital FPU can only transmit SDTV video signals, HDTV transmission streams exceeding the transmission capacity are difficult to transmit, higher compression must be performed, and transmission with reduced image quality I had to transmit the stream.
An object of the present invention is to eliminate these drawbacks and to realize a transmission system capable of transmitting a high-bit-rate transmission stream with a plurality of transmission apparatuses having high versatility but low transmission rates.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, in a transmission system for transmitting and receiving digital data, a signal stream having a predetermined high bit rate is transmitted to a transmitting side by a predetermined low bit to which a time code indicating the order of the signal stream is added. A distribution unit that distributes and outputs the signal stream of n (n is an integer of 2 or more) systems of rate, and an n system transmitter that transmits each of the n signal streams at a predetermined low transmission rate, On the receiving side, n receivers that respectively receive the n signal streams transmitted at a predetermined low transmission rate, and the time code in which the received n signal streams are added to the signal streams. Is a transmission system having a reintegrating unit that reintegrates the original signal stream with a predetermined high bit rate.
Further, the distribution unit has a TStc creation unit that generates a signal stream in which a time code is added to a signal stream of a predetermined high bit rate in a predetermined cycle, and the signal stream with time code is converted into a predetermined signal stream corresponding to each system. A TS creation control unit that performs distribution control, and an n-system TS creation unit that takes in a predetermined signal stream corresponding to each system, converts the signal stream into a signal stream that matches a predetermined low transmission rate, and outputs the signal stream. The reintegration unit stores n received signal streams of n systems and extracts the added time code from the n system TC extraction units, and stores the n system TC extraction units according to the extracted time codes of the respective systems. TSr control unit that reads out the signal stream that has been read, and the above-mentioned time taken in based on the time code of each system The signal stream of the system is a transmission system with an integrated unit that integrates to become a signal stream of the original predetermined high bit rate.
Further, the n systems of TS creation units insert a dummy data stream for matching a predetermined low transmission rate with a predetermined time code into the generated signal stream.
The TStc creation unit detects a synchronization code of a signal stream having a predetermined high bit rate, and generates a signal stream in units of 205 words with a one-word time code added before the synchronization code.
Further, the TStc creation unit generates a signal stream in which a signal stream having a predetermined high bit rate is added in units of 202 words and one synchronization code word and one time code word are added.
The TStc creation unit generates a signal stream in which a signal stream of a predetermined high bit rate is added with 203 words as a unit and one synchronization code word and one time code word are added.
[0005]
That is, according to the present invention, a high bit rate signal is distributed and transmitted to a plurality of systems, and a high bit rate signal stream TS from an MPEG encoder or the like is added with a time code indicating the original order by the distribution unit. Then, it is distributed to a plurality of systems, for example, two systems of low rate signals (TSa, TSb). The signal allocated to the low-rate signal is transmitted to the reception side using a plurality of sets of transmission devices. The plurality of distribution signals are collected according to the time code by the reintegration unit, returned to the original high bit rate signal stream, and input to an MPEG decoder or the like.
Here, the signal stream TS has a specific synchronization code (47h) indicating a delimiter every 204 words (W). Based on the position of the synchronization code, a time code 1W indicating the order is added. Thereafter, the stream TS with time code is distributed to a plurality of sets for every fixed amount (205 W).
For example, if the total bit rate of the two sets of transmission equipment completely matches 205/204 times the bit rate of the signal stream TS and the transmission rates of the two sets of transmission paths are the same, the signal stream TS is as shown below. Are evenly distributed in two sets.
TSa: TSD (1), TSD (3), TSD (5), TSD (7), TSD (9), ...
TSb: TSD (2), TSD (4), TSD (6), TSD (8) ...
However, when the rates of the two sets of transmission lines are not the same, TSs are not equally distributed to the two sets alternately, and as shown below, there are cases where the fifth and sixth TSs are continuously taken into the a system. .
TSa: TSD (1), TSD (3), TSD (5), TSD (6), TSD (9) ...
TSb: TSD (2), TSD (4), TSD (7), TSD (8) ...
[0006]
Furthermore, if the total rate of the two sets of transmission equipment does not match 205/204 times the bit rate of the signal stream TS, that is, if the bit rate 205/204 of the signal stream TS is smaller than the total bit rate of the two sets, the shortage Is eliminated by inserting an unnecessary data stream Gs as dummy data.
TSa: TSD (1), TSD (3), Gs, TSD (6), TSD (8) ...
TSb: TSD (2), TSD (4), TSD (5), TSD (7), TSD (9) ...
Thus, dummy data is included in TSa and TSb according to the difference in bit rate. When the difference is large, the ratio of dummy data increases.
It should be noted that a code 255 indicating that the dummy data Gs is not necessary is added to the dummy data Gs instead of a time code having a value from 0 to 240 indicating the order.
In the signal streams TSar and TSbr distributed to the two systems and transmitted to the receiving side, unnecessary dummy data is inserted for bit rate adjustment. Since this dummy data is assigned a specific time code value 255, it can be distinguished from the required signal stream TS and can be removed.
In addition, since the required signal stream TS is not alternately distributed to the two systems, the original order cannot be restored unless the extraction order of the system a and system b is taken into consideration. For this reason, the time code is checked, the signal stream TS having a young value is sequentially extracted, and two sets of data are rearranged in the original order.
Then, the time code added by the distribution unit is removed, and only the original net data is extracted.
In this state, since the TS data is intermittent in terms of time, the memory is used to expand the time, and the signal stream TS is continuously output. Note that a clock regenerated from the amount of net data excluding dummy data is used as the output clock.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the overall configuration of the transmission apparatus of the present invention is shown in FIG. 1 and will be described in detail below. In this embodiment, in order to make the explanation easy to understand, a case in which a high bit rate signal is distributed and transmitted to two low bit rate signal streams will be described as an example, but the present invention is not limited thereto. It is obvious that the transmission signal may be distributed to three or more systems depending on the bit rate of the signal to be transmitted and the transmission rate of the transmission device.
The transmission apparatus compresses a high-definition video signal (HDTV signal) to a signal having a predetermined high bit rate (for example, 15 Mbit / s) and outputs a high bit rate signal stream TS to the transmission side. The high bit rate signal stream TS is distributed and output to two low bit rate (for example, 8 Mbit / s) signal streams TSa and TSb to which a time code TC indicating the order of the original signals is added. And two FPU transmitters (for example, 800 MHz band OFDM FPU transmitters-hereinafter referred to as transmission 800M-FPUs) 10Ta and 10Tb, respectively, for transmitting the signal streams TSa and TSb.
On the receiving side, two FPU receivers that receive the signal streams TSa and TSb (for example, an 800 MHz band OFDM FPU receiver—hereinafter referred to as a receiving 800M-FPU) 10Ra and 10Rb, The signal streams TSar and TSbr are collected according to the added time code TC and reintegrated with the original signal stream TSr, and the signal stream TSr is converted into the original high-definition video signal with a predetermined high bit rate. It has an MPEG decoder 13D for decoding.
The HDTV high-definition video signal is converted into a signal of a predetermined high bit rate (for example, 15 Mbit / s) by the MPEG encoder 13E. The high bit rate signal stream TS from the MPEG encoder 13E is added with a time code indicating the order of the original signals by the distributing unit 22, and then the low bit rate (for example, 8 Mbit / s) signal stream TSa Allocated to TSb. The signal streams TSa and TSb are transmitted to the reception side using transmissions 800M-FPU10Ta and 10Tb.
On the receiving side, the received signal streams TSa and TSb are received by the receiving 800M-FPUs 10Ra and 10Rb. Then, the signal streams TSar and TSbr received by the reintegration unit 21 are collected according to the added time code and reintegrated into the original signal stream TSr. Then, the reintegrated signal stream TSr is decoded by the MPEG decoder 13D into the original high-definition video signal having a predetermined high bit rate.
[0008]
Hereinafter, a specific configuration and operation of the distribution unit 22 will be described in detail with reference to FIGS. 2, 4, and 6.
The signal stream TS output from the MPEG encoder 13E creates a signal stream TS with a time code TC indicating the order of the signals, and the synchronization code position detection unit 23-1 in the TStc creation unit 23 and the memory 23-3. Entered. The clock CKts is input to the memory control unit 23-2 and the clock (CK) generation unit 24T. The memory write control signal Wcnt and the read control signal Rcnt from the memory control unit 23-2 are input to the memory 23-3. The output TSi of the memory 23-3 is output to the TC insertion unit 23-4 that inserts the time code TC.
The output TStc of the TC insertion unit 23 is input to a TSa creation unit 25a that creates a signal stream TSa and a TSb creation unit 25b that creates b signal stream TSb. The output CKtt of the clock (CK) generator 24T is input to the TStc generator 23, the TSa generator 25a, and the memory controller 25-1 in the TSb generator 25b. Further, aΔ and bΔ indicating the memory accumulation amounts from the memory control unit 25-1 in the TSa creation unit 25a and the TSb creation unit 25b are input to the TS creation control unit 26.
A signal RSta that instructs to read TSa from the TS creation control unit 26 is input to the memory control unit 25-1 in the TSa creation unit 25a. Further, GSta for instructing the output of the dummy data GS is input to the GS insertion unit 25-3 in the TSa creation unit 25a.
Similarly, the signal RSta instructing reading of TSb from the TS creation control unit 26 is input to the memory control unit 25-1 in the TSb creation unit 25b. In addition, GStb that instructs the output of the dummy data GS is input to the GS insertion unit 25-3 in the TSb creation unit 25b.
Signals Wsta and Wstb instructing writing to the TSa system and TSb system from the TS creation control unit 26 are input to the memory control unit 25-1 in the TSa creation unit 25a and the TSb creation unit 25b.
[0009]
Next, the operation of each unit will be described.
The synchronization code (47) position detector 23-1 detects the synchronization code included in every 204W of the input TS signal, and outputs a pulse dts indicating the temporal position. The memory control unit 23-2 and the memory 23-3 write the TS signal into the memory 23-3 in units of 204W at the speed of the clock CKts in accordance with the pulse dts indicating the synchronization code position. If 204W is continuously read out at the speed of the clock CKtt, the process of 205W period in which 1W rests is repeated. As a result, a data stream TSi having a space of 1 W is created.
The TC insertion unit 23-4 outputs the time code TC during the above 1W idle period, and creates a TStc signal of time code 1W + TS204W. Here, since the time code TC is 1W8 bits, 256 kinds of values are given. However, the time code representing the signal order is limited to 250 types, and the remaining six types are set as dummy codes. That is, the time code TC is cyclically used from No. 0 to No. 249, and for example, No. 255 is assigned as a dummy code.
The clock (CK) generator 24T generates a clock CKtt having a frequency obtained by multiplying the frequency of the input clock CKts by 205/204.
The memory control unit 25-1 and the memory 25-2 write the signal stream TStc with the time code TC in the memory 25-2 in units of 205W according to the write instruction signal Wsta.
Further, the signal stream TStc is read in units of 205 W from the memory 25-2 in accordance with the read instruction signal RSta.
The difference between the write amount and the read amount to the memory 25-2 is output as aΔ, for example, in units of 204W or 205W.
[0010]
The GS insertion unit 25-3 passes the input data when there is no dummy insertion instruction signal GSt. When there is a dummy insertion instruction signal GSt, a signal stream TSa composed of dummy data 204W having a TC value of 255 is output.
The TS creation control unit 26 compares aΔ and bΔ every 205 W of the signal stream TStc, and outputs a signal Wst instructing writing to the TS creation unit having a small Δ value. A small Δ value indicates that there is a margin in the memory storage amount. If both values are the same, the system a is prioritized and Wsta is output. As a result, the signal stream TStc is distributed and captured according to the transmission rates of the TSa creating unit 25a and the TSb creating unit 25b.
Next, when aΔ reaches a predetermined value (for example, 7) or more, output of the read instruction signal RSta is started, and the signal stream TStc accumulated in the memory 25-2 is read. Similarly, when bΔ reaches a predetermined value (for example, 7) or more, output of the read instruction signal RStb is started. As a result, the signal stream TStc distributed to the two systems is continuously output from each memory 25-2 to become signal streams TSa and TSb. Here, if there is a shortage of read data where the Δ value is less than a predetermined value due to a mismatch between the input and output bit rates, a dummy data read instruction signal GSt or GStb is output instead of the read instruction signals RSta and RStb. The dummy data GS is output instead of the data of the a system and the b system.
[0011]
Next, the overall operation of the distribution unit 22 will be described in detail using the time chart of FIG.
The output TS from the MPEG encoder 13E is distributed by the distribution unit 22 to TSD1, TSD2, TSD3, TSD4, TSD5,. The memory 23-3 creates TSi with a 1W free period immediately before this synchronization code. The TC insertion unit 23-4 inserts the time code TC during this period and creates a signal stream TStc with a time code.
The TS creation control unit compares the values of Δa and Δb and outputs the corresponding write instruction signals Wsta and Wstb. Here, when both are the same value, it sets so that priority may be given to system a. In FIG. 4, the signal stream TSD1 has the same value at the time of input, and Wsta is output. Therefore, the TSa creation unit 25a takes in TSD1. Since the input time point of TSD2 is Δa <Δb, Wstb is output so as to be taken into the b system, and the TSb creating unit 25b takes in TSD2.
Assume that Δa reaches a predetermined value at time t01. Then, the TS creation control unit 26 outputs a read instruction signal RSta to the TSa creation unit 25a. Thereby, the TSa creating unit 25a starts outputting the signal stream TSa at the rate of the transmission clock CKa. At time t02, Δb also reaches a predetermined value, and the TS creation control unit 26 outputs a read instruction signal RStb to the TSb creation unit 25b. Then, output of the signal stream TSb is started at the rate of the transmission clock CKb. Similarly, the operation continues until time t04.
At time t05, due to a mismatch in input and output bit rates, there is a shortage of read data in which the Δa value is less than a predetermined value, and instead of the read instruction signal RSta, the dummy data read instruction signal GSta is sent to the TSa generator 25a. The output of the dummy data GS instead of the a-system TSD 5 is started.
In this way, the streams TSa and TSb, which are distributed to the two systems and sometimes mixed with the dummy data, are sent to the reception point in separate transmission systems. Here, a difference occurs in the arrival time of the signal stream due to a subtle difference in the transmission path. Therefore, the timings of the streams TSar and TSbr input to the reintegration unit 21 are different from the states of TSa and TSb output from the distribution unit 22.
[0012]
Next, a specific configuration and operation of the reintegration unit 21 will be described in detail with reference to FIGS. 3, 5, and 6.
The input signal stream TSar from the reception 800M-FPU10Ra is input to the TC detection unit 27-1 and the memory 27-3 in the TC extraction unit 27a. The clock CKa synchronized with the speed of the input signal is input to the memory control unit 27-2. The TC detection unit 27-1 output dta is input to the clock (CK) generation unit 30. Outputs Wcnt and Rcnt of the memory control unit 27-2 are input to the memory 27-3. The output Ta of the memory 27-3 is input to the TC extractor 27-4 and the selection unit (SEL) 29-1 in the integration unit 29.
Similarly, the input signal stream TSbr from the reception 800M-FPU 10Rb is input to the TC extraction unit 27b. The clock CKb synchronized with the speed of the input signal is input to the TC extraction unit 27b. The output dtb of the TC extraction unit 27 b is input to the clock (CK) generation unit 30. The output Tb of the TC extraction unit 27b is input to the selection unit (SEL) 29-1 in the integration unit 29.
The output CKr of the clock (CK) generation unit 30 is input to the memory control unit 29-2 in the integration unit 29.
The output CKrr of the clock (CK) generation unit 24R is input to the memory control unit 27-2 in the TC extraction unit 27a, the TC extraction unit 27b, and the memory control 29-2 in the integration unit 29.
The output TCa of the TC extractor 27-4 in the TC extraction unit 27a is input to the TSr control unit 28. Similarly, the output TCb of the TC extraction unit 27 b is input to the TSr control unit 28.
The output REa of the TSr control unit 28 is input to the memory control unit 27-2 in the TC extraction unit 27a. The output REb of the TSr control unit 28 is input to the TC extraction unit 27b. Further, the output SEL of the TSr control unit 28 is input to the control terminal of the SEL 29-1 which is a selection unit in the integration unit 29. The signal Wst is input to the memory control unit 29-2 in the integration unit 29. The output Tsel of the SEL 29-1 is input to the memory 29-3. The outputs Wcnt and Rcnt of the memory control unit 29-2 are input to the memory 29-3. The output of the memory 29-3 is output as TSr.
[0013]
Next, the operation of each unit will be described.
The TC detection unit 27-1 in the TC extraction unit 27a checks the value of the time code TC with reference to the synchronization code in the input stream TSar, and when the value is from 0 to 240 as described above Is necessary data, a dta pulse indicating that is output.
The memory control unit 27-2 and the memory 27-3 write 205 words (W) of this TSar in the memory 27-3 with the clock CKa in accordance with this dta pulse.
The TC extractor 27-4 takes in the read TC value, holds the value, and outputs it as TCa. The TC extraction unit 27b also outputs a dtb pulse and a TCb value by the same operation.
The clock (CK) generator 24R outputs a clock frequency CKrr that is set to a frequency that is the same as or slightly higher than the sum of the frequencies of the clocks CKa and CKb.
The clock (CK) generation unit 30 generates a clock having a frequency such that the effective write count and the integrated Tsel read count are the same except for the dummy data of each stream TSar and TSbr.
As described above, when the difference Δar or Δbr between the write amount and the read amount to the memory in the TC extraction units 27a and 27b reaches a predetermined value (here, 7) or more, the TSr control unit 28 sets the time code TCa. And the value of TCb are compared, the read control signal RE is output only to the younger side, and the corresponding stream TS is read. At the same time, the SEL pulse is output to the selection unit 29-1, and the signal Wst is output to the memory control unit 29-2. That is, the Wcnt signal is output in order to switch the selection unit 29-1 and write to the memory 29-3 so that the system stream to be read is connected to the memory 29-3. Then, when reading of the stream TS to be read is completed, in the read system, the time code of the next stream TS is set to TCa or TCb, and a new time code is sent to the TSr control unit 28. Entered. Then, again, the values of TCa and TCb are compared to determine the stream of the system to be read.
The selection unit 29-1 selects and outputs the stream Ta or Tb according to the control signal SEL. The memory control unit 29-2 and the memory 29-3 take the Tsel signal into the memory 29-3 in accordance with the write instruction signal Wst and the clock CKrr. Then, the stored stream Tsel is read according to the read control signals REa and REb and the clock CKr.
[0014]
Next, the overall operation of the reintegration unit 21 will be described in detail with reference to the time chart of FIG.
In the stream a of the system a, the time code TC included in the first data TSD1 is a value 1 indicating valid data, so dta is output and taken into the memory 27-3. Further, since the time code TC of the second TSD 3 is also a value 3 indicating valid data, dta is output and taken into the memory 27-3. Since the third time code TC is a code 255 indicating dummy data, dta is not output and is not taken into the memory 27-3.
The stream TSDn having the time code TC from 0 to 240 fetched into the memory 27-3 reads only the time code value of the oldest stream TSD stored in the memory 27-3, and waits at that time. .
Similarly, each TSb with a TC fetched into the memory in the TC extraction unit 27b reads only the TC value fetched first and stands by.
Here, when the difference Δar between the write amount and the read amount in the memory 27-3 has reached a predetermined value 7 or more, the a-system has a lower TC value than the b-system TC value. If so, read out.
For example, it is assumed that the condition is satisfied at time t11. In this case, TCa and TCb obtained by extracting the added time code TC are compared, and the a system having the smaller value “1” is read. Specifically, the REa signal is output from the TSr control unit 28 to the TC extraction unit 27a. As a result, the stream TSD1 stored in the memory 27-3 is read out.
[0015]
Next, at time t12, TCa2 obtained by extracting the added time code TC is compared with TCb, and TSD2 is read by reading out the b system having a small TC value (2). .
Thereafter, a stream of any system is read according to the value of TC. Here, when the difference Δar becomes less than the predetermined value 7, reading is temporarily stopped to prevent the read data from being depleted.
As described above, TSD1 is read from system a at time t11, TSD2 from system b at time t12, TSD3 from system a at time t13, and TSD4 from system b at time t14.
Here, the SEL pulse from the TSr control unit 28 becomes level H at time t11, selects the a stream, becomes level L at time t12, selects the stream b, and becomes level H at time t13, and selects the stream a. .
The memory 29-3 takes a TSD stream in a pre-packed state which is free in time from the next TSD, and reads it with a continuous clock, thereby making a continuous state with no free time at each TSD break.
[0016]
In the above-described embodiment, the case where a high bit rate signal is distributed and transmitted in two systems has been described as an example. However, the present invention is not limited to this, and the bit rate of the input signal to be transmitted is distributed and transmitted. A device that distributes and transmits to three or more systems according to the transmission rate of the transmission device operates in the same manner. The transmission rates of the plurality of transmission apparatuses may be the same or different bit rates.
Moreover, in the said Example, as shown to (a) of FIG. 6, the input TS was divided | segmented for every 204 W, and the example which adds 1 word of TC information was shown. However, as shown in FIG. 6B, the stream structure may be such that the input TS is divided every 202 W and a synchronization code 47 and a time code of 2 W are added.
The specific configurations of the distribution unit 22m and the reintegration unit 21m in this case are shown in FIGS. 7 and 8, and portions different from those in FIGS. 2 and 3 will be briefly described.
The memory control unit 23m-2 uniquely divides the stream TS by 202W. The TC / SYNC insertion unit 23-4 inserts 47h as the synchronization code and numbers 0 to 250 as the time code into the stream TSi to create TStc. The clock generator 24T generates a clock CKtt of 204/202 times.
The reintegration unit 21m operates in units of a 204W stream TS composed of a synchronization code + time code + data (202W). In other words, in this embodiment, the part operating in units of 205 / 204W is replaced with the 202W type.
[0017]
【The invention's effect】
As described above, according to the present invention, a high bit rate data stream can be distributed and transmitted using a plurality of low transmission rate transmission apparatuses. Therefore, a system capable of transmitting a high bit rate signal even with a transmission device having high versatility but a low transmission rate is realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the overall configuration of a digital transmission system according to the present invention.
FIG. 2 is a block diagram showing an embodiment of a distribution unit of the present invention.
FIG. 3 is a block diagram showing an embodiment of the reintegration unit of the present invention.
FIG. 4 is a time chart for explaining the operation of the distribution unit of the present invention.
FIG. 5 is a time chart for explaining the operation of the reintegration unit of the present invention;
FIG. 6 is a schematic diagram showing a signal stream form to which a time code of the present invention is added.
FIG. 7 is a block diagram showing a second embodiment of the distribution unit of the present invention.
FIG. 8 is a block diagram showing a second embodiment of the reintegration unit of the present invention.
[Explanation of symbols]
10T: Transmission device (transmission side), 10R: Transmission device (reception side), 13E: MPEG encoder, 13D: MPEG decoder, 21, 21m: Reintegration unit, 22, 22m: Distribution unit, 23, 23m: TStc creation unit 24T, 24R, 30: clock generation unit, 25a, 25am: TSa creation unit, 25b, 25bm: TSb creation unit, 26, 26m: TS creation control unit, 27a, 27am: TSa extraction unit, 27b, 27bm: TSb extraction Unit, 28, 28m: TSr control unit, 29, 29m: integration unit, 23-1: synchronization code position detection unit, 23-4: TC insertion unit, 25-3: Gs insertion unit, 27-1: TC detection unit 27-4: TC extractor.

Claims (6)

In a transmission system for transmitting and receiving digital data, a signal stream of a predetermined high bit rate is transmitted to a transmission side by a predetermined low bit rate n (n is 2 or more) to which a synchronization code and a time code indicating the order of the signal stream are added. A distribution unit that distributes and outputs the signal streams to the system signal streams, and n system transmitters that transmit the n system signal streams at a predetermined low transmission rate, respectively. N-system receivers that respectively receive the n-system signal streams transmitted at a rate, and the original predetermined high bits based on the time code that is added to the received n-system signal streams to the signal streams. have a reintegration section reintegrate the rate of the signal stream,
The distribution unit includes a TStc generation unit that generates a signal stream in which the synchronization code and the time code are added to the signal stream of the predetermined high bit rate at a predetermined period, and the synchronization code and the signal stream with the time code, respectively. TS creation control unit that performs control to allocate to a predetermined signal stream corresponding to each of the systems, and the predetermined signal stream corresponding to each of the above systems is captured and converted into a signal stream that matches each predetermined low transmission rate and output The n-system TC extraction section for storing the received n-system signal streams and extracting the added time code respectively in the re-integration section, and the extracted TC extraction section According to the time code of each system, the signal stream stored from each of the n system TC extraction units is And TSr control unit out look, characterized in that it have the integration unit that integrates to the signal stream of the captured said n systems based on the time code of the respective systems will signal stream of the original predetermined high bit rate Transmission system. In a transmission system for transmitting and receiving digital data, a signal stream having a predetermined high bit rate is transmitted to a transmission side at a predetermined low bit rate n (n is an integer of 2 or more) to which a time code indicating the order of the signal stream is added. A distribution unit that distributes and outputs the signal streams of the system and an n-system transmitter that transmits the n signal streams at a predetermined low transmission rate, respectively, and transmits the signal stream at the predetermined low transmission rate. An n-system receiver for receiving the n-system signal streams, and an original signal having a predetermined high bit rate based on the time code added to the signal streams. Have a reintegration section that reintegrates into the stream,
A TStc creating unit that generates a signal stream in which the time code is added to the signal stream of the predetermined high bit rate at a predetermined period in the distribution unit, and the predetermined signal corresponding to each system of the signal stream with the time code A TS creation control unit that performs control to distribute the streams, and an n-system TS creation unit that takes in a predetermined signal stream corresponding to each of the above-described systems, converts the signal stream into a signal stream that matches a predetermined low transmission rate, and outputs the signal stream. The re-integration unit stores the received n-system signal streams, respectively, and extracts the added time code, and the n-system TC extraction units extract the time code. A TSr control unit that reads out the stored signal streams from the TC extraction unit of the system, and each of the systems The signal stream of the n lines taken on the basis of the time code have a integration unit that integrates to become a signal stream of the original predetermined high bit rate,
The n-system TS creation section inserts a dummy data stream for appropriately adjusting the predetermined low transmission rate with a predetermined time code into the generated signal stream. . 3. The signal of 205 word unit according to claim 1, wherein the TS tc creating unit detects a synchronization code of the signal stream of the predetermined high bit rate, and adds the time code of one word before the synchronization code. A transmission system for generating a stream . In claim 1 or 2, the TStc creation unit is one in which the signal stream of the predetermined high bit rate was 202 words as a unit, to generate a signal stream obtained by adding a sync code 1 word and the time code 1 word A transmission system characterized by that. In claim 1 or 2, the TStc creation unit is one in which the signal stream of the predetermined high bit rate was 203 words as a unit, to generate a signal stream obtained by adding a sync code 1 word and the time code 1 word A transmission system characterized by that. Transmission system according to claim 2 or 5, which uses the 0 th as the time code to the 256-m (m is a natural number), characterized by a dummy encoding one integer 256 from 256-m + 1 .

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