JP4290710B2 - Unit-type programmable controller - Google Patents

Description

  The present invention relates to a unit-type programmable controller including a basic casing unit incorporating a microprocessor and an additional casing unit connected to the basic casing unit.

  It has a basic chassis unit with a built-in microprocessor and an additional chassis unit connected to the basic chassis unit, and is stored in the program memory and the operating status of signals input from external operation switches and various sensors. In the unit-type programmable controller that outputs signals to electrical loads such as various external actuators and display devices in response to the sequence program, the station number setting of the input / output interface circuit provided in the basic chassis unit or extension chassis unit Various means have been proposed.

The conventional programmable controller described in Patent Document 1 includes a main unit (basic casing unit) including a microprocessor and various memories, and a plurality of input / output extension blocks (additional casing units) connected to the main unit. I have.
In addition, this programmable controller determines whether or not there is a knitting update command signal input from the outside when the input / output expansion block is changed, added, or deleted, and is specified by the knitting update command signal according to the determination result. And a rewrite setting means (station number setting means) for updating the contents of the current knitting storage means in accordance with an assignment method selected from a plurality of predetermined assignment methods (see, for example, Patent Document 1).

In the conventional device disclosed in Patent Document 1, the microprocessor in the main unit sequentially designates station numbers for the connected input / output expansion blocks.
When the station number is set, each input / output expansion block transmits the station number obtained by subtracting “1” from the designated station number to the rear. This is repeated sequentially, and the input / output expansion block that has received the station number of “0” has acquired the right to communicate with the microprocessor.

  However, in the programmable controller of the above-mentioned patent document 1, since the station number is sequentially transmitted backward to set the communication right with the microprocessor, when a large number of input / output expansion blocks are connected, the communication right is determined. Takes time. Therefore, there is a problem that high-speed processing cannot be performed.

In order to solve this problem, the conventional programmable controller described in Patent Document 2 includes a central processing unit (basic housing unit) that executes a predetermined program, and a plurality of inputs / outputs connected to the central processing unit. A unit dedicated to termination (terminal block) that is connected to the final stage of each unit (additional chassis unit) and multiple input / output units and transmits a flag to be set at the end of the initial processing of each input / output unit to the central processing unit as a termination detection signal ).
In addition, the central processing unit includes unit drop detection means for detecting that some of the plurality of input / output units are dropped when the termination detection signal transmitted from the termination dedicated unit cannot be detected ( For example, see Patent Document 2).

In the conventional apparatus disclosed in Patent Document 2, the central processing unit sets a station number individually in advance for each input / output unit at the start of operation of the programmable controller. It is confirmed by the termination detection signal from the termination dedicated unit that the station number has been set normally. In addition, the presence of the termination dedicated unit is simultaneously confirmed by this signal.
When the station number is set, the central processing unit directly designates the station number for each input / output unit and communicates with the input / output unit. Here, high-speed processing is performed by stabilizing the data bus by the termination dedicated unit.

JP 2003-167608 A JP-A-6-324721

In the programmable controller of Patent Document 2, it is possible to confirm whether the station number is set normally or whether the termination dedicated unit is connected unless the initial processing of each input / output unit is completed. Can not.
For this reason, if the termination dedicated unit is not connected, the initial processing of each input / output unit is executed while the data bus is unstable, and an abnormal state in which the termination detection signal cannot be obtained occurs. there were.
Another problem is that it is not possible to identify whether the error occurred because the station number could not be set normally due to an error in the input / output unit itself, or because the termination dedicated unit was not connected. It was.

  An object of the present invention is to solve the above-described problems, and an object thereof is to provide a unit-type programmable controller that can reliably set a station number while the data bus is stable. There is to do.

  A unit-type programmable controller according to the present invention includes a basic housing unit having a built-in program memory storing a microprocessor and a sequence program, an additional housing unit connected to the basic housing unit, and an additional housing unit. One end is bus-connected to the basic chassis unit, a through bus including a plurality of control signal lines and a multi-bit data bus, a termination block connected to the other end of the through bus, a basic chassis unit, and an extension An input / output interface circuit that is provided on at least one of the housing units and is selectively connected to the microprocessor, and is connected to the external output device in response to a signal from the external input device and the contents of the program memory. This is a unit-type programmable controller that outputs signals and has a basic housing unit. Includes a system memory including a control program serving as a station number setting means for setting a station number for identifying an input / output interface circuit, an arithmetic processing RAM memory for storing input / output information, a bus connected to a microprocessor and a through bus The input / output interface circuit includes an individual memory for storing card information and station number information indicating a station number, and the card information is an input interface circuit or an output interface circuit. And the connection block logic information indicating whether the connection position of the input / output interface circuit is the final connection position, and the termination block is connected to the input / output interface circuit. Connection to obtain connection position logic information using pull-up resistor or pull-down resistor And a termination processing confirmation circuit that outputs the connection status of the termination block to the microprocessor as a connection confirmation signal. The station number setting means is at the start of the operation of the microprocessor and is terminated by the connection confirmation signal. When the connection is confirmed, different station numbers are sequentially assigned to the input / output interface circuit from the first connection position to the final connection position included in the connection position logic information.

According to the unit type programmable controller of the present invention, the station number setting means is the connection position logic information from the first connection position when the operation of the microprocessor is started and the connection of the terminal block is confirmed by the connection confirmation signal. Are assigned and set sequentially to the input / output interface circuits up to the final connection position included.
Therefore, the station number can be set reliably with the data bus being stable.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding members and parts will be described with the same reference numerals.

Embodiment 1 FIG.
1 is a block diagram showing a unit-type programmable controller 100A according to Embodiment 1 of the present invention.
In FIG. 1, the unit type programmable controller 100A includes a basic housing unit 110A, additional housing units 120, 130, 140, 150, a termination block 160, and a through bus signal line BUS (through bus). .

  The basic housing unit 110A is supplied with power from an external power source 103 of a commercial power source (for example, AC 100V to 240V) and is connected to an external tool 108 (for example, a personal computer or a monitor) via a detachable connector (not shown). The control program can be written and the operation state can be monitored.

The basic chassis unit 110A includes a microprocessor 111, a bus interface circuit 112, a control power supply unit 113, a system memory 114A, a program memory 115A, a RAM memory 116, a watchdog timer 117, a serial interface 118, a pull-up resistor R, a constant voltage power supply. A line Vcc, a ground circuit GND, a connection confirmation signal line 11, a station number setting search signal line 12, and a penetration stop signal line 13 are included.
Here, the bus interface circuit 112, the system memory 114A, the program memory 115A, the RAM memory 116, and the serial interface 118 are connected to the microprocessor 111 by a bus.
The bus interface circuit 112 is provided with a stop logic circuit 119 (described later).

  The control power supply unit 113 is supplied with power from the external power supply 103 and supplies a stabilized voltage of, for example, DC 24V to an input signal circuit (not shown), and supplies a stabilized voltage of, for example, DC 5V to the constant voltage power supply line Vcc. Further, the constant voltage power supply line Vcc and the ground circuit GND are provided from the basic casing unit 110A to the terminal block 160 through the additional casing units 120 to 150, respectively.

The system memory 114A is, for example, a mask ROM memory, and includes various control programs (described later) shown in FIGS. The system memory 114 </ b> A includes a conversion program that converts the sequence program in the sequence language stored in the program memory 115 </ b> A into a machine language corresponding to the microprocessor 111.
The program included in the system memory 114A is stored by the manufacturer at the product shipment stage.

The program memory 115A is, for example, a non-volatile flash memory. A sequence program created by the user using, for example, a personal computer (external tool 108) is written in the program memory 115A via the serial interface 118.
The RAM memory 116 is a memory for arithmetic processing.

The watchdog timer 117 monitors the pulse width of the runaway monitoring pulse signal PLS generated by the microprocessor 111. When the pulse width exceeds a predetermined width, the watchdog timer 117 changes the runaway abnormality detection signal WD to the logic level “L” and outputs it. Further, the watchdog timer 117 stores this state, and performs a reset process and operation stop of the microprocessor 111 by the runaway abnormality detection signal WD.
Here, the runaway abnormality detection signal WD is also output to the stop logic circuit 119.
The runaway abnormality detection signal WD may be changed to a pulse signal so that the microprocessor 111 is initialized and restarted when an abnormality occurs. In this case, the same effect can be obtained.

The connection confirmation signal line 11 connected to the constant voltage power supply line Vcc via the pull-up resistor R passes through the additional enclosure units 120 to 150 and is connected to the termination processing confirmation circuit END (described later) of the termination block 160. Has been. The termination processing confirmation circuit END is connected to the ground circuit GND.
The connection confirmation signal END1 transmitted through the connection confirmation signal line 11 is a signal for recognizing that the termination block 160 is connected when the logic level is “L”. Input to the microprocessor 111.

The stop logic circuit 119 is configured by an AND element to which a runaway abnormality detection signal WD output from the watchdog timer 117 and an inverted logic signal of the connection confirmation signal END1 are input.
The stop logic circuit 119 outputs the through stop signal WD1 having the logic level “L” when the runaway abnormality detection signal WD is at the logic level “L” or when the connection confirmation signal END1 indicates that the terminal block 160 is not connected. Output to the penetration stop signal line 13. Further, the stop logic circuit 119 stops the output of the output interface circuits 132 and 152 (described later) of the additional enclosure units 130 and 150 by the penetration stop signal WD1.
The penetration stop signal line 13 is provided so as to penetrate through the additional enclosure units 120 to 150 and is connected to the respective additional enclosure units 120 to 150.

The through bus signal line BUS includes, for example, a plurality of control signal lines and a 16-bit data bus, and includes a large number of penetrating housing units 120 to 150 extending from the bus interface circuit 112 to the termination block 160. Signal wiring.
The microprocessor 111 outputs a station number setting search signal CF1 to the station number setting search signal line 12 via the bus interface circuit 112. The station number setting search signal line 12 is connected to a selection switching circuit 125a (described later) of the additional enclosure unit 120.
Further, the station number setting search signal CF1 becomes a logical level “L” when setting a station number, and supplies a station number setting command to the additional chassis unit 120 connected to the basic chassis unit 110A.

The additional enclosure unit 120 is connected to the end face position of the basic enclosure unit 110A via a connector (not shown). An external input device 121 is connected to the expansion chassis unit 120 via an input terminal block (not shown).
The external input device 121 is, for example, various operation switches provided on the operation panel or a sensor switch for confirming the operation of the actuator. The extension chassis unit 120 can input, for example, eight signals, and when more external input devices 121 are connected, the number of extension chassis units 120 connected is increased.

The expansion chassis unit 120 includes an input interface circuit 122 (input / output interface circuit), pull-up resistors 123 and 124, selection switching circuits 125a and 125b, and a connection position signal line 14.
The input interface circuit 122 includes an input signal circuit that outputs a signal from the external input device 121 to the through bus signal line BUS via a data selector (not shown), and a card information storage memory (individual memory) that stores card information. ) And a station number information memory (individual memory) indicating a station number for identifying the input interface circuit 122.

The pull-up resistor 123 has one end connected to the constant voltage power supply line Vcc and the other end connected to the connection position signal line 14. The connection position signal line 14 is connected to a connection position confirmation circuit LST (described later) of the termination block 160. The connection position confirmation circuit LST is connected to the ground circuit GND.
The connection position logic signal MDL transmitted by the connection position signal line 14 is input to the card information storage memory, and as connection position logic information indicating whether or not the connection position of the input interface circuit 122 is the final connection position. Remembered.
Here, since the additional enclosure unit 120 is not connected to the terminal block 160 (not the final connection position), the connection position signal line 14 is not connected to the ground circuit GND, and the connection position logic signal MDL is The logic level is “H”.

The selection switching circuits 125a and 125b are composed of a pair of OR elements. A logic level “H” signal is normally input to the first input terminals of the selection switching circuits 125 a and 125 b by the pull-up resistor 124. The station number setting search signal CF1 is input to the first input terminals of the selection switching circuits 125a and 125b, respectively.
An inverted logic signal of the individual completion logic signal FIN including individual completion logic information (described later) stored in the card information storage memory is input to the second input terminal of the selection switching circuit 125a. The individual completion logic signal FIN including the individual completion logic information stored in the card information storage memory is directly input to the second input terminal of the selection switching circuit 125b.
The individual completion logic signal FIN becomes a logic level “H” when the station number setting is completed.

Here, in the case where the microprocessor 111 changes the station number setting search signal CF1 to the logic level “L” in order to set the station number, the station number setting of the additional enclosure unit 120 is not completed (individual completion logic signal). When FIN is at the logic level “L”), the output of the selection switching circuit 125 b is at the logic level “L”, and the additional enclosure unit 120 obtains the right to communicate with the microprocessor 111.
The additional enclosure unit 120 that has obtained the communication right transmits card information to the microprocessor 111 via the through bus signal line BUS. Subsequently, at the next processing timing, the microprocessor 111 transmits a station number (set station number) to be set in the additional chassis unit 120 via the through bus signal line BUS, and the set station number is the station number of the additional chassis unit 120. Write to information memory.

Next, the additional enclosure unit 120 confirms and returns the written station number information to the microprocessor 111 via the through bus signal line BUS. Subsequently, the microprocessor 111 transmits the individual completion logic signal FIN as the logic level “H” to the additional enclosure unit 120 via the through bus signal line BUS.
The additional chassis unit 120 identifies the individual completion logic signal FIN in the card information storage memory as individual completion logic information for switching the selection switching circuits 125a and 125b by identifying whether or not the station number has been set. To do.
When the station number setting of the additional enclosure unit 120 is completed, a signal of logic level “L” is input to the second input terminal of the selection switching circuit 125a. At this time, a signal of logic level “L” is output from the selection switching circuit 125a. That is, the logic level “L” of the station number setting search signal CF1 is input to the first input terminals of the selection switching circuits 135a and 135b (described later) of the next additional enclosure unit 130, and the station numbers are sequentially set in the same manner. Is done.

The expansion enclosure unit 130 is connected to the end face position of the expansion enclosure unit 120 via a connector (not shown). An external load 131 (external output device) is connected to the additional enclosure unit 130 via an output terminal block (not shown).
The external load 131 is, for example, various display lamps provided on the operation panel, an electromagnetic valve for driving an actuator, or an electromagnetic relay for driving a motor. The expansion chassis unit 130 can output, for example, eight signals, and when more external loads are connected, the number of expansion chassis units 130 connected is increased.

The additional enclosure unit 130 includes an output interface circuit 132 (input / output interface circuit), pull-up resistors 133 and 134, selection switching circuits 135a and 135b, and a connection position signal line 14.
The output interface circuit 132 outputs an output signal circuit that outputs the drive signal output from the microprocessor 111 and drives the external load 131 to a latch memory (not shown) from the through bus signal line BUS, and card information that stores card information. A storage memory (individual memory) and a station number information memory (individual memory) indicating a station number for identifying the output interface circuit 132 are provided.
The configurations of the pull-up resistors 133 and 134 and the selection switching circuits 135a and 135b are the same as those of the additional enclosure unit 120 described above.

The expansion enclosure unit 140 is connected to the end face position of the expansion enclosure unit 130 via a connector (not shown). An analog input device 141 (external input device) is connected to the additional enclosure unit 140 via an input terminal block (not shown).
The additional enclosure unit 140 includes an input interface circuit 142 (input / output interface circuit), pull-up resistors 143 and 144, selection switching circuits 145a and 145b, and a connection position signal line 14.
For example, a 4-channel analog signal is input to the additional enclosure unit 140. The expansion enclosure unit 140 converts an analog signal into a digital signal by a multi-channel AD converter (not shown) in the input interface circuit 142, and converts each 12-bit digital conversion data corresponding to the 4-channel analog input into the microprocessor 111. Send to.
The configurations of the pull-up resistors 143 and 144 and the selection switching circuits 145a and 145b are the same as those of the additional enclosure unit 120 described above.

The expansion enclosure unit 150 is connected to the end face position of the expansion enclosure unit 140 via a connector (not shown). An analog load 151 (external output device) is connected to the additional enclosure unit 150 via an output terminal block (not shown).
The additional enclosure unit 150 includes an output interface circuit 152 (input / output interface circuit), pull-up resistors 153 and 154, selection switching circuits 155a and 155b, and a connection position signal line 14.

The additional enclosure unit 150 outputs, for example, 4-channel analog signals. The expansion chassis unit 150 converts a digital signal into an analog signal by a multi-channel DA converter (not shown) in the output interface circuit 152, and performs 4-channel analog to 12-bit digital data transmitted from the microprocessor 111. The converted data is output to the analog load 151.
The configurations of the pull-up resistors 153 and 154 and the selection switching circuits 155a and 155b are the same as those of the additional enclosure unit 120 described above.

When the penetration stop signal WD1 is at the logic level “L”, the output signals to the external load 131 and the analog load 151 are stopped as described above.
However, when the penetration stop signal WD1 is at the logic level “L”, the output signals for the external load 131 and the analog load 151 may be held as they are, and writing of a new output signal may be stopped.
When the penetration stop signal WD1 is at the logic level “L”, whether to stop the output signal or keep the current state is determined by the parameter written in the program memory 115A.

The terminal block 160 is provided at the end surface position of the additional enclosure unit 150.
The termination block 160 includes a termination processing circuit 162, a connection position confirmation circuit LST, and a termination processing confirmation circuit END.
The termination processing circuit 162 is connected to the terminal of the through bus signal line BUS. The termination processing circuit 162 includes a pull-down circuit that connects an impedance element for preventing reflection of a high-speed signal to the ground circuit GND. Alternatively, the termination processing circuit 162 is configured by a pull-up circuit that connects the impedance element to the constant voltage power supply line Vcc.

The connection position confirmation circuit LST connects the connection position signal line 14 connected to the pull-up resistor 153 of the extension chassis unit 150 (the extension chassis unit connected to the final connection position) within the terminal block 160 to the ground circuit GND. Connect to and invert logic.
That is, the connection position signal line 14 connected to the pull-up resistor 153 is connected to the ground circuit GND by the connection position confirmation circuit LST in the termination block 160, and the connection position logic signal MDL becomes the logic level “L”. On the other hand, the connection position signal line 14 connected to the pull-up resistors 123 to 143 of the additional enclosure units 120 to 140 (additional enclosure units connected to an intermediate connection position) is not connected to the ground circuit GND. The connection position logic signal MDL is at the logic level “H”.
Note that the pull-up resistors 123 to 153 may be changed to pull-down resistors, and the pull-down resistors may be connected to the constant voltage power supply line Vcc by the connection position confirmation circuit LST in the termination block 160 and logically inverted. In this case, the same effect can be obtained.

The termination processing confirmation circuit END is a low-level logic generation circuit for transmitting to the microprocessor 111 as the connection confirmation signal END1 transmitted by the connection confirmation signal line 11 that the termination block 160 is connected.
The pull-up resistor R provided in the basic housing unit 110A is changed to a pull-down resistor, and connected to the constant voltage power supply line Vcc by the termination processing confirmation circuit END in the termination block 160 to give a high-level logic signal. Also good. In this case, the same effect can be obtained.

The card information storage memory of the input / output interface circuits 122 to 152 (the input interface circuits 122 and 142 and the output interface circuits 132 and 152) includes, as card information, type-specific logic information, individual completion logic information, and connection position logic information. And have.
The type-specific logic information indicates whether the input / output interface circuits 122 to 152 are input interface circuits or output interface circuits. The individual completion logic information is information for identifying whether the station number setting is completed and switching the selection switching circuits 125 to 155. The connection position logic information indicates whether the connection position of the input / output interface circuits 122 to 152 is the final connection position or an intermediate connection position other than the final connection position.

In addition, information identifying whether the input / output interface circuits 122 to 152 are for ON / OFF signals or analog signals is also added to the above-mentioned logical information for each product type.
When the input / output interface circuits 122 to 152 are for analog signals, a plurality of reading or writing operations are performed between the microprocessor 111 and the multi-channel AD converter or the multi-channel DA converter.

In addition, in the extension case unit having the input / output interface circuit for the ON / OFF signal, the number of signals that can be input to and output from the extension case unit may be 16.
At this time, information identifying whether the signals that can be input / output to / from the additional chassis unit are in units of 8 points or in units of 16 points is added to the type-specific logical information. In this case, one station number is assigned to each of 8 input points or 8 output points.

In addition, the expansion housing unit having the input / output interface circuit for the ON / OFF signal may have 8 inputs / outputs.
Also in this case, one station number is assigned for every 8 input points or 8 output points.

In addition, in an extension case unit having an input / output interface circuit for analog signals, signals that can be input to and output from the extension case unit may be eight channels. Moreover, you may have 4 channels each of input / output.
At this time, information identifying whether the signal that can be input / output to / from the additional chassis unit is in units of 4 channels or in units of 8 channels is added to the logical information for each product type. In this case, one station number is assigned to each of the four input channels or the four output channels.

  The above-mentioned logic information for each product is obtained by connecting a multi-bit input terminal of a data selector provided for connection to or release from a data bus to a ground circuit GND by a printed circuit board or by connecting to a constant voltage power supply line Vcc. The wiring pattern information is determined depending on whether the connection is made. For this reason, the card information storage memory storing the type-specific logic information and the station number information memory storing the station number information are collectively referred to as individual memories, but a readable / writable memory is used for the type-specific logic information. It is not a thing.

The through bus signal line BUS is used as an address bus for setting station numbers for the input / output interface circuits 122 to 152. The through bus signal line BUS is used as a read data bus for reading card information and reading external input signals. The through bus signal line BUS is used as a data bus for writing for setting station numbers and writing control output data for the external load 131.
These usages are determined depending on command data generated by the microprocessor 111.

  In addition, for the analog signal input / output interface circuits 142 and 152 having a large number of input / output data, all data is transmitted by a plurality of communications, and the read / write timing is generated by the microprocessor 111. It is determined by a timing signal which is a control signal.

In the above description, when the input / output interface circuit is for an ON / OFF signal, one station number is assigned for every 8 input points or 8 output points, and when the input / output interface circuit is for an analog signal, the input 4 Although one station number is assigned to each channel or every four output channels, the present invention is not limited to this.
One station number may be assigned to the number of input / output points greater than 8 or the number of input / output channels greater than 4 channels. Further, one station number may be assigned to a mixture of input and output.
In these cases, similar effects can be achieved.

Hereinafter, the operation of the unit programmable controller 100A according to the first embodiment of the present invention will be described with reference to the flowcharts of FIGS. 2 and 3 together with FIG.
Step S23, step S24, and step S28 show the operation of the additional enclosure unit that is the target of station number setting, and the other steps show the operation of the microprocessor 111.
The process shown in this flowchart is executed at predetermined intervals.

  In FIG. 2, first, a power switch (not shown) is turned on, and supply of power to the unit-type programmable controller 100A is started (step S10). Further, the contents of the card information storage memory and the station number information memory in the additional enclosure units 120 to 150 are initialized by a power supply rising pulse (not shown), and the station number is set to an initial value (for example, “00”). (Step S11). As a result, all the individual completion logic signals FIN are at the logic level “L”, so that the outputs of the selection switching circuits 125a to 155a are all at the logic signal “H”.

Subsequently, the operation of the microprocessor 111 is started (step S12).
Next, it is determined whether or not the station number setting has been completed by checking a station number setting completion flag (not shown) which will be described later (step S13).
The station number setting completion flag is set when the station number setting for all the additional chassis units 120 to 150 connected to the basic chassis unit 110A is completed.
Here, in the first operation, it is determined that the station number setting is not completed (ie, No), and the process proceeds to step S14. In the operation after the next time, it is determined that the station number setting has been completed (that is, Yes), and the process proceeds to step S32 in FIG.

Subsequently, it is determined whether or not the termination block 160 is connected by checking the logic level of the connection confirmation signal END1 (step S14).
In step S14, when it is determined that the connection confirmation signal END1 is at the logic level “H” and the terminal block 160 is not connected (ie, No), the abnormal state is stored in the RAM memory 116 and the abnormality is detected. A display LED (not shown) blinks to notify abnormality (step S15).
Note that the connection confirmation signal END1 is not only when the terminal block 160 is not connected, but also when, for example, the additional enclosure units 120 to 150 and a part of the terminal block 160 are in a dropped state due to poor connector contact. Logic level “H”.

Next, the operation of the microprocessor 111 ends (step S16).
After the operation of the microprocessor 111 is finished in step S16, the operation of the microprocessor 111 shown in step S12 is started again at the next processing timing.
Therefore, if the termination block 160 is not connected, steps S12 to S16 are circulated and abnormality notification continues. In order to escape from this state, it is necessary to open the power switch.

On the other hand, if it is determined in step S14 that the terminal block 160 is connected (ie, Yes), the logic level of the station number setting search signal CF1 is changed from “H” to “L” and transmitted. (Step S17).
Here, since the station number setting search signal CF1 becomes the logic level “L”, only the output of the selection switching circuit 125b among the selection switching circuits 125b to 155b becomes the logic level “L”, and the additional enclosure unit 120 is The right to communicate with the microprocessor 111 is obtained.

Subsequently, the card information transmitted to the through bus signal line BUS by the additional enclosure unit 120 that has obtained the communication right is read (step S18), and it is determined whether normal card information is received (step S19). ).
If it is determined in step S19 that normal card information has not been received (ie, No), the process immediately proceeds to step S15.

On the other hand, if it is determined in step S19 that normal card information has been received (ie, Yes), the logic level of the connection position logic signal MDL including the connection position logic information in the card information is confirmed. Thus, it is determined whether or not the connection position of the target additional enclosure unit is an intermediate connection position other than the final connection position (step S20).
Here, since the additional enclosure unit 120 is not the final connection position, it is determined to be an intermediate connection position.

If it is determined in step S20 that the connection position is in the middle (that is, Yes), the set station number is transmitted to the through bus signal line BUS (step S21).
On the other hand, when it is determined in step S20 that the connection position is not the intermediate connection position (the final connection position) (ie, No), the additional enclosure unit for which the station number setting is to be performed is the one with the final connection position. (Step S22), the process proceeds to step S21.

Subsequently, the set station number transmitted to the through bus signal line BUS is received by the additional chassis unit 120 that has obtained the communication right and is written in the station number information memory (step S23).
Next, the station number information written in the station number information memory is confirmed and returned via the through bus signal line BUS by the additional chassis unit 120 that has obtained the communication right (step S24), and the station number information is received (step S24). S25).

Subsequently, it is determined whether or not the set station number transmitted in step S21 matches the station number information received from the additional enclosure unit 120 (step S26).
If it is determined in step S26 that the set station number does not match the station number information (that is, No), the process immediately proceeds to step S15.

On the other hand, if it is determined in step S26 that the set station number and the station number information match (that is, Yes), the station number setting has been completed for the additional enclosure unit 120 that is the target of the station number setting. Is transmitted at the logic level “H” (step S27).
Next, the individual completion logic signal FIN is received by the additional enclosure unit 120 that is the target of station number setting, and is stored in the card information storage memory as individual completion logic information (step S28).

Subsequently, based on the presence / absence of the storage of the final connection position in step S22, it is determined whether or not the station number setting for all the additional chassis units has been completed (step S29).
If it is determined in step S29 that all the station number settings have not been completed (ie, No), the process immediately proceeds to step S17.
On the other hand, if it is determined in step S29 that all the station number settings have been completed (that is, Yes), the process proceeds to step S30 (described later).

Here, at the time of setting the station number of the additional chassis unit 120, since there is no memory about the final connection position in step S22, it is determined that all the station number settings have not been completed, and the process proceeds to step S17.
In step S17, the logic level of the station number setting search signal CF1 is changed from “H” to “L” and transmitted again. At this time, since the station number setting of the additional chassis unit 120 has been completed, a signal of the logic level “L” is input to the second input terminal of the selection switching circuit 125a, and the logic level “ L "signal is output.
That is, only the output of the selection switching circuit 135 b becomes the logic level “L”, and the additional enclosure unit 130 obtains the right to communicate with the microprocessor 111.

Subsequently, the station numbers of the additional enclosure units 130 to 150 are sequentially set in the same manner as described above.
When the station number is set for the additional enclosure unit 150, it is determined in step S20 that it is not an intermediate connection position, in step S22 it is stored that it is the final connection position, and in step S29, all expansions are made. It is determined that the station number setting for the housing unit has been completed.

Next, the correspondence between the station number information and the card information is stored as card organization information (step S30), the station number setting completion flag is set (step S31), and the operation of the microprocessor 111 ends (step S16).
After the operation of the microprocessor 111 is finished in step S16, the operation of the microprocessor 111 shown in step S12 is started again at the next processing timing.

In FIG. 3, first, by checking the state of a RUN / STOP switch (not shown) operated by an operator at the site, it is determined whether or not the RUN mode is set (step S32).
If it is determined in step S32 that the mode is not the RUN mode (the STOP mode) (that is, No), is the external tool 108 (for example, a personal computer) connected and communication as a program mode being executed? It is determined whether or not (step S33).

If it is determined in step S33 that communication as a program mode is being executed (that is, Yes), the sequence program created by the external tool 108 is transferred to the program memory 115A (step S34).
Subsequently, the program mode is released or the connection of the external tool 108 is released, whereby the operation of the microprocessor 111 is finished (step S16).
After the operation of the microprocessor 111 is finished in step S16, the operation of the microprocessor 111 shown in step S12 is started again at the next processing timing.

On the other hand, if it is determined in step S33 that the communication as the program mode is not executed (that is, No), the process immediately proceeds to step S16.
Note that the state where the communication as the program mode is not executed is a state where the external tool 108 is not connected or the communication as the monitor mode is executed even when the external tool 108 is connected. .

Therefore, when the external tool 108 is not connected and the RUN / STOP switch is in the STOP mode, Step S12, Step S13, Step S32, Step S33, Step S16, and Step S12 are circulated.
At this time, the microprocessor 111 is in a state of waiting for the RUN / STOP switch to be set to the RUN mode or the external tool 108 (for example, a personal computer) to be connected to execute communication as the program mode. .

On the other hand, if it is determined in step S32 that the mode is the RUN mode (that is, Yes), by checking an initial operation flag (not shown) set at the time of the first operation in the RUN mode, It is determined whether or not the operation is an initial operation in the RUN mode (step S35).
If it is determined in step S35 that the operation is the first time (that is, Yes), the current card organization information is read (step S36).
In step S36, the microprocessor 111 designates the set station number that has already been set, and the additional enclosure unit corresponding to the designated station number transmits its own card information, thereby confirming the card organization information.

Next, the card organization information stored in step S30 of FIG. 2 is compared with the current card organization information obtained in step S36, and whether or not the card organization information is abnormal (that is, the comparison result is inconsistent). Is determined (step S37).
If it is determined in step S37 that the card organization information is abnormal (that is, Yes), the abnormal state of the card organization information is stored in the RAM memory 116, and the abnormality indication LED blinks to notify the abnormality. (Step S38), the operation of the microprocessor 111 ends (Step S16).
After the operation of the microprocessor 111 is finished in step S16, the operation of the microprocessor 111 shown in step S12 is started again at the next processing timing.
On the other hand, when it is determined in step S37 that the card organization information is not abnormal (that is, No), the process proceeds to step S43 described later.

On the other hand, if it is determined in step S35 that the operation is not the first operation (ie, No), the sequence program transferred to the program memory 115A in step S34 is executed (step S39).
Subsequently, it is determined whether or not an END instruction in the sequence program has been executed (step S40).

If it is determined in step S40 that the END instruction has not been executed (that is, No), the process proceeds to step S39 again to determine whether or not the END instruction has been executed.
Therefore, step S39 and step S40 are circulated until the END instruction is executed.
On the other hand, if it is determined in step S40 that the END instruction has been executed (that is, Yes), by confirming the logical level of the connection confirmation signal END1, the additional enclosure units 120 to 150 and the termination block 160 are confirmed. Is determined to be normally connected (step S41).

In step S41, if it is determined that the connection confirmation signal END1 is at the logic level “H” and the additional enclosure units 120 to 150 and the terminal block 160 are not normally connected (that is, No), immediately. Control goes to step S38.
On the other hand, when it is determined in step S41 that the additional enclosure units 120 to 150 and the terminal block 160 are normally connected (that is, Yes), as the execution result of the sequence program executed in step S39, Writing of an output signal, which is a control signal, is executed for the additional enclosure units 130 and 150 (step S42).

Next, input signals are read from the additional enclosure units 120 and 140, transferred to the RAM memory 116 (step S43), the process proceeds to step S32, and it is determined again whether the RUN mode is set.
In step S42 and step S43, the input / output signal is read and written by the additional enclosure unit set with the station number that matches the station number specified by the microprocessor 111 with the right to communicate with the microprocessor 111. Executed.

In the flowcharts shown in FIGS. 2 and 3, the block composed of Step S17 to Step S29 is a station number setting means. This station number setting operation is executed in the first operation after the power is turned on.
Step S14 serves as first abnormality determination means that is executed before the station number is set by the station number setting means. The first abnormality determination means determines that the termination process is not completed when the termination block 160 is not connected or is connected, but the connection confirmation signal END1 does not become the logic level “L” due to, for example, a connector contact failure. Determine.

Step S19 serves as second abnormality determination means. When the card information cannot be obtained from the input / output interface circuit before the final connection position, or the second abnormality determination means has a logic level of the connection position logic signal MDL including the connection position logic information among the card information. "" Is not obtained even after a predetermined time has elapsed, an abnormality is determined.
Step S26 serves as third abnormality determination means. The third abnormality determination means determines an abnormality when the set station number transmitted in step S21 and the station number information received in step S25 do not match.

Step S15 serves as a setting abnormality processing means. The setting abnormality processing means acts when the first, second, or third abnormality determining means makes an abnormality determination, stores the abnormal state in the RAM memory 116, and notifies the abnormality by blinking the abnormality display LED. .
Step S30 serves as card organization storage means. The card organization storage means stores the correspondence between the station number information and the card information in the RAM memory 116 as card organization information when the station number setting for all the additional enclosure units is completed.

Step S37 serves as a knitting abnormality detection means. The knitting abnormality detecting means makes an abnormality determination when the current card knitting information obtained in step S36 does not match the card knitting information stored in step S30.
Step S41 serves as dropout abnormality detection means. Even if the terminal block 160 is not connected during the operation or is connected, the dropout abnormality detecting means detects that the additional enclosure units 120 to 150 and a part of the terminal block 160 are not connected due to, for example, poor connector contact. When the connection confirmation signal END1 does not become the logic level “L” due to the dropped state, it is determined that the termination process is not completed.
Step S38 serves as a knitting abnormality processing means. The knitting abnormality processing means acts when the knitting abnormality detecting means detects an abnormality in the card knitting information, or when the dropping abnormality detecting means determines that the termination process is not completed, and stores the abnormal state in the RAM memory 116. Then, the abnormality display LED blinks to notify the abnormality.

In the above description, the drop abnormality detecting means in step S41 is executed every time the END instruction of the sequence program is executed in step S40. On the other hand, the knitting abnormality detection means in step S37 is collectively executed when it is determined in step S35 that the operation is the initial operation in the RUN mode.
However, each time the END instruction of the sequence program is executed, the card organization abnormality relating to one additional enclosure unit is checked, and multiple operation cycles are performed during operation while checking the card organization abnormality relating to other extension enclosure units sequentially. You may check for abnormal card formation.

At this time, if the calculation cycle of the unit-type programmable controller 100A is, for example, 10 ms, the card organization abnormality is checked unnecessarily frequently. However, the card program abnormality check can be executed at an appropriate frequency in the sequence program.
As one of the methods, there is a method in which card information is stored in a specific memory area accessible in a sequence program, and abnormality determination and abnormality processing are executed using a general sequence instruction.
As another method, there is a method of preparing an abnormality determination dedicated instruction that can be used in a sequence program and executing an abnormality determination using the abnormality determination dedicated instruction in the sequence program.
Thus, when performing abnormality determination and abnormality processing in a sequence program, the determination frequency and abnormality processing method based on the user's intention can be employed.

According to the unit programmable controller 100A according to the first embodiment of the present invention, the basic casing unit 110A including the microprocessor 111 and the program memory 115A in which the sequence program is stored is connected to the basic casing unit 110A. An additional chassis unit 120-150, a through bus that passes through the additional chassis unit 120-150 and is connected to the basic chassis unit 110A by bus and includes a plurality of control signal lines and a multi-bit data bus, and a basic chassis The terminal block 160 connected to the through bus so as to be opposite to the unit 110 </ b> A, and at least one of the basic chassis unit 110 </ b> A and the additional chassis units 120 to 150 are selectively connected to the microprocessor 111. Input / output interface circuit 22-152, a unit-type programmable controller 100A that outputs a signal to an external output device in response to a signal from the external input device 121 and the contents of the program memory 115A. A system memory 114A including a control program serving as station number setting means (steps S17 to S29) for setting station numbers for identifying the input / output interface circuits 122 to 152, and an arithmetic processing RAM memory 116 for storing input / output information. And a microprocessor 111 and a bus interface circuit 112 connected to the through bus. The input / output interface circuits 122 to 152 include an individual memory for storing card information and station number information indicating a station number. Input / output interface circuit 122-1 2 is logic information for each product type indicating whether it is an input interface circuit or an output interface circuit, and connection position logic information indicating whether or not the connection position of the input / output interface circuits 122 to 152 is the final connection position. The termination block 160 includes a connection position confirmation circuit LST that obtains connection position logic information using pull-up resistors 123 to 153 or pull-down resistors connected to the input / output interface circuits 122 to 152, and a termination block 160. And a termination processing confirmation circuit END that outputs a connection confirmation signal END1 to the microprocessor 111 as a connection confirmation signal END1, and the station number setting means is at the start of the operation of the microprocessor 111, and is connected to the termination block 160 by the connection confirmation signal END1. When the connection is confirmed, the connection position logical information is displayed from the first connection position. Different station numbers are sequentially assigned to the input / output interface circuits 122 to 152 up to the final connection position included in the information.
That is, the station number setting is started when the termination processing confirmation circuit END confirms the connection of the termination block 160, and the card information stored in the card information storage memory of the additional enclosure units 120 to 150 is confirmed. It is determined whether the setting is completed.
Therefore, the station number is not set when the terminal block 160 is not connected and the data bus is unstable, and the station number can be reliably set by preventing erroneous setting of the station number.

Also, among the card information, the type-specific logic information is fixed information determined by the wiring pattern provided on the printed circuit board, whereas the connection position logic information is the connection position of the input / output interface circuits 122 to 152. It is variable information that varies depending on.
However, the connection position logic information that is variable information is also determined by the termination processing confirmation circuit END that is a wiring pattern provided in the termination block 160.
Therefore, connection position logic information can be easily transmitted to the microprocessor 111 using an existing data bus without depending on a complicated control operation.

The input / output interface circuits 122 to 152 receive the station number setting search signal CF1 output from the microprocessor 111, and set the station numbers in the input / output interface circuits 122 to 152 sequentially connected to the subsequent stage when the station number setting is completed. Selection switching circuits 125 to 155 for transmitting the search signal CF1 are connected, and the card information identifies whether or not the setting of station numbers has been completed, and individual completion logic for switching the selection switching circuits 125 to 155. The station number setting means reads the card information of the input / output interface circuits 122 to 152 that received the station number setting search signal CF1 via the data bus, and receives the station number setting search signal CF1 via the data bus. The corresponding station number is written in the individual memory of the input / output interface circuits 122 to 152 After the setting of the station number is completed, the microprocessor 111 designates the station number via the data bus and communicates data with the input / output interface circuits 122 to 152 of the designated station number via the data bus. To do.
Therefore, it is possible to reliably set station numbers for the plurality of input / output interface circuits 122 to 152 using the selection switching circuits 125 to 155 without omission. Further, the input / output interface circuits 122 to 152 at the final connection position can be clarified.

The basic housing unit 110A further includes a watchdog timer 117 that monitors the operation of the microprocessor 111, and a stop logic circuit 119 that stops the output of the output interface circuit or maintains the current state. The watchdog timer 117 includes the microprocessor. When the pulse width of the runaway monitoring pulse signal PLS output from 111 becomes larger than a predetermined width, the runaway abnormality detection signal WD is output to the microprocessor 111 and the stop logic circuit 119, and the microprocessor 111 is reset. The operation is stopped or restarted, and the stop logic circuit 119 displays the through stop signal line 13 when the runaway abnormality detection signal WD is received and when the connection confirmation signal END1 indicates that the terminal block 160 is not connected. Output interface circuit output stop via Others do currently being held.
Therefore, when an abnormality occurs in the operation of the microprocessor 111, the microprocessor 111 can be promptly reset, stopped, or restarted, and the output of the output interface circuit can be stopped or the current status can be maintained.
Further, even when the connection confirmation signal END1 indicates that the termination block 160 is not connected, the output interface circuit can be stopped or the current state can be maintained by using the penetration stop signal line 13, so that the safety can be achieved with fewer control lines. Can be improved.

In addition, the system memory 114A includes at least one of a first abnormality determination unit (step S14), a second abnormality determination unit (step S19), and a third abnormality determination unit (step S26), and a setting abnormality processing unit (step S15). The first abnormality determining means determines an abnormality when the connection confirmation signal END1 indicates an unconnected state of the terminal block 160, and the second abnormality determining means is an input before the final connection position. When the card information of the output interface circuits 122 to 152 cannot be obtained, or when the input / output interface circuits 122 to 152 at the final connection position are not found even after a predetermined time has passed, the abnormality determination is made, and the third abnormality determination means The station number set in the input / output interface circuits 122 to 152, and the input / output interface circuit in which the station number is set An abnormality is determined when the station numbers confirmed and returned from 22 to 152 do not match, and the setting abnormality processing means has determined that one of the first abnormality determination means, the second abnormality determination means, and the third abnormality determination means is abnormal. In this case, the abnormal state is stored in the RAM memory 116 and notified to the outside.
Therefore, when the terminal block 160 is not connected or when the station number setting is not completed, an abnormality is determined, so that maintenance and inspection can be easily performed.

In addition, the system memory 114A is a control program serving as card knitting storage means (step S30), knitting abnormality detection means (step S37), dropout abnormality detection means (step S41), and knitting abnormality processing means (step S38). The card organization storage means stores the correspondence between the card information and the station number information in the RAM memory 116 as the card organization information when the setting of the station number is completed, and the organization abnormality detection means designates the station number. When the card organization information obtained from the input / output interface circuits 122 to 152 does not match the card organization information stored in the card organization storage means, an abnormality determination is made, and the dropout abnormality detection means receives the connection confirmation signal END1 during operation. When the terminal block 160 indicates an unconnected state, an abnormality is determined, and the knitting abnormality processing means detects the knitting abnormality. Stage, and when any one of the dropping abnormality detection means abnormality determination, stores the abnormal condition in the RAM memory 116, to notify the outside.
Therefore, the safety of the control can be improved by checking the card organization information at the start of driving and detecting the dropout abnormality during driving.

Embodiment 2. FIG.
FIG. 4 is a block diagram showing a unit programmable controller 100B according to Embodiment 2 of the present invention. Hereinafter, the description will focus on the differences from FIG.
4, the unit type programmable controller 100B includes a basic housing unit 110B, an additional housing unit 180, a termination block 160, and a through bus signal line BUS.

The basic chassis unit 110B includes a microprocessor 111, a bus interface circuit 112, a control power supply unit 113, a system memory 114B, a program memory 115B, a RAM memory 116, a watchdog timer 117, a serial interface 118, input / output boards 170a and 170b, pulls. An up resistor R, a constant voltage power supply line Vcc, a ground circuit GND, a connection confirmation signal line 11, a station number setting search signal line 12, and a through stop signal line 13 are included.
Here, the bus interface circuit 112, the system memory 114B, the program memory 115B, the RAM memory 116, and the serial interface 118 are connected to the microprocessor 111 by a bus.

The input / output board 170a corresponds to, for example, the additional enclosure unit 120 shown in FIG. The input / output board 170b corresponds to, for example, the additional enclosure unit 130 illustrated in FIG. The input / output boards 170a and 170b do not have independent casings, but are incorporated in the basic casing unit 110B.
Further, the additional enclosure unit 180 represents one of the additional enclosure units 120 to 150 shown in FIG.

Input / output devices 101a, 101b, and 101c are connected to the input / output boards 170a and 170b and the additional enclosure unit 180, respectively. The input / output boards 170a and 170b and the additional enclosure unit 180 include input / output interface circuits 172a, 172b, and 182; selection switching circuits 175a, 175b, and 185;
The input / output device 101a corresponds to, for example, the external input device 121 illustrated in FIG. The input / output device 101b corresponds to, for example, the external load 131 illustrated in FIG. The input / output device 101c corresponds to any of the external input device 121, the external load 131, the analog input device 141, and the analog load 151 shown in FIG. To do.

Each of the input / output interface circuits 172a, 172b, and 182 includes an input / output signal circuit, a multi-channel AD converter, and a multi-channel DA converter, a card information storage memory, and a station number setting memory.
In addition, the selection switching circuits 175a, 175b, and 185 are each configured by a pair of OR elements similarly to the selection switching circuits 125a and 125b shown in FIG.

As will be described later, when a predetermined station number is assigned in advance to the input / output interface circuits 172a and 172b in the basic chassis unit 110B, the final connection position in the basic chassis unit 110B. Only the selection switching circuit 175b connected to the (final stage) is necessary, and the selection switching circuit 175a is unnecessary.
That is, the station number setting search signal CF1 output from the microprocessor 111 is directly supplied to the input / output board 170b connected to the final stage.
Further, the connection position signal line 14 may be omitted in the input / output board 170a to which the terminal block 160 is not connected (not the final stage) among the input / output boards 170a and 170b in which predetermined station numbers are set in advance.

In the above description, the selection switching circuits 175a and 175b are each constituted by a pair of OR elements. However, the hardware is not used, and the selection switching circuits 175a and 175b are replaced by selection switching means controlled by the microprocessor 111. Also good.
At this time, the microprocessor 111 first reads out model code information (to be described later) from the card information to confirm the type of input / output organization of the basic chassis unit 110B. Subsequently, the microprocessor 111 transmits a station number setting search signal CF1 to the additional enclosure unit 180.

Moreover, there are various points in the scale of signals input to and output from the basic chassis unit 110B, and the number of inputs and outputs can be selected according to the scale of the control points for the application to be applied.
Here, for example, when the number of input points larger than the number of output points is required, when the number of input / output points of the provided basic housing unit 110B is insufficient compared to the actual application, or analog input / output is required. In such a case, the additional enclosure unit 180 is added as appropriate.
However, when the number of input / output points of the basic chassis unit 110B can be met, it is not necessary to connect the additional chassis unit 180, and the terminal block 160 is directly connected to the end face position of the basic chassis unit 110B.

Note that the station numbers of the input / output interface circuits 172a and 172b provided in the basic chassis unit 110B may be sequentially assigned and set in the same manner as the additional chassis units 120 and 130 shown in FIG.
However, in this embodiment, the station number “1” is preset in the input / output interface circuit 172a, and the station number “2” is preset in the input / output interface circuit 172b. That is, station numbers after station number “3” are sequentially set in the additional enclosure unit 180.

The card information storage memory of the input / output interface circuits 172a and 172b has internal / external identification logical information as card information in addition to product type logical information, individual completion logical information, and connection position logical information. .
The inside / outside identification logic information indicates that the input / output interface circuits 172a and 172b are built in the basic casing unit 110B.

Further, the card information storage memory of the input / output interface circuit 172b connected to the last stage has model code information indicating the type of input / output organization of the basic chassis unit 110B as card information.
As this model code, for example, the number of input points / output points in the basic housing unit 110B is 8 points / 8 points, 16 points / 16 points, 32 points / 32 points, and 64 points / 64 points. Depending on the device type, 4 types of 2-bit model codes are given.
However, as the model code, the station number itself given to the input / output interface circuit 172b at the final stage in the basic casing unit 110B can also be used.

Of the card information stored in the card information storage memory of the input / output interface circuits 172a and 172b and the station number information stored in the station number information memory, the connection position logic information of the input / output interface circuit 172b at the final stage is the termination block 160. The logic level changes depending on whether or not is connected, but the other card information and station number information are all fixed information.
The fixed information is obtained by connecting a multi-bit input terminal of a data selector provided for connection to or release from the data bus to the ground circuit GND by a printed circuit board or by connecting to the constant voltage power supply line Vcc. The wiring pattern information is determined depending on whether the connection is made. For this reason, the individual memory is collectively called, but a readable / writable memory is not used for information other than the connection position logical information of the input / output interface circuit 172b.
Other configurations are the same as those in the first embodiment, and the description thereof is omitted.

Hereinafter, the operation of the unit programmable controller 100B according to the second embodiment of the present invention will be described with reference to the flowcharts of FIGS. 5 and 6 together with FIG.
Note that the description of the same operation as in the first embodiment is omitted.

In FIG. 5, when it is determined in step S14 that the termination block 160 is connected (ie, Yes) by checking the logic level of the connection confirmation signal END1, the logic level of the station number setting search signal CF1 Is transmitted from “H” to “L” (step S17).
Here, when the station number setting search signal CF1 becomes the logic level “L”, the input / output board 170b including the input / output interface circuit 172b obtains the right to communicate with the microprocessor 111.
Subsequently, the card information transmitted from the input / output board 170b to the through bus signal line BUS is read (step S18), and it is determined whether normal card information is received (step S19).

If it is determined in step S19 that normal card information has been received (that is, Yes), the model code information in the card information read out in step S18 is checked to be the target. It is determined whether the input / output interface circuit is provided in the basic casing unit 110B (step S50).
Here, since the input / output interface circuit 172b is provided in the final stage, it is determined that the input / output interface circuit 172b is provided in the basic casing unit 110B.

In step S50, when it is determined that it is provided in the basic chassis unit 110B (that is, Yes), the logic level of the connection position logic signal MDL including the connection position logic information in the card information is confirmed. (Step S51).
That is, when the end block 160 is directly connected to the basic housing unit 110B, the connection position logic signal MDL is at the logic level “L”. When the terminal block 160 is connected to the basic chassis unit 110B via the additional chassis unit 180, the connection position logic signal MDL is at the logic level “H”.
Here, since the terminal block 160 is connected to the basic chassis unit 110B via the additional chassis unit 180, the connection position logic signal MDL is at the logic level “H”.

Next, based on the logic level of the connection position logic signal MDL confirmed in step S51, it is determined whether or not the additional chassis unit is connected (step S52).
If it is determined in step S52 that the additional chassis unit is not connected (that is, No), it is set in advance based on the model code information in the card information read in step S18. Card organization information including type-specific logic information corresponding to the station number is generated and stored in the RAM memory 116 (step S53), and the process proceeds to step S31.

On the other hand, if it is determined in step S52 that the additional chassis unit is connected (that is, Yes), the individual completion logic signal FIN in the input / output interface circuit 172b at the final stage is set to the logic level “H”. After starting up (step S54), the process proceeds to step S29.
In step S54, the microprocessor 111 reads out the station number of the input / output interface circuit 172b, for example, and if this station number matches the station number corresponding to the model code information confirmed in step S50, the individual completion logic signal FIN is read. Is raised to a logic level “H”.
Here, by raising the individual completion logic signal FIN to the logic level “H”, the station number setting search signal CF1 input to the selection switching circuit 175b is transmitted to the selection switching circuit 185 in the subsequent stage.

Thereafter, step S29, step S17, step S18, step S19, step S50, step S20, step S21, step S25, step S26, step S27, and step S29 are circulated, and station numbers for a plurality of additional enclosure units are sequentially set. Is done.
Subsequently, in step S20, the connection of the termination block 160 is confirmed by the logic level of the connection position logic signal MDL being changed from “H” to “L”. Next, in step S29, it is determined that the station number setting for all the additional enclosure units has been completed, and the process proceeds to step S30.

On the other hand, if it is determined in step S50 that it is not provided in the basic housing unit 110B (that is, No), the process immediately proceeds to step S20.
In step S50, it is determined that the first operation is provided in the basic casing unit 110B, and in the next and subsequent operations, it is not provided in the basic casing unit 110B. It is normal to be judged.

In the flowchart shown in FIG. 5, the block composed of step S17 to step S29 and step S50 to step S54 serves as a station number setting unit, similarly to step S17 to step S29 shown in FIG. 2.
Further, step S53 serves as a card organization storage means, similarly to step S30 shown in FIG.

In FIG. 6, when it is determined in step S35 that the initial operation flag is the initial operation in the RUN mode (ie, Yes), the process proceeds to step S43.
If it is determined in step S40 that the END instruction in the sequence program has been executed (that is, Yes), for example, it is determined whether the calculation cycle of the sequence program is shorter than a predetermined time. (Step S60).

If it is determined in step S60 that the calculation cycle of the sequence program is longer than the predetermined time (that is, No), the process proceeds to step S42.
On the other hand, if it is determined in step S60 that the operation cycle of the sequence program is shorter than the predetermined time (ie, Yes), the logical level of the connection confirmation signal END1 is confirmed to check the additional enclosure unit 180, It is then determined whether the end block 160 is normally connected (step S61).

In step S61, if it is determined that the connection confirmation signal END1 is at the logic level “L” and the additional enclosure unit 180 and the terminal block 160 are normally connected (ie, Yes), the current card The organization information is read out (step S62).
In step S62, the microprocessor 111 designates the set station number that has already been set, and the additional enclosure unit corresponding to the designated station number transmits its own card information, thereby confirming the card organization information.

Next, the card organization information stored in step S30 or S53 of FIG. 5 is compared with the current card organization information obtained in step S62, and the card organization information is abnormal (that is, the comparison result is inconsistent). Is determined (step S63).
If it is determined in step S63 that the card organization information is abnormal (that is, Yes), the abnormal state of the card organization information is stored in the RAM memory 116, and the abnormality indication LED blinks to notify the abnormality. (Step S64), the operation of the microprocessor 111 ends (Step S16).
After the operation of the microprocessor 111 is finished in step S16, the operation of the microprocessor 111 shown in step S12 is started again at the next processing timing.

On the other hand, if it is determined in step S63 that the card organization information is not abnormal (that is, No), the process proceeds to step S42.
If it is determined in step S61 that the additional enclosure unit 180 and the terminal block 160 are not normally connected (that is, No), the process immediately proceeds to step S64.

In the flowchart shown in FIG. 6, step S61 serves as a dropout abnormality detection unit, similar to step S41 shown in FIG.
Further, step S63 serves as a knitting abnormality detection means, similarly to step S37 shown in FIG.
Further, step S64 serves as a knitting abnormality processing means, similarly to step S38 shown in FIG.

Step S61 serving as a dropout abnormality detecting unit, step S62 serving as a card composition confirmation unit, step S63 serving as a composition abnormality detection unit, and step S64 serving as a composition abnormality processing unit are part of a sequence program created by the user. Is stored in the program memory 115B.
The specific control contents of the dropout abnormality detecting means, the knitting abnormality detecting means, and the knitting abnormality processing means are determined by the user program.
Also, the card organization abnormality check can be performed by checking the basic chassis unit 110B and the additional chassis unit together.

According to the unit-type programmable controller 100B according to the second embodiment of the present invention, the basic casing unit 110B including the microprocessor 111 and the program memory 115B storing the sequence program is connected to the basic casing unit 110B. An extension chassis unit 180, a penetration bus that passes through the extension chassis unit 180 and is connected to the basic chassis unit 110B, and includes a plurality of control signal lines and a multi-bit data bus, and the opposite of the basic chassis unit 110B Terminal block 160 connected to the through bus so as to be on the side, a plurality of input / output interface circuits that are provided in the basic chassis unit 110B and the additional chassis unit 180, and are selectively connected to the microprocessor 111 172a, 172b, 182 , A unit-type programmable controller 100B that outputs a signal to an external output device in response to a signal from the external input device 121 and the contents of the program memory 115B, and an input / output provided in the basic casing unit 110B A predetermined station number is set in advance for identification in the interface circuits 172a and 172b, and the basic chassis unit 110B sets a station number for identifying the input / output interface circuit 182 provided in the additional chassis unit 180. System memory 114B including a control program serving as station number setting means (steps S17 to S29 and steps S50 to S54), an arithmetic processing RAM memory 116 for storing input / output information, a microprocessor 111 and a through bus Bus in connected to And the input / output interface circuits 172a, 172b, and 182 include individual memories that store card information and station number information indicating station numbers. The card information is stored in the input / output interface circuits 172a, 172b, and 182. Type-specific logic information indicating whether the interface circuit is an input interface circuit or an output interface circuit; connection position logic information indicating whether the connection position of the input / output interface circuits 172a, 172b, and 182 is the final connection position; When the input / output interface circuits 172a, 172b, and 182 are provided in the basic casing unit 110B, and the input / output interface circuits 172a, 172b, and 182 are provided in the basic casing unit 110B, Type of input / output organization of basic chassis unit 110B The terminal block 160 includes a connection position confirmation circuit LST that obtains connection position logic information using a pull-up resistor or a pull-down resistor connected to the input / output interface circuits 172a, 172b, and 182. The terminal block 160 includes a termination processing confirmation circuit END that outputs the connection state of the termination block 160 to the microprocessor 111 as a connection confirmation signal END1, and the station number setting means is at the start of the operation of the microprocessor 111 and is based on the connection confirmation signal END1. When the connection of the terminal block 160 is confirmed, the basic chassis unit 110B is connected to the input / output interface circuit 182 from the first connection position of the additional chassis unit 180 to the final connection position included in the connection position logic information. Input / output interface circuits 172a, 172 The station following the set codes to be sequentially set allocation.
That is, the station number setting is started when the termination processing confirmation circuit END confirms the connection of the termination block 160, and the station number setting is confirmed by confirming the card information stored in the card information storage memory of the additional enclosure unit 180. It is determined whether or not it has been completed.
Therefore, the station number is not set when the terminal block 160 is not connected and the data bus is unstable, and the station number can be reliably set by preventing erroneous setting of the station number.
In addition, since a predetermined station number is assigned and set in advance to the input / output boards 170a and 170b in the basic casing unit 110B, the efficiency of station number setting can be improved.

Further, the final stage input / output interface circuit 172b built in the basic chassis unit 110B is connected to the subsequent stage when the microprocessor 111 completes reading the card information from the final stage input / output interface circuit 172b. The selection switching means for transmitting the station number setting search signal CF1 output from the microprocessor 111 is connected to the input / output interface circuit 182 in the additional enclosure unit 180, or the system memory 114B As the card information is completely read out by the microprocessor 111 from the final stage input / output interface circuit 172b built in the chassis unit 110B, the input / output interface circuit 182 in the additional chassis unit 180 connected to the subsequent stage is transferred to the input / output interface circuit 182. In contrast, the microprocessor Whether or not the card information of the input / output interface circuit 172b at the final stage has been read by the microprocessor 111, including a control program serving as a selection switching means for transmitting the station number setting search signal CF1 output by the processor 111. And the individual completion logic information for switching the selection switching means, and the input / output interface circuit 182 built in the additional enclosure unit 180 receives the station number setting search signal CF1 and sets the station number. Upon completion, the selection switching circuit 185 for transmitting the station number setting search signal CF1 is connected to the input / output interface circuit sequentially connected to the subsequent stage, and the card information of the input / output interface circuit 182 built in the additional enclosure unit 180 is connected. Identifies whether the station number setting is complete and And individual completion logic information for switching the circuit 185. The station number setting means reads the card information of the final stage I / O interface circuit 172b via the data bus, and the card of the final stage I / O interface circuit 172b. When the connection position logic information in the information indicates that it is not the final connection position, it is connected to the subsequent stage via the data bus based on the model code information in the card information of the input / output interface circuit 172b at the final stage. The corresponding station number is written to the individual memory of the input / output interface circuit 182 in the additional enclosure unit 180. After the setting of the station number is completed, the microprocessor 111 designates the station number via the data bus. Data is exchanged with the input / output interface circuit of the specified station number via the data bus.
Therefore, it is possible to reliably set the station numbers for the input / output interface circuits 182 of the plurality of additional enclosure units 180 by using the selection switching circuit 185 without omission.
In addition, the type of input / output organization of the basic chassis unit 110B is obtained from the card information stored in the input / output interface circuit 172b at the final stage in the basic chassis unit 110B, and the station number following this is obtained as the additional chassis unit 180. Can be assigned.

The basic housing unit 110B further includes a watchdog timer 117 that monitors the operation of the microprocessor 111, and a stop logic circuit 119 that stops the output of the output interface circuit or maintains the current state. The watchdog timer 117 includes the microprocessor. When the pulse width of the runaway monitoring pulse signal PLS output from 111 becomes larger than a predetermined width, the runaway abnormality detection signal WD is output to the microprocessor 111 and the stop logic circuit 119, and the reset processing of the microprocessor 111 is performed. The operation is stopped or restarted, and the stop logic circuit 119 supplies the through stop signal line 13 when the runaway abnormality detection signal WD is received and when the connection confirmation signal END1 indicates that the terminal block 160 is not connected. Output interface circuit output stop via Others do currently being held.
Therefore, when an abnormality occurs in the operation of the microprocessor 111, the microprocessor 111 can be promptly reset, stopped, or restarted, and the output of the output interface circuit can be stopped or the current status can be maintained.
Further, even when the connection confirmation signal END1 indicates that the termination block 160 is not connected, the output interface circuit can be stopped or the current state can be maintained by using the penetration stop signal line 13, so that the safety can be achieved with fewer control lines. Can be improved.

Further, the system memory 114B includes at least one of a first abnormality determination unit (step S14), a second abnormality determination unit (step S19) and a third abnormality determination unit (step S26), and a setting abnormality processing unit (step S15). The first abnormality determining means determines an abnormality when the connection confirmation signal END1 indicates the unconnected state of the terminal block 160, and the second abnormality determining means is an input before the final connection position. When the card information of the output interface circuits 172b and 182 is not obtained, or when the input / output interface circuit 182 at the final connection position is not found even after a predetermined time has elapsed, an abnormality is determined. The station number set in the output interface circuit and the station that was confirmed and returned from the I / O interface circuit in which the station number was set Is determined to be abnormal, and the setting abnormality processing means indicates the abnormal state when any of the first abnormality determination means, the second abnormality determination means, and the third abnormality determination means determines an abnormality. And informing the outside.
Therefore, when the terminal block 160 is not connected or when the station number setting is not completed, an abnormality is determined, so that maintenance and inspection can be easily performed.

Further, the system memory 114B further includes a control program serving as card knitting storage means (steps S30 and S53), and the program memory 115B includes knitting abnormality detection means (step S63) and dropout abnormality detection means (step S61). And a control program serving as knitting abnormality processing means (step S64), and the card knitting storage means stores the correspondence between the card information and the station number information in the RAM memory 116 as card knitting information when the setting of the station number is completed. And the knitting abnormality detecting means determines an abnormality when the card knitting information obtained from the input / output interface circuit designating the station number and the card knitting information stored in the card knitting storage means do not match, and a drop abnormality detecting means Indicates that the connection confirmation signal END1 is not connected to the end block 160 during operation. If any of the knitting abnormality detection means and the dropout abnormality detection means makes an abnormality determination, the knitting abnormality processing means stores the abnormal state in the RAM memory 116 and notifies the outside. .
Therefore, the abnormality process according to a use can be performed by performing abnormality determination in driving | operation with a user's sequence program.

Embodiment 3 FIG.
FIG. 7 is a configuration diagram showing a unit programmable controller 100C according to Embodiment 3 of the present invention. Hereinafter, the description will focus on the differences from FIG.
Note that the description of the same configuration as that of Embodiment 1 is omitted.

  In FIG. 7, the unit-type programmable controller 100C includes a basic casing unit 110C, an extended master station unit 190A, basic column additional casing units 180a to 180c, a basic column end block 160, and an extension station unit 290A. And an expansion column extension housing units 280a to 280c, an expansion column end block 260, and a through bus signal line BUS.

The basic chassis unit 110C includes a microprocessor 111, a bus interface circuit 112, a control power supply unit 113, a system memory 114C, a program memory 115C, a RAM memory 116, a watchdog timer 117, a serial interface 118, a pull-up resistor R, a constant voltage power supply. A line Vcc, a ground circuit GND, connection confirmation signal lines 11a and 11b, station number setting search signal lines 12a and 12b, and a through stop signal line 13 are included.
Here, the bus interface circuit 112, the system memory 114C, the program memory 115C, the RAM memory 116, and the serial interface 118 are connected to the microprocessor 111 by a bus.

The microprocessor 111 outputs the station number setting search signal CF1 for the basic column to the station number setting search signal line 12a via the bus interface circuit 112, and the station number setting search signal for the extension column to the station number setting search signal line 12b. Output CF2 (extended string station number setting search signal).
Further, the connection confirmation signal lines END1 for indicating whether or not the termination block 160 is connected to the connection confirmation signal lines 11a and 11b connected to the constant voltage power supply line Vcc via the pull-up resistor R, respectively. The extension string connection confirmation signal END2 (expansion string connection confirmation signal) indicating whether or not the termination block 260 is connected is transmitted. The connection confirmation signals END1 and END2 are input to the microprocessor 111 via the bus interface circuit 112.

The additional enclosure units 180a to 180c and 280a to 280c are representative of any of the additional enclosure units 120 to 150 shown in FIG.
Further, the end blocks 160 and 260 are the same as each other, and are given different symbols for convenience depending on the connection sequence.
The basic chassis unit 110C may include an input / output board, as in the basic chassis unit 110B shown in FIG. 4, but in this embodiment, the basic chassis unit does not include an input / output board. 110C will be described as an example.

The extended master station unit 190A is provided between the basic chassis unit 110C and the additional chassis unit 180a, and includes a buffer circuit 196 and a master station connector 197.
The extension master station unit 190A includes a constant voltage power supply line Vcc, a ground circuit GND, a connection confirmation signal line 11a, a station number setting search signal line 12a, a penetration stop signal line 13, and a penetration bus signal line BUS from the basic casing unit 110C. A through connection is made to the additional chassis unit 180a.
Here, the through bus signal line BUS connected to the additional enclosure unit 180a is referred to as a through bus signal line BUS1.

  The extension master station unit 190A branches the constant voltage power supply line Vcc, the ground circuit GND, the penetration stop signal line 13, and the penetration bus signal line BUS, and is provided in the master station connector 197 and the extension station unit 290A. The extension station unit 290A is connected via the station connector 297. Further, the connection confirmation signal line 11b and the station number setting search signal line 12b used in the extension column are also connected to the extension station unit 290A via the master station connector 197 and the slave station connector 297.

The extension station unit 290A is provided between the extension master station unit 190A and the additional enclosure unit 280a, and includes a buffer circuit 296, a slave station connector 297, and an extension string stop logic circuit 298.
The extension station unit 290A connects the constant voltage power supply line Vcc, the connection confirmation signal line 11b, the station number setting search signal line 12b, and the through bus signal line BUS to the additional enclosure unit 280a.
Here, the through bus signal line BUS connected to the additional enclosure unit 280a is referred to as a through bus signal line BUS2.

The through bus signal line BUS2 is connected to the through bus signal line BUS via a buffer circuit 296 and a buffer circuit 196 respectively configured by a driver / receiver.
The buffer circuit 196 provided in the extension master station unit 190A is effective when the wiring distance between the extension master station unit 190A and the extension station unit 290A is relatively long.
Further, the buffer circuit 296 provided in the extension station unit 290A is effective when a large number of additional enclosure units are connected to the extension station unit 290A.

The extension column stop logic circuit 298 provided in the extension station unit 290A is configured by a 2-input AND element.
The penetration stop signal WD1 output to the penetration stop signal line 13 is input to one input terminal of the extended column stop logic circuit 298, and the inverted logic signal of the connection confirmation signal END2 is input to the other input terminal. The The extended column stop logic circuit 298 outputs a through stop signal WD 2 to the through stop signal line 15.

Here, the arrangement of the connector pins provided in the extension case extension units 280a to 280c connected to the extension station unit 290A is the arrangement of the connector pins provided in the extension case units 180a to 180c in the basic row. It is the same.
In addition, the constant voltage power supply line Vcc, the ground circuit GND, the connection confirmation signal line 11b, the station number setting search signal line 12b, the penetration stop signal line 13, and the penetration bus signal line BUS2 which are representatively described in the additional enclosure unit 280a Arrangement and connector pins of constant voltage power supply line Vcc, ground circuit GND, connection confirmation signal line 11a, station number setting search signal line 12a, penetration stop signal line 13, and penetration bus signal line BUS1 which are representatively described in the additional chassis unit 180a This arrangement is the same.
However, the connection confirmation signal line 11b and the station number setting search signal line 12b, which are representatively described in the additional chassis unit 280a, are provided in the basic chassis unit 110C via the extension station unit 290A and the extension master station unit 190A. The connection confirmation signal line 11b and the station number setting search signal line 12b are connected to each other.

In addition, the basic column is configured by a basic casing unit 110C, additional casing units 180a to 180c, and a terminal block 160, as shown in FIG.
Here, the extended master station unit 190A for branching and extracting various signal lines and through bus signal lines BUS is interposed, and the microprocessor 111 has a plurality of connection confirmation signals END1, END2 and a plurality of station number setting search signals. The point of handling CF1 and CF2 is different from that shown in FIG.
Further, the extension row is different in that an extension station unit 290A is provided instead of the basic housing unit 110C.

In the above configuration, the connection confirmation signal END1 transmitted through the connection confirmation signal line 11a passes through the extension master station unit 190A and the additional enclosure units 180a to 180c, and is logically processed by the termination processing confirmation circuit END of the termination block 160. The level is set to “L”. Further, the connection confirmation signal END2 transmitted through the connection confirmation signal line 11b passes through the extension master station unit 190A, the extension station unit 290A, and the additional enclosure units 280a to 280c, and terminates the termination processing confirmation circuit of the termination block 260. The logic level is set to “L” at END.
Further, the station number setting search signal line 12a is sequentially detoured via the selection switching circuit in the additional enclosure units 180a to 180c. Further, the station number setting search signal line 12b is sequentially detoured via the selection switching circuit in the additional enclosure units 280a to 280c.

  Further, in the additional enclosure unit 180c connected to the final connection position in the basic row, the connection position logic signal MDL transmitted by the connection position signal line is logical level “L” by the connection position confirmation circuit LST of the termination block 160. To be. In addition, the connection position logic signal MDL transmitted by the connection position signal line in the additional enclosure unit 280c connected to the final connection position of the expansion row is logical level “L” by the connection position confirmation circuit LST of the termination block 260. To be.

Further, the penetration stop signal WD1 output to the penetration stop signal line 13 is the same as that when the runaway abnormality detection signal WD output from the watchdog timer 117 is at the logic level “L” or the connection confirmation signal END1 is at the logic level “H”. ”, The logic level becomes“ L ”, and the output of the output interface circuit in the additional enclosure units 180a to 180c is stopped or the current status is maintained.
On the other hand, the through stop signal WD2 output to the through stop signal line 15 includes the runaway abnormality detection signal WD at the logic level “L”, the connection confirmation signal END1 at the logic level “H”, or When the connection confirmation signal END2 is at the logic level “H”, the logic level becomes “L”, and the output of the output interface circuit in the additional chassis units 280a to 280c is stopped or the current status is maintained.

  If the output of the output interface circuit in the expansion column expansion unit 280a to 280c is not stopped or the current status is not maintained due to the connection abnormality of the expansion column units 180a to 180c in the basic column, the expansion column stop logic Instead of inputting the penetration stop signal WD1 at one input terminal of the circuit 298, a runaway abnormality detection signal WD output from the watchdog timer 117 may be input.

Hereinafter, the operation of the unit programmable controller 100C according to the third embodiment of the present invention will be described with reference to FIG.
Note that the description of the same operation as in the first embodiment is omitted.

First, at the start of operation of the unit-type programmable controller 100C, if it is determined that the end blocks 160 and 260 are connected, the station number setting for the additional case units 180a to 180c in the basic row is performed by the station number setting search signal CF1. Is done.
Subsequently, the station number is set for the additional chassis units 280a to 280c in the expansion row by the station number setting search signal CF2.
Here, the station number of the additional chassis unit 280a is the station number following the station number of the additional chassis unit 180c connected to the final connection position in the basic row.

According to the unit-type programmable controller 100C according to the third embodiment of the present invention, the extension master station unit provided between the basic housing unit 110C and the terminal block 160, and the extension station connected to the extension master station unit And an extension column extension housing unit 280a to 280c and an extension column termination block 260 connected to the subsequent stage of the extension station unit, and the extension master station unit and the extension station unit are connected to the through bus The microprocessor 111 includes a buffer circuit, and the microprocessor 111 is a station number setting search signal CF1 for setting the station number of the input / output interface circuit in the basic column composed of the basic chassis unit 110C, the additional chassis units 180a to 180c, and the termination block 160. It is a different signal, and the expansion row expansion enclosure unit 280a The expansion column input / output interface circuit provided in 280c outputs the expansion column station number setting search signal CF2 for starting the station number setting, and the microprocessor 111 receives a connection confirmation signal END1 indicating the connection state of the termination block 160. The extension column connection confirmation signal END2 indicating the connection state of the extension column termination block 260 is input, and the station number setting means is connected to the basic chassis unit 110C or the extension column input / output interface circuit. A station number subsequent to the station number set in the input / output interface circuit of the additional enclosure units 180a to 180c is set.
Therefore, a large number of additional enclosure units can be arranged in a double row to reduce the installation size.
In addition, by connecting a through bus including a plurality of control signal lines and a data bus via a buffer circuit, it is possible to suppress a voltage drop of the control signal line and the data bus, and to suppress noise circulation. be able to.
Further, when setting the station number, the station number of the input / output interface circuit connected to the final position in the front row is confirmed using the connection position logic signal MDL, so that the subsequent station number is easily set in the input / output interface circuit in the back row. be able to.

The basic chassis unit 110C further includes a watchdog timer 117 that monitors the operation of the microprocessor 111, and the extension station unit stops output of the output interface circuits provided in the extended column extension chassis units 280a to 280c. Alternatively, the watchdog timer 117 further includes a stop logic circuit 298 that holds the current state, and the watchdog timer 117 includes the microprocessor 111 and the stop logic when the pulse width of the runaway monitoring pulse signal PLS output from the microprocessor 111 becomes larger than a predetermined width. A runaway abnormality detection signal WD is output to the circuit 298 to perform reset processing and operation stop or restart of the microprocessor 111. The stop logic circuit 298 receives the runaway abnormality detection signal WD and The connection confirmation signal END2 In the case shown the unconnected state of the click 260, performs output stop or currently being held in the output interface circuit via the through-stop signal line 15.
Therefore, when an abnormality occurs in the operation of the microprocessor 111, the microprocessor 111 can be promptly reset, stopped, or restarted, and the output of the output interface circuit can be stopped or the current status can be maintained.
Even when the connection confirmation signal END2 indicates the unconnected state of the extended column termination block 260, the output interface circuit can be stopped using the through stop signal line 13 or the current state can be maintained. Safety can be improved.

Embodiment 4 FIG.
FIG. 8 is a block diagram showing a unit programmable controller 100D according to Embodiment 4 of the present invention. Hereinafter, the description will be focused on the difference from FIG.
Note that the description of the same configuration as that of Embodiment 3 is omitted.

  In FIG. 8, the unit-type programmable controller 100D includes a basic chassis unit 110D, basic chassis extension chassis units 180d and 180e, an extension master station unit 190B, a terminal block 160, an extension station unit 290B, The extended enclosure units 280d and 280e in the row, the end block 260, the extended grandchild station unit 390B, the extended enclosure units 380d and 380e in the extended grandchild row, and the end block 360 are provided.

The basic chassis unit 110D includes a microprocessor 111, a bus interface circuit 112, a system memory 114D, a program memory 115D, a RAM memory 116, a watchdog timer 117, connection confirmation signal lines 11a to 11c, station number setting search signal lines 12a to 12c, And a through stop signal line 13.
Although the control power supply unit 113, serial interface 118, pull-up resistor R, constant voltage power supply line Vcc, ground circuit GND, and through bus signal line BUS shown in FIG. 7 are provided in the same manner, FIG. Then, illustration is abbreviate | omitted.

The microprocessor 111 cooperates with the system memory 114D to output the base number station number setting search signal CF1 to the station number setting search signal line 12a via the bus interface circuit 112, and to the station number setting search signal line 12b. The station number setting search signal CF2 for the extension string is output, and the station number setting search signal CF3 for extension grandchild string (the station number setting search signal for extension grandchild string) is output to the station number setting search signal line 12c.
The connection confirmation signal lines 11a to 11c connected to the constant voltage power supply line Vcc through the pull-up resistor R are connected to the connection confirmation signal END1 for the basic column indicating whether or not the termination block 160 is connected. , An extension column connection confirmation signal END2 indicating whether or not the termination block 260 is connected, and an extension grandchild connection confirmation signal END3 (extended grandchild column connection) indicating whether or not the termination block 360 is connected. Confirmation signal) is transmitted. The connection confirmation signals END1 to END3 are input to the microprocessor 111 through the bus interface circuit 112.

The additional enclosure units 180d, 180e, 280d, 280e, 380d, and 380e include connection confirmation signal lines 11a to 11c, station number setting search signal lines 12b and 12c, a penetration stop signal line 13, and a constant voltage power supply line Vcc (not shown). The ground circuit GND and the through bus signal line BUS are through-connected.
Other configurations of the additional enclosure units 180d, 180e, 280d, 280e, 380d, and 380e are the same as those of the additional enclosure units 180a to 180c and 280a to 280c shown in FIG.
The end blocks 160 to 360 are the same as each other.

Here, the extension enclosure units 280d, 280e, 380d, and 380e are not necessarily connected through the connection confirmation signal lines 11b and 11c and the station number setting search signal lines 12b and 12c.
However, since the additional enclosure units are standardized by configuring the additional enclosure units 280d, 280e, 380d, and 380e as described above, they can be used in any row.

The extension master station unit 190B is provided between the extension chassis unit 180b and the terminal block 160, and includes a master station connector 197. Note that illustration of the buffer circuit 196 shown in FIG. 7 is omitted.
The extension master station unit 190B includes connection confirmation signal lines 11a to 11c, station number setting search signal lines 12a to 12c, a penetration stop signal line 13, and a connection position signal line 14, a constant voltage power supply line Vcc, a ground circuit GND, Further, the through bus signal line BUS is through-connected.
Here, since the extended master station unit 190B is configured as described above, all the data is exchanged regardless of the position between the basic housing unit 110D and the terminal block 160. can do.

  The extension master station unit 190B branches the connection confirmation signal lines 11b and 11c, the station number setting search signal lines 12b and 12c, and the penetration stop signal line 13, and is provided in the master station connector 197 and the extension station unit 290A. The extension station unit 290B is connected to the slave station first connector 297a.

The extension station unit 290B is provided between the extension master station unit 190B and the additional enclosure unit 280d, and includes a slave station first connector 297a, a slave station second connector 297b, and an extension string stop logic circuit 298. Yes.
The extension station unit 290B penetrates and connects the connection confirmation signal line 11b and the station number setting search signal line 12b to the additional enclosure unit 280d.
Further, the extension station unit 290B includes a connection confirmation signal line 11c, a station number setting search signal line 12c, and a penetration stop signal line 15 that are connected to the slave station second connector 297b and the extension slave station unit 390B. It connects to the extension grand station unit 390B via the connector 397a.

The extension column stop logic circuit 298 provided in the extension station unit 290B is configured by a 2-input AND element.
The penetration stop signal WD1 output to the penetration stop signal line 13 is input to one input terminal of the extended column stop logic circuit 298, and the inverted logic signal of the connection confirmation signal END2 is input to the other input terminal. The The extended column stop logic circuit 298 outputs a through stop signal WD 2 to the through stop signal line 15.

The extended slave station unit 390B is provided between the extension station unit 290B and the additional enclosure unit 380d, and includes a first slave station first connector 397a, a second slave station second connector 397b, and an extended grandchild row stop logic circuit 398. It is out.
The extended sub-station unit 390B connects the connection confirmation signal line 11c and the station number setting search signal line 12c through the extension housing unit 380d.

The extended grandchild train stop logic circuit 398 provided in the extended grandchild station unit 390B is configured by a 2-input AND element.
A penetration stop signal WD2 output to the penetration stop signal line 15 is input to one input terminal of the extended grandchild stop logic circuit 398, and an inverted logic signal of the connection confirmation signal END3 is input to the other input terminal. Is done. The extension grandchild stop logic circuit 398 outputs a penetration stop signal WD 3 to the penetration stop signal line 16.

  Here, the extension cabinet units for the base row, the extension row, and the extension grandchild row have the same structure, and the extension station unit 290B and the extension grandchild station unit 390B have the same structure. Things are used.

Note that the extension station unit 290A shown in FIG. 7 is not configured to use the extended slave station unit, and therefore, the extension station unit 290A includes a slave station provided in the extension station unit 290B of FIG. A connector corresponding to the second connector 297b is not provided.
Further, in FIG. 7, by connecting the connection confirmation signal lines 11a and 11b and the station number setting search signal line 12b through the extension chassis units 180a to 180c and 280a to 280c, the extension master station unit 190A is connected to the basic chassis. It can be provided at any position between the unit 110C and the end block 160.

  In FIG. 8, the arrangement of the connector pins of the penetration stop signal lines 13, 15 and 16 is the same. That is, three penetration stop signal lines do not penetrate through each additional enclosure unit, but one penetration stop signal line is penetrated by the same connector pin. The same applies to the penetration stop signal lines 13 and 15 shown in FIG.

  In the above configuration, the connection confirmation signal END1 for the basic column transmitted by the connection confirmation signal line 11a passes through the additional enclosure units 180d and 180e and the extended master station unit 190B and confirms the termination process of the termination block 160. The circuit END is set to a logic level “L”.

Further, the connection confirmation signal END2 for the extended column transmitted by the connection confirmation signal line 11b is used for the extension chassis units 180d and 180e, the extension master station unit 190B, the extension station unit 290B, and the extension chassis units 280d and 280e. The signal passes through and is set to the logic level “L” by the termination processing confirmation circuit END of the termination block 260.
Here, in the extension chassis units 280d and 280e, the signal is transmitted using the connection confirmation signal line 11a for the connection confirmation signal END1, and the connection confirmation for the connection confirmation signal END2 is performed in the extension station unit 290B. Transfer connection is made to the signal line 11b.

Further, the connection confirmation signal END3 for the extended grandchild train transmitted by the connection confirmation signal line 11c includes the extension chassis units 180d and 180e, the extension master station unit 190B, the extension station unit 290B, the extension grandchild station unit 390B, and the extension. The signal passes through the housing units 380d and 380e and is set to the logic level “L” by the termination processing confirmation circuit END of the termination block 360.
Here, in the extension chassis units 380d and 380e, a signal is transmitted using the connection confirmation signal line 11a for the connection confirmation signal END1, and the extension station unit 290B and the extension grandchild station unit 390B Transfer connection is made to the connection confirmation signal line 11c for the sequential connection confirmation signal END3.

Further, the station number setting search signal line 12a for the basic column is sequentially detoured via the selection switching circuit in the additional enclosure units 180d and 180e and connected to the subsequent stage.
Further, the station number setting search signal line 12b for the extension string passes through the extension casing units 180d and 180e, the extension master station unit 190B, and the extension station unit 290B, and passes through the selection switching circuit in the extension casing units 280d and 280e. Bypass detours are routed sequentially and connected to the subsequent stage.
Here, in the extension chassis units 280d and 280e, a signal is transmitted using the station number setting search signal line 12a for the station number setting search signal CF1, and for the station number setting search signal CF2 in the extension station unit 290B. Is connected to the station number setting search signal line 12b.

Further, the station number setting search signal line 12c for the extended grandchild row penetrates through the additional chassis units 180d and 180e, the extended master station unit 190B, the extension station unit 290B, and the extended slave station unit 390B, and the extended chassis unit 380d. 380e is sequentially routed via a selection switching circuit in 380e and connected to the subsequent stage.
Here, in the extension chassis units 380d and 380e, signals are transmitted using the station number setting search signal line 12a for the station number setting search signal CF1, and the extension grand station unit 390B and the extension station unit 290B sequentially The transfer connection is made to the station number setting search signal line 12c for the station number setting search signal CF3.

  In addition, in the additional enclosure unit 180e connected to the final connection position in the basic row, the connection position logic signal MDL transmitted by the connection position signal line 14 passes through the extended master station unit 190B and passes through the extension block unit 160B. The connection level confirmation circuit LST sets the logic level to “L”.

Hereinafter, the operation of the unit programmable controller 100D according to the fourth embodiment of the present invention will be described with reference to FIG.
Note that description of operations similar to those of the third embodiment is omitted.

First, at the start of the operation of the unit-type programmable controller 100D, if it is determined that the end blocks 160 to 360 are connected, the station number setting for the additional case units 180d and 180e in the basic row is performed by the station number setting search signal CF1. Is done.
Subsequently, the station number is set for the additional chassis units 280d and 280e in the expansion row by the station number setting search signal CF2.
Next, the station number is set for the expanded chassis units 380d and 380e of the extended grandchild row by the station number setting search signal CF3.
Here, the station number of the expansion chassis unit 280d is the station number following the station number of the expansion chassis unit 180e connected to the final connection position in the basic column, and the station number of the expansion chassis unit 380d is the last connection in the expansion column. The station number follows the station number of the additional enclosure unit 280e connected to the position.

According to the unit-type programmable controller 100D according to the fourth embodiment of the present invention, the extension master station unit provided between the basic housing unit 110D and the terminal block 160, and the extension station connected to the extension master station unit Unit, extension column extension housing units 280d and 280e and extension column termination block 260 connected to the subsequent stage of the extension station unit, the extension slave station unit connected to the extension station unit, and the subsequent stage of the extension slave station unit And an extended grandchild station termination block 360, and the extended master station unit, the extension station unit, and the extended grandchild station unit are buffers connected to the through bus. Including a circuit, the microprocessor 111 includes a basic chassis unit 110D, an additional chassis unit 1 This is a signal different from the station number setting search signal CF1 for setting the station number of the input / output interface circuit of the basic column composed of 0d, 180e and the termination block 160, and is provided in the expansion column provided in the expansion column expansion enclosure units 280d, 280e The station number setting search signal CF2 for the extended column for starting the station number setting of the input / output interface circuit is output, and the station number setting of the expanded grandchild column input / output interface circuit provided in the expanded grandchild column expansion chassis units 380d and 380e The extension grandchild station number setting search signal CF3 for starting the output is output, and the microprocessor 111 is a signal different from the connection confirmation signal END1 indicating the connection state of the termination block 160. The connection confirmation signal END2 for the extended column indicating the connection state is input and A connection confirmation signal END3 for the extended grandchild row indicating the connection state of the grandchild row termination block 360 is input, and the station number setting means sends the basic case unit 110D or the extended case unit 180d to the extended row input / output interface circuit. A station number following the station number set in the input / output interface circuit of 180e is set, and a station number following the station number set in the extended column input / output interface circuit is set for the extended grandchild column input / output interface circuit.
Therefore, a large number of additional enclosure units can be arranged in a double row to reduce the installation size.
In addition, by connecting a through bus including a plurality of control signal lines and a data bus via a buffer circuit, it is possible to suppress a voltage drop of the control signal line and the data bus, and to suppress noise circulation. be able to.
Further, when setting the station number, the station number of the input / output interface circuit connected to the final position in the front row is confirmed using the connection position logic signal MDL, so that the subsequent station number is easily set in the input / output interface circuit in the back row. be able to.

The basic chassis unit 110D further includes a watchdog timer 117 that monitors the operation of the microprocessor 111, and the extension station unit and the extended grandchild station unit are the extension column extension chassis units 280d and 280e and the extension grandchild column extension. It further includes stop logic circuits 298 and 398 for stopping the output of the output interface circuits provided in the housing units 380d and 380e or holding the current state, and the watchdog timer 117 is a pulse of the runaway monitoring pulse signal PLS output from the microprocessor 111. When the width becomes larger than the predetermined width, a runaway abnormality detection signal WD is output to the microprocessor 111 and the stop logic circuits 298 and 398, and the microprocessor 111 is reset and stopped or restarted. Logic circuit 298, 98, when the runaway abnormality detection signal WD is received, and when the extended column connection confirmation signal END2 or the extended grandchild column connection confirmation signal END3 is not connected to the extended column termination block 260 or the extended grandchild column termination block 360. In this case, the output of the output interface circuit is stopped or the current status is maintained through the penetration stop signal lines 15 and 16.
Therefore, when an abnormality occurs in the operation of the microprocessor 111, the microprocessor 111 can be promptly reset, stopped, or restarted, and the output of the output interface circuit can be stopped or the current status can be maintained.
Even when the connection confirmation signals END2 and END3 indicate the unconnected state of the extended column termination block 260 or the extended grandchild column termination block 360, the output interface circuit is stopped using the through stop signal lines 15 and 16, or the current state Since it can hold | maintain, safety | security can be improved with few control lines.

Among the plurality of station number setting search signals, the signal lines for transmitting the station number setting search signals CF2 and CF3 excluding the station number setting search signal CF1 for the basic column and the signal lines for transmitting the plurality of connection confirmation signals are extended. The signal line that transmits the base station station number setting search signal CF1 and the signal line that transmits the connection position logic information are connected to the master station unit and the extension chassis units 180d and 180e through the extension master station. It is connected through through the unit.
Therefore, the extension master station unit can be connected at any position from the front stage position to the rear stage position of the additional enclosure units 180d and 180e.

Of the plurality of station number setting search signals, the signal lines for transmitting the station number setting search signals CF2 and CF3 excluding the station number setting search signal CF1 for the basic column, and the signal lines END1 and END2 for transmitting the plurality of connection confirmation signals, The END3 and the END3 are cross-connected in the extension station unit, respectively, so that they are transferred to different signal lines.
For this reason, the extended chassis unit can use the same standardized structure regardless of the basic row, the extended row, and the extended grandchild row.
In addition, the extension station unit and the extension grand station unit can use the same standardized structure.

Embodiment 5 FIG.
FIG. 9 is a block diagram showing a unit programmable controller 100E according to Embodiment 5 of the present invention. Hereinafter, a description will be given with reference to FIG.
Note that the description of the same configuration as that of Embodiment 4 is omitted.

  In FIG. 9, the unit-type programmable controller 100E includes a basic casing unit 110E, an extended master station unit 190C, basic casing additional casing units 180a to 180c, a terminal block 160, an extension station unit 290C, The extended enclosure units 280a to 280c in the row, the end block 260, the extended grandchild station unit 390C, the extended enclosure units 380a to 380c in the extended grandchild row, and the end block 360 are provided.

Here, the basic column includes a basic casing unit 110E, an extended master station unit 190C, additional casing units 180a to 180c, and a terminal block 160.
Further, the extension column is composed of an extension station unit 290C, additional enclosure units 280a to 280c, and a terminal block 260.
The extended grandchild row includes an extended grandchild station unit 390C, additional enclosure units 380a to 380c, and a terminal block 360.

The basic chassis unit 110E includes a CPU board 1 on which a microprocessor 111 and various memories are mounted, an input / output board 2 on which an input / output interface circuit is mounted, a power board 3 on which a control power unit 113 is mounted, An input / output connector 9 serving as a terminal block connector is included.
Here, the CPU board 1 and the input / output board 2 are connected to each other by a connector. The input / output board 2 and the power supply board 3 are connected to each other by a connector.
The input / output board 2 is provided with a sending side connector 8a (second sending side connector) for connecting the extension master station unit 190C.
The input / output connector 9 is a terminal block connector for connecting input / output devices corresponding to the input / output devices 101a and 101b in FIG.

An extension board 4a, which is a double-sided printed board on which a buffer circuit is mounted, is attached and fixed to the extension master station unit 190C.
A receiving-side connector 7 that mates with the sending-side connector 8a of the basic housing unit 110E is surface-mounted on the expansion board 4a. Further, on the back surface of the extension board 4a with respect to the receiving side connector 7, a post-stage sending side connector 8 is surface-mounted.
Note that each terminal of the receiving connector 7 in the extension master station unit 190C and each terminal of the sending connector 8 are connected to each other by through-hole plating provided on the extension board 4a.
Further, a master station connector 197 is connected and fixed to the extension board 4a, and is connected to a slave station first connector 297a provided in the extension station unit 290C by a connection cable (not shown).

An extension board 6a, which is a double-sided printed board, is attached and fixed to the extension housing unit 180a.
On the extension board 6a, circuit components such as an input / output interface circuit and a selection switching circuit are mounted, and a receiving-side connector 7 that engages with the preceding-stage sending-side connector 8 and a sending-side connector 8 for the subsequent stage are surface-mounted. ing.

Here, the terminals other than the terminal to which the station number setting search signal line 12a for transmitting the station number setting search signal CF1 is connected among the terminals of the receiving side connector 7 and the terminals of the sending side connector 8 in the additional enclosure unit 180a. The terminals are connected to each other by through-hole plating provided on the extension board 6a.
The station number setting search signal CF1 inputted to the receiving side connector 7 is connected to the sending side connector 8 via the selection switching circuit in the extension board 6a and outputted to the subsequent stage.
Further, an input / output connector 9a serving as a terminal block connector is connected and fixed to the extension board 6a and connected to input / output devices corresponding to the input / output devices 101a to 101c of FIG.
The configuration of the additional enclosure units 180b and 180c is the same as that of the additional enclosure unit 180a.

A terminal block 160 is connected to the subsequent stage of the additional enclosure unit 180c connected to the final connection position in the basic row.
A termination substrate 6e, which is a printed circuit board, is attached and fixed to the termination block 160. Circuit components such as a termination processing circuit, a connection position confirmation circuit, and a termination processing confirmation circuit are mounted on the termination board 6e, and a reception side connector 7 (second reception side connector, A third receiving side connector) is surface mounted.
The terminal block 160 also serves as a dust-proof cover for the sending-side connector 8, and is fitted and attached to the end face position of the basic housing unit 110E, the extended master station unit 190C, or the additional housing units 180a to 180c. .
Here, the basic casing unit 110E and the end block 160 are shipped in a mutually intertwined manner.

An extension board 4b, which is a double-sided printed board mounted with a buffer circuit, is attached and fixed to the extension station unit 290C.
A slave station first connector 297a and a slave station second connector 297b are connected and fixed to the extension board 4b. The slave station first connector 297a is connected to the master station connector 197 by a connection cable. The slave station second connector 297b is connected to the grandchild station first connector 397a provided in the extended grandchild station unit 390C by a connection cable.
Further, on the extension board 4b, a sending-side connector 8 (third sending-side connector) for the rear stage is surface-mounted.
Here, the extension station unit and the termination block 260 are shipped after being engaged with each other.

Note that the extension station unit 290C and the extended grandchild station unit 390C are identical to each other as hardware, and different reference numerals are given for convenience depending on the connection sequence.
Further, the additional enclosure units 180a to 180c, 280a to 280c, and 380a to 380c respectively provided in the basic row, the extended row, and the extended grandchild row have different functions depending on the models, but the same functions are provided. It has the same structure and can be freely connected to any column.
The same applies to the end blocks 160 to 360, and the hardware is the same as each other.

In FIG. 9, the X-axis indicates the left-right direction with respect to the drawing, the Y-axis indicates the front-rear direction with respect to the drawing, and the Z-axis indicates the vertical direction with respect to the raw surface.
The unit-type programmable controller 100E is attached via a DIN rail (not shown) with the lower side of FIG. 9 as a wall surface.
Therefore, the CPU board 1, the input / output board 2, and the power supply board 3 are installed in parallel to the wall surface, and the input / output connector 9 has a terminal block structure that is long in the left-right direction in two vertical rows.
That is, the dimension in the left-right direction of the basic casing unit 110E is determined by the number of input / output units built in the basic casing unit 110E.

According to the unit-type programmable controller 100E according to the fifth embodiment of the present invention, the additional enclosure units 180a to 180c, 280a to 280c, and 380a to 380c are double-sided printed boards on which an input / output interface circuit and a selection switching circuit are mounted. The extension board 6a includes a receiving-side connector 7 on the surface of one wiring surface and a sending-side connector 8 on the other wiring surface. A plurality of control signal lines and a plurality of bit data buses excluding the signal line for transmitting the signal CF1 are connected to an extension casing unit that penetrates from the receiving side connector 7 to the sending side connector 8 and is connected to the subsequent stage. Station number setting search signal CF1 is input from the receiving connector 7 to the selection switching circuit and is selected. The output signal from the Rikae circuit, as station number setting search signal for the next stage of the expanded chassis units are delivered from the delivery side connector 8.
for that reason,
Therefore, the bypass connection of the station number setting search signal CF1 and the through connection of other control signal lines and data buses can be easily performed.

The basic housing unit 110E further includes a second sending-side connector 8a that engages with the receiving-side connector 7, and the end block 160 further includes a second receiving-side connector 7 that engages with the sending-side connector 8a. The sending-side connector 8a and the second receiving-side connector 7 are shipped after being engaged with each other, and when the additional housing unit is expanded and used, the second receiving-side connector 7 is connected to the final connection position. Relocation contract is made to the sending connector 8 of the unit.
Therefore, it is possible to prevent the occurrence of operation troubles due to unarrangement of the end block 160 or connection leakage.

Also, an extension master station unit provided between the basic chassis unit 110E and the terminal block 160, an extension station unit connected to the extension master station unit, and an extension column extension connected to the subsequent stage of the extension station unit Enclosure units 280a to 280c and extended column termination block 260, an extended grandchild station unit connected to the extension station unit, an extended grandchild row additional chassis unit 380a to 380c and an extension connected to the subsequent stage of the extended slave station unit The extension station unit or the extended slave station unit includes a third sending side connector 8 that engages with the receiving side connector 7, and the end blocks 260 and 360 are connected to the sending side connector 8. It further includes a third receiving side connector 7 to be engaged, and the third sending side connector 8 and the third receiving side connector 7 are: When the extension chassis unit is expanded and used via the extension station unit or the extension sub-station unit, the extension chassis in which the third receiving side connector 7 is connected to the final connection position is used. Relocation contract is made to the sending connector 8 of the unit.
Therefore, it is possible to prevent the occurrence of an operation trouble due to unarrangement of the extended row termination block 260 or the extended grandchild row termination block 360 or connection leakage.

It is a block diagram which shows the unit type programmable controller which concerns on Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the unit type programmable controller which concerns on Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the unit type programmable controller which concerns on Embodiment 1 of this invention. It is a block diagram which shows the unit type programmable controller which concerns on Embodiment 2 of this invention. It is a flowchart which shows operation | movement of the unit type programmable controller which concerns on Embodiment 2 of this invention. It is a flowchart which shows operation | movement of the unit type programmable controller which concerns on Embodiment 2 of this invention. It is a block diagram which shows the unit type programmable controller which concerns on Embodiment 3 of this invention. It is a block diagram which shows the unit type programmable controller which concerns on Embodiment 4 of this invention. It is a block diagram which shows the unit type programmable controller which concerns on Embodiment 5 of this invention.

Explanation of symbols

  6a expansion board, 7 receiving side connector (second receiving side connector, third receiving side connector), 8, 8a sending side connector (second sending side connector, third sending side connector), 11, 11a-11c connection confirmation signal Line, 12, 12a to 12c Station number setting search signal line, 13, 15, 16 Penetration stop signal line, 100A to 100E unit type programmable controller, 110A to 110E basic casing unit, 111 microprocessor, 112 bus interface circuit, 114A to 114D system memory, 115A to 115D program memory, 116 RAM memory, 117 watchdog timer, 119 stop logic circuit, 120 to 150, 180, 180a to 180e, 280a to 280e, 380a to 380e additional chassis unit 121 External input device, 122-152, 172a, 172b, 182 I / O interface circuit, 123-153, 124-154, R pull-up resistor, 125a-155a, 125b-155b, 175a, 175b, 185 selection switching circuit, 131 External load, 160 terminal block, 190A to 190C extended master station unit, 260 extended column terminal block, 290A to 290C extension station unit, 298 extended column stop logic circuit, 360 terminal block, 390B to 390C extended grand station unit, 398 Extended grandchild stop logic circuit, BUS, BUS1, BUS2 through bus signal line, CF1-CF3 station number setting search signal, END termination processing confirmation circuit, END1-END3 connection confirmation signal, FIN individual completion logic signal, GND ground times , LST connection position confirmation circuit, PLS runaway monitoring pulse signal, WD runaway abnormality detection signal, WD1 to WD3 penetration stop signal, S17 to S29, S50 to S54 station number setting means, S14 first abnormality judgment means, S19 second abnormality judgment Means, S26 third abnormality determining means, S15 setting abnormality processing means, S30, S53 card knitting storage means, S37, S63 knitting abnormality detecting means, S41, S61 dropout abnormality detecting means, S38, S64 knitting abnormality processing means.

Claims (17)

A basic chassis unit having a built-in program memory storing a microprocessor and a sequence program;
An additional enclosure unit connected to the basic enclosure unit;
Passing through the additional chassis unit, one end is bus-connected to the basic chassis unit, and a through bus including a plurality of control signal lines and a multi-bit data bus,
A termination block connected to the other end of the through bus;
An input / output interface circuit provided in at least one of the basic chassis unit and the additional chassis unit and selectively connected to the microprocessor;
A unit-type programmable controller that outputs a signal to an external output device in response to a signal from an external input device and the contents of the program memory,
The basic housing unit is
A system memory including a control program serving as a station number setting means for setting a station number for identifying the input / output interface circuit;
RAM memory for arithmetic processing for storing input / output information;
A bus interface circuit connected to the microprocessor and the through bus;
The input / output interface circuit includes:
An individual memory for storing card information and station number information indicating the station number;
The card information includes product type logic information indicating whether the input / output interface circuit is an input interface circuit or an output interface circuit, and whether the connection position of the input / output interface circuit is the final connection position. Connection location logical information indicating
The end block is
A connection position confirmation circuit that obtains the connection position logic information using a pull-up resistor or a pull-down resistor connected to the input / output interface circuit;
A termination processing confirmation circuit that outputs the connection state of the termination block to the microprocessor as a connection confirmation signal;
The station number setting means is at the start of the operation of the microprocessor, and when the connection of the terminal block is confirmed by the connection confirmation signal, the final number included in the connection position logic information from the first connection position. A unit-type programmable controller characterized in that different station numbers are assigned and set sequentially to the input / output interface circuit up to the connection position. A basic chassis unit having a built-in program memory storing a microprocessor and a sequence program;
An additional enclosure unit connected to the basic enclosure unit;
Passing through the additional chassis unit, one end is bus-connected to the basic chassis unit, and a through bus including a plurality of control signal lines and a multi-bit data bus,
A termination block connected to the other end of the through bus;
A plurality of input / output interface circuits that are provided in each of the basic chassis unit and the additional chassis unit and selectively connected to the microprocessor;
A unit-type programmable controller that outputs a signal to an external output device in response to a signal from an external input device and the contents of the program memory,
In the input / output interface circuit provided in the basic casing unit, a predetermined station number is set in advance for identification,
The basic housing unit is
A system memory including a control program serving as a station number setting means for setting a station number for identifying an input / output interface circuit provided in the additional chassis unit;
RAM memory for arithmetic processing for storing input / output information;
A bus interface circuit connected to the microprocessor and the through bus;
The input / output interface circuit includes:
An individual memory for storing card information and station number information indicating the station number;
The card information includes product type logic information indicating whether the input / output interface circuit is an input interface circuit or an output interface circuit, and whether the connection position of the input / output interface circuit is the final connection position. Connection position logic information indicating whether or not the input / output interface circuit is provided in the basic casing unit, and when the input / output interface circuit is provided in the basic casing unit, Model code information indicating the type of input / output organization of the basic chassis unit,
The end block is
A connection position confirmation circuit that obtains the connection position logic information using a pull-up resistor or a pull-down resistor connected to the input / output interface circuit;
A termination processing confirmation circuit that outputs the connection state of the termination block to the microprocessor as a connection confirmation signal;
The station number setting means is at the start of operation of the microprocessor, and when the connection of the terminal block is confirmed by the connection confirmation signal, the connection position logic information from the first connection position of the additional enclosure unit The station numbers following the station number set in the input / output interface circuit provided in the basic housing unit are sequentially assigned and set to the input / output interface circuit up to the final connection position included in Unit-type programmable controller. The input / output interface circuit receives the station number setting search signal output from the microprocessor, and transmits the station number setting search signal to the input / output interface circuit sequentially connected to the subsequent stage upon completion of the station number setting. A selection switching circuit is connected,
The card information further includes individual completion logic information for identifying whether the station number setting is completed and switching the selection switching circuit,
The station number setting means reads the card information of the input / output interface circuit that has received the station number setting search signal via the data bus, and the input of the input / output interface circuit that has received the station number setting search signal via the data bus. Write the corresponding station number in the individual memory,
After the setting of the station number is completed, the microprocessor designates the station number via the data bus, and communicates data with the input / output interface circuit of the designated station number via the data bus. The unit-type programmable controller according to claim 1. The final-stage input / output interface circuit built in the basic chassis unit includes an additional chassis connected to the subsequent stage as the card information is read from the final-stage input / output interface circuit by the microprocessor. A selection switching means for transmitting a station number setting search signal output from the microprocessor is connected to an input / output interface circuit in the body unit,
The card information of the final stage I / O interface circuit further includes individual completion logic information for identifying whether or not reading by the microprocessor is completed and switching the selection switching means,
The station number setting search signal is received by the input / output interface circuit built in the additional chassis unit, and the station number setting search signal is transmitted to the input / output interface circuit connected to the subsequent stage as the station number setting is completed. A selection switching circuit is connected to
The card information of the input / output interface circuit built in the additional chassis unit further includes individual completion logic information for identifying whether or not the setting of the station number has been completed and switching the selection switching circuit,
The station number setting means reads the card information of the final stage input / output interface circuit via the data bus, and the connection position logic information in the card information of the final stage input / output interface circuit is the final connection. The input / output interface circuit in the additional enclosure unit connected to the subsequent stage via the data bus based on the model code information in the card information of the final stage input / output interface circuit when indicating that the position is not a position. Write the corresponding station number in the individual memory
After the setting of the station number is completed, the microprocessor designates the station number via the data bus, and communicates data with the input / output interface circuit of the designated station number via the data bus. The unit type programmable controller according to claim 2. The system memory has an input / output in an additional chassis unit connected to a subsequent stage upon completion of reading of card information by the microprocessor from the final stage input / output interface circuit built in the basic chassis unit. A control program serving as a selection switching means for transmitting a station number setting search signal output by the microprocessor to the interface circuit;
The card information of the final stage I / O interface circuit further includes individual completion logic information for identifying whether or not reading by the microprocessor is completed and switching the selection switching means,
The station number setting search signal is received by the input / output interface circuit built in the additional chassis unit, and the station number setting search signal is transmitted to the input / output interface circuit connected to the subsequent stage as the station number setting is completed. A selection switching circuit is connected to
The card information of the input / output interface circuit built in the additional chassis unit further includes individual completion logic information for identifying whether or not the setting of the station number has been completed and switching the selection switching circuit,
The station number setting means reads the card information of the final stage input / output interface circuit via the data bus, and the connection position logic information in the card information of the final stage input / output interface circuit is the final connection. The input / output interface circuit in the additional enclosure unit connected to the subsequent stage via the data bus based on the model code information in the card information of the final stage input / output interface circuit when indicating that the position is not a position. Write the corresponding station number in the individual memory
After the setting of the station number is completed, the microprocessor designates the station number via the data bus, and communicates data with the input / output interface circuit of the designated station number via the data bus. The unit type programmable controller according to claim 2. The system memory further includes a control program serving as a first abnormality determination unit, at least one of a second abnormality determination unit and a third abnormality determination unit, and a setting abnormality processing unit.
The first abnormality determination means determines an abnormality when the connection confirmation signal indicates an unconnected state of the termination block,
The second abnormality determination unit is configured such that the card information of the input / output interface circuit before the final connection position cannot be obtained, or the input / output interface circuit at the final connection position is not found even after a predetermined time has elapsed. Is judged abnormal,
The third abnormality determining means determines an abnormality when the station number set in the input / output interface circuit and the station number confirmed and returned from the input / output interface circuit in which the station number is set do not match,
The setting abnormality processing means stores an abnormal state in the RAM memory when any of the first abnormality determination means, the second abnormality determination means, and the third abnormality determination means makes an abnormality determination, and externally The unit-type programmable controller according to any one of claims 1 to 5, wherein the unit-type programmable controller is notified. The system memory further includes a control program serving as card knitting storage means, knitting abnormality detection means, dropout abnormality detection means, and knitting abnormality processing means,
The card organization storage means stores the correspondence between the card information and the station number information in the RAM memory as card organization information when the setting of the station number is completed,
The knitting abnormality detecting means determines abnormality when the card knitting information obtained from the input / output interface circuit designating the station number and the card knitting information stored in the card knitting storage means do not match,
The drop abnormality detection means determines an abnormality when the connection confirmation signal indicates an unconnected state of the terminal block during operation,
The knitting abnormality processing means stores an abnormal state in the RAM memory and notifies the outside of the abnormality state when any of the knitting abnormality detection means and the dropout abnormality detection means makes an abnormality determination. The unit-type programmable controller according to any one of claims 1 to 6. The system memory further includes a control program serving as card organization storage means,
The program memory further includes a control program serving as a knitting abnormality detecting means, a dropout abnormality detecting means, and a knitting abnormality processing means,
The card organization storage means stores the correspondence between the card information and the station number information in the RAM memory as card organization information when the setting of the station number is completed,
The knitting abnormality detecting means determines abnormality when the card knitting information obtained from the input / output interface circuit designating the station number and the card knitting information stored in the card knitting storage means do not match,
The drop abnormality detection means determines an abnormality when the connection confirmation signal indicates an unconnected state of the terminal block during operation,
The knitting abnormality processing means stores an abnormal state in the RAM memory and notifies the outside of the abnormality state when any of the knitting abnormality detection means and the dropout abnormality detection means makes an abnormality determination. The unit-type programmable controller according to any one of claims 1 to 6. The basic housing unit is
A watchdog timer for monitoring the operation of the microprocessor;
A stop logic circuit for stopping output or maintaining the current state of the output interface circuit,
The watchdog timer outputs a runaway abnormality detection signal to the microprocessor and the stop logic circuit when the pulse width of the runaway monitoring pulse signal output by the microprocessor is larger than a predetermined width, Microprocessor reset processing and operation stop or restart,
The stop logic circuit stops the output of the output interface circuit via a through stop signal line when receiving the runaway abnormality detection signal and when the connection confirmation signal indicates an unconnected state of the termination block. The unit-type programmable controller according to any one of claims 1 to 8, wherein the current status is maintained. An extended master station unit provided between the basic housing unit and the terminal block;
An extension station unit connected to the extended master station unit;
An extension column extension housing unit and an extension column termination block connected to a subsequent stage of the extension station unit;
The extended master station unit and the extension station unit include a buffer circuit connected to the through bus,
The microprocessor is a signal different from a station number setting search signal for setting a station number of the input / output interface circuit in a basic column composed of the basic chassis unit, the additional chassis unit, and the termination block, and the extension Outputs the station number setting search signal for the extension column to start the station number setting of the extension column input / output interface circuit provided in the column extension chassis unit.
The microprocessor is a signal different from the connection confirmation signal indicating the connection state of the termination block, and is input with a connection confirmation signal for an extension column indicating the connection state of the extension column termination block,
The station number setting means sets a station number subsequent to the station number set in the input / output interface circuit of the basic chassis unit or the extension chassis unit for the extended column input / output interface circuit. The unit-type programmable controller according to any one of claims 3 to 8. An extended master station unit provided between the basic housing unit and the terminal block;
An extension station unit connected to the extended master station unit;
An extended column extension housing unit and an extended column termination block connected to the subsequent stage of the extension station unit;
An extension grand station unit connected to the extension station unit;
An extended grandchild row expansion housing unit connected to the subsequent stage of the extended grandchild station unit and an extended grandchild row termination block;
The extension master station unit, the extension station unit, and the extension slave station unit include a buffer circuit connected to the through bus,
The microprocessor is a signal different from a station number setting search signal for setting a station number of the input / output interface circuit in a basic column composed of the basic chassis unit, the additional chassis unit, and the termination block, and the extension Outputs an expansion column station number setting search signal for starting the station number setting of the expansion column input / output interface circuit provided in the column expansion chassis unit, and extends the grandchild in the expansion grand column expansion chassis unit. Output station number setting search signal for extended grandchild row to start station number setting of column I / O interface circuit,
The microprocessor is supplied with a connection confirmation signal for an extended column that is different from a connection confirmation signal that indicates a connection state of the termination block, and that indicates a connection state of the extension column termination block. The connection confirmation signal for the extended grandchild row indicating the connection status of the column end block is input,
The station number setting means sets a station number subsequent to the station number set in the input / output interface circuit of the basic chassis unit or the extension chassis unit for the extended column input / output interface circuit, and the extended grandchild 9. The unit according to claim 3, wherein a station number subsequent to the station number set in the extended column input / output interface circuit is set for a column input / output interface circuit. Programmable controller. Among the plurality of station number setting search signals, a signal line for transmitting a station number setting search signal excluding the station number setting search signal for the basic column, and a signal line for transmitting the plurality of connection confirmation signals are the extended master station While being connected through the unit and the additional enclosure unit,
11. The signal line for transmitting the station number setting search signal for the basic column and the signal line for transmitting the connection position logic information are connected through the extended master station unit. The unit type programmable controller according to claim 11.   Among the plurality of station number setting search signals, a signal line for transmitting a station number setting search signal excluding a station number setting search signal for the basic column and a plurality of signal lines for transmitting the plurality of connection confirmation signals are respectively the extensions. The unit-type programmable controller according to any one of claims 10 to 12, wherein the unit-type programmable controller is transferred to different signal lines by being cross-connected in the station unit. The basic housing unit further includes a watchdog timer that monitors the operation of the microprocessor,
At least one of the extension station unit and the extended grandchild station unit is a stop logic circuit that stops output or maintains the current status of the output interface circuit provided in the extension column extension chassis unit or the extension grandchild extension chassis unit Further including
The watchdog timer outputs a runaway abnormality detection signal to the microprocessor and the stop logic circuit when the pulse width of the runaway monitoring pulse signal output by the microprocessor is larger than a predetermined width, Microprocessor reset processing and operation stop or restart,
The stop logic circuit receives the runaway abnormality detection signal, and the extension row connection confirmation signal or the extension grandchild row connection confirmation signal is sent to the extended row termination block or the extended grandchild row termination block. The unit according to any one of claims 10 to 13, wherein when the unconnected state is indicated, the output of the output interface circuit is stopped or the current state is maintained through a through stop signal line. Programmable controller. The extension chassis unit includes an extension board that is a double-sided printed board on which the input / output interface circuit and the selection switching circuit are mounted,
The extension board has a receiving-side connector surface-mounted on one wiring surface and a sending-side connector surface-mounted on the other wiring surface,
A plurality of control signal lines excluding signal lines for transmitting the station number setting search signal for the basic column and a plurality of bit data buses are extended from the receiving side connector to the sending side connector and connected to the subsequent stage. Connected to the unit,
The base column station number setting search signal is input from the receiving connector to the selection switching circuit, and the output signal from the selection switching circuit is transmitted as the station number setting search signal for the additional chassis unit at the next stage. The unit-type programmable controller according to any one of claims 3 to 14, wherein the unit-type programmable controller is sent from a side connector. The basic housing unit further includes a second sending side connector that engages with the receiving side connector,
The termination block further includes a second receiving connector that engages with the sending connector,
The second sending-side connector and the second receiving-side connector are shipped after being engaged with each other, and the second receiving-side connector is connected to the final connection position when the additional enclosure unit is added and used. The unit-type programmable controller according to claim 15, wherein the unit-type programmable controller is transferred to the transmission side connector of the additional enclosure unit. An extended master station unit provided between the basic housing unit and the terminal block;
An extension station unit connected to the extended master station unit;
An extended column extension housing unit and an extended column termination block connected to the subsequent stage of the extension station unit;
An extension grand station unit connected to the extension station unit;
An extended grandchild row expansion housing unit connected to the subsequent stage of the extended grandchild station unit and an extended grandchild row termination block;
The extension station unit or the extended sub-station unit includes a third sending side connector that engages with the receiving side connector,
The termination block further includes a third receiving connector that engages with the sending connector,
When the third sending side connector and the third receiving side connector are shipped in contact with each other, and when the extension housing unit is used via the extension station unit or the extension grandchild station unit, The unit-type programmable controller according to claim 16, wherein the third receiving-side connector is transferred to the sending-side connector of the additional enclosure unit connected to the final connection position.

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