JP4281639B2 - Error correction circuit and physical quantity sensor device having the same - Google Patents

Description

  The present invention relates to an error correction circuit for a storage device that stores, as check data, an exclusive logical sum of at least two arbitrary bits of a data sequence to be subjected to error correction, among stored binary data sequences. The present invention relates to a physical quantity sensor device comprising:

For example, in a storage device such as a semiconductor memory, the stored information and data may be read out as different data, so-called garbled data may be generated. It can also be a cause of problems. For this reason, for example, in the technique disclosed in Patent Document 1 below, an error correction circuit using a so-called majority decision method or an error correction circuit having a redundant configuration according to the importance of data may cause data corruption. Even if it occurs, the data content can be guaranteed.
Japanese Patent Application Laid-Open No. 2002-288046 (pages 2 to 6, FIG. 3, FIG. 7 and FIG. 8)

  However, according to such disclosed technology, for example, in an error correction circuit using the majority method, as shown in FIG. 8, the same data D0a, D0b, D0c, data D1a, D1b, D1c, etc. stored in three memories Must be input to the majority decision determining unit 101 (Patent Document 1; data A1, A2, A3 shown in FIG. 7). In other words, since it is necessary to adopt a redundant configuration having the same data in triplicate, a memory corresponding to three times the required data capacity must be provided originally, which causes an increase in product cost. Further, since such a three-fold memory is mounted, there is a problem in that the substrate area is increased.

  In addition, an error correction circuit adopting a redundant configuration in accordance with the importance of data uses SEC (Single Error Collect), which is a general parity correction method, as an error correction circuit having a medium capability. Although this patent document 1 does not disclose the circuit configuration of the SEC determination unit 92, for example, the configuration shown in FIG. 9 is adopted. For this reason, as shown in FIG. 9, the EXOR (exclusive OR) required for determining the parity is complicatedly configured in the range indicated by the symbol α, so that the data subject to error correction As the number increases, the complexity of the wiring pattern increases, and there is a problem that the wiring pattern is likely to be complicated. Further, in the range indicated by the symbol β, since a plurality of wiring patterns crossing in a bus shape is required, there is a problem in that the occupied area is increased and the loss of the wiring area is likely to occur in the board layout.

  Furthermore, if the number of memory, logic gates, or wiring patterns to be mounted increases in either the case of an error correction circuit based on the majority method or the case of an error correction circuit having a redundant configuration according to the importance of data, Along with this, there is also a problem that an increase in failure rate as an electronic device is easily caused.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an error correction circuit capable of reducing the substrate area.
Another object of the present invention is to provide an error correction circuit capable of reducing the failure rate.
Furthermore, another object of the present invention is to provide a physical quantity sensor device capable of reducing the size and weight and reducing the failure rate.

  In order to achieve the above object, the means of claim 1 described in claims is adopted. According to this means, the exclusive OR of data bit D0 and data bit D1 is checked bit P0,1 and the exclusive OR of data bit D1 and data bit D2 is checked bit P1,2, data bit D2 and data bit D0 Is the check bit P2,0, and the data bits D0, D1, D2 and the check bits P0,1, P1,2, P2,0 are input adjacently in the positional relationship on the circuit board. A logic circuit that corrects errors in the data bit D0, the data bit D1, and the data bit D2 based on the following logical expressions (1) to (3) and outputs the data bit Dout0, the data bit Dout1, and the data bit Dout2, respectively. Is provided.

  Thus, error correction is performed on the data bit D1 by the logical expression (2). For example, when the data bit D1 is garbled, the result of the logical operation in () of the equation (2) is “1”, and the logic in {} of the equation (2) Since the result of the operation is also “1”, the data bit D1 taking an exclusive OR with “1” is inverted, that is, the data bit error is corrected and output as the data bit Dout1. On the other hand, when the data bit D1 is not garbled, it is not necessary to correct the data bit D1. Therefore, the result of the logical operation in () of the equation (2) is “0”, and the result of the logical operation in {} of the equation (2) is also “0”. And the data bit D1 taking the exclusive OR is output as the data bit Dout1 as it is. Similarly, error correction is performed on the data bit D2 by the logical expression (3) and on the data bit D1 by the logical expression (1).

  Thus, three check bits P0,1, P1,2, and P2,0 are sufficient to correct the three data bits D0, D1, and D2. These data bits D0, D1, D2 and check bits P0,1, P1,2, P2,0 are input adjacently in the arrangement positional relationship on the circuit board. As a result, the required data capacity can be reduced as compared with the error correction circuit based on the majority voting system having the same data triple. In addition, since the error is corrected using the three data bits D0, D1, D2 and the three check bits P0,1, P1,2, P2,0, the circuit wiring can be simplified and the circuit can be simplified. It is possible to prevent the wiring pattern on the substrate from being complicated. In addition, the length of the wiring pattern on the circuit board can be shortened. Further, since errors can be corrected independently of other data bits in units of 3 bits, by setting the target range of error correction with the 3 bits unit as one block at a plurality of locations in the binary data string, A data error of 2 bits or more can be corrected between the blocks.

  By adopting the means of claim 2 according to the claims, when the data string to be error-corrected is n bits, the exclusive OR of the data bit Di and the data bit Di + 1 is a check bit. When Pi, i + 1, a logic circuit for correcting an error of the data bit Di and outputting the data bit Douti based on the following logical expression (4) is provided (where i is from 0 to n) , I-1 is n when i is 0, and i + 1 is 0 when i is n.)

  Thus, error correction is performed on the data bit Di by the logical expression (4). For example, when the data bit Di is garbled, the result of the logical operation in () of the equation (4) becomes “1”, and the logic in {} of the equation (4) Since the result of the operation is also “1”, the data bit Di that is exclusively ORed with “1” is inverted, that is, the data bit error is corrected and output as the data bit Douti. On the other hand, when the data bit Di is not garbled, it is not necessary to correct the data bit Di. Therefore, the result of the logical operation in () of the equation (4) is “0”, and the result of the logical operation in {} of the equation (4) is also “0”. And the data bit Di taking an exclusive OR is output as it is as the data bit Douti.

  In this way, n bits of check bits Pn, 0, P0,1,..., Pn-1, n are sufficient to correct the n data bits D0, D1,. These data bits D0, D1,..., Dn and check bits Pn, 0, P0,1,..., Pn-1, n are input adjacently in the arrangement positional relationship on the circuit board. As a result, the required data capacity can be reduced as compared with the error correction circuit based on the majority voting system having the same data triple. Also, the n-bit data bits D0, D1,..., Dn and the n-bit check bits Pn, 0, P0,1,. Since errors are corrected using n, circuit wiring can be simplified and the wiring pattern on the circuit board can be prevented from being complicated. In addition, the length of the wiring pattern on the circuit board can be shortened. Furthermore, when the data string subject to error correction is 4 bits or more, 2-bit errors can be corrected in a predetermined combination.

  In order to achieve the above object, the means of claim 3 described in claims is adopted. According to this means, the sensor voltage adjusting means for controlling the adjustment of the sensor voltage by the sensor voltage generating means based on the correction data read from the semiconductor memory device comprises the error correction circuit according to claim 1 or 2. The correction data is read from the semiconductor memory device via the error correction circuit. Thereby, in the sensor voltage adjusting means, even if the correction data read from the semiconductor memory device is garbled, it is corrected by the error correction circuit, so that appropriate correction data can be read. Further, it is possible to simplify the circuit wiring of the error correction circuit and to prevent the wiring pattern on the circuit board from being complicated. Furthermore, the length of the wiring pattern on the circuit board can be shortened.

  According to the first aspect of the present invention, three check bits P0,1, P1,2, and P2,0 are sufficient to correct the three data bits D0, D1, and D2. These data bits D0, D1, D2 and check bits P0,1, P1,2, P2,0 are input adjacently in the arrangement positional relationship on the circuit board. As a result, the required data capacity can be reduced as compared with the error correction circuit based on the majority voting system having the same data triple. In addition, since the error is corrected using the three data bits D0, D1, D2 and the three check bits P0,1, P1,2, P2,0, the circuit wiring can be simplified and the circuit can be simplified. It is possible to prevent the wiring pattern on the substrate from being complicated. In addition, the length of the wiring pattern on the circuit board can be shortened. Further, since errors can be corrected independently of other data bits in units of 3 bits, by setting the target range of error correction with the 3 bits unit as one block at a plurality of locations in the binary data string, A data error of 2 bits or more can be corrected between the blocks. Therefore, the board area can be reduced by reducing the occupied area by the wiring pattern on the circuit board. In addition, the shortening of the wiring pattern length also reduces the wiring pattern disconnection, signal attenuation, and external noise, so that the failure rate can be reduced.

  In the second aspect of the present invention, n check bits Pn, 0, P0,1,..., Pn-1, n are sufficient to correct the n data bits D0, D1,. These data bits D0, D1,..., Dn and check bits Pn, 0, P0,1,..., Pn-1, n are input adjacently in the arrangement positional relationship on the circuit board. As a result, the required data capacity can be reduced as compared with the error correction circuit based on the majority voting system having the same data triple. Also, the n-bit data bits D0, D1,..., Dn and the n-bit check bits Pn, 0, P0,1,. Since errors are corrected using n, circuit wiring can be simplified and the wiring pattern on the circuit board can be prevented from being complicated. In addition, the length of the wiring pattern on the circuit board can be shortened. Furthermore, when the data string subject to error correction is 4 bits or more, 2-bit errors can be corrected in a predetermined combination. Therefore, the board area can be reduced by reducing the occupied area by the wiring pattern on the circuit board. In addition, the shortening of the wiring pattern length also reduces the wiring pattern disconnection, signal attenuation, and external noise, so that the failure rate can be reduced.

  According to the third aspect of the invention, the sensor voltage adjusting means can read out the correct correction data because the error correction circuit corrects the correction data read from the semiconductor memory device even if the data is garbled. Further, it is possible to simplify the circuit wiring of the error correction circuit and to prevent the wiring pattern on the circuit board from being complicated. Furthermore, the length of the wiring pattern on the circuit board can be shortened. Therefore, the physical quantity sensor device can be reduced in size and weight and the failure rate can be reduced.

  Hereinafter, an embodiment in which an error correction circuit of the present invention is applied to a physical quantity sensor device will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a physical quantity sensor device 10 according to the present embodiment. FIG. 2 is a block diagram showing the configuration of the trimming voltage control circuit unit 14 of the physical quantity sensor device 10. First, the configuration of the physical quantity sensor device 10 will be described with reference to FIGS. 1 and 2.

  As shown in FIG. 1, the physical quantity sensor device 10 is mainly configured by a logic circuit unit 12, a trimming voltage control circuit unit 14, an analog circuit unit 16, and a sensor element Sen. For example, the sensor element Sen is configured by arranging piezoelectric elements in a bridge shape, and can detect a physical quantity (for example, pressure, acceleration, yaw rate) based on a sensor driving voltage (sensor voltage) applied from the outside. It is comprised. The sensor element Sen may correspond to “sensor means” recited in the claims.

  The logic circuit unit 12 is configured to perform various controls of the trimming voltage control circuit unit 14 based on a trimming adjustment TRM signal externally input from the terminal 18a. Specifically, the logic circuit unit 12 generates an address bus and a mode control signal to the trimming voltage control circuit unit 14 and transmits / receives data to / from the trimming voltage control circuit unit 14, thereby controlling the trimming voltage control. Data obtained from the circuit unit 14 can be output to the analog circuit unit 16 as a DataOUT signal.

  The trimming voltage control circuit unit 14 stores data related to trimming adjustment (hereinafter referred to as “trimming data”) based on various control signals from the logic circuit unit 12 or a sensor based on the stored correction data. A trimming voltage Vtrm for trimming the sensor drive voltage applied to the element Sen can be generated. The trimming voltage control circuit unit 14 can correspond to “sensor voltage adjusting means” described in the claims, and the trimming data corresponds to “correction data” described in the claims. To get. Here, the configuration of the trimming voltage control circuit unit 14 will be described with reference to FIG.

  As shown in FIG. 2, the trimming voltage control circuit unit 14 is mainly composed of a memory circuit unit 14a, an error correction circuit unit 14b, and a D / A conversion unit 14c, and the error correction circuit unit is changed from the memory circuit unit 14a. A trimming voltage Vtrm is generated by the D / A converter 14c based on the trimming data read out via 14b.

  The memory circuit unit 14a is, for example, a PROM (storage device, semiconductor storage device), in addition to trimming data (binary data sequence) for generating the trimming voltage Vtrm, at least a data sequence that is subject to error correction. Are stored as test data. In this embodiment, the data bits D0 to Dn of all trimming data are set as error correction targets.

  That is, when the trimming data (data string) to be corrected is data bits D0, D1, and D2, check bits Pn, 0 and data D0 in which an exclusive OR of the data Dn and the data D0 is set. Are stored in the memory circuit section 14a. The check bit P0,1 for setting the exclusive OR of the data D1 and the check bit P1,2 for setting the exclusive OR of the data D1 and the data D2 are stored. In other words, if the data string to be subjected to error correction is data bits Dn-1, Dn, Dn + 1, check bits Pn-1, n for which an exclusive OR of data Dn-1 and data Dn is set, data Check bit Pn, n + 1 for which an exclusive OR of Dn and data Dn + 1 is set, and check bit Pn + 1, n-1 for which an exclusive OR of data Dn + 1 and data Dn-1 is set Are stored in the memory circuit portion 14a.

  The error correction circuit unit 14b constitutes a logic circuit capable of performing error correction on the data Dn based on the check bit Pn-1, n and the check bit Pn, n + 1 stored in the memory circuit unit 14a. is there. Specifically, "exclusive OR of data Dn-1, data Dn and check bit Pn-1, n" and "exclusive OR of data Dn, data Dn + 1 and check bit Pn, n + 1" By constructing a logic circuit so as to be able to take an exclusive OR with the data Dn with respect to the logical product with, the error of the data Dn is corrected. The error correction circuit unit 14b can correspond to an “error correction circuit” recited in the claims, and a specific configuration and the like will be described later.

  The D / A converter 14c is a so-called DAC (Digital to Analog Converter) that can convert the trimming data (Dout1 to Doutn) after the error correction by the error correction circuit 14b into an analog signal. An output from the unit 14c is applied to the analog circuit unit 16 as a trimming voltage Vtrm.

  The analog circuit unit 16 adjusts the sensor drive voltage applied to the sensor element Sen based on the trimming voltage Vtrm from the trimming voltage control circuit unit 14, and adjusts the sensor detection voltage output from the sensor element Sen. And three terminals connectable to the outside, that is, a Vcc terminal 18b, a Vout terminal 18c, and a GND terminal 18d. These adjustments enable final sensitivity adjustment, offset adjustment, offset temperature characteristic adjustment, and the like. The analog circuit unit 16 receives the DataOUT signal output from the logic circuit unit 12 and outputs a sensor output voltage based on the content of the trimming data stored in the memory circuit unit 14a of the trimming voltage control circuit unit 14. The output is possible from the Vout terminal 18c. The analog circuit section 16 may correspond to “sensor voltage generating means” described in the claims.

Here, a configuration example of the error correction circuit unit 14b will be described with reference to FIGS. First, a minimum configuration example of the error correction circuit constituting the error correction circuit unit 14b will be described with reference to FIG.
As shown in FIG. 3, the error correction circuit 20 sets the data string to be subjected to error correction as data bits D0, D1, and D2, and uses the exclusive OR of the data bit D0 and the data bit D1 as the check bits P0,1 ( Next logical expression (5)), exclusive OR of data bit D1 and data bit D2 is checked bit P1,2 (next logical expression (6)), exclusive OR of data bit D2 and data bit D0 is checked bit P2,0 (the following logical expression (7)).

  When these data bits D0, D1, D2 and check bits P0,1, P1,2, P2,0 are input adjacently in the arrangement positional relationship on the circuit board, the following logical expressions (8) to (8) 10), a logic circuit is provided for correcting the errors of the data bit D0, the data bit D1, and the data bit D2, respectively, and outputting the data bit Dout0, the data bit Dout1, and the data bit Dout2.

  That is, for data bit D1, check bit P0,1 and data bit D1 are exclusive so that the exclusive OR of data bit D0, check bit P0,1 and data bit D1 is output as E0,1. The logical sum XOR-2a is inputted, and the output of the exclusive logical sum XOR-2a and the data bit D0 can be inputted to the exclusive logical sum XOR-2b. Further, the check bit P1,2 and the data bit D2 are converted into an exclusive OR XOR-3a so that the exclusive OR of the data bit D1, the check bit P1,2 and the data bit D2 is output as E1,2. The exclusive OR XOR-3a and the data bit D1 can be input to the exclusive OR XOR-3b. Then, E0,1 and E1,2 are inputted to the logical product AND-2, and the output of the logical product AND-2 and the data bit D1 can be inputted to the exclusive logical sum XOR-2c. As a result, the logical operation according to the logical expression (9), that is, the error correction of the data bit D1 can be performed.

  For example, if the data bit D1 is garbled, the logical operation in () of the equation (9), that is, “the exclusive OR of the data bit D0, the check bits P0,1 and the data bit D1 Since “result (E0,1)” and “result of exclusive OR of data bit D1, check bit P1,2 and data bit D2 (E1,2)” are both “1”, the equation (9) The logical operation in {}, that is, the logical product of E0,1 and E1,2 is also “1”, and the data bit D1 taking the exclusive OR with “1” is inverted, that is, the error of the data bit is It is corrected and output as data bit Dout1.

  On the other hand, when the data bit D1 is not garbled, it is not necessary to correct the data bit D1. Therefore, the logical operation in () of the equation (9), that is, “the result of exclusive OR of data bit D0, check bit P0,1 and data bit D1 (E0,1)” and “data bit D1, check The result of the exclusive OR of the bit P1,2 and the data bit D2 (E1,2) "becomes" 0 ", and the logical operation in {} in the equation (9), that is, E0,1 and E1 , 2 is also “0”, so that the data bit D1 that is exclusively ORed with “0” is output as it is as the data bit Dout1.

  For data bit D2, check bit P1,2 and data bit D2 are exclusive so that the exclusive OR of data bit D1, check bit P1,2 and data bit D0 is output as E1,2. The logical sum XOR-3a is inputted, and the output of the exclusive logical sum XOR-3a and the data bit D1 can be inputted to the exclusive logical sum XOR-3b. Further, the check bit P2,0 and the data bit D0 are converted into an exclusive OR XOR-1a so that the exclusive OR of the data bit D2, the check bit P2,0 and the data bit D0 is output as E2,0. The exclusive OR XOR-1a and the data bit D2 can be input to the exclusive OR XOR-1b (circular connection 25a). Then, E1,2 and E2,0 are inputted to the logical product AND-3 (circular connection 25b), and the output of the logical product AND-3 and the data bit D2 can be inputted to the exclusive logical sum XOR-3c. Constitute. As a result, the logical operation by the logical expression (10) described above, that is, the error correction of the data bit D2 can be performed.

  For example, if the data bit D2 is garbled, the logical operation in () of the equation (10), that is, “the exclusive OR of the data bit D1, the check bit P1,2 and the data bit D2 Since “result (E1,2)” and “result of exclusive OR of data bit D2, check bit P2,0 and data bit D0 (E2,0)” are both “1”, equation (10) The logical operation within {}, that is, the logical product of E1,2 and E2,0 is also “1”, and the data bit D2 that is exclusive OR with “1” is inverted, that is, an error in the data bit occurs. It is corrected and output as data bit Dout2.

  On the other hand, when the data bit D2 is not garbled, it is not necessary to correct the data bit D2. Therefore, the logical operation in () of the equation (10), that is, “the result of exclusive OR of data bit D1, check bit P1,2 and data bit D2 (E1,2)” and “data bit D2, check The result of the exclusive OR of the bit P2,0 and the data bit D0 (E2,0) "becomes" 0 ", and the logical operation in {} of the equation (10), that is, E1,2 and E2 , 0 is also “0”, so that the data bit D2 that is exclusively ORed with “0” is output as the data bit Dout2.

  Further, for data bit D0, check bit P2,0 and data bit D0 are exclusive so that the exclusive OR of data bit D2, check bit P2,0 and data bit D0 is output as E2,0. An input to the logical sum XOR-1a is configured so that the output of the exclusive logical sum XOR-1a and the data bit D2 can be input to the exclusive logical sum XOR-1b (circular connection 25a). Further, the check bit P0,1 and the data bit D1 are converted into an exclusive OR XOR-2a so that the exclusive OR of the data bit D0, the check bit P0,1 and the data bit D1 is output as E0,1. The exclusive OR XOR-2a and the data bit D0 can be input to the exclusive OR XOR-2b. Then, E2,0 and E0,1 are inputted to the logical product AND-1, and the output of the logical product AND-1 and the data bit D0 can be inputted to the exclusive logical sum XOR-1c. As a result, the logical operation according to the above-described logical expression (8), that is, the error correction of the data bit D0 becomes possible.

  For example, when the data bit D0 is garbled, the logical operation in () in the equation (8), that is, “the exclusive OR of the data bit D2, the check bit P2,0 and the data bit D0” Since “result (E2,0)” and “result of exclusive OR of data bit D0, check bit P0,1 and data bit D1 (E0,1)” are both “1”, the equation (8) The logical operation in {}, that is, the logical product of E2,0 and E0,1 is also “1”, and the data bit D0 taking the exclusive OR with “1” is inverted, that is, the error of the data bit is It is corrected and output as data bit Dout0.

  On the other hand, when the data bit D0 is not garbled, it is not necessary to correct the data bit D0. Therefore, the logical operation in () of the equation (8), that is, “the result of exclusive OR of data bit D2, check bit P2,0 and data bit D0 (E2,0)” and “data bit D0, check The result of the exclusive OR of the bit P0,1 and the data bit D1 (E0,1) "becomes" 0 ", and the logical operation in {} of the equation (8), that is, E2,0 and E0 , 1 is also “0”, so that the data bit D0 that is exclusively ORed with “0” is output as the data bit Dout0 as it is.

  In this way, the exclusive OR between the three bits of data bits D0, D1, and D2 is stored in advance in the memory circuit unit 14a as check bits P0,1, P1,2, and P2,0. Thus, the error of the data bits D0, D1, and D2 can be corrected by the error correction circuit 20 shown in FIG. Accordingly, error correction can be performed by preparing 3 detection bits for 3 bits of data bits D0, D1, and D2. In other words, detection data having the same amount of data as the data subject to error correction may be stored in the storage device in advance, so that it is necessary as compared with an error correction circuit based on a redundant majority voting system having the same data in triplicate. It is possible to reduce the storage capacity of the error correction circuit unit 14b. Further, since the error is corrected by using the three data bits D0, D1, D2 and the three check bits P0,1, P1,2, P2,0, the circuit wiring of the error correction circuit unit 14b is simplified. In addition, it is possible to prevent the wiring pattern on the circuit board of the error correction circuit unit 14b from being complicated. In addition, the length of the wiring pattern on the circuit board of the error correction circuit unit 14b can be shortened. Therefore, the substrate area of the trimming voltage control circuit unit 14 can be reduced by reducing the occupied area by the wiring pattern on the circuit board of the error correction circuit unit 14b. Further, the shortening of the wiring pattern length also reduces the disconnection of the wiring pattern, signal attenuation, and the introduction of external noise, so that the failure rate of the trimming voltage control circuit unit 14 and thus the physical quantity sensor device 10 can be reduced.

  Such an error correction circuit 20 that enables error correction of 3-bit data may be used as one block, and a plurality of error correction circuits 20 may be provided to enable error correction in a plurality of blocks. For example, as shown in FIG. 4, the data bits D0, D1, and D2 are corrected by the error correction circuit 20A, and the data bits D3, D4, and D5 are corrected by the error correction circuit 20B. Thereby, since an error can be corrected independently of other data bits (other blocks) in units of 3 bits, a data error of 2 bits or more can be corrected between these blocks. Therefore, since it is possible to cope with errors of a plurality of bits between such blocks, the error correction capability can be improved.

Next, as an example of the configuration of the error correction circuit unit 14b, an example of the error correction circuit 30 when the object of error correction is n bits, that is, a plurality of bits will be described with reference to FIG.
As shown in FIG. 5, the error correction circuit 30 sets the data string subject to error correction as data bits D0, D1,..., Dn, and checks the exclusive OR of the data bit Di and the data bit Di + 1 as a check bit. Pi, i + 1 (the following logical expression (11)). However, i is from 0 to n. When i is 0, i-1 is set to n, and when i is n, i + 1 is set to 0.

  When these data bits D0, D1,..., Dn and check bits Pn, 0, P0,1,..., Pn-1, n are input adjacently in the arrangement positional relationship on the circuit board, A logic circuit is provided that corrects errors in the data bits D0, D1,..., Dn based on the equation (12) and outputs the data bits Dout0, Dout1,.

  That is, the error correction circuit 20 having the minimum configuration described above is expanded so that the exclusive OR of the data bit Di-1, the check bit Pi-1, i and the data bit Di is Ei-1, i for the data bit Di. The check bit Pi-1, i and the data bit Di are input to the exclusive OR XOR- (i + 1) a to output the exclusive OR XOR- (i + 1) a And the data bit Di-1 can be input to the exclusive OR XOR- (i + 1) b. The check bit Pi, i + 1 and the data bit Di + 1 are output so that the exclusive OR of the data bit Di, the check bit Pi, i + 1 and the data bit Di + 1 is output as Ei, i + 1. Are input to the exclusive OR XOR- (i + 2) a, and the output of the exclusive OR XOR- (i + 2) a and the data bit Di are converted to the exclusive OR XOR- (i + 2) b. Configure to allow input. Then, Ei-1, i and Ei, i + 1 are inputted to the logical product AND- (i + 1), and the output of the logical product AND- (i + 1) and the data bit Di are exclusive ORed. Configure to allow input to XOR- (i + 1) c. As a result, the logical operation according to the logical expression (12), that is, the error correction of the data bit Di can be performed. As described above, i is from 0 to n, i-1 is n when i is 0, and i + 1 is 0 when i is n.

  For example, if the data bit Di is garbled, the logical operation in () of the equation (12), that is, “exclusion of the data bit Di−1, the check bit Pi−1, i and the data bit Di "Logical OR (Ei-1, i)" and "exclusive OR of data bit Di, check bit Pi, i + 1 and data bit Di + 1 (Ei, i + 1)" Since it becomes “1”, the logical operation in {} of the formula (12), that is, the result of the logical product of Ei−1, i and Ei, i + 1 also becomes “1” and is exclusive with “1”. The data bit Di taking the logical sum is inverted, that is, the error of the data bit is corrected and output as the data bit Douti.

  On the other hand, when the data bit Di is not garbled, it is not necessary to correct the data bit Di. Therefore, the logical operation in () of the equation (12), that is, “exclusive OR result of data bit Di−1, check bit Pi−1, i and data bit Di (Ei−1, i)” “The result of exclusive OR of data bit Di, check bit Pi, i + 1 and data bit Di + 1 (Ei, i + 1)” is all “0”, and { }, I.e., the logical product of Ei-1, i and Ei, i + 1 is also "0", so the data bit Di taking an exclusive OR with "0" is directly used as the data bit Douti. Is output.

  As described above, the exclusive OR between the n-bit data bits D0, D1,..., Dn is preliminarily stored in the memory circuit as the check bits Pn, 0, P0,1,. By storing in the unit 14a, the error of the data bits D0, D1,..., Dn can be corrected by the error correction circuit 30 shown in FIG. Thus, error correction can be performed by preparing n detection bits for n data bits D0, D1,..., Dn. In other words, detection data having the same amount of data as the data subject to error correction may be stored in the storage device in advance, so that it is necessary as compared with an error correction circuit based on a redundant majority voting system having the same data in triplicate. It is possible to reduce the storage capacity of the error correction circuit unit 14b. Further, since the n bits of data bits D0, D1,..., Dn and check bits Pn, 0, P0,1,. Compared to the error correction circuit 20, it is not necessary to provide the annular connections 25 a and 25 b every 3 bits. Therefore, compared to the error correction circuit 20, the circuit wiring of the error correction circuit unit 14b can be simplified, and the wiring pattern on the circuit board of the error correction circuit unit 14b can be prevented from being complicated. In addition, the length of the wiring pattern on the circuit board of the error correction circuit unit 14b can be shortened. Therefore, the substrate area of the trimming voltage control circuit unit 14 can be further reduced by further reducing the occupied area due to the wiring pattern on the circuit board of the error correction circuit unit 14b. Further, since the wiring pattern length is further shortened, disconnection of the wiring pattern, signal attenuation, and mixing of external noise are further reduced, so that the failure rate of the trimming voltage control circuit unit 14 and thus the physical quantity sensor device 10 can be further reduced. it can.

  Further, in the configuration in which n-bit data as shown in FIG. 5 is subjected to error correction, a combination as shown in FIGS. 6 and 7 can cope with a 2-bit error. FIG. 6 is an explanatory diagram showing whether correction is possible for a 2-bit error (x mark) in the error correction circuit shown in FIG. FIG. 7 is an explanatory diagram showing combinations of two-bit errors that can be corrected with respect to the number of bits n to be corrected (bits connected by a broken line).

  That is, as shown in FIG. 6, when the error bit interval of 2-bit error is from 1 bit to 3 bits, for example, when the combination of the data bit D0 and the detection bits P0,1 shown in FIG. (Error bit interval is 1 bit), if the combination of data bit D0 and data bit D1 is incorrect (error bit interval is 2 bits), or if the combination of data bit D0 and detection bits P1,2 is incorrect None of the bits can be corrected (the error bit interval is 3 bits). However, when such an error bit combination interval (error bit interval) is 4 bits or more, it is possible to correct errors of both bits in the following combinations.

  For example, in the example shown in FIG. 5, if the combination of the detection bit P0,1 and the detection bit P2,3 is incorrect (the error bit interval is 4 bits), the combination of the data bit D0 and the detection bit P2,3 is incorrect. If the error occurs (the error bit interval is 5 bits) or the combination of the detection bits P0,1 and the data bit D3 is incorrect (the error bit interval is 5 bits), any bit can correct the error. it can. It should be noted that the error-correctable bit combinations are bits connected by a broken line shown in FIG.

From the viewpoint of the bit error rate, the error correction circuits 20 and 30 described above are examined as follows. If the error rate of a single bit is p, the error rate at which two bits are erroneous at the same time is p ² , and the error rate at which three bits are erroneous at the same time is p ³ , and p << 1. Therefore, p >> p ² >> p ³ is satisfied. Therefore, as an error rate after error correction, a simultaneous error rate of 3 bits or more is ignored and only a 2-bit simultaneous error is considered. In the case of the minimum configuration shown in FIG. 3, if 2-bit simultaneous errors occur, they cannot be corrected. The combination of such two-bit _errors, since 15 types in 6 _{C 2,} the error rate is 15p ^2.

On the other hand, in the case of an n-bit configuration as shown in FIG. 5, simultaneous errors of 2 bits or more can be handled if the inter-bit distance is more than a certain distance. This is because, as described above, error correction is performed using information of only a few adjacent bits. Then, when looking at how far the bit interval should be, as shown in FIG. 6, it is possible to correct both bits when they are separated by about 4 bits or more. The error rate is 7 np ² from the number of combinations of error bit patterns that cannot be corrected. Therefore, when n = 5, it becomes 35p ² , when n = 6, it becomes 42p ² , and when n = 7, it becomes 49p ² . It has been found that when n = 4, 26p ² (= 6.5 np ² ) is obtained.

  As described above, according to the physical quantity sensor device 10, in the error correction circuit unit 14b constituting the trimming voltage control circuit unit 14, even if the trimming data read from the memory circuit unit 14 is garbled, The logical operation in () of the logical expression (12), that is, “the result of exclusive OR of the data bit Di−1, the check bit Pi−1, i and the data bit Di (Ei−1, i)” and “data Since the result of the exclusive OR of the bit Di, the check bit Pi, i + 1 and the data bit Di + 1 (Ei, i + 1) "is" 1 ", the value in {} in the expression (12) The result of the logical operation of Ei-1, i and Ei, i + 1 is also "1", and the data bit Di taking the exclusive OR with "1" is inverted, that is, the error of the data bit is It is corrected and output as data bit Douti.

  Thereby, appropriate trimming data can be read. In addition, the circuit wiring of the error correction circuit unit 14b can be simplified, and the wiring pattern on the circuit board of the error correction circuit unit 14b can be prevented from being complicated. In addition, the length of the wiring pattern on the circuit board of the error correction circuit unit 14b can be shortened. Therefore, the substrate area of the trimming voltage control circuit unit 14 can be further reduced by further reducing the occupied area due to the wiring pattern on the circuit board of the error correction circuit unit 14b. Further, since the wiring pattern length is further shortened, disconnection of the wiring pattern, signal attenuation, and mixing of external noise are further reduced, so that the failure rate of the trimming voltage control circuit unit 14 and thus the physical quantity sensor device 10 can be further reduced. it can.

  In the above-described embodiment, the semiconductor memory device is illustrated as the storage device that stores the binary data string. However, the present invention is not limited to this, and information that can store the binary data string is stored. A storage medium such as a magnetic bubble memory, a magnetic disk, a magnetic tape, an optical disk, a magneto-optical disk, a CD, an MD, or a DVD may be used, and the same operations and effects as described above can be obtained.

It is a block diagram which shows the structure outline | summary of the physical quantity sensor apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows the structure of the trimming voltage control circuit part of the physical quantity sensor apparatus which concerns on this embodiment. It is a circuit diagram which shows the basic composition of the error correction circuit applicable to the error correction circuit part of a trimming voltage control circuit part. FIG. 4 is a circuit diagram showing a configuration when a plurality of correction circuits shown in FIG. 3 are combined. It is a circuit diagram which shows an example of the error correction circuit applicable to the error correction circuit part of a trimming voltage control circuit part. FIG. 6 is an explanatory diagram showing whether correction is possible for a 2-bit error (x mark) in the error correction circuit of FIG. 5. It is explanatory drawing which shows the combination (bits connected with the broken line) of 2 bit error which can carry out error correction with respect to the bit number n used as error correction. It is a circuit diagram which shows an example of the error correction circuit by a majority method. It is a circuit diagram which shows an example of the error correction circuit which takes the redundant structure according to the importance of data.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Physical quantity sensor apparatus 12 ... Logic circuit part 14 ... Trimming voltage control circuit part (sensor voltage adjustment means)
14a ... Memory circuit unit (storage device, semiconductor storage device)
14b ... Error correction circuit section (error correction circuit)
14c ... D / A converter 16 ... Analog circuit (sensor voltage generating means)
20, 30 ... error correction circuit (logic circuit)
Sen ... Sensor element (sensor means)
Vtrm ... Trimming voltage

Claims (3)

An error correction circuit for a storage device that stores, as check data, an exclusive OR of at least two arbitrary bits of a data sequence to be error-corrected among stored binary data sequences,
The exclusive OR of the data bit D0 and the data bit D1 is the check bit P0,1 and the exclusive OR of the data bit D1 and the data bit D2 is the check bit P1,2, the exclusive OR of the data bit D2 and the data bit D0 Is the check bit P2,0, and when these data bits D0, D1, D2 and check bits P0,1, P1,2, P2,0 are input adjacently in the arrangement positional relationship on the circuit board, A logic circuit that corrects errors in the data bit D0, the data bit D1, and the data bit D2 based on the equations (1) to (3) and outputs the data bit Dout0, the data bit Dout1, and the data bit Dout2 is provided. An error correction circuit.

When the error correction target data string is n bits, and the exclusive OR of the data bit Di and the data bit Di + 1 is the check bit Pi, i + 1, the following logical expression (4) 2. The error correction circuit according to claim 1, further comprising a logic circuit that corrects an error of the data bit Di based on the data and outputs the data bit Douti. However, i is from 0 to n. When i is 0, i-1 is set to n, and when i is n, i + 1 is set to 0.

Sensor means capable of detecting a physical quantity based on an applied sensor voltage;
Sensor voltage generating means capable of generating the sensor voltage in an adjustable manner;
Sensor voltage adjusting means for controlling adjustment of the sensor voltage by the sensor voltage generating means based on correction data read from the semiconductor memory device;
A physical quantity sensor device comprising:
3. The physical quantity sensor device according to claim 1, wherein the sensor voltage adjustment unit includes the error correction circuit according to claim 1, and reads the correction data from the semiconductor storage device via the error correction circuit.

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