JP4279731B2 - Image display device - Google Patents

Description

  The present invention relates to an image display device that displays image information in an image display area, and more particularly to an image display device that switches and displays a plurality of types of images.

  Hereinafter, a conventional image display device will be described.

1. DPVL
Conventionally, a video signal from a personal computer to an image display device such as an LCD or CRT is analog-transmitted via a VGA cable. In analog transmission, since waveform distortion occurs during transmission, there is a problem that bleeding and ghosting are likely to occur on the display screen of the image display apparatus.

  DVI (Digital Visual Interface) has been defined as one of the solutions for such analog transmission problems. DVI is a standard for digital transmission of video signals to image display devices such as LCDs and CRTs. With a DVI-compatible video card, cable, and monitor, you can easily get high-quality image display.

  In DVI, the video signal transmission is changed from analog transmission to digital transmission, but the frame rate of the video signal is a raster transfer method in which transmission is performed at 60 Hz as in the conventional case. Therefore, in DVI, when displaying on a recent ultra-high resolution monitor, there is a problem that the image output by the existing DVI exceeds the transmission band.

  DPVL (Digital Packet Video Link) has been defined as one of the solutions to such DVI problems. DPVL (Digital Packet Video Link) is not a raster transfer method that transmits image data of a full screen at a frame rate of 60 Hz as in the past, but needs to be updated by a graphic card (and driver) on the personal computer (host) side. The rectangular area and its position information are packetized and transmitted, and the monitor receives the packet and updates only the relevant part of the screen. In other words, DPVL realizes reduction of the transmission band by transmitting packets instead of performing raster transfer on the host side and processing the received packets on the monitor side.

  As an image display apparatus using such DPVL, there is an image display system disclosed in JP-A-2002-278526. The image display system includes an image data transmission device as a host side (transmission side) composed of a PC or the like, and a reception side monitor which is an image display device. The transmission device and the reception side monitor include a DVI (Digital Visual Interface). ) It is connected by an existing monitor cable which is a digital monitor cable such as a cable. The transmission apparatus has a function of extracting a changed area and a function of transmitting header information including data and image control information corresponding to the changed area. The reception-side monitor includes, for example, a large high-definition panel such as QUXGA and a packet reception device that receives image data from the transmission device via a monitor cable.

  A method for generating packet data to be transmitted from the transmission apparatus to the reception side monitor will be described with reference to FIG. As shown in FIG. 37A, the frame memory in the graphics card of the transmission device includes a display area 113-1 and a non-display area 113-2. In this display area 113-1, a rectangle including an area changed by drawing is drawn. In addition, header information is written in the non-display area 113-2. The transmission apparatus scans the frame memory in the change area portion, generates a transmission packet as shown in FIG. 37C in which a header is inserted in the portion one line ahead, and transmits it to the reception side monitor.

JP 2002-278526 A

  FIG. 38 shows a multi-input monitor system 100 constructed using a monitor corresponding to the DPVL standard. The multi-input monitor system 100 includes host computers 103 and 104 and a monitor 105 corresponding to the DPVL standard. Such a multi-input monitor system 100 has the following problems. In accordance with the DPVL standard, the host computers 103 and 104 transmit only the area where the image has been updated to the monitor 105 as a DPVL packet.

  Therefore, it is assumed that an image of the DPVL packet currently input from the host computer 103 is displayed, and when the image displayed here is switched to the image from the host computer 104, as shown in FIG. In addition, there is a problem that an image defect occurs in an image displayed after image switching. This is because, as described above, in the DPVL packet, the host computer transmits only the image data of the area where the image has been updated. Such image loss will occur until the entire range of the screen is covered by the acquired DPVL packet.

  Accordingly, an object of the present invention is to provide an image display device in which no image loss occurs when switching images or turning on the power no matter what image information is acquired.

  Means for solving the problems relating to the present invention and effects of the present invention will be described below.

  The image display device according to the present invention acquires image information, generates display image information for displaying an image in an image display area for each type of image based on the image information acquired from the image information acquisition unit, The generated display image information is held in the display image information holding unit for each type of image.

  As a result, even if the image type is switched and displayed in the image display area, the image can be reliably displayed without causing image loss regardless of the image type.

  The image display device according to the present invention further acquires image selection information for selecting an image to be displayed in the image display area from among a plurality of types of images, and acquires display image information corresponding to the acquired image selection information. The acquired display image information is displayed in the image display area, the image selection information is acquired, and even if the acquired image selection information is to select a certain image, the display image for other images is displayed. Information is held in display image information holding means for each type of image.

  As a result, even if the image is switched to a different image from the currently displayed image, the image can be displayed reliably without causing image loss.

  The image display device according to the present invention acquires partial image information, which is image information for displaying a part of the image, for at least one of a plurality of images, and based on the acquired partial image information, the image Display image information is generated for each type.

  As a result, even if the image type is switched and displayed in the image display area, even if the image is related to the partial image information, the image can be reliably displayed without causing image loss.

  The image display device according to the present invention displays the display image information based on the partial image information for each type of the image even if the image not selected in the image selection information corresponds to the partial image information. It holds in the information holding means.

  As a result, even when the currently displayed image is switched to the image related to the partial image information, the image can be reliably displayed without causing image loss in the image related to the partial image information.

  The image display device according to the present invention acquires a plurality of display image information based on the partial image information, generates one display image information obtained by integrating the acquired plurality of display image information, and is selected in the image selection information. Even if the missing image corresponds to the partial image information, the display image information generated by the display image information integration unit is held in the display image information holding unit for each type of image.

  This eliminates the need to hold the generated display image information in the display image information holding unit every time the partial image information is acquired. That is, the timing for holding the display image information in the display image information holding unit can be freely determined, so that an efficient image information holding process can be performed.

  The image display device according to the present invention holds the display image information in the display image information holding unit when determining that the processing for the display image information holding unit is not performed. Thus, efficient image information holding processing can be performed.

  The image display device according to the present invention acquires, for at least one of a plurality of images, entire image information that is image information for displaying the entire image, and further, an image that is not selected in the image selection information However, if it corresponds to the entire image information, the display image information is not generated based on the entire image information.

  As a result, when the entire image information is not selected as an image to be displayed, it is not necessary to perform display image information generation processing, so that power consumption can be reduced. Further, since display image information is not generated, it is not necessary to perform a holding process in the display image information holding unit, so that it is possible to further reduce power consumption.

  The image display apparatus according to the present invention further outputs request information for requesting provision of image information necessary for generating display image information when acquiring acquisition information indicating that image selection information has been acquired.

  As a result, even when the type of image to be displayed is switched, it is possible to reliably display an image without causing image loss regardless of the type of image.

  The image display device according to the present invention further determines whether or not the power source of the image display device is turned on, and further outputs request information when obtaining a determination that the power source is turned on.

  As a result, even when the power is turned on, it is possible to reliably display an image without causing image loss regardless of the type of image.

  The image display device according to the present invention further includes an adjustment display image for displaying in the image display area until display image information corresponding to the request information is displayed in the image display area of the image display device. After the information is generated and the request information is output, the adjusted display image information is displayed in the image display area until the display image information corresponding to the request information is displayed in the image display area.

  Thus, the display image information lacking the image is displayed in the image display area by displaying the adjusted display image information until the display image information corresponding to the request information is displayed in the image display area of the image display device. You can avoid it.

  The image display device according to the present invention further initializes the display image information holding means when acquiring the selection acquisition information indicating that the image selection information has been acquired.

  Thereby, at the time of image switching, it is possible to clearly determine a portion corresponding to the acquired image information and a portion in which an image defect has occurred because the image information has not yet been acquired.

  The image display device according to the present invention further initializes the display image information holding means when obtaining a determination that the power is turned on.

  As a result, when the power is turned on, it is possible to clearly determine the portion corresponding to the acquired image information and the portion where the image defect has occurred because the image information has not yet been acquired.

  “Image type” refers to each set divided into those having a common or series of images. When each pair is formed for each input port regardless of whether the image sources are the same or different, when each pair is formed for each image source regardless of whether the input ports are the same or different, etc. It includes the concept of

  “Generate display image information” means not only the case of generating display image information displayed in the entire image display area based on the acquired image information, but also an image corresponding to the display image information based on the acquired image information. This is a concept including a case where display image information is generated by specifying the position of information and storing the image information in a predetermined area of the display image information holding means.

  “Initialization” means that a value of a predetermined area in the display image information holding unit is a specific value, and is a concept including a case where the value is “0”.

  Here, the correspondence between the constituent elements described in the claims and the constituent elements in the embodiment is shown. The image display device corresponds to the monitors 5, 25 and 35. The display image information holding means is in the frame memories 515a and 515b, the image information acquiring means is in the input port 501, the display image information generating means is in the DPVL analysis circuit 507 and the frame memory control circuit 513, and the image holding control means is in the frame memory. In the memory control circuit 513 and the microcomputer 535, the image selection information acquisition means is in the switching circuit 531 and the microcomputer 535, the image display means is in the frame memory control circuit 513 and the microcomputer 535, and the power state determination means is in the power supply circuit 533 and the microcomputer 535. The request information output means is in the microcomputer 535 and the USB port 505, the initialization means is in the frame memory control circuit 513 and the microcomputer 535, the adjustment display image information generation means is in the dummy image generation circuit 537, and the adjustment display image information display means. Is the microcomputer 535 and dummy image generation times To 537, each corresponding.

  The image holding control means performs the processes of S2103 to S2121, S2201 to S2205, S2501 to S2513, S2601 to S2613, and S2903 to S2907, the image selection information acquisition means performs the processes of S2101 and S2901, and the image display means includes S2101 and S2221 to S2215. The power state determination means performs the processing of S2111, the request information output means performs the processes of S2113, S2117, and S2903, the initialization means performs the processes of S2111, S2113, and S2221 to S2225, and the adjustment display image information display means The processes of S2115, S2119 to S2121, and S2907 are performed.

  Image information corresponds to DPVL packets and raster image data, partial image information corresponds to DPVL packets, whole image information corresponds to raster image data, and display image information corresponds to monitor image data. The image selection information corresponds to switching information, the selection acquisition information corresponds to switching information output from the switching circuit 531 to the microcomputer 535, and the request information corresponds to full-screen request information. Further, the determination that the power supply is turned on corresponds to the power supply information output from the power supply circuit to the microcomputer 535.

The “program” is a concept including not only a directly executable program but also a source format program, a compressed program, an encrypted program, and the like. In addition, the function realized by the program may be realized by the program alone or may be realized in cooperation with another program (for example, an operating system).

  Before describing an embodiment of the multi-input monitor according to the present invention, a virtual screen, a monitor screen, a packet display area, and an updated image display area will be described.

  Here, the virtual screen refers to an image display area serving as a reference for the monitor screen. In the virtual screen, a coordinate system serving as a reference for determining the position of the monitor screen, the position of the packet display area, and the like is set. The monitor screen refers to an image display area where the monitor can actually display an image. The image data displayed on the entire monitor screen is taken as monitor image data. The packet display area is an image display area in which the image data of the DPVL packet is displayed. The updated image area is an image display area where the packet display area and the monitor screen overlap. That is, the updated image area is an image display area in which an image is actually updated on a monitor screen of a monitor.

  The positional relationship among the virtual screen, the monitor screen, the packet display area, and the update image area will be described with reference to FIG. Assume that the upper left end point of the virtual screen R1 is the origin (0, 0), the X axis is in the right direction, and the Y axis is in the downward direction. The position of the monitor screen R5 constituting a part of the virtual screen R1 with respect to the virtual screen R1, the position of the upper left end point (MXORG, MYORG) of the monitor screen R5, and the size of the monitor screen R5 in the X direction and Y direction ( MXWID, MYWID). Further, the position of the packet display area R7 with respect to the virtual screen R1, the position of the upper left end point T1 of the packet display area R7 (XORG, YORG), and the size of the packet display area R7 in the X direction and Y direction (XSIZE, YSIZE) ). Further, the position of the update image area R9 with respect to the virtual screen R1, the position of the upper left end point T1 ′ of the update image area R9 (XORG ′, YORG ′), and the size of the packet display area R7 in the X direction and Y direction ( XSIZE ', YSIZE').

  Next, the data structure of the DPVL packet is shown in FIG. The DPVL packet is composed of a header part H1 and a body part B1. The header portion H1 has an area for describing HTYP, XORG, XSIZE, HOFF, YORG, and YSIZE. Here, HTYP represents a header type. XORG, YORG, XSIZE, and YSIZE represent the position (XORG, YORG) of the upper left end point T1 of the packet display area R7, and the sizes (XSIZE, YSIZE) of the packet display area R7 in the X direction and Y direction, respectively. HOFF is a value indicating an area (hereinafter referred to as an offset area) provided in the − (minus) direction of the X axis with respect to the update image area R9. In the offset area, the image is not updated. This offset value is defined by the DPVL standard.

  The body part B1 has image data to be displayed in the packet display area R7. In the DPVL standard, the packet display area R7 is defined as a rectangular area.

1. Functional Block Diagram FIG. 3 shows a functional block diagram of the image display device M1 in this embodiment. The image display device M1 includes display image information holding means M11, image information acquisition means M12, display image information generation means M19, image holding control means M13, image selection information acquisition means M14, image display means M15, power supply state determination means M16, Request information output means M17, initialization means M18, adjustment display image information generation means 10 and adjustment display image information display means M20 are provided.

  The image information acquisition unit M12 acquires image information. Further, the image information acquisition unit M12 acquires partial image information that is image information for displaying a part of the image for at least one of the plurality of images.

  The display image information generation means M19 generates display image information for displaying an image in the image display area for each type of image based on the image information acquired from the image information acquisition means M12. The display image information generation unit M19 generates display image information for each type of image based on the partial image information acquired from the image information acquisition unit M12.

  The image holding control unit M13 holds the display image information generated by the display image information generating unit M19 in the display image information holding unit M11 for each image type. Further, the image holding control means M13 acquires the image selection information from the image selection information acquisition means M14, and even if the acquired image selection information indicates that a certain image is selected, the display image for other images is displayed. Information is generated, and the generated display image information is held in the display image information holding unit M11 for each type of image. Further, the image holding control means M13 displays the display image information based on the partial image information for each type of the image even if the image not selected in the image selection information corresponds to the partial image information. The information is held in the information holding means M11.

  The image selection information acquisition unit M14 acquires image selection information for selecting an image to be displayed in the image display area from among a plurality of types of images.

  The image display means M15 acquires image selection information from the image selection information acquisition means M14, acquires display image information corresponding to the acquired image selection information from the display image information holding means M11, and displays the acquired display image information as an image display. Display in the area.

  The power state determination means M16 determines whether or not the power of the image display apparatus M1 is turned on.

  The request information output unit M17 outputs the request information upon obtaining a determination that the power is turned on from the power supply state determination unit M16.

  The initialization unit M18 initializes the display image information holding unit M11 when acquiring the determination that the power is turned on from the power state determination unit M16.

  The adjusted display image information generating unit M10 generates adjusted display image information for displaying in the image display area until the display image information corresponding to the request information is displayed in the image display area of the image display device. .

  The adjusted display image information display means M20 displays the adjusted display image information in the image display area until the display image information corresponding to the request information is displayed in the image display area after the output of the request information.

  As a result, even if the image type is switched and displayed in the image display area, the image can be reliably displayed without causing image loss regardless of the image type. In addition, even when the image is switched to a different image from the currently displayed image, the image can be reliably displayed without causing image loss. Furthermore, even if the image type is switched and displayed in the image display area, even if it is an image related to partial image information, the image can be reliably displayed without causing image loss. Furthermore, even when the currently displayed image is switched to the image related to the partial image information, the image can be reliably displayed without causing image loss in the image related to the partial image information.

  Furthermore, even when the power is turned on, an image can be displayed reliably without causing image loss regardless of the type of image. Furthermore, when the power is turned on, it is possible to clearly determine the portion corresponding to the acquired image information and the portion where the image defect has occurred because the image information has not yet been acquired.

  Further, the display image information lacking the image is displayed in the image display area by displaying the adjusted display image information until the display image information corresponding to the request information is displayed in the image display area of the image display device. You can prevent it from happening.

2. Hardware configuration
2.1. Hardware Configuration of Multi-Input Monitor System 1 FIG. 4 shows a hardware configuration of the multi-input monitor system 1 using the image display device according to the present invention. The multi-input monitor system 1 includes host computers 3a and 3b and monitors 5a, 5b and 5c. The host computers 3a, 3b and the monitors 5a, 5b, 5c are connected via a digital cable 7a (hereinafter referred to as a DVI cable 7a) corresponding to the DVI standard for transmitting DPVL packets. The host computer 3a and the monitors 5a, 5b, and 5c are connected to each other through the USB 9a. Similarly to the host computer 5a, the host computer 3b is also connected to the monitors 5a, 5b and 5c via the DVI cable 7b and the USB 9b. The monitors 5a, 5b, and 5c are cascade-connected using the DVI cables 7a and 7b in this order.

  The host computers 3a and 3b transmit DPVL packets corresponding to the aforementioned DPVL standard to the monitors 5a, 5b and 5c. The monitor 5a displays an image based on the DPVL packet received from the host computers 3a and 3b. The monitor 5b displays an image based on the DPVL packet received from the cascade-connected monitor 5a. The monitor 5c displays an image based on the DPVL packet received from the cascade-connected monitor 5b.

  Furthermore, the monitors 5a, 5b, and 5c are provided with the positions (MXORG, MYORG) of the upper left corners of the monitor screen R5 (see FIG. 1) of each monitor, and the sizes (MXWID, MYWID) is received from the host computers 3a, 3b via the USB 9a, 9b.

2.2. Hardware Configuration of Monitor 5 One of the features of the hardware configuration of monitors 5a, 5b, 5c (hereinafter referred to as monitor 5) in this embodiment is at least an image displayed on the entire monitor screen R5. It has two frame memories that can hold monitor image data for one frame.

  The hardware configuration of the monitor 5 is shown in FIG. The monitor 5 includes an A and B2 channel input port 501, an A and B2 channel output port 503, a USB port 505, a two channel DPVL analysis circuit 507, bit width conversion circuits 509 and 517, data buffers 511 and 519, and a frame. A memory control circuit 513, frame memories 515a and 515b, an LCD output port 521, an LCD 523, a switching circuit 531, a power supply circuit 533, a microcomputer 535 (microcomputer 535), and a dummy image generation circuit 537 are provided.

  The input port 501 receives a DPVL packet from the host computer 3a, 3b (see FIG. 4) or the monitor 5 connected before itself. The output port 503 transmits a DPVL packet to the monitor 5 connected after itself. The USB port 505 receives monitor screen position information from the host computer 3. The monitor screen position information is recorded at a predetermined position according to various control tables for devices called HID Usage Tables (HID table) defined by the USB standard.

  The DPVL analysis circuit 507 performs packet analysis processing, header analysis processing, address calculation processing, and packet reconstruction processing on the received DPVL packet. The DPVL analysis circuit 507 will be described later.

  The bit width conversion circuit 509 converts the DPVL packet received from the outside into the number of bits that can be processed internally. The data buffer 511 temporarily holds DPVL packets received from the outside and converted in bit width.

  The frame memory control circuit 513 performs processing for writing / reading image data to be displayed on the LCD 523 to / from the frame memory 515. The operation of the frame memory control circuit 513 will be described later.

  The frame memory 515 includes a frame memory 515a and a frame memory 515b. Each of the frame memories 515a and 515b has a capacity sufficient to hold one frame of monitor image data displayed on the LCD 523.

  The bit width conversion circuit 517 performs bit width conversion for displaying image data on the LCD 523. The data buffer 519 temporarily holds the DPVL packet whose bit width has been converted when it is output to the LCD 523. The LCD output port 521 outputs image data for display on the LCD 523. The LCD 523 displays image data on its own monitor screen R5.

  The switching circuit 531 has a switching button and an infrared receiving unit for acquiring a switching signal from an external remote controller. When the switching circuit 531 acquires a switching signal from a switching button or the like, the switching circuit 531 transmits switching information indicating image switching to the microcomputer 535.

  When the power of the monitor 5 is turned on, the power supply circuit 533 generates power supply information and transmits it to the microcomputer 535.

  The microcomputer 535 controls operations of the memory control circuit 513 and the dummy image generation circuit 537. The microcomputer 535 communicates with the host computers 3a and 3b via the USB port 505. The operation of the microcomputer 535 will be described later.

  The dummy image generation circuit 537 generates a dummy image and outputs it to the LCD 523.

3. DPVL analysis circuit 507
The DPVL analysis circuits 507 for the A, B, and 2 channels perform monitor image data generation processing on the DPVL packets acquired from the corresponding input ports 501 and output the monitor image data to the memory control circuit 513. The monitor 5 displays either one of the monitor image data generated based on the acquired DPVL packet acquired from one of the input ports 501 on the monitor screen R5 of the LCD 523. The DPVL analysis circuit 507 Regardless of whether it is displayed on the screen R5, monitor image data generation processing is performed for each input port on the DPVL packet acquired from the input port 501.

  First, the logic circuit of each DPVL analysis circuit 507 is shown in FIG. The DPVL analysis circuit 507 includes an input port 507a, an output port 507b, a packet analysis circuit 507c, a header analysis circuit 507d, a cache 507e, an address calculation circuit 507f, and a packet reconstruction circuit 507g.

  The input port 507a receives the DPVL packet received by the input port 501 (see FIG. 5) as an acquired DPVL packet. The output port 507b transmits the reconstructed DPVL packet acquired from the packet restructuring circuit 507g to the output port 503 and the bit width conversion circuit 509 (see FIG. 5).

  The packet analysis circuit 507c separates the acquired DPVL packet acquired from the input port 507a into a header part H1 and a body part B1. Further, the packet analysis circuit 507c transmits the separated header portion H1 to the header analysis circuit 507d. Further, the packet analysis circuit 507c transmits the separated body part B1 to the bit width conversion circuit 509 (see FIG. 5) via the output port 507b.

  The header analysis circuit 507d determines the positional relationship of the packet display area R7 with respect to the monitor screen R5 in the acquired DPVL packet based on the header portion H1 of the acquired DPVL packet and the monitor screen position information held in the HID table.

  The packet reconstruction circuit 507g determines the image data corresponding to the monitor screen R5 from the image data of the acquired DPVL packet based on the determination of the positional relationship of the packet display area R7 with respect to the monitor screen R5 in the acquired DPVL packet performed by the header analysis circuit 507d. Image data other than is extracted as output image data. Further, the packet reconstruction circuit 507g determines the positional relationship of the packet display area R7 with respect to the monitor screen R5 in the acquired DPVL packet by the header analysis circuit 507d with respect to the virtual screen R1 of the image display area displayed by the extracted output image data. A header part indicating the positional relationship is generated as an output header part. The packet restructuring circuit 507g newly generates an output DPVL packet to be output to the cascaded monitor based on the extracted output image data and the generated output header part.

  The address calculation circuit 507f calculates a physical address when the image data corresponding to the updated image area R9 is held in the frame memories 515a and 515b (see FIG. 5).

  Hereinafter, the processes of the header analysis circuit 507d, the address calculation circuit 507f, and the packet reconstruction circuit 507g in the monitor image data generation process will be described in detail.

3.1. Header analysis circuit 507d
The header analysis circuit 507d first determines in which position the packet display area R7 of the acquired DPVL packet is located with respect to the monitor screen R5 of the LCD 523.

  The header analysis circuit 507d extracts XORG, XSIZE, YORG, and YSIZE from the header portion H1 (see FIG. 2) of the acquired DPVL packet, and holds it in the cache 507e (see FIG. 6). Next, the header analysis circuit 507d determines where the upper left end point T1 of the packet display area R7 (see FIG. 1) of the acquired DPVL packet is located with respect to the monitor screen R5. First, the header analysis circuit 507d determines whether the end point T1 exists inside or outside the monitor screen R5 with respect to the left side of the monitor screen R5. As shown in FIG. 7, the case where the end point T1 is outside the monitor screen R5 with respect to the left side LL of the monitor screen R5 is the case where the end point T1 is at the position A and the case where the end point T1 is inside. This is the case where the end point T1 is at the position B. In order to determine whether the end point T1 is at the position A or B, the header analysis circuit 507d compares XORG indicating the X coordinate of the end point T1 with MXORG indicating the X coordinate of the left side LL. When MXORG> = XORG, the header analysis circuit 507d determines that the end point T1 is at the position A, sets the value of “cmp_mx0px0” to “0”, and holds it in the cache 507e. On the other hand, when XORG> MXORG, the header analysis circuit 507d determines that the end point T1 is at the position B, and stores the value of “cmp_mx0px0” in the cache 507e as “1”.

  Next, the header analysis circuit 507d determines whether the end point T1 exists inside or outside the monitor screen R5 with respect to the right side RR of the monitor screen R5. As shown in FIG. 7, the case where the end point T1 is inside the monitor screen R5 with respect to the right side RR of the monitor screen R5 is the case where the end point T1 is at the position C, and the case where the end point T1 is outside is the end point. This is the case when T1 is at the position D. In order to determine whether the end point T1 is at the position C or D, the header analysis circuit 507d compares XORG indicating the X coordinate of the end point T1 with MXORG + MXWID indicating the X coordinate of the right side RR. When MXORG + MXWID> = XORG, the header analysis circuit 507d determines that the end point T1 is at the position C, sets the value of “cmp_mx1px0” to “0”, and holds it in the cache 507e. On the other hand, when XORG> MXORG + MXWID is satisfied, the header analysis circuit 507d determines that the end point T1 is at the position D, stores the value of “cmp_mx1px0” in the cache 507e as “1”.

  FIG. 11A shows an example of a logic circuit when the header analysis circuit 507d realizes the processing so far. Here, “+” indicates the full addition circuit shown in FIG. 12A, and “<” indicates the 4-bit comparison circuit shown in FIG. 12B.

  Next, the header analysis circuit 507d determines whether the end point T1 is inside or outside the monitor screen R5 with respect to the upper side of the monitor screen R5, and the monitor screen R5 with respect to the lower side of the monitor screen R5. It is judged whether it exists inside or outside. As shown in FIG. 8, the case where the end point T1 is outside the monitor screen R5 with respect to the upper side TT of the monitor screen R5 is the case where the end point T1 is at the position A and the case where the end point T1 is inside. This is the case where the end point T1 is at the position B. Further, the case where the end point T1 is outside the monitor screen R5 with respect to the lower side BB of the monitor screen R5 is the case where the end point T1 is at the position D, and the case where the end point T1 is inside is that the end point T1 is C. It will be the case. The header analysis circuit 507d calculates the values of “cmp_my0py0” and “cmp_my1py0” and holds them in the cache 507e in the same way as the determination of the positional relationship between the end point T1 and the left and right sides.

  Next, the header analysis circuit 507d determines where the lower right end point T4 of the packet display area R7 (see FIG. 1) of the acquired DPVL packet is located with respect to the monitor screen R5. The header analysis circuit 507d determines whether the end point T4 exists inside or outside the monitor screen R5 with respect to the left side of the monitor screen R5, and inside the monitor screen R5 with respect to the right side of the monitor screen R5. Whether it exists or not is determined. As shown in FIG. 9, the case where the end point T4 is outside the monitor screen R5 with respect to the left side LL of the monitor screen R5 is the case where the end point T4 is at the position A, and the case where the end point T4 is inside. This is the case where the end point T1 is at the position B. Further, the case where the end point T4 is outside the monitor screen R5 with respect to the right side RR of the monitor screen R5 is the case where the end point T4 is at the position D, and the case where the end point T4 is inside is that the end point T4 is C. It will be the case. The header analysis circuit 507d calculates the values of “cmp_mx0px1” and “cmp_mx1px1” and holds them in the cache 507e in the same manner as in the case of the end point T1.

  Finally, the header analysis circuit 507d determines whether the end point T4 is inside or outside the monitor screen R5 with respect to the upper side of the monitor screen R5, and the monitor screen R5 with respect to the lower side of the monitor screen R5. It is judged whether it exists inside or outside. As shown in FIG. 10, the case where the end point T4 is outside the monitor screen R5 with respect to the upper side TT of the monitor screen R5 is the case where the end point T4 is at the position A and the case where the end point T4 is inside. This is the case where the end point T1 is at the position B. The case where the end point T4 is outside the monitor screen R5 with respect to the lower side BB of the monitor screen R5 is the case where the end point T4 is at the position D, and the case where the end point T4 is inside is the case where the end point T4 is C. It will be the case. The header analysis circuit 507d calculates the values of “cmp_my0py1” and “cmp_my1py1” and holds them in the cache 507e in the same manner as in the case of the end point T1.

  As described above, in the DPVL standard, since the image displayed by the DPVL packet is rectangular, if the positions of the end portions T1 and T4 can be specified, the end portions T2 and T3 can also be specified. As a result, the header analysis circuit 507d can specify the position of the packet display area R7 of the acquired DPVL packet with respect to the monitor screen R5.

  Next, the header analysis circuit 507d specifies which area of the monitor screen R5 of the LCD 523 is updated by the acquired DPVL packet. That is, the header analysis circuit 507d specifies the positions (see FIG. 1) of the end points T1 ′, T2 ′, T3 ′, and T4 ′ of the update image region R9 in order to specify the range of the update image region R9 (see FIG. 1). To do. As shown in FIG. 1, since the update image area R9 is rectangular, the update image area R9 can be specified if the positions of the end portions T1 'and T4' can be specified.

  The header analysis circuit 507d determines the values of hdst, vdst, hdd, vded, xoff, yoff, hdst_flag, and hdd_flag based on the position specification table shown in FIG. 13, and stores the values in the cache 507e. Here, hdst represents the X coordinate of the end point T1 'with respect to the monitor screen R5. vdst represents the Y coordinate of the end point T1 'with respect to the monitor screen R5. xoff indicates the magnitude of the offset set in the end point T1 'in the X direction. yoff indicates the magnitude of the offset set in the end point T1 'in the Y direction. vdst represents the X coordinate of the end point T4 'with respect to the monitor screen R5. vded indicates the Y coordinate of the end point T4 'with respect to the monitor screen R5. hdst_flag is a flag indicating whether or not the X coordinate of the end point T1 'exists in the monitor screen R5 of the LCD 523. If it exists in the monitor screen R5, it is "1", and if it does not exist, it is "0". vdst_flag is a flag indicating whether or not the Y coordinate of the end point T <b> 1 ′ exists in the monitor screen R <b> 5 of the LCD 523. The hdd_flag is a flag indicating whether or not the X coordinate of the end point T4 'exists in the monitor screen R5 of the LCD 523. vded_flag is a flag indicating whether or not the Y coordinate of the end point T4 'exists in the monitor screen R5 of the LCD 523. Each is “1” if it exists in the monitor screen R5, and “0” if it does not exist.

  A procedure for specifying the positions of the end points T1 'and T4' using the position specifying table shown in FIG. 13 will be described. In the position specification table, cmp_mx1px0, cmp_mx0px0,... Indicate values calculated when the header analysis circuit 507d specifies the positions of the end points T1 and T4 in the packet display area R7 (see FIG. 1) of the acquired DPVL packet.

  First, consider the case where the position of the X coordinate of the end point T1 'is specified. In the case of (cmp_mx1px0, cmp_mx0px0) = (0, 0), the end point T1 of the packet display area R7 of the acquired DPVL packet is at the position of A or A ′ as shown in FIG. That is, if (cmp_mx1px0, cmp_mx0px0) = (0, 0), there is a possibility that there is an area where the packet display area R7 of the acquired DPVL packet and the monitor screen R5 overlap, that is, the image update area R9. Therefore, “1” is set to hdst_flag. If the image update region R9 exists, the X coordinate of the end point T1 'is always MXORG. Therefore, hdst indicating the X coordinate of the end point T1 'with respect to the monitor screen R5 is MXORG-MXORG (= 0). Since the end point T1 'is always on the left side of the monitor screen R5, xoff = 0. Whether the end point T1 is at the position A or the position A 'is determined by the position of the end point T4.

  Next, when (cmp_mx1px0, cmp_mx0px0) = (0, 1), the end point T1 of the packet display area R7 of the acquired DPVL packet is at the position B or C as shown in FIG. That is, if (cmp_mx1px0, cmp_mx0px0) = (0, 1), the image update region R9 always exists. Therefore, “1” is set to hdst_flag. The X coordinate of the end point T1 'of the image update region R9 is always XORG. Therefore, hdst indicating the X coordinate of the end point T1 'with respect to the monitor screen R5 is XORG-MXORG. Xoff related to the end point T1 'sets a value of HOFF which is an offset value in the acquired DPVL packet.

  Next, considering the case of (cmp_mx1px0, cmp_mx0px0) = (1, 0), such a case cannot occur (see FIG. 7). Therefore, “0” is set to hdst_flag. In this case, it is not necessary to set hdst and xoff in particular, so the values set previously are set as they are.

  Finally, considering the case of (cmp_mx1px0, cmp_mx0px0) = (1, 1), as shown in FIG. 7, the packet display area R7 of the acquired DPVL packet always exists outside the monitor screen R5, and the image update area R9 is It will not always exist. Therefore, “0” is set to hdst_flag. In this case, it is not necessary to set hdst and xoff in particular, so the values set previously are set as they are.

  When the position of the Y coordinate of the end point T1 'is specified, it is considered in the same way as when the position of the X coordinate of the end point T1' is specified (see FIG. 9).

  Next, consider a case where the position of the X coordinate of the end point T4 'is specified. Considering the case of (cmp_mx1px1, cmp_mx0px1) = (0, 0), as shown in FIG. 8, the end point T4 of the packet display area R7 of the acquired DPVL packet exists at the position A, and the image update area R9 Will not always exist. Therefore, “0” is set in hded_flag. In this case, since it is not necessary to set hded, the value set previously is set as it is.

  Next, when (cmp_mx1px1, cmp_mx0px1) = (0, 1), as shown in FIG. 8, the end point T4 of the packet display area R7 of the acquired DPVL packet is at the position of B or C. That is, if (cmp_mx1px1, cmp_mx0px1) = (0, 1), the image update region R9 always exists. Therefore, “1” is set in hded_flag. The X coordinate of the end point T4 'of the image update region R9 is always XORG + XSIZE. Therefore, hded indicating the X coordinate of the end point T4 'with respect to the monitor screen R5 is XORG + XSIZE-MXORG.

  Next, considering the case of (cmp_mx1px1, cmp_mx0px1) = (1, 0), such a case cannot occur (see FIG. 8). Therefore, “0” is set in hded_flag. In this case, since it is not necessary to set hded, the value set previously is set as it is.

  Finally, considering the case of (cmp_mx1px1, cmp_mx0px1) = (1, 1), the end point T4 of the packet display area R7 of the acquired DPVL packet is at the position of D or D ′ as shown in FIG. . That is, if (cmp_mx1px1, cmp_mx0px1) = (1, 1), there is a possibility that there is an area where the packet display area R7 of the acquired DPVL packet and the monitor screen R5 overlap, that is, the image update area R9. Therefore, “1” is set to hdst_flag. If the image update region R9 exists, the X coordinate of the end point T4 'is always MXORG + MXWID. Therefore, hded indicating the X coordinate of the end point T4 'with respect to the monitor screen R5 is MXORG + MXWID-MXORG = MXWID. Whether the end point T4 is at the position D or the position D 'is determined by the position of the end point T1.

  When the position of the Y coordinate of the end point T4 'is specified, it is considered in the same way as when the position of the X coordinate of the end point T4' is specified (see FIG. 10).

  Through the above procedure, the header analysis circuit 507d specifies the positions of the end portions T1 'and T4'.

3.2. Address calculation circuit 507f
When the header analysis circuit 507d finishes specifying the positions of the end points T1 ′, T2 ′, T3 ′, and T4 ′ of the update image area R9, the address calculation circuit 507f (see FIG. 6) displays the image data corresponding to the update image area R9. An address when the (updated image data) is held in the frame memories 515a and 515b is calculated.

  The frame memories 515a and 515b hold at least one frame of monitor image data currently displayed on the monitor screen R5 of the LCD 523. A logical address space R515 in the frame memories 515a and 515b is shown in FIG. In the logical address space R515 in the frame memories 515a and 515b in FIG. 14, the upper left end point is the address “00000000h” and the lower right end point is “FFFFFFFFh”.

  In the logical address space R515, an area where monitor image data displayed on the monitor screen R5 is held is an area R5 ', and an area where updated image data is held is an area R9'. The address calculation circuit 507f specifies the position of the region R9 'in the logical address space R515 based on the hdst, vdst, xoff, hded, and vded calculated by the header analysis circuit 507d and held in the cache 507e.

  The address calculation circuit 507f determines whether or not the updated image area R9 obtained by the header analysis circuit 507d is completely included in the monitor screen R5 before obtaining the logical address. In the header analysis circuit 507d, the positions of the end points T1 'and T4' of the update image region R9 are specified individually. Therefore, the address calculation circuit 507f determines whether or not the entire update image area R9 exists in the monitor screen R5. The address calculation circuit 507f acquires hdst_flag, vdst_flag, hdd_flag, and vded_flag calculated by the header analysis circuit 507d, and calculates a logical product of them. If the calculated logical product is “1”, the address calculation circuit 507f calculates a logical address. The logical product being “1” means that the end points T1 ′ and T4 ′ are both present in the monitor screen R5, that is, the updated image region R9 is present in the monitor screen R5. To do.

  FIG. 15A shows an example of a logic circuit when the address arithmetic circuit 507f determines whether or not the updated image region R9 exists in the monitor screen R5.

  As shown in FIG. 14, if the area R5 starts from the address “00000000h”, the address calculation circuit 507f sets the address of frame width (the width of the frame memory 515) × vdst + hdst as the end point T1 of the update image area R9. Calculate as the address corresponding to '.

  Similarly, the address calculation circuit 507f calculates an address of frame width (width of the frame memory 515) × vded + hded as an address corresponding to the end point T4 ′. The address arithmetic circuit 507f converts the calculated logical address into a physical address. FIG. 15B shows an example of a logic circuit when the address arithmetic circuit 507f converts a logical address into a physical address.

  As described above, by calculating the physical address, the monitor image data is generated when the image data included in the updated image region R9 is stored in the predetermined region R9 'of the frame memory.

  The address calculation circuit 507 f transmits, to the frame memory control circuit 513, update area information in which the port identification information for identifying the input port 501 that acquired the acquired DPVL packet and the converted physical address are associated with each other.

3.3. Packet reconstruction circuit 507g
The processing performed by the packet reconstruction circuit 507g will be described based on the flowchart shown in FIG. The packet reconstruction circuit 507g determines whether or not the packet display area R7 of the acquired DPVL packet fits within the monitor screen R5, that is, whether or not the acquired DPVL packet is a packet within the monitor screen R5, under Condition 1 shown in FIG. Based on the determination (S1701). If the packet reconstruction circuit 507g determines that the packet display area R7 of the acquired DPVL packet fits within the monitor screen R5, the packet reconstructing circuit 507g deletes the acquired DPVL packet (S1703) and does not output it to the monitor connected thereafter.

  On the other hand, if it is determined in step S1701 that the packet display area R7 of the acquired DPVL packet does not fit within the monitor screen R5, the packet reconstruction circuit 507g determines whether the acquired DPVL packet is a DPVL packet that can be reconstructed. (S1705). Condition 2 determines that the packet display area R7 of the acquired DPVL packet is outside the range of the monitor screen R5.

  If it is determined in step S1705 that the packet can be reconstructed, the packet reconstruction circuit 507g determines whether there is image data that can be deleted in the Y-axis direction based on Condition 3 shown in FIG. 17 (S1707). . Condition 3 is that the packet display region R7 of the acquired DPVL packet includes only the upper boundary (a), includes only the lower boundary (b), and includes the upper and lower boundaries (c). It is judged whether it corresponds to either.

  Then, according to the determination based on the condition 3, the packet reconstruction circuit 507g reconstructs the packet based on the conversion formula 1 shown in FIG. 18 (S1709). The packet reconstruction circuit 507g divides the image data of the acquired DPVL packet that satisfies the condition 3 at the upper and lower boundaries. Further, the packet reconstruction circuit 507g needs to generate a header part for packet reconstruction of the divided image data. The header part is generated based on the conversion formula 1. In the conversion formula 1, the X and Y coordinates of the upper right end point of the divided image data are XORG ′ (or XORG ″), YORG ′ (YORG ″), the size of the image data in the X axis direction, the Y axis The size of the direction is set to XSIZE ′ (XSIZE ″) and YSIZE ′ (YSIZE ″).

  Next, the packet restructuring circuit 507g has, for each reconstructed DPVL packet, whether or not the DPVL packet can be reconstructed based on the condition 2, that is, has only the packet display area R7 outside the monitor screen R5. It is determined whether the packet is a DPVL packet (S1711). When the packet reconstruction circuit 507g determines that the reconstructed DPVL packet matches the conditional expression 2, that is, it is impossible to reconstruct the packet, the packet reconstruction circuit 507g directly outputs the DPVL packet to the subsequent monitor (S1719). .

  If the packet reconstruction circuit 507g does not satisfy the conditional expression 2, that is, if it is determined that the reconstructed DPVL packet can be reconstructed, the condition shown in FIG. 17 indicates whether there is image data that can be deleted in the X-axis direction. 4 is determined (S1713). Condition 4 indicates that any of the case where the packet display region R7 of the acquired DPVL packet includes only the left boundary (a), only the right boundary (b), and the left and right boundaries (c). It is judged whether it corresponds to.

  If the packet reconstruction circuit 507g determines that there is image data that can be deleted in the X-axis direction, the packet reconstruction circuit 507g reconstructs the DPVL packet based on the conversion equation 2 (S1715). Note that the reconstruction of the DPVL packet in step S is performed in the same manner as the reconstruction of the DPVL packet in step S1709. Then, the packet reconstruction circuit 507g determines whether or not the reconstructed DPVL packet can be reconstructed based on the condition 2 in the same manner as in step S1711 (S1717). The packet reconstruction circuit 507g deletes the reconstructed DPVL packet that satisfies the condition 2 (S1721). On the other hand, the packet reconstruction circuit 507g outputs the reconstructed DPVL packet that does not meet the condition 2 to the subsequent monitor as it is (S1719).

  When a DPVL packet is output in step S1719, a DPVL packet is output from the output port 502 corresponding to the input port 501 that acquired the acquired DPVL packet that is the source of the output DPVL packet (see FIG. 5). .

  The processing performed by the packet reconstruction circuit 507g will be specifically described with reference to FIG. In FIG. 19, A to J indicate packet display areas of acquired DPVL packets. FIG. 19 also shows the coordinate values of some packet display areas.

  The acquired DPVL packets of G and H are deleted by the packet reconstruction circuit 507g according to the condition 1. Further, the acquired DPVL packets of H and I are output as they are to the subsequent monitor according to the condition 2.

  Eventually, the acquired DPVL packets to be reconstructed are those including the boundary of the monitor screen R5, that is, acquired DPVL packets A to F. First, the acquired DPVL packets of A, A ′, B, and C including the upper or lower boundary are extracted according to the condition 3. Then, the image data of each acquired DPVL packet is divided into image data existing above the boundary and image data existing below the boundary. A's acquired DPVL packet is divided into A1 and A2 image data. The acquired DPVL packet of A ′ is divided into A1 ′ and A2 ′ image data. Next, a header part is generated for the divided image data. For example, for A1 image data, YORG '= YORG and YSIZE' = YORG + YSIZE-MYORG are obtained from the conversion formula 1 (see FIG. 18). Note that XORG 'and XSIZE' are the same as the XORG and XSIZE of the header portion relating to the image data before division. Then, the DPVL packet is reconstructed with the image data of A1 and the generated header part.

  Since the DPVL packets reconstructed with respect to A1 and A1 'meet the condition 2 (see FIG. 17), they are output as they are to the subsequent monitor. On the other hand, DPVL packets reconstructed for A2 and A2 'are subject to determination in Condition 4 (see FIG. 17).

  The target of condition 4 is the acquired DPVL packets of A2, A2 ', D, E, and F. Here, the acquired DPVL packet of A2 is deleted from condition 4. Since the acquired DPVL packets of A2 ', D, E, and F include the right or left boundary of the monitor screen R5, they are subject to reconstruction based on the conversion formula 2. For E acquired DPVL packets, DPVL packets are reconstructed for E1 and E2. Then, the DPVL packet reconstructed for E1 is deleted according to the condition 2. On the other hand, the DPVL packet reconstructed for E2 is output to the subsequent monitor. The same applies to other acquired DPVL packets.

4. Microcomputer 535
The microcomputer 535 controls the operation of the frame memory control circuit 513 and the like based on the switching information from the switching circuit 531 and the power supply information from the power supply circuit 533. The operation of the microcomputer 535 will be described based on the flowchart shown in FIG.

  When the microcomputer 535 obtains the switching information from the switching circuit 531 (S2101), the microcomputer 535 displays the switching control information for reading the image information from a frame memory different from the frame memory from which the monitor image data has been read so far. The data is output to the control circuit 513 (S2103).

  In addition, when the microcomputer 535 acquires the power supply information indicating that the power supply is turned on from the power supply circuit 533 (S2111), the microcomputer 535 initializes the value of the area holding the monitor image data in the frame memories 515a and 515b, Initialization control information indicating that reading is not performed until the timing is output to the frame memory control circuit 513 (S2113). Further, the microcomputer 535 controls the dummy image generation circuit 537 to generate a dummy image and outputs it to the LCD 523 (S2115). In this embodiment, the dummy image generation circuit 537 generates a blue screen as a dummy image.

  Further, when the microcomputer 535 obtains the power supply information indicating that the power of the monitor 5 is turned on from the power supply circuit 533, the microcomputer 535 sends the full screen request information requesting all the transmission of the monitor image data via the USB port 505. It outputs (S2117).

  Further, when the microcomputer 535 determines that the update completion information (described later) has been acquired (S2119), the microcomputer 535 controls the dummy image generation circuit 537 to stop generating the dummy image (S2121).

5. Frame memory control circuit 513
The operation of the frame memory control circuit 513 will be described with reference to the flowcharts shown in FIGS. 21a and 21b. As shown in FIG. 21a, when the frame memory control circuit 513 acquires the update area information (S2201), it extracts the port identification information (S2203). The frame memory control circuit 513 updates the values of the frame memories 515a and 515b corresponding to the extracted port information number information with the updated image data based on the physical address calculated by the address calculation circuit 507f (S2205).

  Similar to the DPVL analysis circuit 507 described above, the frame memory control circuit 513 performs the step regardless of whether the monitor image data currently displayed on the LCD 523 is acquired from which input port 501 or not. The processing of S2201 to S2205 is executed. Thereby, even if the monitor image data displayed on the monitor screen R5 is switched, it is possible to prevent image loss at the time of switching.

  Further, the frame memory control circuit 513 periodically reads monitor image data from the frame memory at a predetermined timing (S2241), and outputs the read monitor image data (S2243).

  Further, when the frame memory control circuit 513 acquires the switching control information output from the microcomputer 535 in step S2103 (see FIG. 20) (S2211), the frame memory that reads monitor image data is switched and the switched frame memory is switched. Monitor image data is read out from (S2213). Then, the frame memory control circuit 513 outputs the read monitor image data (S2215).

  Next, the operation when the frame memory control circuit 513 acquires the initialization control information will be described with reference to FIG. When obtaining the initialization control information (S2221), the frame memory control circuit 513 stops reading monitor image data from the frame memory (S2223). Then, the frame memory control circuit 513 initializes the frame memories 515a and 515b with predetermined values (S2225).

  When the frame memory control circuit 513 determines that the monitor image data transmitted in accordance with the full-screen request information from the microcomputer 535 has been acquired (S2227), the frame memory control circuit 513 stores the monitor image data in the frame memories 515a and 515b. The value is updated (S2229). When the frame memory control circuit 513 updates all the values of the area holding the monitor image data in the frame memories 515a and 515b with the acquired monitor image data, the frame memory control circuit 513 updates the value of the frame memory with the newly acquired monitor image data. Update completion information indicating that it has been sent is transmitted to the microcomputer 535 (S2231). The frame memory control circuit 513 reads the monitor image data updated in step S2229 from predetermined frame memories 515a and 515b (S2233). The predetermined frame memory is a frame memory that holds monitor image data that was displayed when the power was turned off last time. The frame memory control circuit 513 outputs the read monitor image data (S2235).

1. Functional Block Diagram FIG. 22 shows a functional block diagram of the image display device M2 in this embodiment. The image display device M2 includes a display image information holding unit M11, an image holding control unit M13, an image selection information acquisition unit M14, an image display unit M15, a power state determination unit M16, a request information output unit M17, an initialization unit M18, and an adjustment display. The image information generating means 10, the adjusted display image information displaying means M20, the image information acquiring means M22, and the display image information generating means M29 are provided.

  For at least one of the plurality of images, the image information acquisition unit M22 acquires overall image information that is image information for displaying the entire image. About others, it is the same as that of the image information acquisition means M12 in Example 1. FIG.

  If the image not selected in the image selection information corresponds to the entire image information, the display image information generating unit M29 does not generate display image information based on the entire image information.

  The display image information holding means M11, the image holding control means M13, the image selection information acquiring means M14, the image display means M15, the power supply state determining means M16, the request information output means M17, the initialization means M18, and the adjusted display image information generating means. 10 and the adjustment display image information display means M20 are the same as those in the first embodiment.

  As a result, when the entire image information is not selected as an image to be displayed, it is not necessary to perform a display image information generation process and a display image information holding unit holding process, thereby reducing power consumption. .

2. Hardware Configuration The hardware configuration of the multi-input multi-monitor system in this embodiment is the same as that of the first embodiment (see FIG. 4). Further, the hardware configuration of the monitor 25 according to the present embodiment constituting the multi-input multi-monitor is the same as that of the first embodiment (see FIG. 5). However, the operations of the packet analysis circuit 507c, the frame memory control circuit 513, and the microcomputer 535 in the DPVL analysis circuit 507 are different from those in the first embodiment.

  When the raster image data acquired by the input port 501 is acquired via the DPVL analysis circuit 507, the frame memory control circuit 513 performs monitor image data generation processing based on the raster image data. Other operations relating to the frame memory control circuit 513 are the same as those in the first embodiment.

  Hereinafter, operations of the packet analysis circuit 507c and the microcomputer 535 different from those in the first embodiment will be described.

3. Packet analysis circuit 507c
When the packet analysis circuit 507c of the DPVL analysis circuit 507 acquires data related to an image from the host computers 3 and 4 via the DVI cables 7a and 7b, whether the acquired data is a DPVL packet or is related to raster image data. It is judged whether it is. The operation of the packet analysis circuit 507c will be described based on the flowchart shown in FIG.

  When the packet analysis circuit 507c acquires the vertical synchronization signal (S2501), the width of the vertical synchronization signal is less than twice the period from the horizontal synchronization signal to the horizontal synchronization signal (horizontal synchronization period), that is, less than the period of two-line scanning. It is determined whether or not there is (S2503). Further, the packet analysis circuit 507c determines whether or not the back porch following the vertical synchronization signal is not more than 5 times the horizontal synchronization period (S2505). Further, the packet analysis circuit 507c determines whether or not a frame in which the width of the vertical synchronization signal is 2 times or less of the horizontal synchronization period and the back porch following the vertical synchronization signal is 5 times or less of the horizontal synchronization period continues for 30 frames or more. It is determined whether or not (S2507).

  In the packet analysis circuit 507c, the width of the vertical synchronization signal is 2 times or less of the horizontal synchronization period, and the back porch following the vertical synchronization signal is 5 times or less of the horizontal synchronization period. Such a frame continues for 30 frames or more. If it is determined that the DPVL packet has been acquired, it is determined that the DPVL packet has been acquired (S2509). Then, the packet analysis circuit 507c outputs to the microcomputer 535 the acquisition information configured by acquiring the port identification number indicating the port number of the corresponding input port 501 and the DPVL packet (S2511).

  On the other hand, the packet analysis circuit 507c determines that the width of the vertical synchronization signal is greater than twice the horizontal synchronization period, or the back porch following the vertical synchronization signal is greater than five times the horizontal synchronization period, or the width of the vertical synchronization signal. Is determined to have acquired raster image data when it is determined that the back porch following the vertical synchronization signal does not continue for 30 frames or more, which is less than twice the horizontal synchronization period and less than 5 times the horizontal synchronization period ( S2513). Then, the packet analysis circuit 507c outputs to the microcomputer 535 acquisition information indicating the port number indicating the number of the corresponding input port 501 (see FIG. 5) and the fact that the raster image data has been acquired (S2511).

  When the packet analysis circuit 507c (see FIG. 6) determines that the raster image data has been acquired, the header analysis circuit 507d, the address calculation circuit 507f, and the packet reconstruction circuit 507g in the monitor image data generation process for the DPVL packet. The data relating to the acquired raster image data is output to the frame memory control circuit 513 as it is, and is output from the corresponding output port 502 (see FIG. 5) to the subsequent monitor.

4. Microcomputer 535
The operation of the microcomputer 535 will be described based on the flowchart shown in FIG. When acquiring the acquired information (S2601), the microcomputer 535 extracts the port identification number and the type of acquired image data (S2603). Then, the microcomputer 535 acquires a frame / memory control correspondence table recorded in the memory (S2605).

  An example of the frame / memory control correspondence table is shown in FIG. The frame memory control correspondence table is a table for controlling the operation of the frame memory control circuit 513 according to the type of image data acquired from each input port 501 (see FIG. 5) and the state of switching of images.

  For example, when the DPVL packet is acquired from the A channel, the raster image data is acquired from the B channel, and the B channel is currently selected, the monitor 35 indicates that the image data on the non-display side relates to DPVL. The data is held in the frame memory 515a. Therefore, as shown in the column 2 of the frame / memory control correspondence table in FIG. 25, the DPVL packet on the non-display side is subjected to the update processing of the frame memory 515a, while the raster image data on the display side is processed. Performs the process of holding and updating the acquired raster image data in the frame memory 515b and reading the monitor image data from the frame memory 515b in order to display it on the monitor screen R5. The same applies to other cases.

  Referring back to FIG. 24, the microcomputer 535 transmits frame memory control information for controlling the frame memory control circuit 513 based on the frame memory control correspondence table (S2607). As described above, when raster image data is acquired, unnecessary processing can be reduced by controlling to stop access to the frame memory, and the entire monitor can save power. Can do.

1. Functional Block Diagram FIG. 26 shows a functional block diagram of the image display device M3 in this embodiment. The image display device M3 includes a display image information holding unit M11, an image selection information acquisition unit M14, an image display unit M15, a power supply state determination unit M16, a request information output unit M17, an initialization unit M18, an adjusted display image information generation unit 10, It has adjustment display image information display means M20, image information acquisition means M22, display image information generation means M29, image retention control means M33, and display image information integration means M39.

  The image holding control means M33 displays the display image information generated by the display image information integration means M39 for each type of image even if the image not selected in the image selection information corresponds to the partial image information. The image information is held in the image information holding means. If it is determined that the display image information holding unit M11 has not been processed, the display image information is held in the display image information holding unit M11. Other processes of the image holding control unit M33 are the same as those of the image holding unit M13 in the second embodiment.

  The display image information integration unit M39 acquires a plurality of display image information based on the partial image information, and generates one display image information that integrates the acquired plurality of display image information.

  The display image information holding means M11, the image selection information obtaining means M14, the image display means M15, the power state determination means M16, the request information output means M17, the initialization means M18, the adjustment display image information generation means 10, the adjustment display image information. The display unit M20, the image information acquisition unit M22, and the display image information generation unit M29 are the same as those in the second embodiment.

  Accordingly, the timing for holding the display image information in the display image information holding unit can be freely determined, so that an efficient image information holding process can be performed. Further, since the display image information is held in the display image information holding unit when the process for the display image information holding unit M11 is not performed, an efficient image information holding process can be performed.

2. Hardware Configuration The hardware configuration of the multi-input multi-monitor system in this embodiment is the same as that of the first embodiment (see FIG. 4). Further, the hardware configuration of the monitor 25 according to the present embodiment constituting the multi-input multi-monitor is the same as that of the second embodiment (see FIG. 5). However, the hardware configuration of the frame memory control circuit 513 is different.

  An example of the hardware configuration of the frame memory control circuit 513 is shown in FIG. The frame memory control circuit 513 includes an integration circuit 513a, a raster image data processing circuit 513b, a reading circuit 513c, an integration buffer 513d, a raster buffer 513e, a reading buffer 513f, and an arbitration circuit 513g.

  The integration circuit 513a acquires the plurality of monitor image data generated by the DPVL analysis circuit 507 (see FIG. 5) based on the acquired DPVL packet, and generates one monitor image data by integrating the acquired plurality of monitor image data. . The integration circuit 513a is connected to the integration buffer 513d. The operation of the integrated circuit 513a will be described later.

  The raster image data processing circuit 513b generates monitor image data based on the raster image data. The raster image data processing circuit 513b is connected to a raster buffer 513e. The operation of the raster image data processing circuit 513b is the same as the raster image data generation processing of the frame memory control circuit 513 in the second embodiment.

  The reading circuit 513c performs processing for reading monitor image data to be output to the LCD 523. The reading circuit 513c is connected to the reading buffer 513f.

  When the arbitration circuit 513g determines that the processing for the frame memory 515 is not performed, the arbitration circuit 513g holds the monitor image data in the frame memory 515. The operation of the arbitration circuit 513g will be described later.

3. Integrated circuit 513a
When determining that the image data of the acquired DPVL packet is newly acquired, the integrated circuit 513a determines whether the image data of the previous acquired DPVL packet remains in the data buffer 513d. If the integrated circuit 513a determines that no image data remains in the data buffer 513d, the integrated circuit 513a performs a process of writing the acquired image data of the acquired DPVL packet into the frame memory 515a or the frame memory 515b.

  On the other hand, when the integration circuit 513a determines that the previous image data remains in the data buffer 513d, the integration circuit 513a performs an integration process of the monitor image data. The monitor image data management process of the integrated circuit 513a will be described with reference to the flowchart shown in FIG. Here, an area updated by the image data of the acquired DPVL packet acquired this time is a late arrival update area, and an area updated by the image data of the acquired DPVL packet acquired previously is an early arrival update area.

  The integrated circuit 513a determines whether the upper left end point of the late arrival update area is included in the early arrival update area (S2701). The integrated circuit 513a determines this determination based on the overlapping area condition table. An example of the overlapping area condition table is shown in FIG.

  The overlapping area condition table is a table for determining the positional relationship between each end point of the late arrival update area and the first arrival update area. Condition (1) in the overlapping area condition table is a condition for determining whether or not the upper left end point of the late arrival update area is included in the early arrival update area.

  Here, the coordinate value (X coordinate, Y coordinate) of the upper left end point of the first arrival update area = (XORG1, YORG1), the size of the first arrival update area (the size in the horizontal direction, the size in the vertical direction) = (HSIZE1, VSIZE1). Also, the coordinate value (X coordinate, Y coordinate) of the upper left end point of the late arrival update area = (XORG2, YORG2), the size of the first arrival update area (the horizontal size, the vertical size) = (HSIZE2, VSIZE2). The integrated circuit 513a calculates and generates these values from a physical address that indicates a writing destination of an image to be written to the frame memory. Note that these values may be transferred from the DPVL analysis circuit 507 to the integrated circuit 513a.

  In order for the upper left end point of the late arrival update area to exist in the first arrival update area, the upper left end point (XORG2) of the late arrival update area is the upper left end point (XORG1) of the first arrival update area with respect to the X coordinate. It must exist between the end points (XORG1 + XSIZE1). Further, regarding the Y coordinate, the upper left end point (YORG2) of the late arrival update area needs to exist between the upper left end point (YORG1) and the lower left end point (YORG1 + VSIZE1) of the first arrival update area. A condition (1) in the overlapping area condition table represents such a condition. Similarly, in condition (2), the upper right end point of the late arrival update area is in the first arrival update area, and in condition (3), the lower left end point of the late arrival update area is in the first arrival update area. Condition (4) shows the condition because the lower right end point of the late arrival update area exists in the early arrival update area.

  Returning to FIG. 28, when the integrated circuit 513a determines that the upper left end point of the late arrival update area is present in the early arrival update area, the integration circuit 513a identifies areas that do not overlap each other (hereinafter referred to as non-overlapping areas) ( S2703). The integrated circuit 513a specifies a non-overlapping area using the non-overlapping area specifying table. An example of the non-overlapping area specification table is shown in FIG.

  The non-overlapping area specifying table is a table for specifying non-overlapping areas from the positional relationship between the first arrival update area and the later arrival update area. Each condition in the non-overlapping area specification table is a condition applied when it is determined that the corresponding condition in the overlapping area condition table matches. That is, the condition (1) in the non-overlapping area specifying table is a condition applied after it is determined that the condition (1) in the overlapping area specifying table is met, that is, the upper left end point of the late arrival update area is the first update. This is a condition that is applied after it is determined that the area exists.

  FIG. 31 shows a typical positional relationship between the first arrival update area and the later arrival update area in the condition (1) of the non-overlapping area specifying table, and the condition (1) of the non-overlapping area specifying table will be described using this positional relation. To do. The integrated circuit 513a specifies a region F1 'existing above the upper left end point of the late arrival update region F2 in the first arrival update region F1. From FIG. 30, the area F1 'has the coordinates of the upper left end point (X coordinate, Y coordinate) = (XORG1, YORG1) and size (horizontal direction, vertical direction) = (HSIZE1, YORG2-YORG1). Since this area F1 'exists above the late arrival update area F2, it corresponds to a non-overlapping area.

  Further, among the areas obtained by removing the area F1 'from the first arrival update area F1, the area F1 "existing on the left side of the later arrival update area F2 is specified. From FIG. 30, the region F1 ″ has the coordinates of the upper left end point (X coordinate, Y coordinate) = (XORG1, YORG2), size (horizontal direction, vertical direction) = (XORG2-XORG1, VSIZE1- (YORG2-YORG1). )). Since this area F1 ″ exists on the left side of the late arrival update area F2, it corresponds to a non-overlapping area.

  The remaining area F1 '' 'of the first arrival update area is an area including an area overlapping with the second arrival update area F2. In FIG. 31, the area F1 ′ ″ is an area overlapping the late arrival update area F2, but the upper right (lower right) end point of the early arrival update area F1 exists on the right side of the early arrival update area F1. The region F1 ′ ″ includes a non-overlapping region.

  FIG. 32 shows a typical positional relationship between the first arrival update area F1 and the second arrival update area F2 and the positions of the areas F1 ′ and F1 ″ in the conditions (1) to (4) of the non-overlapping area specification table.

  Returning to FIG. 28, the integrated circuit 513a identifies the non-overlapping area, and then sets the area F1 "" (see FIG. 31) including the overlapping area as the first update area (S2705).

  The integrated circuit 513a determines whether or not the upper right end point of the late arrival update area exists in the newly set first arrival update area using the overlapping area condition table (S2707). Then, the integrated circuit 513a performs non-overlapping area specifying processing (S2709) and first-arrival updating area setting processing (S2711).

  The integrated circuit 513a performs the same processing on the lower left end point (S2713 to S2717) and the lower right end point (S2719 to S2721) of the late arrival update area.

  The integrated circuit 513a updates the data in the frame memory 515a or the frame memory 515b using the image data corresponding to the late arrival update area and the specified non-overlapping area using the image data corresponding to the early arrival update area.

4. Arbitration circuit 513g
The arbitration circuit 513g adjusts the timing at which the integration circuit 513a, the raster image data processing circuit 513b, and the reading circuit 513c access the frame memories 515a and 515b.

  The arbitration circuit 513g adjusts access from each circuit according to the following rules. Access that records image data related to the image currently displayed on the LCD 523 in the frame memories 515a and 515b is processed with the highest priority. Next, the access from the reading circuit 513c is processed. Finally, the access from the integrated circuit 513a is processed.

  In order to implement such a rule, it is necessary for the arbitration circuit 513g to determine whether the image currently displayed on the LCD 523 is based on the acquired DPVL packet or the raster image. In this embodiment, the integration buffer 513d and the raster buffer 513e switch the operation mode when the switching information is acquired. For example, it is assumed that the integration buffer 513d has acquired switching information indicating that the displayed image data is related to the acquired DPVL packet. In this case, the integration buffer 513d adds priority information indicating that the image data is displayed when the image data acquired from the integration circuit 513a is output to the arbitration circuit 513g. When the arbitration circuit 513g acquires the image data from the integration buffer 513d, the arbitration circuit 513g checks the content of the priority information and processes the image data with the highest priority.

  In the above-described case, the image data from the integration buffer 513d corresponds to the access from the integration circuit 513a, but priority is given to the image data currently displayed, and as a result, the integration buffer 513d. Is processed with the highest priority.

  Even when the raster buffer 513e acquires the switching information indicating that the raster image data is displayed, the raster buffer 513e performs the same processing.

  Access processing performed by the arbitration circuit 513g to the frame memories 515a and 515b, an integration circuit 513a (integration buffer 513d), a raster image data processing circuit 513b (raster buffer 513e), and a reading circuit 513c (reading buffer 513f) FIG. 33 shows the correlation with the access occurrence status. In FIG. 33, it is assumed that raster image data is currently displayed and image data related to the acquired DPVL packet is not displayed. If there is an access (1) from the currently displayed raster buffer 513e (display side), it is processed with the highest priority. Even if there is an access from the reading buffer 513f (reading side) during the processing for the display side, the processing for the reading side is not started immediately, but the processing on the display side ends. Then, the processing on the reading side is started. If there is an access (3) from the integration buffer 513d (non-display side) immediately after the access on the reading side, the processing on the non-display side is started after the processing on the reading side is completed.

  In this way, by giving priority to the processing for access from each circuit, the arbitration circuit 513g eventually displays the image data on the non-display side when processing for the frame memory 515 is not performed. It can be recorded in the frame memory 515a, 515b. That is, the monitor image data is held in the frame memories 515a and 515b when the processing for the frame memories 515a and 515b is not performed, so that an efficient monitor image data holding process can be performed.

1. Functional Block Diagram FIG. 34 shows a functional block diagram of the image display device M4 in the present embodiment. The image display device M1 includes a display image information holding unit M11, an image information acquiring unit M12, a display image information generating unit M19, an image holding control unit M13, an image display unit M15, a power supply state determining unit M16, and an adjusted display image information generating unit 10. Adjustment display image information display means M20, image selection information acquisition means M44, request information output means M47, and initialization means M48.

  The image selection information acquisition unit M44 outputs selection acquisition information indicating that the image selection information has been acquired.

  When the request information output means M47 acquires selection acquisition information indicating that the image selection information has been acquired from the image selection information acquisition means M44, the request information output means M47 outputs request information for requesting provision of image information necessary for generating display image information. To do. Others are the same as the request information output means M17 in the first embodiment.

  When acquiring the selection acquisition information indicating that the image selection information has been acquired from the image selection information acquisition unit M44, the initialization unit M48 initializes the display image information holding unit M11. About others, it is the same as that of the initialization means M18 in Example 1.

  The display image information holding means M11, the image information acquiring means M12, the display image information generating means M19, the image holding control means M13, the image display means M15, the power supply state determining means M16, the adjusted display image information generating means 10 and the adjusted display image. The information display means M20 is the same as that in the first embodiment.

  As a result, even when the type of image to be displayed is switched, it is possible to reliably display an image without causing image loss regardless of the type of image. Further, at the time of image switching, it is possible to clearly determine a portion corresponding to the acquired image information and a portion in which an image defect has occurred because the image information has not yet been acquired.

2. Hardware Configuration The hardware configuration of the multi-input multi-monitor system in this embodiment is the same as that in the first embodiment. The hardware configuration of the monitor 35 according to the present embodiment constituting the multi-input multi-monitor is substantially the same as that of the first embodiment as shown in FIG.

  However, the monitor 35 has only one frame memory 515 '. The frame memory 515 'can hold monitor image data for at least one frame of an image displayed on the entire monitor screen R5, similarly to the frame memories 515a and 515b in the first embodiment.

  Further, the operation of the microcomputer 535 is different from that of the first embodiment. Hereinafter, the operation of the microcomputer 535 will be described.

3. Microcomputer 535
The operation of the microcomputer 535 will be described based on the flowchart shown in FIG. When the microcomputer 535 acquires the switching information from the switching circuit 531 (S2901), the microcomputer 535 is different from the host computer that is currently transmitting the image data displayed on the LCD 523, that is, is not currently displayed on the LCD 523. Full-screen request information is transmitted via the USB port 505 to the host computer that is transmitting the image data (S2903). Further, the microcomputer 535 controls the frame memory control circuit 513 to stop reading image data from the frame memory 515 ′ (S2905). Further, the microcomputer 535 controls the dummy image generation circuit 537 to generate a dummy image and output it to the LCD 523 (S2907).

The subsequent operation of the microcomputer 535 is the same as the operation of steps S2117 to S2121 (see FIG. 20) in the first embodiment. The operation of the frame memory control circuit 513 is the same as the operation of steps S2225 to S2235 (see FIG. 21b) in the first embodiment.

[Other Examples]
In the first to fourth embodiments described above, a multi-monitor environment in which each monitor 5a, 5b, 5c, etc. has a multi-input input port 501 and a plurality of monitors are cascade-connected is illustrated as a multi-input monitor system. However, a multi-input monitor system may be constructed with only one monitor without constructing a multi-monitor environment.

  In the first embodiment, the monitor 5 has the two frame memories 515a and 515b, and the monitor image data corresponding to the input port 501 is held in each frame memory. However, the present invention is not limited to this as long as the monitor image data corresponding to the input port 501 can be held. For example, the inside of one frame memory may be divided into a plurality of areas, and the input port 501 may be associated with the divided areas. Thus, the generated monitor image data can be held for each type of image in each of the divided frame memories.

  In the first embodiment described above, the monitor 5 holds monitor image data in each frame memory for each type of image of the acquired DPVL packet, and transmits monitor image data for the entire screen when the power is turned on. Is required. However, it may be a monitor that realizes one of the functions. Further, in the first embodiment, when the power is turned on, the monitor 5 requests initialization of the frame memory, generation of dummy images, and transmission of monitor image data relating to the entire screen. It is good also as a monitor which implement | achieves a function.

  Further, in the first embodiment described above, the adjustment display image information to be displayed in the image display area before the display image information corresponding to the request information is displayed in the image display area of the image display device. Although the dummy image generation circuit 537 is exemplified as the adjustment display image information generation means to be generated, the invention is not limited to this as long as the adjustment image information is generated. For example, a predetermined image may be stored in advance in a storage unit such as a memory, and the image may be used as adjusted display image information. In this case, the adjustment display image information is generated by reading the image from the storage unit.

  In the above-described second embodiment, the monitor 25 determines whether or not the acquired data is held in each frame memory for each type of the acquired DPVL packet and raster image data, and the power is turned on. In this case, transmission of monitor image data relating to the entire screen is requested. However, it may be a monitor that realizes one of the functions.

  In the third embodiment, the frame memory control circuit 513 has the integrated circuit 513a and the arbitration circuit 513g, but may have either one.

  In the above-described fourth embodiment, the monitor 35 holds monitor image data in each frame memory for each type of image of the acquired DPVL packet, and when the power is turned on or the image is switched, the entire screen is displayed. The monitor image data is requested to be transmitted. However, it may be a monitor that realizes one of the functions.

  In the first to fourth embodiments, the DPVL packet is exemplified as the partial image information which is image information for displaying a part of the image. However, the present invention is not limited to this as long as the part of the image is displayed. . For example, partial image information may be configured by packetizing a part of an image according to a standard other than DPVL.

  Further, in the first to fourth embodiments, the host computers 3a and 3b and the monitors 5, 25 and 35 and the monitors 5a, 5b and 5c are connected by DVI cables 7a and 7b. Raster image data transmission / reception is performed. However, the present invention is not limited to this as long as DPVL packet / raster image data can be transmitted and received. For example, the host computers 3a, 3b and the monitors 5, 25, 35 may be connected by radio. Further, the host computers 3a, 3b and the monitors 5, 25, 35 are connected by wire in the same manner as the DVI cable 7a, but a transmission path other than the DVI standard may be used. The same applies to the monitors 5a, 5b and 5c.

  A function for holding monitor image data in each frame memory for each image type of the acquired DPVL packet realized by the first to fourth embodiments, and a function for requesting transmission of monitor image data for the entire screen when the power is turned on. A function for determining whether or not the acquired data is held in each frame memory for each type of acquired DPVL packet and raster image data. When there is an image change, monitor image data relating to the entire screen is transmitted. A monitor that combines a function to request, a function to integrate acquired DPVL packets, and a function to adjust timing of recording in a frame memory may be used. For example, the monitor may have a function of holding monitor image data in each frame memory for each type of image of the acquired DPVL packet and a function of requesting transmission of monitor image data for the entire screen when the image is switched.

  Furthermore, in the combination described above, the combined function may be selected and made effective. For example, a monitor having a function of holding monitor image data in each frame memory for each type of image of the acquired DPVL packet and a function of requesting transmission of monitor image data for the entire screen when there is an image change In order to realize a function of requesting transmission of monitor image data for the entire screen when the image is switched, it is necessary to be connected to the host computers 3a and 3b (see FIG. 4) by the USB 9a and 9b as control lines. However, if the USB 9a and 9b are not connected, only the function of holding the monitor image data in each frame memory for each image type of the acquired DPVL packet is valid. The function for requesting transmission of monitor image data relating to the screen may be invalidated. Further, when connected by the USB 9a, 9b, only the function for requesting transmission of monitor image data regarding the entire screen may be made valid when the image is switched. Further, such validity / invalidity determination may be automatically detected.

  Furthermore, it is automatically determined whether or not the host computers 3a and 3b connected by the USBs 9a and 9b support the monitor image data transmission request function related to the full screen based on the full screen request information. If the image is switched, a function for requesting transmission of monitor image data for the entire screen may be made effective.

  The HID table is a partial position information holding unit, the input port 507a is an image display information acquisition unit, the packet analysis circuit 507c and the header analysis circuit 507d are positional relationship determination units, and the packet reconstruction circuit 507g is an output image information generation unit. The packet reconstruction circuit 507g corresponds to output image position information generation means and image display information generation means, respectively.

  The output image information generation means performs the processes of S1701 to S1707 and S1711 to S1713, the output image position information generation means performs the processes of S1709 and S1715, and the image display information generation means performs the processes of S1709, S1715 and S1719.

  The image display information acquisition means performs the processing of S3501, the positional relationship determination means performs the processes of S3503 and S3505, the output image information generation means performs the processing of S3507, the output image position information generation means performs the processing of S3509, and the image display. The information generation unit executes the process of S3511.

The virtual screen R1 is the entire image display area, the monitor screen R5 is the partial image display area, the packet display area R7 is the image display area, and the image display area where the image data of the newly generated DPVL packet is displayed is the output image display area Respectively. The DPVL packet corresponds to the image display information, and the acquired DPVL packet corresponds to the acquired image display information. Further, the image data of the DPVL packet corresponds to the image information, and the image data of the newly generated DPVL packet corresponds to the output image information. Furthermore, the monitor screen position information stored and held in the HID table corresponds to the partial position information, the header portion H1 of the DPVL packet corresponds to the image position information, and the header portion H1 of the newly generated DPVL packet corresponds to the output image position information. To do.

It is a figure for demonstrating the relationship of virtual screen R1, monitor screen R5, packet display area | region R7, and update image area | region R9 in a multi-input multi-monitor system. It is the figure which showed the data structure of the DPVL packet. 2 is a functional block diagram of Embodiment 1. FIG. 2 is a diagram illustrating a hardware configuration of a multi-input monitor system 1. FIG. 2 is a diagram illustrating a hardware configuration of a monitor 5. FIG. 5 is a diagram illustrating an example of a logic circuit of a DPVL analysis circuit 507. FIG. It is a figure for demonstrating the positional relationship with respect to the end point T1 of the packet display area | region R7, and the monitor screen R5. It is a figure for demonstrating the positional relationship with respect to the end point T1 of the packet display area | region R7, and the monitor screen R5. It is a figure for demonstrating the positional relationship with respect to the end point T4 and monitor screen R5 of packet display area R7. It is a figure for demonstrating the positional relationship with respect to the end point T4 and monitor screen R5 of packet display area R7. It is the figure which showed an example of the actual logic circuit which comprises the header analysis circuit 507d. It is the figure which showed an example of the actual logic circuit which comprises the header analysis circuit 507d. It is the figure which showed the example of a position of a position specific table. FIG. 6 is a diagram showing a logical address space R515 in the frame memory 515. It is a figure showing an example of an actual logic circuit which constitutes address calculation circuit 507f, and A is an example of a logic circuit at the time of judging whether update image field R9 exists in monitor screen R5. Shows an example of a logic circuit for converting a logical address into a physical address. It is the flowchart which showed the operation | movement of the packet reconstruction circuit 507g. It is a figure which shows an example of a conditional expression. It is a figure which shows an example of a conversion type | formula. It is the figure which illustrated concretely the positional relationship of monitor screen R5 and packet display field R7 of an acquisition DPVL packet. 5 is a flowchart showing the operation of a microcomputer 535. 5 is a flowchart showing the operation of a frame memory control circuit 513. 5 is a flowchart showing the operation of a frame memory control circuit 513. 6 is a functional block diagram of Embodiment 2. FIG. It is the flowchart which showed operation | movement of the packet analysis circuit 507c. 5 is a flowchart showing the operation of a microcomputer 535. It is a figure showing an example of a frame memory control correspondence table. 10 is a functional block diagram of Embodiment 3. FIG. 3 is a diagram illustrating an example of a hardware configuration of a frame memory control circuit 513. FIG. It is a flowchart which shows the control process of the monitor image data of the integrated circuit 513a. It is the figure which showed an example of the duplication area | region condition table. It is the figure which showed an example of the non-overlapping area | region identification table. It is the figure which showed the positional relationship of the typical first arrival update area of the condition (1) of a non-overlapping area | region identification table, and the last arrival update area. It is the figure which showed the positional relationship of the typical first arrival update area | region F1 and the last arrival update area | region F2, and the position of area | region F1 ', F1' 'in each condition of a non-overlapping area | region identification table. It is the figure which showed the correlation with the access process with respect to the frame memory 515a, 515b of the arbitration circuit 513g, and the access generation condition of the integrated circuit 513a. 10 is a functional block diagram of Embodiment 4. FIG. 2 is a diagram illustrating a hardware configuration of a monitor 35. FIG. 5 is a flowchart showing the operation of a microcomputer 535. It is a figure for demonstrating a prior art. It is a figure for demonstrating a prior art. It is a figure for demonstrating a prior art.

Explanation of symbols

5: Monitor 507: DPVL analysis circuit 507c: Packet analysis circuit 507d: Header analysis circuit 507e: Cache 507f: Address operation circuit

Claims (8)

An image display device that displays image information in an image display area, and an image display device capable of acquiring a plurality of types of image information ,
Image information acquisition means for acquiring partial image information which is image information for displaying a part of an image as the image information;
Image selection information acquisition means for acquiring image selection information for selecting an image to be displayed in the image display area from the plurality of types of image information;
Display image information generating means for generating display image information for displaying a selected type of image in the image display area based on the image selection information;
Image holding control means for holding the display image information which the display image information generation means to generate Viewing the image information holding means,
Image display means for displaying display image information held in the image holding control means in the image display area;
In an image display device comprising:
The display image information generation means generates display image information as non-selected image information for an image of a type not selected as an image to be displayed in the image selection information,
The image holding control means holds the non-selected image information in the display image information holding means;
An image display device characterized by the above. The image display device according to claim 1 , further comprising:
Display image information integration means for acquiring the non-selected image information and generating one display image information by integrating the acquired plurality of display image information;
Have
The image holding control means further includes
Holding the display image information generated by the display image information integration unit in the display image information holding unit;
An image display device characterized by the above. Either of the image display devices according to claim 1 and claim 2 ,
The image information acquisition means further includes:
As the image information, the whole image information which is image information for displaying the whole image is also acquired,
The image holding control means further includes
If the image not selected in the image selection information corresponds to the whole image information, the display image information holding means based on the whole image information is not held in the display image information holding means;
An image display device characterized by the above. In any one of the image display apparatuses which concern on Claims 1-3 ,
The image display device further includes:
Power state determination means for determining whether or not the power of the image display device is turned on;
Power-on request information for outputting power-on request information for requesting provision of image information necessary for generating the display image information upon obtaining a determination that the power is turned on from the power state determination unit Output means,
An image display apparatus. In an image display program for acquiring a plurality of types of image information and displaying the acquired image information in an image display area,
The image display program is stored in a computer.
As the image information, an image information acquisition step of acquiring partial image information that is image information for displaying a part of the image ;
An image selection information acquisition step for acquiring image selection information for selecting an image to be displayed in the image display area from the plurality of types of image information;
A display image information generation step for generating display image information for displaying a selected type of image in the image display area based on the image selection information;
Display image information holding step of holding the generated display image information Viewing the image information holding means,
Displaying the display image information held in the image holding control means in the image display area;
A program for executing
In the display image information generation step, display image information is generated as non-selected image information for the types of images that are not selected as images to be displayed in the image selection information,
In the display image information holding step, the non-selected image information is also held in the display image information holding unit;
An image display program characterized by the above . In the image display program according to claim 5 ,
The computer
In the image information acquisition step, further, as the image information, acquiring overall image information that is image information for displaying the entire image,
Holding in the display image information generation step, the not selected in the image selection information image, in the case corresponding to the entire image information, the display image information based on the entire image information to the display image information holding means Do not let,
An image display program characterized by the above . In an image display method for acquiring a plurality of types of image information using a computer and displaying the acquired image information in an image display area,
Computer
As the image information, an image information acquisition step of acquiring partial image information that is image information for displaying a part of the image ;
An image selection information acquisition step for acquiring image selection information for selecting an image to be displayed in the image display area from the plurality of types of image information;
A display image information generating step for generating display image information for displaying the selected type of image information in the image display area based on the image selection information;
Display image information holding step of holding the generated display image information Viewing the image information holding means,
Displaying the display image information held in the image holding control means in the image display area;
An image display method of the execution,
The computer
In the display image information generation step, display image information is generated as non-selected image information for the types of images that are not selected as images to be displayed in the image selection information,
In the display image information holding step, the non-selected image information is also held in the display image information holding unit;
An image display method characterized by the above. The image display method according to claim 7 , further comprising:
Computer
In the image information acquisition step, further, as the image information, acquiring overall image information that is image information for displaying the entire image,
Holding in the display image information generation step, the not selected in the image selection information image, in the case corresponding to the entire image information, the display image information based on the entire image information to the display image information holding means Do not let,
An image display method characterized by the above.

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