JP4276911B2 - Arrangement method and arrangement program for circuit elements of integrated circuit - Google Patents

Description

  The present invention relates to the design of an integrated circuit that implements parallel processing, and more particularly to the placement of circuit elements of the integrated circuit and the connection between circuit elements.

  Several languages are used to design integrated circuits such as LSIs and ASICs. What is called a high-level language with a high degree of abstraction such as C language is a procedural level language, and is suitable for showing how the entire processing is executed in order for each instruction. This level of description is generally an application program that has no hardware dependency and is accepted by an appropriate computer, and is used to generally describe the specifications of the LSI or the entire process executed in the LSI.

  Also, hardware description language (HDL) such as Verilog-HDL or VHDL is sometimes referred to as RTL, and it is a register-transistor level, and a data path or path in which a specific instruction is executed by specific hardware. Used to describe the driving sequence.

  An algorithm is defined as a set of a finite number of rules that are clearly defined and ordered to solve a problem. Conventionally, parallel processing is a process that sequentially advances the entire processing (application) described by the algorithm. Thus, the independently executable portions (processes) are executed in parallel to reduce the processing time. When an application is executed in advance by a system provided with hardware resources suitable for parallel processing, a part that can be processed in parallel by a compiler or the like is parallelized to try to improve the execution speed.

Also, when designing hardware for the purpose of executing a specific application, the circuit is designed so that parts that can be executed independently are processed in parallel to reduce the processing time. The technique described in Patent Document 1 is a method of designing a circuit by HDL that can describe a process whose execution time is not constant by parallel processing, synchronous communication, or the like. In synchronous communication, when two functions are executed in parallel, the reception side waits until the transmission side can prepare the processes included therein, and the process proceeds after the communication is completed. Therefore, even if these functions are described in parallel, they are not executed independently, and the execution time is variable. On the other hand, processing that does not perform synchronous communication is performed independently as parallel processing. These reduce the number of execution cycles by executing, in the hardware design, parallel processing in the hardware design or using synchronous communication in the entire processing given in the source language. It is a technology that aims to do.
JP-A-10-116302

  In recent years, hardware capable of reconfiguring a part of a circuit constituting an LSI by software has been provided. Furthermore, in International Publication No. WO 03/007155, the basic unit to be reconfigured is an arithmetic unit having an arithmetic function of a certain scale from gate level to ALU, and a plurality of types of arithmetic units are arranged in a matrix, It is disclosed to reduce the time required for reconfiguration. A system in which a plurality of arithmetic units are arranged in a matrix can be regarded as a system having a large number of hardware resources suitable for parallel processing because each arithmetic unit can execute processing in parallel. .

  However, it is not easy to design an integrated circuit suitable for this kind of parallel processing. A high-level language suitable for software design, such as C language, is premised on processing an algorithm in the order of time. Therefore, the program counter is advanced so that instructions are executed sequentially, and it is difficult to introduce the concept of non-sequential parallelism. Even if it is allowed to describe instructions in parallel, it is only possible to extend the processing that can be executed independently in parallel in a range that does not cause any hesitation in the temporal order. Hardware resources suitable for processing cannot be actively used. Furthermore, since a high-level language describes instructions that do not depend on hardware, the timing at which instructions written in parallel are actually started or ended in hardware is unknown. Therefore, even if the processing range is expanded spatially, the designer cannot define or grasp how parallel processing is actually executed on hardware.

  Since HDL describes a circuit configuration that operates independently, it essentially describes parallel processing. In addition, since the hardware becomes clear, the timing at which the process is executed can be checked or adjusted. However, HDL requires a sufficient knowledge of the integrated circuit and its circuit elements, and there is a problem that it is substantially impossible to grasp the circuit configuration by looking at the items described in HDL. The knowledge includes hardware design rules and the like.

  The present invention provides an arrangement method of circuit elements, which can design an integrated circuit, in particular, an integrated circuit disclosed in International Publication No. WO 03/007155, even if there is no expertise related to the integrated circuit and circuit elements. An object is to provide a placement program.

  An object of the present invention is to provide a visual symbol and a connection established between the visual symbols, which are arranged by selecting from a definition file in which visual symbols of circuit elements constituting an integrated circuit and DDDL are stored in association with each other. And assigning the circuit element to an actual circuit element that is pre-arranged on the integrated circuit and having a corresponding specific function, and according to the latency of the circuit element, between the assigned circuit elements A step of interposing a circuit element having a delay function arranged on the integrated circuit, and a DDDL describing the assigned or intervening circuit element in a memory as arrangement information of the circuit element of the integrated circuit And the step of storing the circuit element.

  In a preferred embodiment, the integrated circuit includes a step of interposing an actual circuit element having a delay function in the connection of the circuit element between segments including a certain group of circuit elements.

Further, in a preferred embodiment, when an actual circuit element having the delay function is interposed, at least one or more actual circuit elements having the delay function according to at least the maximum latency of the actual circuit element The step of assigning is provided.
Furthermore, in a preferred embodiment, when an actual circuit element having the delay function is interposed, the number of input ports and the number of output ports of the actual circuit element having the delay function is referred to as a single unit. And assigning to actual circuit elements.

  In another preferred embodiment, it is configured not to intervene an actual circuit element having a delay function between specific circuit elements selected by the user regardless of the latency.

  Further, a step of interposing an actual multiplexer for designating an input port of the circuit element may be provided between the circuit elements.

  An object of the present invention is set between a visual symbol selected from a definition file in which a visual symbol of a circuit element constituting an integrated circuit and a DDDL are stored in association with each other, and the visual symbol. And assigning the circuit element to an actual circuit element having a specific function corresponding to the pre-arranged circuit element on the integrated circuit, and the assigned circuit element according to the latency of the circuit element. Between the step of interposing a circuit element having a delay function arranged on the integrated circuit and the DDDL describing the assigned or intervening circuit element as arrangement information of the circuit element of the integrated circuit The step of storing in the memory is also achieved by a circuit element arrangement program characterized in that the computer executes the step. It is.

  According to the present invention, it is possible to provide a circuit element arrangement method and an arrangement program capable of designing an integrated circuit even when there is no specialized knowledge about the integrated circuit and circuit elements.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an outline of an arrangement system of circuit elements of an integrated circuit according to an embodiment of the present invention. As shown in FIG. 1, a hardware library 10 in which various circuit elements (elements) described in DDDL (Device Dependent Description Language) are stored, and read from the hardware library 10 according to an operation of a user input device. Display control unit 12 that displays the output circuit elements as visual symbols (referred to as a mapping configuration in the present embodiment), and hardware described in DDDL based on the mapping configuration arranged by the user A compiler 16 for generating the configuration 14 and a storage unit 18 that stores data described by the DDDL and generated by the compiler 16 and corresponding to an actual integrated circuit.

The display control unit 12 and the compiler 16 are realized by a computer, and when the necessary program is started, the computer functions as the display control unit and the compiler. The program is read from a storage medium such as a CD-ROM or downloaded via a network and stored in a storage device of a computer.
Prior to processing by the circuit element arrangement system according to this exemplary embodiment, a parallel processing system suitable for using this exemplary embodiment will be described. This parallel processing system corresponds to an integrated circuit in which each element simultaneously performs separate processing.

  FIG. 2 is a diagram illustrating an example of a parallel processing system that uses circuit elements of the hardware library 10. This parallel processing system is a reconfigurable processor (RP) disclosed in the applicant's international application publication WO 03/007155. The RP 20 is adapted to specific data processing by a general-purpose basic processor 21 that performs general-purpose processing including error processing based on an instruction set given by a program and the like, and operations or logic elements arranged in a matrix. An AAP (Adoptive Application Processor) unit or AAP unit (hereinafter referred to as “AAP”) 50 in which the data flow or pseudo data flow is formed in a variable manner, an interrupt control unit 22 that controls interrupt processing from the AAP 50, A clock generation unit 28 for supplying an operating clock signal to the AAP 50, an FPGA unit 27 for further improving the flexibility of an arithmetic circuit that can be provided by the RP 20, and a bus control for controlling input / output of data to / from the outside Part 29. The basic processor 21 and the AAP 50 are connected by a data bus 24a capable of exchanging data between them and an instruction bus 24b for controlling the configuration and operation of the AAP 50 from the basic processor 21. Further, when an interrupt signal is supplied from the AAP 50 to the interrupt control unit 22 via the signal line 25, the processing in the AAP 50 is completed, and when an error occurs during the processing, the state of the AAP 50 can be fed back to the basic processor 21. It has become.

  The AAP 50 and the FPGA 27 are also connected by the data bus 26, so that data can be supplied from the AAP 50 to the FPGA 27 for processing, and the result can be returned to the AAP 50. Further, the AAP 50 is connected to the bus control unit 29 by a load bus 23a and a store bus 23b, and can exchange data with a data bus outside the RP 20.

  An outline of the AAP unit 50 is shown in FIG. The AAP unit 50 supplies a logical block, a logical unit, or a logical unit or a logical element (hereinafter referred to as an element) that performs a plurality of arithmetic and / or logical operations in a matrix, and supplies data to the matrix unit 51. And an output buffer 53 for storing data output from the matrix section 51. Each of the input buffer 52 and the output buffer 53 is composed of four small-capacity input memories, and is connected to the input / output buses 23a and 23b via the access arbitration unit 54.

  The matrix unit 51 is an integrated circuit section that is the center of a parallel processing system that can reconfigure a data path or data flow, and elements 55 that are a plurality of types of arithmetic units form, for example, four lines in the vertical direction. Thus, they are arranged in an array or a matrix. The matrix section 51 includes a row wiring group 57 extending between the elements 55 and a column wiring group 58 extending in the vertical direction, which are disposed between the elements 55. The column wiring group 58 includes a pair of wiring groups 58x and 58y arranged separately on the left and right sides of the arithmetic units 55 arranged in the column direction. A switching unit 59 is disposed at the intersection of the row wiring group 57 and the column wiring group 58, and an arbitrary channel of the row wiring group 57 can be switched and connected to an arbitrary channel of the column wiring group 58. Yes. Each switching unit 59 includes a configuration RAM for storing settings, and rewrites the contents of the configuration RAM with data supplied from the processor unit 21 to connect the row wiring group 57 and the column wiring group 58. Can be arbitrarily controlled dynamically. For this reason, in this matrix portion 51, the configuration of the data flow formed by connecting all or a part of the plurality of elements 55 by the wiring groups 57 and 58 can be dynamically changed arbitrarily.

  In the RP 20, the element 55 is an element that operates in parallel, and information such as the function, delay, and input / output data conditions of each type of element 55 is stored in the hardware library 3. Since the element 55 operates in synchronization with the clock signal supplied from the clock generator 28, the number of cycles consumed for processing and outputting input data for each type of element in the hardware library 3 Is stored as delay information. Further, the arrangement of each type of element 55, information on the wiring groups 57 and 58, and the switching unit 59 are also stored in the hardware library 3. The compiler 2 implements an algorithm defined in DIDL1. The connection information (data flow configuration) of the element 55 is output as hardware configuration information (DDDL) 4. Therefore, by controlling the matrix unit 51 so that the element 55 is connected by the wiring groups 57 and 58 according to DDDL4, the algorithm defined in DIDL1 can be spatially allocated to the matrix unit 51 by the element 55. Become.

  Each element 55 outputs a set of selectors 54 for selecting input data from each of a set of column wiring groups 58x and 58y, and performs a specific arithmetic and / or logical operation process on the selected input data, and outputs it. An internal data path unit 56 that outputs data to the row wiring group 57 is provided. In the matrix unit 51 of this example, different types of elements 55 including an internal data path unit 56 for performing different processing for each row are arranged side by side. For example, the elements 55 arranged in the first row include a data path unit (LD) 56 i suitable for processing for receiving data from the input buffer 52. The element 55a arranged in the second row is an element for writing data from an external device to the input buffer 52, and has a data path unit having an internal data path suitable for generating an address for block loading. (BLA) 56a. All elements 55 constituting the matrix 51 can change the configuration or initial value of the internal data path to some extent, and the setting is set in the configuration RAM of each element 55 by the control signal 24b from the basic processor 21. Instructed.

  The element 55b arranged in the third row includes a data path unit (LDA) 56b that generates an input read address for loading desired data from each of the input RAMs to the matrix unit 51. The elements 55c arranged in the fourth row and the fifth row include a data path unit (SMA) 56c suitable for arithmetic operations and logical operations. The data path unit 56c includes, for example, a configuration RAM for setting operations to be processed by a shift circuit, a mask circuit, logical operation units ALU and ALU. Therefore, the data input to the matrix unit 51 can be added or subtracted, compared, or logical sum or logical product can be obtained by the instruction written by the processor 21, and the result is the output signal of the element 55. Is output as

  The elements 55d arranged in the lower row include a data path unit (DEL) 56d suitable for processing for delaying the timing at which data is transmitted. The elements 55e arranged in the lower row include a data path unit (MUL) 56e suitable for multiplication processing including a multiplier and the like. As another element 55f, an element having a data path unit 56f for interfacing with the FPGA 27 prepared outside the matrix unit 51 is also prepared. After the data is once supplied to the FPGA 27 and processed, the matrix is again processed. The processing can be continued by returning to the unit 51.

  Further below these reconfigurable integrated circuit sections 51 are arranged elements 55g and 55h respectively having data path portions 56g and 56h suitable for generating an address for storing. These perform control for outputting data to an external device via the output buffer 53. In the lowermost row, an element 55 having a data path unit (ST) 56s suitable for outputting data for storage is arranged. Therefore, by dynamically changing the connection of the elements 55 using the matrix unit 51, various data flows can be configured flexibly and various processes can be performed.

  Further, in the present embodiment, the APP 50 has a structure including a plurality of segments each including a group of elements. FIGS. 15-17 shows the part of AAP50 in RP concerning this Embodiment. FIGS. 15 to 17 show segments 1501 to 1701 having segment numbers “0”, “1”, and “2” in the AAP 50, respectively. In addition, instead of displaying “MUL”, “SMAM” is displayed for elements suitable for multiplication processing. Hereinafter, elements suitable for multiplication processing are referred to as “SMAM elements”. As shown in FIGS. 15 to 17, elements suitable for delaying the timing of data transmission (hereinafter referred to as “DEL elements”) are arranged between the segments, and the elements are connected across the segments. In this case, a DEL element is interposed. In addition to using DEL elements for connection between segments, certain design rules are provided for actually arranging circuit elements in the APP 50. Therefore, the compiler 16 executes various processes to be described later according to the design rules in the arrangement and connection of the circuit elements.

  The user operates the input device to read the mapping configuration visually representing the elements described in DDDL, and arranges the mapping configuration in the layout area in the screen of the display device. The hardware library 10 stores visual symbols (mapping configurations) of elements (corresponding to reference numerals 56a to 56i and 56s in FIG. 3) constituting the AAP 50 described above.

  FIG. 18 is a diagram showing a structure of a DDDL describing elements according to the present embodiment. As shown in FIG. 18A, in the DDDL, a PHID that uniquely identifies a type of a circuit element, a processor ID, a UID that identifies an actual position of the circuit element on the APP together with an arrangement position described later, It consists of an arrangement position of a circuit element having UID, connection information of the circuit element, and device parameters.

  FIG. 18B is a diagram illustrating an example of connection information. In the example of FIG. 18B, “UQID = 100” is included and the arrangement position is not specified (that is, (segment number, column number, row number) = (− 1, −1, −1). ) For the SMA element (element suitable for arithmetic and logical operations), input is not required for the input port # 0, but the output of the element “UQID = 102” is output to the second input port input port # 1. It shows getting input from port # 0. Thus, in DDDL, the connection between elements can be defined by prescribing the output port of an element having a UCID that is connected to each input port of the element. In the hardware library 10, each element is described by DDDL having the above-described structure, but the circuit arrangement position and the value of connection information are indefinite.

  When the user selects an element in the definition file and arranges the layout area, at least the element type and the connection between the elements may be defined. That is, a desired element may be arranged in the layout area, and the output port of one element may be connected to the input port of the other element. Of course, in the case of feedback, the output port of a single element may be connected to the input port. The connection between elements, that is, the output port of one element and the input port of the other element are connected by user input, so that the compiler 16 gives a necessary value to connection information in DDDL.

  FIG. 4A is a diagram illustrating connection of the simplest mapping configuration. In this example, an output port of an element suitable for processing for receiving data from the input buffer 52 (hereinafter also referred to as “LD element”) 401 and an element suitable for outputting data for storage (hereinafter “ Also referred to as an “ST element”.) 402 is connected to the input port. FIG. 4B is a diagram illustrating connection of another mapping configuration. In this example, in addition to the LD element and ST element, elements suitable for arithmetic and logical operations (hereinafter also referred to as “SMA elements”) and elements suitable for multiplication processing (hereinafter also referred to as “SMAM elements”). DEL elements suitable for processing for delaying the timing at which data is transmitted are used. For example, in the first path 410, the output port of the LD element 411 is connected to the input port of the DEL element 411, the output port of the DEL element 412 is connected to the input port of the SMAM element 413, and the output of the SMAM element 413 The port is connected to the input port of another DEL element 414, and the output port of the DEL element 414 is connected to one input port of the ST element 415. On the other hand, in the second path 420, the output port of the LD element 421 is connected to the input port of the SMA element 422, and the output port of the SMA element 422 is connected to the input port of the SMAM element 423. Are connected to the input port of the other SMA element 424, and the output port of the SMA element 424 is connected to the other input port of the ST element 415.

  The hardware library also includes the latency of each element. Therefore, the user may set the latency of the DEL element with reference to the latency of the element arranged by the user. In the example of FIG. 4B, since the user can know that the latency of the SMA element is “3”, the latency of the DEL elements 412 and 414 is considered in consideration of the synchronization between the path 410 and the path 420. Each can be set to “3”.

  When the arrangement of the elements and the connection between them according to the data flow based on the circuit specifications are completed, the user operates the input device to activate the compiler 16. The compiler 16 performs the following processing to arrange the positions where the elements are actually arranged in the AAP 50, routing of connections between the elements whose arrangement positions are determined in the AAP 50, and necessary elements. Insertion of a DEL element or the like is realized. FIG. 5 is a flowchart showing an outline of processing executed in the compiler 16.

  As shown in FIG. 5, the compiler 16 determines the arrangement position of each element in the AAP 50 based on the elements arranged in the layout area (step 500). In this embodiment, as shown in FIGS. 15 to 17, the AAP 50 is structurally configured such that the actual LD element is arranged on the most upstream side in the data flow or the pseudo data flow, and the actual ST element is the most downstream. Arranged on the side. In addition, the number of elements (for example, SMA elements and SMAM elements) suitable for calculation in each segment is defined. Therefore, the compiler 16 according to the present embodiment first determines the actual arrangement positions of the LD element and the ST element arranged in the layout area, and then determines the actual arrangement positions of the SMA element and the SMAM element ( Steps 501, 502). Thereafter, the actual arrangement positions of other elements such as DEL elements arranged by the user and arranged in the layout area are determined (step 503).

  In the present embodiment, the position of the element on the APP 50 is specified by (segment number, column number, row number). Therefore, the arrangement position can be determined by assigning an actual position on the AAP 50, that is, (segment number, column number, row number) to the element arranged in the layout area by the user.

  In the example shown in FIG. 15, the segment 1501 of the APP 50 includes 16 SMA elements. Therefore, if the map configuration placed in the layout area by the user requires more SMA elements or SMAM elements that do not exist in this segment, the SMA elements and SMAM elements of other segments may be used. . Similarly, similar cases may occur for the other segments shown in FIGS. 16 and 17.

When the arrangement of each element arranged by the user in the layout area on the actual APP 50 is completed, the compiler 16 refers to the latency of each element and adds a DEL element as necessary (steps 504 and 505). .
When the position of each element in the APP 50 is determined in step 500, a routing process for determining a connection between the elements in the actually arranged APP is executed based on the connection between the elements set by the user (step 500). 510). Here, as will be described later, addition of a multiplexer (MUX) and switching processing are also executed.

  Hereinafter, the processing of Step 500 and Step 510 will be described in more detail with reference to an actual example. FIG. 6 is a diagram for explaining an example of insertion of a DEL element. For example, consider the case where the LD element 601 and the ST element 602 are connected (FIG. 6A). Here, when the LD element 601 and the ST element 602 have different segments in the APP 50 to be actually arranged, the DEL element is inserted according to the design rule. For example, when the LD element is arranged at the segment number “0” and the ST element is arranged at the segment number “2”, the DEL element interposed between the segment number “0” and the segment number “1” 611 and the DEL element 612 interposed between the segment number “1” and the segment number “2” are generated by the compiler 16, the LD element 601 and the DEL element 611 are connected, and the DEL element 611 and the DEL element 612 is connected, and DEL element 612 and ST element 602 are connected. In this case, the latency of each of the DEL elements 611 and 612 is set to “1”. A DEL element interposed between segments is also referred to as an “intersegment DEL element”.

  FIG. 7 is a diagram for explaining an example of insertion of another DEL element. Here, the map configuration (FIG. 7A) input by the user is the same as that shown in FIG. 4B. In the map configuration input by the user, DEL elements 712 and 714 having a latency of “3” are arranged in one path 710, respectively.

  For example, LD elements 711 and 721 are each arranged at segment number “0”, and ST element 715 is arranged at segment number “2”. Also, due to the restriction on the number of elements, the compiler is arranged so that the SMAM elements 713 and 723 are arranged in the segment number “1” and the SMA elements 722 and 724 are arranged in the segment numbers “0” and “1”, respectively. I think that it was decided to 16.

  In such a case, in the first pass 710, the DEL element 712 set by the user input is an inter-segment DEL element having a latency “3” from the segment number “0” to the segment number “1”, and , DEL element 714 is an inter-segment DEL element from segment number “1” to segment number “2”, and the actual arrangement position on APP 50 is determined. In this example, the arrangement position of the inter-segment DEL element 732 is actually determined as (0, 0, 7), and the arrangement position of the inter-segment DEL element 734 is determined as (1, 0, 7).

  On the other hand, also in the second path 720, it is necessary to arrange inter-segment DEL elements between the segments. In this example, an inter-segment DEL element 745 is arranged between the SMA element 722 having the segment number “0” and the SMAM element 723 having the segment number “1”, and the SMA element 724 having the segment number “1” The inter-segment DEL element 746 is also disposed between the ST element 715 having the segment number “2”. The arrangement positions of the inter-segment DEL elements 745 and 746 are determined as (0, 1, 7) and (1, 1, 7).

  As described above, the insertion of the DEL element in one path (second path) 720 may require adjustment of the latency in the other path (first path) 710. In such a case, the compiler 16 again adjusts the latency of the DEL element. In this example, the latency of the inter-segment DEL element 734 is changed from “3” to “5”.

  In the example of FIG. 7, the arrangement position in the APP 50 composed of (segment number, column number, row number) is determined from the DEL element in which only the latency is defined by the user, and other paths, etc. The latency is also adjusted in consideration of the latency. That is, in this embodiment, the compiler 16 has a function of converting an incomplete DEL element into a final DEL element whose arrangement position and latency are determined.

  Further, the compiler 16 determines the maximum latency and / or the minimum latency for the DEL element in advance, and determines the arrangement position of the DEL element in a form in which the DEL elements input by the user are divided or integrated. You can also. For example, as shown in FIG. 8A, it is considered that a DEL element 802 having a latency of “N (N is an integer set by the user)” is arranged between the SMA element 801 and the SMA element 803 by user input. . In this example, the compiler 16 compares the latency of the DEL element input by the user with the latency of the DEL element in the APP 50 to which the function can be actually assigned, thereby realizing the function of the DEL element input by the user. Therefore, the arrangement positions of the three DEL elements 812-1 to 812-3 are determined (FIG. 8B). The latency of each DEL element is “A”, “B”, and “C”, and the sum of the latency basically matches “N” applied to the user setting.

  For example, consider a case where the DEL element actually arranged on the APP is a four-input four-output element having four input ports and four output ports. For example, as shown in FIG. 9A, when a map structure in which a DEL element is interposed between SMA elements is created by user input, the user input is made to a single DEL element on the APP. In order to function as each of the DEL elements, a configuration as shown in FIG. 9B may be employed.

  Further, in the present embodiment, in order to protect the critical path, the user can set to prohibit the insertion of the DEL element in the connection between the elements by the user input. For example, in the example shown in FIG. 10, it is considered that prohibition of insertion of DEL elements is set for connection lines (paths) 1001 to 1005. In such a case, the compiler 16 assigns related elements (SMA elements 1011 to 1014 and DEL element 1015 in the example of FIG. 10) to a single in the APP so that no DEL element is inserted between them. Place in the segment.

  Furthermore, in the user input, the user can specify the column position where the element is arranged. For example, in the example of FIG. 11, an LDB (Load Buffer) element, an LD element, and an element that functions as a counter that gives a counter value to the LDB element (C16L element and C32L element) are appropriately connected to an external memory. In order to access, it is considered that there is a design rule that the same column number is arranged in APP. In this case, if the user gives a specific column number to any one of the above elements, the compiler 16 gives the same column number to the other elements.

  Further, as shown in FIG. 12, a case is considered in which an ID can be directly given to these elements so as to designate column numbers for the counter elements C16L or C32L. Also in this case, for example, if “EID_C16L = 0”, that is, if the user sets the column number of the counter element C16L as “0”, the compiler 16 also sets the column numbers of other elements to “0”. The

  Next, multiplexer addition and switching processing in the routing processing (step 510) will be described. The multiplexer has a function of specifying an input port on the data input side when connecting elements. This multiplexer includes at least a number for identifying an input port in addition to the arrangement position (segment number, column number, row number). The compiler 16 specifies the arrangement position of the multiplexer to be actually arranged on the APP 50 based on the connection between the elements concerning the user input, and specifies the input port (see FIG. 13).

  Further, in the routing process (step 510), the following switching process can also be executed in order to effectively use a finite element. For example, between SMA elements, it is also possible to switch ports so as not to affect the calculation result in a specific case. 14A, between the SMA elements input by the user, the data output port “do” of one SMA element 1401 and one data input port “dix” of the other SMA element 1402 are connected. Yes. However, the compiler 16 may connect the data output port “do” of one SMA element 1401 and the other data input port “diy” of the other SMA element 1402 on the actual APP 50 (FIG. 14). (See (b)).

  Furthermore, in the present embodiment, in the DEL element having a plurality of input ports and a plurality of output ports, the input port and the output port can be switched in the routing process. In the example illustrated in FIG. 14C, the DEL element delays the data input through the first input port “dix” and outputs the data from the first output port “dox”, as usual, by user input. However, the compiler 16 causes the DEL element on the actual APP 50 to delay the data input at the first input port “dix” and output it from the second output port “doy”. Alternatively, it may be used (see FIG. 14D). Even in this case, it goes without saying that the logic by the user input is not changed and does not affect the operation result.

  As described above, according to the present embodiment, the mapping configuration in which the elements described in DDDL are visually displayed is arranged in the layout area by the user operating the input device, and the elements are connected to each other. Then, the arrangement of each element on the actual APP and the connection between the elements can be realized by the compiler according to the design rule. Therefore, the user may arrange a mapping configuration that visually represents an element in accordance with a data flow based on a desired circuit design specification.

  The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

FIG. 1 is a block diagram showing an outline of an arrangement system of circuit elements of an integrated circuit according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a parallel processing system using circuit elements of a hardware library. FIG. 3 is a diagram showing an outline of the AAP unit. FIG. 4 is a diagram illustrating an example of a mapping configuration. FIG. 5 is a flowchart showing an outline of processing executed in the compiler. FIG. 6 is a diagram for explaining an example of insertion of a DEL element. FIG. 7 is a diagram for explaining an example of insertion of another DEL element. FIG. 8 is a diagram for explaining an example of insertion of another DEL element. FIG. 9 is a diagram for explaining an example of insertion of another DEL element. FIG. 10 is a diagram for explaining connection protection. FIG. 11 is a diagram for explaining an example of determining a column number. FIG. 12 is a diagram for explaining another example of determining the column number. FIG. 13 is a diagram for explaining an example of inserting a multiplexer. FIG. 14 is a diagram illustrating an example of switching. FIG. 15 is a diagram showing a portion of AAP in the RP according to the present embodiment. FIG. 16 is a diagram showing an AAP part in the RP according to the present embodiment. FIG. 17 is a diagram showing a portion of AAP in the RP according to the present embodiment. FIG. 18 is a diagram showing a structure of a DDDL describing elements according to the present embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Hardware library 12 Display control part 14 Hardware structure 16 Compiler 18 Memory | storage part

Claims (12)

A visual symbol selected from a definition file in which a visual symbol of a circuit element constituting an integrated circuit and hardware configuration information including connection information of the circuit element are stored in association with each other, and the visual symbol Assigning the circuit element to an actual circuit element having a corresponding specific function pre-arranged on the integrated circuit, based on the connection established between
Interposing a circuit element having a delay function arranged on the integrated circuit between the assigned circuit elements according to the latency of the circuit element;
Storing hardware configuration information including connection information of the circuit elements describing the assigned or intervening circuit elements in a memory as arrangement information of the circuit elements of the integrated circuit. To arrange circuit elements.   2. The method according to claim 1, further comprising the step of interposing an actual circuit element having a delay function in connection of the circuit elements between segments including a certain group of circuit elements in the integrated circuit. .   Allocating at least one or more actual circuit elements according to at least the maximum latency of the actual circuit elements having the delay function when the actual circuit elements having the delay function are interposed. 3. A method according to claim 1 or 2, characterized in that   When interposing an actual circuit element having the delay function, a step of referring to the number of input ports and the number of output ports of the actual circuit element having the delay function and assigning the actual circuit element to a single actual circuit element The method according to claim 1, further comprising:   5. The method according to claim 1, wherein an actual circuit element having a delay function is not interposed between specific circuit elements selected by a user regardless of latency. 6.   6. The method according to claim 1, further comprising the step of interposing an actual multiplexer for designating an input port of the circuit element between the circuit elements. A visual symbol selected from a definition file in which a visual symbol of a circuit element constituting an integrated circuit and hardware configuration information including connection information of the circuit element are stored in association with each other, and the visual symbol Assigning the circuit element to an actual circuit element having a corresponding specific function pre-arranged on the integrated circuit, based on the connection established between
Interposing a circuit element having a delay function arranged on the integrated circuit between the assigned circuit elements according to the latency of the circuit element;
Causing the computer to execute a step of storing hardware configuration information including connection information of the circuit elements describing the assigned or intervening circuit elements in a memory as arrangement information of the circuit elements of the integrated circuit. A circuit element arrangement program characterized by the above.   8. The computer according to claim 7, further comprising a step of interposing an actual circuit element having a delay function in connection of the circuit elements between segments including a certain circuit element group in the integrated circuit. The program described in.   Assigning at least one or more actual circuit elements to the computer according to at least the maximum latency of the actual circuit elements having the delay function when interposing the actual circuit elements having the delay function. The program according to claim 7 or 8, wherein the program is executed.   When interposing an actual circuit element having the delay function, a step of referring to the number of input ports and the number of output ports of the actual circuit element having the delay function and assigning the actual circuit element to a single actual circuit element The program according to claim 7, wherein the program is executed by the computer.   11. The computer according to claim 7, wherein the computer is operated such that an actual circuit element having a delay function is not interposed between specific circuit elements selected by a user regardless of latency. The program according to one item. 12. The method according to claim 7, further comprising the step of interposing an actual multiplexer for designating an input port of the circuit element between the circuit elements. The listed program.

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