JP4275094B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a single-package semiconductor device in which a plurality of semiconductor devices are integrated into a single package, and more particularly to a technique for using an external terminal necessary for each single semiconductor device as a common terminal.

  A semiconductor device mounted on a small portable device or the like is a device in which a CPU constituting a system and a plurality of semiconductor devices such as various peripheral controllers and interface functions are integrated in one package to reduce the size and cost of the device. Has become the mainstream.

  Semiconductor devices integrated in one packaged semiconductor device are often developed by different manufacturers, and it is generally difficult to perform a test in consideration of the contents. When a separation circuit between semiconductor devices is inserted for testing, there arises a problem that it becomes necessary to test the separation circuit.

  As a countermeasure for this problem, there is a method in which a test is performed by separating semiconductor devices by controlling an enable signal of a buffer on a signal line connecting the semiconductor device and an external terminal without inserting a separation circuit (for example, Patent Document 1).

  FIG. 12 is a diagram showing a common terminal connection method in such a single packaged semiconductor device in which a plurality of conventional single semiconductor devices are integrated. In FIG. 12, 201 is a first semiconductor device, 202 is a second semiconductor device, 203 is a tristate buffer, 204 is a buffer, and 205 is an enable generation circuit.

The output of the first semiconductor device 201 is conducted when the tristate buffer 203 is enabled, and becomes an external output of the one-package semiconductor device. When the tri-state buffer 203 is in a disabled state, an input signal from an external terminal of one packaged semiconductor device is input to the second semiconductor device 202.
JP 2001-56358 A

  Semiconductor devices integrated in one packaged semiconductor device include those developed by different manufacturers and those having various interface functions, and those having different external power supply voltages may be used.

  However, in the configuration of the common terminal of the conventional one-package semiconductor device, there is a restriction that the external power supply voltage of the single semiconductor device to be mounted must be the same, and further, depending on the change timing of the output signal of the single semiconductor device. May cause signal collision.

  The present invention relates to a single packaged semiconductor device configured by mounting a plurality of single semiconductor devices, and using external terminals necessary for the multiple single semiconductor devices as shared terminals in the single packaged semiconductor device. Another object is to realize sharing of independent semiconductor devices independent of the external power supply voltage. It is another object of the present invention to prevent signal collision when a single semiconductor device is individually output. That is, an object is to realize a single packaged semiconductor device that does not depend on the operation specifications of a single semiconductor device.

  The semiconductor device of the present invention is made into one package on which the first semiconductor device, the second semiconductor device, and the output device connected to the shared external terminal of the first semiconductor device and the second semiconductor device are mounted. A first buffer having a function of converting an amplitude level of an output signal of the first semiconductor device; and an amplitude level of an output signal of the second semiconductor device. A second buffer having a function to perform the operation, and a selection circuit that receives the output signal of the first buffer and the output signal of the second buffer, and connects the output signal of the selection circuit to a shared external terminal It is the structure to do.

  According to the above configuration, since the output signals of the first semiconductor device and the second semiconductor device are respectively selected by the selection circuit and connected to the shared external terminal via the buffer for converting the amplitude level, A one-package semiconductor device that does not depend on the external power supply voltage value can be formed, and signal collision can be prevented regardless of the change timing of the output signals of the first semiconductor device and the second semiconductor device.

  The present invention includes a circuit for controlling conduction / non-conduction between the output of the selection circuit and the shared external terminal. According to the above configuration, since conduction / non-conduction between the shared external terminals can be controlled, the shared external terminal that is normally used as an output terminal to the outside is used as an external input terminal as necessary. Therefore, it is possible to use the semiconductor device usefully in testing a semiconductor device.

  In the present invention, the selection circuit and the control circuit operate based on an externally input signal.

  In the present invention, the selection circuit and the control circuit operate according to a signal output from the first semiconductor device or a signal input from the outside by selection from the first semiconductor device.

  In the present invention, a first tri-state buffer having an input connected to the shared external terminal and an output connected to the input of the first semiconductor device, an input connected to the shared external terminal, and an output connected to the first external terminal And a second tri-state buffer connected to the input of the semiconductor device.

  In the present invention, there is provided a coincidence detection circuit that detects a coincidence between the output signal of the first buffer and the output signal of the second buffer and uses a detection result as an input of the selection circuit. According to the above configuration, when the first semiconductor device and the second semiconductor device have the same specifications, an inspection method using the output of the coincidence detection circuit as a pass / fail judgment signal of the semiconductor device is possible.

  In the present invention, a mismatch detection holding circuit is provided between the match detection circuit and the selection circuit and holds a mismatch output of the match detection circuit. According to the above configuration, in the inspection of the semiconductor device, the mismatch detection holding circuit can hold that the match detection circuit has detected a mismatch even in one test cycle. Defective products can be determined, the test cycle for observing expected values can be greatly shortened, and the test vector length can be reduced.

  In the present invention, a compression processing circuit is provided in which the compression output of the output signal of the first buffer and the output signal of the second buffer is input to the selection circuit. According to the above configuration, in the scan test of the semiconductor device, the result of compression processing of the shift-out signal by the compression processing circuit can be used as the signal to be inspected in the scan test, so that the shift-out output must be sequentially output during the shift operation. And at least two scan shift outputs can be collected in one external terminal, and the efficiency of the scan test can be improved.

  In the present invention, a plurality of the output devices or the output devices divided into a plurality are arranged close to the input / output portions of the first semiconductor device and the second semiconductor device according to their connection relations. is there. According to the above configuration, since the output device is divided and installed close to the terminals of the first semiconductor device and the second semiconductor device, the wire wiring between the single semiconductor devices is prevented from being congested, and the wire wiring is further reduced. It can be shortened.

  In the present invention, the plurality of output devices or the plurality of output devices are incorporated in an input / output unit of the first semiconductor device. According to the above configuration, by incorporating the output device in the first semiconductor device, it is possible to reduce the area of the substrate for making one package, and the first semiconductor device and the second semiconductor device. By stacking the output devices, it is possible to suppress the height of one packaged semiconductor device.

  In the present invention, the plurality of output devices or the plurality of output devices are formed on a substrate for packaging.

  A method for designing a semiconductor device according to the present invention is a method for designing a semiconductor device according to the present invention, comprising: selecting a function of the output device from terminal specifications of the first semiconductor device and the second semiconductor device; The first semiconductor device or the second semiconductor device alone is connected to an external terminal with respect to the output signal line of the second semiconductor device that is connected to the input of the first semiconductor device and not connected to the external terminal. Arranging the output device by combining signal lines connected to each other, dividing the output device into a plurality of groups, and arranging the plurality of devices according to the terminal arrangement of the first semiconductor device and the second semiconductor device. And determining a terminal order in each of the output devices divided into two.

  According to the above configuration, in designing one packaged semiconductor device, it is possible to appropriately select and realize sharing of the external terminals of the single semiconductor device. In addition, the signal line that is not connected to the external terminal by design can share the signal line that is connected to the external terminal and the external terminal of the first semiconductor device or the second semiconductor device alone. Observable from outside the semiconductor device. Furthermore, congestion of wire wiring can be prevented by dividing the output device.

  According to the present invention, the output signal of each semiconductor device mounted on one packaged semiconductor device is selected by the selection circuit via the buffer for converting the amplitude level and connected to the shared external terminal. A one-package semiconductor device that does not depend on the external power supply voltage value can be configured, and signal collision can be prevented regardless of the change timing of the output signal of each semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one packaged semiconductor device according to Embodiment 1 of the present invention, and shows a method of connecting external terminal portions when a plurality of single semiconductor devices are packaged.

  In FIG. 1, 101 is a first semiconductor device, 102 is a second semiconductor device, 103 is a first buffer having a function of converting the amplitude level of the output signal, and 104 is a function of converting the amplitude level of the output signal. A second buffer 105 has a selection circuit. Here, a circuit including the first buffer 103, the second buffer 104, and the selection circuit 105 is an output device.

  A signal output from the first semiconductor device 101 is converted into a signal amplitude level of an external terminal of one packaged semiconductor device by the first buffer 103. The signal output from the second semiconductor device 102 is converted by the second buffer 104 into the signal amplitude level of the external terminal of one packaged semiconductor device.

  Here, the amplitude level of the output signal of the first semiconductor device 101 and the amplitude level of the output signal of the second semiconductor device 102 do not have to be the same, and the first buffer 103 and the second buffer 104 respectively It is converted into the amplitude level of the external output signal of one packaged semiconductor device. Thus, a one-package semiconductor device that does not depend on the external power supply voltage value of the first semiconductor device 101 and the external power supply voltage value of the second semiconductor device 102 can be configured.

  The output of the first buffer 103 and the output of the second buffer 104 are input to the selection circuit 105, and are selectively output as an external output signal of one packaged semiconductor device by a selection control signal. The selection circuit 105 can prevent signal collision without depending on the change timing of the output signals of the first semiconductor device 101 and the second semiconductor device 102.

  Further, by reducing the power supply voltage of the output device from the external power supply voltage of the first semiconductor device 101 or the external power supply voltage of the second semiconductor device 102, it is possible to reduce the current consumption of one packaged semiconductor device. Become.

  Further, by installing the output device of the present invention, the external terminal of the first semiconductor device 101 and the external terminal of the second semiconductor device 102 do not require an output current for driving the input terminal of a device having a large load. Thus, the external power supply voltage of the first semiconductor device 101 or the external power supply voltage of the second semiconductor device 102 can be lowered.

  FIG. 2 is a block diagram showing a configuration example of one packaged semiconductor device according to Embodiment 2 of the present invention, and shows a configuration of an output device when a plurality of single semiconductor devices are packaged. 2, 101 to 105 are the same as those in FIG. 1, 106 is a coincidence detection circuit, and 107 is a conduction / non-conduction control circuit.

  A signal output from the first semiconductor device 101 and converted in amplitude level by the first buffer 103 and a signal output from the second semiconductor device 102 and converted in amplitude level by the second buffer 104 are sent to the coincidence detection circuit 106. If it is input and the logic matches, “H” level is output, and if they do not match, “L” level is output.

  The output of the first buffer 103, the output of the second buffer 104, and the output of the coincidence detection circuit 106 are input to the selection circuit 105, and in accordance with the selection control signal, the output of the first buffer 103 or the second output in the normal operation mode. The output of the buffer 104 is selected, and the output of the coincidence detection circuit 106 is selected in the test mode. Further, the conduction / non-conduction control circuit 107 determines whether or not to output the signal selected by the selection circuit 105 to one packaged semiconductor device.

  In the test mode, the output of the first semiconductor device 101 and the output of the second semiconductor device 102 change sequentially, and the output of the coincidence detection circuit 106 also changes sequentially. During the test, a non-defective product and a defective product are determined by observing signals externally output from one packaged semiconductor device from the start to the end.

  As a specific example, when the first semiconductor device 101 is a logic integrated device and the second semiconductor device 102 is a memory device, the output of the logic integrated device becomes an expected value, and the output of the memory device becomes a test target. In the test cycle in which the output of the logic integrated device and the output of the memory device match, the match detection circuit 106 outputs “H” level, and in the test cycle in which the mismatch occurs, the match detection circuit 106 outputs “L” level.

  Further, in the test in which the first semiconductor device 101 is the memory device A and the second semiconductor device 102 is the memory device B having the same physical configuration as the memory device A, a non-defective product or a defective product does not require an expected value. Can be determined. That is, if a test cycle in which the output of the memory device A and the output of the memory device B do not match occurs, it means that either the memory device A or the memory device B is defective.

  In FIG. 2, the selection control signal and the conduction / non-conduction control signal are input from an external terminal of one packaged semiconductor device. In the present invention, it is also assumed that the output signal of the first semiconductor device 101 is used for the selection control signal and the conduction / non-conduction control signal.

  Further, the present invention includes a selection control signal and a conduction / non-conduction control signal input from the outside of one packaged semiconductor device, and a selection control signal and a conduction / non-conduction control signal generated and output by the first semiconductor device 101. It is also assumed that the output device can be selected.

  FIG. 3 is a block diagram showing a configuration of one packaged semiconductor device according to the third embodiment of the present invention, and shows a configuration of an output device when a plurality of single semiconductor devices are packaged. 3, 101 to 107 are the same as those in FIG. 2, 108 is a first tristate buffer having a function of converting the amplitude level of the input signal, and 109 is a second having a function of converting the amplitude level of the input signal. This is a tri-state buffer.

  For example, when the output of the first semiconductor device 101 becomes the external output of one packaged semiconductor device, the output of the first semiconductor device 101 is the signal amplitude level of the external terminal of one packaged semiconductor device by the first buffer 103. Converted to. When the 2-bit selection control signal of the selection circuit 105 becomes “00”, the output of the first buffer 103 is selected as the output of the selection circuit 105, and the conduction / non-conduction control signal becomes “1” level. Output from the conduction / non-conduction control circuit 107 to the outside.

  At this time, the enable signal of the first tristate buffer 108 is at “1” level, the output of the first tristate buffer 108 becomes high impedance, the output of the first semiconductor device 101 and the selection circuit 105 It is possible to prevent output from colliding.

  During this series of operations, the output state of the second semiconductor device 102 does not affect the operation of the one-package semiconductor device. However, when the second semiconductor device 102 is in the output state, the enable signal of the second tristate buffer 109 needs to be at “1” level, and when the second semiconductor device 102 is in the input state, The enable signal of the second tri-state buffer 109 needs to be at “0” level.

  An operation of inputting a signal to the second semiconductor device 102 from the outside of one packaged semiconductor device will be described. When the conduction / non-conduction control signal becomes “0” level, the conduction / non-conduction control circuit 107 enters a non-conduction state, and a signal input from the outside of one packaged semiconductor device is input to the second tri-state buffer 109. Entered.

  Then, when the enable signal of the second tri-state buffer 109 becomes “0” level, the second tri-state buffer 109 becomes conductive, and the signal is input to the second semiconductor device 102. At this time, the input signal to the selection control signal of the selection circuit 105 and the output of the selection circuit 105 do not affect the operation of inputting a signal from the outside of one packaged semiconductor device.

  When a signal input from the outside of one packaged semiconductor device is input to the first semiconductor device 101 and the second semiconductor device 102, the conduction / non-conduction control signal is set to “0” level. Thus, the conduction / non-conduction control circuit 107 is turned off, the enable signal of the first tri-state buffer 108 is set to “0” level, and the enable signal of the second tri-state buffer 109 is set to “0” level. Thus, the first tristate buffer 108 and the second tristate buffer 109 are turned on, and signals input from the outside of one packaged semiconductor device are supplied to the first semiconductor device 101 and the second semiconductor device 102. Entered.

  Further, when the output of the second semiconductor device 102 is used as the input of the first semiconductor device 101, the output of the second semiconductor device 102 is input to the selection circuit 105 via the second buffer 104 and 2 bits. When the selection control signal becomes “01”, the output of the selection circuit 105 is obtained. Then, when the conduction / non-conduction control signal becomes “1” level, it is input to the first tri-state buffer 108 via the conduction / non-conduction control circuit 107, and the enable signal of the first tri-state buffer 108 is received. When it becomes “0” level, it becomes conductive and is input to the first semiconductor device 101.

  In the test mode state, the enable signal of the first tri-state buffer 108 is “1”, the first tri-state buffer 108 is non-conductive, and the enable signal of the second tri-state buffer 109 is “1”. This tri-state buffer 109 is also turned off. The output of the coincidence detection circuit 106 becomes the selection output of the selection circuit 105 when the selection control signal of the selection circuit 105 becomes “10”. When the conduction / non-conduction control signal becomes “1” level, the conduction / non-conduction control circuit 107 becomes conductive and becomes an external output of one packaged semiconductor device.

  The coincidence detection circuit 106 outputs an “H” level when the output of the first semiconductor device 101 and the output of the second semiconductor device 102 coincide, and outputs an “L” level when they do not coincide. As a result, it is possible to determine whether the product is non-defective or defective by sequentially observing the external output of one packaged semiconductor device from the start to the end of the test.

  FIG. 4 adds a function of holding the output of the coincidence detection circuit in the one-package semiconductor device of the third embodiment described with reference to FIG. In FIG. 4, the coincidence detection circuit 106 outputs an “L” level during a test cycle in which the output of the first semiconductor device 101 and the output of the second semiconductor device 102 do not coincide in the test mode.

  The mismatch detection holding circuit 110 holds the “L” level when the match detection circuit 106 outputs “L” level even in one test cycle. When the selection control signal becomes “10”, the selection circuit 105 selectively outputs the output of the mismatch detection holding circuit 110. Then, when the conduction / non-conduction control signal becomes “1” level, the conduction / non-conduction control circuit 107 becomes conductive and becomes an external output of one packaged semiconductor device.

  When the coincidence detection holding circuit 110 outputs “L” level even in one test cycle, the mismatch detection holding circuit 110 can hold the “L” level even if all other cycles are at “H” level. In an actual test, it is possible to determine a non-defective product or a defective product by observing this external output for at least one test cycle when the test is completed. As a result, the test cycle for observing the expected value is greatly shortened, and the test vector length can be reduced.

  FIG. 5 shows a single packaged semiconductor device according to the third embodiment described with reference to FIG. 3, to which a function for holding the output of the coincidence detection circuit and a function for compressing the output signals of a plurality of single semiconductor devices are added. .

  In FIG. 5, during the scan test, the shift output of the first semiconductor device 101 and the shift output of the second semiconductor device 102 are input to the compression processing circuit 111 for each clock cycle and compressed. The signal after compression processing is selected by the selection circuit 105 when the selection control signal becomes “11”, and is output to the outside of one packaged semiconductor device through the conduction / non-conduction control circuit 107.

  In a series of operations, it is not necessary to sequentially output the shift-out output of the first semiconductor device 101 and the shift-out output of the second semiconductor device 102 during the shift operation, and at least two scan shift outputs are output to one external terminal. It becomes possible to aggregate.

  Further, when the first semiconductor device 101 is a logic integrated device and the second semiconductor device 102 is a memory device, only the logic integrated device is subjected to the scan test, but the output of the memory device during the scan test is used. Can be tested by outputting to the external terminal a signal obtained by compressing the scan shift output of the logic integrated device.

  FIG. 6 is a configuration diagram for facilitating testing of a terminal of a single semiconductor device that is not assigned as an external terminal when a plurality of single semiconductor devices are packaged in one embodiment of the present invention. In FIG. 6, the output 102 a of the second semiconductor device 102 is connected to the input 101 a of the first semiconductor device 101.

  In the specification of one packaged semiconductor device, it is not necessary to output these terminals as external terminals of the one packaged semiconductor device. However, in order to facilitate the inspection of the output 102a of the second semiconductor device 102, the second buffer 104 having a function of converting the amplitude level of the output signal is disposed in the output 102a of the second semiconductor device 102. Further, by arranging the selection circuit 105, the output of the first buffer 103 is selected during the normal operation, and the output of the second buffer 104 is selected during the test operation. As a result, the output 102a can be observed from the outside during the test operation.

  FIG. 7 is a diagram showing a first example of a physical arrangement of a plurality of single semiconductor devices and output devices on a substrate in the embodiment of the present invention. In FIG. 7, 101 is a first semiconductor device, 102 is a second semiconductor device, 121 is a first output device, 122 is a second output device, 123 is a third output device, and 124 is a fourth output. The device 130 is a substrate for making one package.

  The first semiconductor device 101 and the second semiconductor device 102 each have an input terminal, an output terminal, and an input / output terminal. The series of terminals are arranged on the four sides of the first semiconductor device 101 and the second semiconductor device 102, and the output devices are moved from the first output device 121 to the fourth output device 124 so as to be close to the series of terminal arrangements. And is arranged on a substrate 130 for making one package.

  In this way, the output device is divided into four parts and installed close to the terminals of the first semiconductor device 101 and the second semiconductor device 102, thereby preventing the wire wiring from being congested between the single semiconductor devices, and further the wire Wiring can be shortened.

  FIG. 8 is a diagram illustrating a second example of a physical arrangement of a plurality of single semiconductor devices and an output device on a substrate in the embodiment of the present invention. In FIG. 8, the output device divided into four parts is not arranged on the substrate 130 for making one package, but as a part of the output device or the input / output device of the first semiconductor device 101. 101 is arranged inside.

  Accordingly, the height of one packaged semiconductor device can be suppressed by stacking the first semiconductor device 101, the second semiconductor device 102, and the output device. Further, the output to the first semiconductor device 101 can be suppressed. By incorporating the device, the area of the substrate 130 for making one package can be reduced.

  FIG. 9 is a diagram illustrating a third example of a physical arrangement of a plurality of single semiconductor devices and an output device on a substrate in the embodiment of the present invention. In FIG. 9, the output devices 121 to 124 divided into four parts are built in a substrate 130 for making one package, and the connection between the first semiconductor device 101 and the second semiconductor device 102 is made into one package. This is performed by wiring in the substrate 130.

  As a result, it is possible to reduce wire wiring between the first semiconductor device 101, the second semiconductor device 102, and the output devices 221 to 224 divided into four parts to be packaged.

  FIG. 10 is a truth table showing the state of the control signals and the external terminals of the output device of one packaged semiconductor device in the embodiment of the present invention. When the plurality of single semiconductor devices shown in FIG. 5 are packaged, an output device includes a 1-bit enable signal for controlling the conduction / non-conduction control circuit 107 and a 1-bit for controlling the first tristate buffer 108. The control signal of 5 bits in total including the enable signal, the 1-bit enable signal for controlling the second tri-state buffer 109, and the 2-bit selection control signal of the selection circuit 105 is required.

  When “0” is input to the conduction / non-conduction control signal, the output of the output device becomes high impedance regardless of the state of other control signals. By using this function, it is possible to perform a connection test and a terminal leakage current test of a single packaged semiconductor device.

  Next, when “0” is input to the conduction / non-conduction control signal and “0” is input to the enable signal of the first tristate buffer 108, the output device is in the “input from the external terminal to the first semiconductor device 101” state. become. At this time, the output of the second semiconductor device 102 does not collide with an input signal from the external terminal, and the output state of the second semiconductor device 102 does not affect the operation of the one-package semiconductor device.

  Further, when “0” is input to the conduction / non-conduction control signal and “0” is input to the enable signal of the second tristate buffer 109, the output device enters the “input from the external terminal to the second semiconductor device 102” state. Become. At this time, the output of the first semiconductor device 101 does not collide with the input signal from the external terminal, and the output state of the first semiconductor device 101 does not affect the operation of the one-package semiconductor device.

  Further, when “0” is input to the conduction / non-conduction control signal, “0” is input to the enable signal of the first tristate buffer 108, and “0” is input to the enable signal of the second tristate buffer 109, the output device “ The state is “input from the external terminal to the first semiconductor device 101 and the second semiconductor device 102”.

  “1” for the conduction / non-conduction control signal, “0” for the enable signal of the first tri-state buffer 108, “1” for the enable signal of the second tri-state buffer 109, and “01” for the 2-bit selection control signal. When "" is input, the output device enters the "input from the output of the second semiconductor device 102 to the first semiconductor device 101" state.

  Similarly, “1” for the conduction / non-conduction control signal, “1” for the enable signal of the first tristate buffer 108, “0” for the enable signal of the second tristate buffer 109, and a 2-bit selection control signal. When “00” is input to the output device, the output device enters the “input from the output of the first semiconductor device 101 to the second semiconductor device 102” state. By using this function, it is possible to sequentially observe the terminal state during the operation test between the first semiconductor device 101 and the second semiconductor device 102.

  When “1” is input to the conduction / non-conduction control signal, “1” is input to the enable signal of the second tri-state buffer 109, and “01” is input to the 2-bit selection control signal, the output device is “second semiconductor device 102”. Output to external terminal "status.

  When “1” is input to the conduction / non-conduction control signal, “1” is input to the enable signal of the first tristate buffer 108, and “00” is input to the 2-bit selection control signal, the output device is “first semiconductor”. The output is from the output of the device 101 to the external terminal. By using this function, it is possible to perform an output current test of one packaged semiconductor device.

  “1” for the conduction / non-conduction control signal, “1” for the enable signal of the first tri-state buffer 108, “1” for the enable signal of the second tri-state buffer 109, and “10” for the 2-bit selection control signal. When "" is input, the output device enters the "output from the output of the coincidence detection circuit to the external terminal" state.

  By utilizing this function, a function test of a single packaged semiconductor device is performed by observing an external terminal with the output of the first semiconductor device 101 as an expected value and the output of the second semiconductor device 102 as a test target. It is possible to determine whether the product is non-defective or defective.

  “1” for the conduction / non-conduction control signal, “1” for the enable signal of the first tri-state buffer 108, “1” for the enable signal of the second tri-state buffer 109, and “11” for the 2-bit selection control signal. When "" is input, the output device enters the "output from the compression processing circuit output to the external terminal" state.

  By using this function, during the scan test, the shift output of the first semiconductor device 101 and the shift output of the second semiconductor device 102 are compressed by the compression processing circuit 111, and the output is observed at the external terminal. A non-defective product or a defective product can be determined.

  FIG. 11 is a flowchart showing a design procedure of an output device built in one packaged semiconductor device of the present invention.

  In order to package a plurality of single semiconductor devices into one package, as a first step, the terminal specifications of the first semiconductor device 101 and the second semiconductor device 102 and the terminal specifications required for one packaged semiconductor device are shared. The specifications of the functioning terminal (A group), the terminal used alone (B group), and the terminal of the first semiconductor device 101 or the terminal of the second semiconductor device 102 are used as external terminals of one packaged semiconductor device. The terminal (C group) not to be assigned is determined. Specifically, the terminal specifications of one packaged semiconductor device are determined based on whether the terminal functions of the first semiconductor device 101 and the second semiconductor device 102 are input only, output only, or input / output shared, respectively. .

  As a second step, the C group terminals determined in the first step are combined with the B group terminals and assigned to the output device defined in the present invention as a shared input / output compatible terminal. Next, as a third step, the output device assigned in the first step and the second step is divided into four from the terminal arrangement of the first semiconductor device 101 and the second semiconductor device 102. Finally, as a fourth step, the terminal order in each of the output devices divided into four is determined.

  In the semiconductor device of the present invention, the output signal of each semiconductor device mounted on one packaged semiconductor device is selected by a selection circuit via a buffer that converts the amplitude level and connected to a shared external terminal. A single packaged semiconductor device that does not depend on the external power supply voltage value can be configured, and a signal collision can be prevented regardless of the change timing of the output signal of each semiconductor device. It is useful as a one-package semiconductor device or the like that integrates a single package into a single package.

1 is a block diagram illustrating a method for connecting external terminal portions in a one-package semiconductor device according to a first embodiment of the present invention. The block diagram which shows the structural example of the output device in the 1 packaged semiconductor device which concerns on Embodiment 2 of this invention. The block diagram which shows the structural example of the output device in the 1 packaged semiconductor device which concerns on Embodiment 3 of this invention. The block diagram which shows the structure which added the function to hold | maintain the output of a coincidence detection circuit in the output device in the 1 packaged semiconductor device which concerns on Embodiment 3 of this invention. The block diagram which shows the structure which added the function which hold | maintains the output of a coincidence detection circuit, and the function which compresses the output signal of a several single semiconductor device in the output device in the 1 packaged semiconductor device which concerns on Embodiment 3 of this invention. FIG. 5 is a block diagram illustrating a configuration example for facilitating testing of a terminal of a single semiconductor device that is not assigned as an external terminal in the one-package semiconductor device of the present invention. The figure which shows the 1st example of the physical arrangement | positioning on the board | substrate of the several single semiconductor device and output device in 1 packaged semiconductor device of this invention. The figure which shows the 2nd example of the physical arrangement | positioning on the board | substrate of the several single semiconductor device and output device in 1 packaged semiconductor device of this invention. The figure which shows the 3rd example of the physical arrangement | positioning on the board | substrate of the several single semiconductor device and output device in 1 packaged semiconductor device of this invention. The truth table which shows the control signal of the output device of 1 packaged semiconductor device in the embodiment of the present invention, and the state of an external terminal. The flowchart which shows the design procedure of the output device incorporated in 1 packaged semiconductor device of this invention. The figure which shows the connection method of the common terminal in the 1 packaged semiconductor device which integrated the conventional several single semiconductor device.

Explanation of symbols

101, 201 1st semiconductor device 102, 202 2nd semiconductor device 103 1st buffer 104 2nd buffer 105 selection circuit 106 coincidence detection circuit 107 conduction / non-conduction control circuit 108 1st tristate buffer 109 2nd Tristate buffer 110 mismatch detection holding circuit 111 compression processing circuit 121 first output device 122 second output device 123 third output device 124 fourth output device 130 1 substrate for packaging 203 tristate buffer 204 Buffer 205 enable generation circuit

Claims (12)

A semiconductor device packaged in one package on which a first semiconductor device, a second semiconductor device, and an output device connected to a shared external terminal of the first semiconductor device and the second semiconductor device are mounted. The output device includes a first buffer having a function of converting an amplitude level of an output signal of the first semiconductor device into a signal amplitude level of the shared external terminal, and an amplitude of an output signal of the second semiconductor device. A second buffer having a function of converting a level to a signal amplitude level of the shared external terminal; and a selection circuit having the output signal of the first buffer and the output signal of the second buffer as inputs. the semiconductor device is configured to connect the output signal of the selection circuit to the common external terminal. The output device is
The semiconductor device according to claim 1, further comprising a control circuit that controls conduction / non-conduction between an output of the selection circuit and the shared external terminal. The selection circuit selects an output signal based on a signal input from the outside, and the control circuit performs conduction / conduction between the output of the selection circuit and the shared external terminal based on a signal input from the outside. The semiconductor device according to claim 2, wherein non-conduction is controlled . The selection circuit selects an output signal based on a signal output from the first semiconductor device or an externally input signal by selection from the first semiconductor device, and the control circuit selects the first semiconductor device. The conduction / non-conduction between the output of the selection circuit and the shared external terminal is controlled by a signal output from the first semiconductor device or a signal input from the outside by selection from the device. Semiconductor device. The output device is
A first tristate buffer having an input connected to the shared external terminal and an output connected to an input of the first semiconductor device; an input connected to the shared external terminal; and an output connected to the second semiconductor device The semiconductor device according to claim 2, further comprising: a second tristate buffer connected to the input of the first tristate buffer.   2. The semiconductor device according to claim 1, further comprising: a coincidence detection circuit that detects coincidence between the output signal of the first buffer and the output signal of the second buffer and uses a detection result as an input of the selection circuit. The output device is
7. The semiconductor device according to claim 6, further comprising a mismatch detection holding circuit that is provided between the match detection circuit and the selection circuit and holds a mismatch output of the match detection circuit. The output device is
The semiconductor device according to claim 1, further comprising: a compression processing circuit that uses a compressed output of the output signal of the first buffer and the output signal of the second buffer as an input to the selection circuit. A plurality of the output equipment, each connection relation in accordance with the first semiconductor device and the second semiconductor device a semiconductor device according to claim 1, wherein is arranged close to the input and output portions of the. Said plurality of output equipment, said first semiconductor device a semiconductor device according to claim 9 in which is incorporated to the input and output of the. Wherein the plurality of the output equipment, the semiconductor device according to claim 9, wherein the element formed on a substrate for packaging.   12. The method of designing a semiconductor device according to claim 1, wherein a function of the output device is selected from terminal specifications of the first semiconductor device and the second semiconductor device; The output signal line of the second semiconductor device that is connected to the input of the first semiconductor device and not connected to the external terminal is connected to the external terminal alone of the first semiconductor device or the second semiconductor device. Dividing the output device into a plurality of groups, dividing the output device into a plurality of groups, and dividing the output device into a plurality according to the terminal arrangement of the first semiconductor device and the second semiconductor device Determining a terminal order for each of the output devices, and a method for designing a semiconductor device.

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