JP4271703B2 - Near-field probe using SOI substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a near-field optical probe using an SOI substrate and a manufacturing method thereof, and more particularly, to a near-field probe applied to a near-field scanning optical microscope and a near-field light information storage device. The present invention relates to a needle and a manufacturing method thereof.

  A near-field scanning optical microscope is used to examine the optical characteristics of a sample with a light resolution that is more accurate than the diffraction limit of an incident light source. The near field probe used here includes an optical fiber type near field probe and a cantilever type near field probe.

  The near-field light information storage device uses a near-field probe to reduce the size of the optical recording mark to less than the diffraction limit of the recording light source and use it for high-density optical information storage.

  The near-field probe used in the near-field scanning optical microscope and the near-field light information storage device includes a cantilever-type and slide-type near-field probe manufactured on a silicon substrate, and an optical fiber-type near-field probe. And can be distinguished. A near-field probe manufactured on a silicon substrate has an advantage that it is more mechanically stable and easy to mass-produce.

  The near-field probe manufacturing method using a silicon substrate uses a part of the manufacturing process common to the existing atomic microscope probe manufacturing process, but the major difference is that a near-field is generated at the tip of the chip. This means that the aperture must be formed. Due to such differences, the manufacturing method of the near-field probe is more difficult and the manufacturing process procedure is complicated than the manufacturing method of the atomic microscope probe.

  In particular, when a silicon substrate is used, there is a technical problem in coupling a manufacturing process of a chip in which an aperture is formed and a manufacturing process of a cantilever arm including the chip. In addition, when a silicon substrate is used, there is a problem that it is difficult to adjust the size of the chip edge aperture so as to be reproducible in the nanometer range.

Korean Publication No. 1020034035497 “Fabrication of a High-Throughput Cantilever-Style Aperture Tip by the Use of the Bird ’s Beak Effect” (Jpn.J.Appl.Phys.Vol.42 (2003) pp.4353-4356) `` SNOM / AFM microprobe integrated with piezoresistive cantilever beam for multifunctional surface analysis '' (Microelectronic Engineering 61-62 (2002) 981-986)

  The present invention has been made in view of such problems, and an object thereof is to provide a near-field probe manufactured based on an SOI (Silicon On Insulator) substrate without using a single silicon substrate. There is to offer.

  Another object of the present invention is to provide a manufacturing method of a near-field probe that can easily combine a manufacturing process of a chip formed with an aperture using an SOI substrate and a manufacturing process of a cantilever arm provided with the chip. By the way.

  In order to achieve the above-described technical problem, a near-field probe according to the present invention includes a cantilever arm support portion formed of a lower silicon layer of an SOI substrate and having a through hole on one side of the lower silicon layer. .

  Furthermore, the near-field probe of the present invention includes a bonding oxide layer pattern and an upper silicon layer pattern of an SOI substrate that are supported on the upper surface of the lower silicon layer and have both holes smaller than the through holes, and the upper silicon layer. A cantilever arm formed of a silicon oxide layer pattern including a chip having an aperture at the tip portion in accordance with the hole on the pattern, and a light transmission preventing layer formed without embedding the aperture on the silicon oxide layer pattern And. The tip is conical or parabolic. It is desirable that the aperture protrudes above the SOI substrate.

  In the manufacturing method of the near-field probe of the present invention, first, a junction oxide layer pattern having a first hole is formed on the lower silicon layer. Next, an upper silicon layer is formed on the first hole and the junction oxide layer pattern to complete an SOI substrate. Next, a chip structure is formed on the upper silicon layer formed on the first hole. Next, a silicon oxide layer pattern and an upper silicon layer pattern constituting a cantilever arm are sequentially formed on the outer surface of the chip structure and the upper silicon layer. Next, an etching mask layer pattern is formed on the back surface of the lower silicon layer constituting the cantilever arm support. Next, the etching mask layer pattern is used to etch the lower silicon layer and the upper silicon layer pattern in the chip structure on the first hole to expose the bonding oxide layer pattern. A chip having an aperture at the tip is formed in the through hole and the second hole smaller than the through hole. Next, a light transmission preventing layer is formed on the silicon oxide layer pattern without embedding the aperture.

  Accordingly, the present invention provides an upper silicon layer pattern and a junction oxide layer pattern each having a second hole smaller than the through hole while being supported on the upper surface of the lower silicon layer, and a tip portion corresponding to the second hole. The cantilever arm is formed of a silicon oxide layer pattern including a chip having an aperture and an anti-translucent layer.

  In the chip structure, a silicon nitride layer pattern is formed on a part of the upper silicon layer, and the upper silicon layer is wet-etched using the silicon nitride layer pattern as a mask to form a conical shape or a parabolic shape.

  The silicon oxide layer pattern and the upper silicon layer pattern constituting the cantilever arm oxidize the upper silicon layer having the chip structure to form a silicon oxide layer on the outer surface and the upper silicon layer of the chip structure. The silicon oxide layer and the upper silicon layer are formed by patterning.

  The through hole, the second hole and the chip are formed by etching the lower silicon layer using the etching mask layer pattern and an etching mask to form a through hole exposing the bonding oxide layer pattern, The bonding oxide layer pattern is obtained by etching the upper silicon layer pattern in the chip structure on the first hole using an etching mask.

  The near-field probe of the present invention as described above is configured such that the chip protrudes above the SOI substrate based on the SOI substrate. In addition, the near-field probe of the present invention can easily combine a manufacturing process of a chip in which an aperture is formed and a manufacturing process of a cantilever arm provided with the chip.

  The near-field probe of the present invention is manufactured based on an SOI substrate. Accordingly, the near-field probe of the present invention forms a cantilever arm support portion with the lower silicon layer of the SOI substrate, and is formed on the junction oxide layer pattern, the upper silicon layer pattern, and the upper silicon layer pattern of the SOI substrate. A cantilever arm is composed of a silicon oxide layer pattern including a chip having a chip and a light transmission preventing layer formed on the silicon oxide layer pattern.

  As described above, the near-field probe of the present invention is configured such that the tip faces the upper side, that is, the upper side of the SOI substrate, and can prevent the tip from colliding with the sample to be measured.

  Furthermore, the manufacturing method of the near-field probe of the present invention includes a manufacturing process of a chip in which an aperture is formed while the chip is formed so as to face the upper side of the SOI substrate, that is, an upper part, and a cantilever arm including the chip. The manufacturing process can be easily combined.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The embodiments of the present invention exemplified below are modified into various other forms, and the scope of the present invention is not limited to the embodiments described later, and can be embodied in various different forms. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the size or thickness of the film or region is exaggerated for clarity.

First, the structure of a near-field probe according to the present invention will be described with reference to FIGS.
14 is a cross-sectional view showing the structure of the near-field probe according to the present invention, FIG. 15 is a plan view of the near-field probe according to the present invention, and FIG. 14 is a cross-sectional view taken along line AA in FIG. It is.

  In FIG. 14, a plurality of near-field probes 100 are formed in a plurality of divided regions 52 of the SOI substrate 18 constituted by the lower silicon layer 10, the junction oxide layer pattern 12, and the upper silicon layer pattern 16a. The near-field probe 100 formed in the segmented region 52 is connected to a silicon layer 50 (a lower silicon layer or an upper silicon layer) constituting the SOI substrate 18. The near-field probe 100 is individually provided by cutting the silicon layer 50 using a diamond top or a cutting tool.

  The near-field probe 100 includes a cantilever part 66 formed by a cantilever arm support part 62 and a cantilever arm 64 supported by the cantilever arm support part 62. Reference numeral 68 denotes a separation part from which a part of the SOI substrate 18 is removed.

  Referring again to FIG. 14, the near-field probe 100 of the present invention is formed from the lower silicon layer 10 of the SOI substrate 18 and has a cantilever arm support 62 having a through hole 34 on one side of the lower silicon layer 10. A cantilever arm 64 supported by the cantilever arm support 62 and corresponding to the through hole 34 is roughly divided. The cantilever arm 64 includes a tip 38 and an aperture 40 corresponding to the through hole 34. The cantilever arm 64 is supported on the upper surface of the lower silicon layer 10 of the SOI substrate 18 that constitutes the cantilever arm support portion 62.

  More specifically, the cantilever arm 64 is supported on the upper surface of the lower silicon layer 10 of the SOI substrate 18 constituting the cantilever arm support portion 62 and has the bonding oxide layer pattern 12 of the SOI substrate 18 having a hole 36 smaller than the through hole 34. On the upper silicon layer pattern 16a, on the upper silicon layer pattern 16a, on the silicon oxide layer pattern 26a including the chip 38 having the aperture 40 at the tip in accordance with the hole 36, on the silicon oxide layer pattern 26a, The light transmission preventing layer 42 is formed without embedding the aperture 40. The tip 38 has a conical shape or a parabolic shape. The reason why the shape of the tip 38 is conical or parabolic is to improve the light transmittance. The light transmission preventing layer 42 is composed of a metal layer.

  Further, the near-field probe 100 of the present invention is configured such that light travels from below to above as indicated by reference numeral 46 and the chip 38 is directed to the upper side, that is, the upper side of the SOI substrate 18. . Thus, when the chip 38 faces the upper side of the SOI substrate 18, it has an advantage that the chip 38 can prevent a collision with a sample to be measured. Further, according to the present invention, the manufacturing process of the chip in which the aperture 40 is formed and the manufacturing process of the cantilever arm 64 including the chip 38 can be easily combined through the manufacturing process described below.

Below, the manufacturing method of the near field probe by this invention is demonstrated.
1 to 14 are cross-sectional views for explaining a manufacturing method of a near-field probe according to the present invention. 1 to 14 are cross-sectional views taken along line AA in FIG. FIGS. 1 to 14 illustrate a method for manufacturing one of the near-field probes 100 formed on the SOI substrate 18 of FIG. 1 to 14 show an example in which only one chip 38 is formed, but a plurality of chips may be formed in one near-field probe.

  First, in FIG. 1 and FIG. 2, a junction oxide layer pattern 12 having a first hole 14 is formed on the lower silicon layer 10. The first hole 14 is formed in advance to form a near-field probe tip in a later process. Next, the first hole 14 is formed by forming a bonding oxide layer to a thickness of 0.5 μm to 2 μm by thermal oxidation deposition on the lower silicon layer 10 having a thickness of 200 μm to 600 μm. It is formed by patterning.

  Next, an upper silicon layer 16 having a thickness of 7 μm to 20 μm is bonded on the first hole 14 and the bonding oxide layer pattern 12. As a result, the SOI substrate 18 is completed by the lower silicon layer 10, the junction oxide layer pattern 12 having the first holes 14, and the upper silicon layer 16. As described above, FIGS. 1 and 2 show a process of forming the necessary first holes 14 in advance in the bonding oxide layer in order to facilitate chip formation in a subsequent process before the SOI substrate 18 is manufactured.

  Next, in FIG. 3, a first silicon nitride layer 20 is formed to a thickness of 200 nm to 300 nm on the upper silicon layer 16 and the lower silicon layer 10 of the SOI substrate 18. That is, the silicon nitride layer 20 is formed on the front and back surfaces of the SOI substrate 18.

  Next, the silicon nitride layer 20 formed on the upper silicon layer 16 of the SOI substrate 18 is patterned by a photo etching process and etched by a dry etching method to form a silicon nitride layer pattern 22. The silicon nitride layer pattern 22 serves as an etching mask layer in a later process. The silicon nitride layer pattern 22 is formed so as to be aligned with the upper portion of the first hole 14 necessary for forming a chip in a later process.

Next, in FIG. 4, the silicon nitride layer pattern 22 is isotropically etched using the etching mask to form the upper silicon layer 16 constituting the SOI substrate 18 to form a conical chip structure 24. The isotropic etching of the upper silicon layer 16 uses a wet etching method using a mixed solution of hydrofluoric acid, nitric acid and acetic acid, or a dry etching method using RIE (Reactive Ion Etch) equipment in an SF ₆ gas atmosphere. Is used. In FIG. 4, when the upper silicon layer 16 constituting the SOI substrate 18 is isotropically etched, an undercut 23 is generated below the silicon nitride layer pattern 22.

  As a result, during isotropic etching, the conical chip structure 24 is formed while adjusting the width W1 of the bonding surface between the silicon nitride layer pattern 22 and the upper silicon layer 16 to be less than a micron (μm). In particular, when the etching time or etching conditions of the upper silicon layer 16 constituting the SOI substrate 18 are adjusted, the chip structure 24 can be freely formed conically or parabolically.

  Next, in FIG. 5, the upper silicon layer 16 of the SOI substrate 18 including the chip structure 24 is oxidized to form a silicon oxide layer 26 having a predetermined thickness of 500 nm to 800 nm. In other words, the silicon oxide layer 26 is formed on the outer surface of the chip structure 24 and the upper silicon layer 16. As a result, the silicon oxide layer 26 is formed in a parabolic shape or a conical shape on the outer surface of the chip structure 24.

  In particular, when forming the silicon oxide layer 26 by oxidizing the upper silicon layer 16 of the SOI substrate 18, the width W2 of the upper silicon layer 16 in contact with the silicon nitride layer pattern 22 is 100 nm or less, preferably 10 nm to 100 nm. To do. The upper silicon layer 16 portion in contact with the silicon nitride layer pattern 22 is a portion to be a hole in which a near-field probe tip will be formed later, and the width is the resolution of the near-field scanning optical microscope or the near-field light information storage device. This greatly affects the storage density.

  Next, in FIG. 6, the silicon nitride layer 20 formed on the back surface of the SOI silicon substrate 18 and the silicon nitride layer pattern 22 formed on the top surface of the SOI silicon substrate 18 are removed by wet etching using a phosphoric acid solution. To do. Next, a cantilever forming mask pattern 28 is formed on the silicon oxide layer 26. The cantilever forming mask pattern 28 is formed into a photoresist pattern using a photographic process. The cantilever forming mask pattern 28 is formed only on the cantilever portion 66 of the SOI substrate 18. The SOI substrate 18 other than the cantilever part 66 becomes a separation part 68.

  Next, in FIG. 7, the silicon oxide layer 26 and the upper silicon layer 16 are etched using the cantilever forming mask pattern 28 to form the silicon oxide layer pattern 26a constituting the cantilever arm 64 and the upper silicon layer pattern 16a. Form. A silicon oxide layer pattern 26 a and an upper silicon layer pattern 16 a are formed on the cantilever arm 64.

  Next, in FIG. 8, after removing the cantilever forming mask pattern 28, the etching mask layer pattern 30 is formed on the back surface of the SOI substrate 18, that is, on the back surface of the lower silicon layer 10. The etching mask layer pattern 30 is formed of a silicon oxide layer pattern. The etching mask layer pattern 30 is formed by forming a silicon oxide layer with a thickness of 2 μm to 4 μm on the back surface of the lower silicon layer 10 that does not correspond to the chip structure 24, and then patterning the silicon oxide layer in a photo etching process. The etching mask layer pattern 30 is formed using a photographic process and an etching process using a double-side exposure apparatus.

  In particular, the portion where the etching mask layer pattern 30 is formed is a portion that becomes the cantilever arm support portion 62 that supports the cantilever arm 64 in a subsequent process. A portion of the cantilever portion 66 excluding the cantilever arm support portion 62 is a portion where the tip 38 and the aperture 40 are formed in the subsequent process to become the cantilever arm 64.

  Next, in FIG. 9, a cantilever arm protection pattern 32 is formed on the silicon oxide layer pattern 26a. The cantilever arm protection pattern 32 is formed by forming a photoresist film (not shown) on the entire surface of the SOI substrate 18 on which the upper silicon layer pattern 16a and the silicon oxide layer pattern 26a are formed, and then patterning.

  Next, in FIG. 10, the lower silicon layer 10 is etched using the etching mask layer pattern 30 and the etching mask to form a through hole 34 exposing the bonding oxide layer pattern 12 constituting the SOI substrate 18. . When the lower silicon layer 10 is etched, only the bonding oxide layer pattern 12 is etched.

  Next, in FIG. 11, the upper silicon layer pattern 16a in the chip structure 24 on the first hole 14 is etched using the bonding oxide layer pattern 12 using an etching mask to form the second hole 36. When the second hole 36 is formed, the upper silicon layer pattern 16 a other than the chip structure 24 is protected by the bonding oxide layer pattern 12. Then, by etching the upper silicon layer pattern 16a in the chip structure 24, a chip 38 having an aperture 40 formed at the tip thereof in a conical or parabolic shape is formed. The aperture 40 is formed so as to protrude above the SOI substrate.

  Next, in FIG. 12, the bonding oxide layer pattern 12 formed in the separation portion 68 is removed. If it becomes like this, only the cantilever part 66 comprised by the cantilever arm support part 62 and the cantilever arm 64 will remain. The cantilever arm 64 is formed with the junction oxide layer pattern 12, the upper silicon layer pattern 16a, and the silicon oxide layer pattern 26a that constitute the cantilever.

  Next, in FIGS. 13 and 14, the cantilever protection pattern 32 is removed. Next, a light transmission preventing layer 42 for preventing light transmission without forming the aperture 40 is formed on the silicon oxide layer pattern 26a. The light transmission preventing layer 42 is formed using a metal such as aluminum (Al) or gold (Au) as a material for preventing light transmission. Thereby, the near-field probe 100 including the cantilever arm 64 supported by the cantilever arm support portion 62 is completed.

  The cantilever arm 64 includes a junction oxide layer pattern 12, an upper silicon layer pattern 16a, a silicon oxide layer pattern 26a having an aperture 40 on the chip 38, and a light transmission preventing layer 42 formed on the silicon oxide layer pattern 26a. Has been. As described above, according to the present invention, a near-field probe can be manufactured by easily combining a manufacturing process of a chip in which an aperture is formed using an SOI substrate and a manufacturing process of a cantilever arm including the chip.

  The present invention relates to a near-field probe using an SOI substrate and a manufacturing method thereof, and is preferably used for a near-field scanning optical microscope and a near-field light information storage device. It is possible to prevent the chip from colliding with the sample to be measured by configuring the chip so as to face the upper side, that is, the upper side of the SOI substrate.

It is sectional drawing (the 1) for demonstrating the near-field probe and its manufacturing method by this invention. It is sectional drawing (the 2) for demonstrating the near-field probe by this invention, and its manufacturing method. It is sectional drawing (the 3) for demonstrating the near-field probe and its manufacturing method by this invention. It is sectional drawing (the 4) for demonstrating the near-field probe by this invention, and its manufacturing method. It is sectional drawing (the 5) for demonstrating the near-field probe by this invention, and its manufacturing method. It is sectional drawing (the 6) for demonstrating the near-field probe and its manufacturing method by this invention. It is sectional drawing (the 7) for demonstrating the near-field probe and its manufacturing method by this invention. It is sectional drawing (the 8) for demonstrating the near-field probe by this invention, and its manufacturing method. It is sectional drawing (the 9) for demonstrating the near-field probe by this invention, and its manufacturing method. It is sectional drawing (the 10) for demonstrating the near-field probe by this invention, and its manufacturing method. It is sectional drawing (the 11) for demonstrating the near-field probe and its manufacturing method by this invention. It is sectional drawing (the 12) for demonstrating the near-field probe by this invention, and its manufacturing method. It is sectional drawing (the 13) for demonstrating the near-field probe and its manufacturing method by this invention. It is sectional drawing (the 14) for demonstrating the near-field probe by this invention, and its manufacturing method. It is a top view of the near field probe by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Lower silicon layer 12 Junction oxide layer pattern 14 1st hole 16 Upper silicon layer 16a Upper silicon layer pattern 18 SOI substrate 20 Silicon nitride layer 22 Silicon nitride layer pattern 23 Undercut 26 Silicon oxide layer 26a Silicon oxide layer pattern 28 For cantilever formation Mask pattern 30 Etching mask layer pattern 32 Cantilever arm protection pattern 34 Through hole 36 Second hole 38 Chip 40 Aperture 42 Light transmission prevention layer 46 Near field probe 62 Cantilever arm support portion 64 Cantilever arm 66 Cantilever portion 68 Separating portion

Claims (10)

A cantilever arm support formed of a lower silicon layer of an SOI substrate and having a through hole on one side of the lower silicon layer;
A bonded oxide layer pattern and an upper silicon layer pattern of an SOI substrate, both of which are supported on the upper surface of the lower silicon layer and have holes smaller than the through-holes, and on the upper end of the upper silicon layer pattern in accordance with the holes. A near-field comprising: a silicon oxide layer pattern including a chip having an aperture; and a cantilever arm formed from a light-transmitting prevention layer formed without embedding the aperture on the silicon oxide layer pattern. Probe.   The near-field probe according to claim 1, wherein the tip has a conical shape or a parabolic shape.   The near-field probe according to claim 1, wherein the aperture protrudes above the SOI substrate. Forming a junction oxide layer pattern having a first hole on the lower silicon layer;
Forming an upper silicon layer on the first hole and the junction oxide layer pattern to complete an SOI substrate;
Forming a chip structure on the upper silicon layer formed on the first hole;
Sequentially forming a silicon oxide layer pattern and an upper silicon layer pattern constituting a cantilever arm on an outer surface and an upper silicon layer of the chip structure;
Forming an etching mask layer pattern on the back surface of the lower silicon layer constituting the cantilever arm support;
Using the etching mask layer pattern as an etching mask, etching the upper silicon layer pattern in the chip structure on the lower silicon layer and the first hole to expose the junction oxide layer pattern; Forming a chip having an aperture at the tip in a second hole smaller than the through hole;
Forming a light transmission preventing layer on the silicon oxide layer pattern without embedding the aperture,
The upper silicon layer pattern and the junction oxide layer pattern, both of which are supported on the upper surface of the lower silicon layer and have a second hole smaller than the through-hole, and a tip having an aperture at the tip in accordance with the second hole And forming the cantilever arm formed from the silicon oxide layer pattern and the light transmission preventing layer. The chip structure is
5. The silicon nitride layer pattern is formed on a portion of the upper silicon layer, and the upper silicon layer is wet-etched using the silicon nitride layer pattern as a mask to form a conical shape or a parabolic shape. The manufacturing method of the near-field probe as described in 2. The silicon oxide layer pattern and the upper silicon layer pattern constituting the cantilever arm are:
Forming by oxidizing the upper silicon layer having the chip structure to form a silicon oxide layer on the outer surface of the chip structure and the upper silicon layer, and patterning the silicon oxide layer and the upper silicon layer The method for manufacturing a near-field probe according to claim 5, wherein:   7. The near field probe according to claim 6, wherein when the upper silicon layer is oxidized, the silicon oxide layer is not formed on an upper end portion of the chip structure and the aperture is formed in a subsequent process. Needle manufacturing method.   7. The method of manufacturing a near-field probe according to claim 6, wherein when the upper silicon layer is oxidized, a width of the upper silicon layer in contact with the silicon nitride layer pattern is adjusted.   5. The method of manufacturing a near-field probe according to claim 4, wherein after forming the etching mask layer pattern, the cantilever arm protection pattern is further formed on the silicon oxide layer pattern. The through hole, the second hole and the chip are formed as follows:
The etching mask layer pattern is etched using the etching mask, the lower silicon layer is etched to form the through hole exposing the bonding oxide layer pattern, and the bonding oxide layer pattern is etched using the etching mask. The method of manufacturing a near-field probe according to claim 9, wherein the method is obtained by etching an upper silicon layer pattern in the chip structure on the first hole.

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