JP4268655B1 - Power-on reset circuit and combination IC card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide reliable and highly reliable in any case for various power supply modes in a combination type IC card having a contact interface operable with a plurality of power supply voltage specifications and a non-contact interface. A power-on reset circuit for outputting a reset signal is provided.
An internal reset signal PRSTB for controlling a reset state of a combination IC card is output at the time of rising of a power supply voltage VCC acquired from an external power supply source by a non-contact interface or a contact interface, and the power supply voltage is a predetermined threshold value. Is a power-on reset circuit that cancels the internal reset signal PRSTB when it is detected that the signal level rises above the threshold level, and the signal level of the input terminal RSTB of the external reset signal directly supplied from the external device when operating in the contact type mode is In the activation level and the deactivation level, the predetermined threshold is set to a lower voltage at the activation level than at the deactivation level.
[Selection] Figure 1

Description

  The present invention obtains power from an external power supply source in a non-contact manner, for example via electromagnetic waves, and converts the power supply voltage into a predetermined voltage to perform a non-contact communication operation; and Non-contact / contact-shared type that has a contact IC card interface that performs contact communication operation by directly acquiring power from an external power supply source via a power supply terminal, etc., and converting the power supply voltage into a predetermined voltage. The present invention relates to a power-on reset circuit used for a combination type IC card or the like.

  In recent years, an IC card in which a semiconductor integrated circuit device is mounted on the card is becoming widespread. The IC card can exchange information between an external reader / writer device and a semiconductor integrated circuit device mounted in the IC card. As a result, it is possible to store necessary information in the nonvolatile memory built in the semiconductor integrated circuit device, or to read information from the nonvolatile memory. Such an IC card can realize various functions performed by a conventional magnetic card.

  This IC card has come to incorporate a non-volatile memory having a larger capacity due to recent advances in semiconductor integrated circuit technology. Therefore, multipurpose IC cards in which a plurality of applications are stored in one IC card are also becoming popular. Such IC cards have a variety of usage conditions for each application. For example, one card can be used for entrance / exit management, attendance / exit management, train and bus tickets, personal computer security and ATM (automatic cash deposit). A combination type (non-contact / contact common type) IC card having both a non-contact type IC card interface and a contact type IC card interface has been developed so as to be compatible with a payment machine).

  One of the characteristics of the combination type IC card is that it has a contact type interface. Since a direct current voltage is directly supplied from an external power supply source through a power supply terminal or the like, the power conduction efficiency is higher than that of a non-contact interface. It is good that the power consumption of the external communication device can be kept relatively low. For example, when communication is performed with a device that operates with relatively low power, such as a small portable device, the use of a contact interface has an effect of suppressing battery consumption.

  On the other hand, one of the features of having a non-contact type interface is that it is possible to configure a system that can be operated easily and perform information exchange processing more quickly than when a contact type interface is used. It is. For example, when using a non-contact type IC card as a ticket for railways, buses, etc., simply hold the non-contact type IC card over the ticket gate (holding process) or touch it momentarily (touch and go process). Ticket gate processing can be performed.

  As described above, in the combination type IC card, various methods can be considered as a form of information exchange between the IC card and the reader / writer device. For example, (1) a method of holding an IC card in a space separated from the non-contact type reader / writer device within a few centimeters (holding process), and (2) a card holder installed in the non-contact type reader / writer device. A method of inserting an IC card (dropping processing), (3) a method of supplying power by turning on a power switch after setting the card in a non-contact type reader / writer device, and (4) a card in the contact type reader / writer device. A method of directly supplying the power supply voltage by turning on the power switch after setting is considered.

  These methods are different from each other in the method of inserting or approaching the IC card into the reader / writer device. Therefore, when power is supplied from the reader / writer device to the IC card, the conditions for generating the power supply voltage in the IC card are also different.

  In addition, when the contact type interface is used, the power supply voltage is directly supplied via the power supply terminal or the like, so that the current capacity of the power supply voltage can be set relatively large by the external reader / writer device. When a non-contact type interface is used, power supply is performed by electromagnetic induction, and the current capacity is limited. Therefore, the stability of the power supply voltage is various. Therefore, in a combination type IC card, a reliable and highly reliable power-on reset operation is required for any of the various power supply modes.

  Hereinafter, an example of what power-on reset circuit is used in a conventional combination IC card will be described. For example, Patent Document 1 below discloses a circuit configuration for performing a power-on reset in a combination IC card.

  In the prior art disclosed in Patent Document 1, as shown in FIG. 5, the first reset circuit 41 that detects the rising of the voltage VCC2V supplied to the logic unit and generates the first reset signal RST1, and the external And a second reset circuit 42 that generates a second reset signal RST2 by detecting the rise of the output voltage REGIN of the rectifier circuit that rectifies the power supply voltage obtained from the power supply source of the power supply source. By outputting the reset signal with the later release timing, it is possible to output a stable power-on reset signal PRST corresponding to the rising timing of various power sources in the non-contact operation. Further, it is possible to output a reset signal based on an external reset signal RSTB input from a contact type interface. As a result, it is possible to provide a power-on reset circuit capable of accurately controlling the reset state of the system regardless of whether power is supplied by a non-contact type or a contact type.

  Here, a resetting method in the contact IC card will be described. In the case of a contact-type IC card, two types of reset methods are defined in ISO / IEC7816-3. One of them is a standard called cold reset. The cold reset is a predetermined voltage level of an RSTB terminal (the last letter B of the terminal name means that the signal is activated when the signal level is low) which is an input terminal for an external reset signal. The whole IC card is shifted to the reset state by raising the power supply voltage in a state where it is fixed at a low level (activation level) during this period. The other is a standard called warm reset, in which only a part of the IC card is shifted to the reset state by setting the RSTB terminal to a low level (activation level) while the power supply voltage is raised. In the contact IC card, it is essential to have the above-mentioned two types of reset. Generally, when a contact type IC card is connected to an ISO compliant contact type reader / writer device, the cold reset is always executed first.

JP 2003-44176 A

  In the case of a combination type IC card, its usage forms are various, and the rising waveform of the voltage supplied from the non-contact type reader / writer device or the contact type reader / writer device differs depending on each use situation. In recent years, the power supply voltage used in the contact type interface has also been diversified. In addition to CLASS-A (VCC = 5V ± 10%) and CLASS-B (VCC = 3V ± 10%), CLASS-C (VCC = 1.8V) The specification of ± 10%) is defined in ISO / IEC7816-3. Therefore, there is a need for a stable and reliable power-on reset circuit at the rise of various power sources at the non-contact interface and at all the various power supply voltages at the contact interface.

  Here, the relationship between the voltage and current in the electric power supplied from the non-contact type reader / writer device and the contact type reader / writer device and the power-on reset voltage appropriate for each in the above-described use situation will be described. .

  Usually, a non-contact type reader / writer emits a certain amount of electromagnetic field using a carrier frequency of about several hundred kHz to several tens of MHz via an antenna coil, and supplies power to the IC card. The power received by the IC card varies depending on the distance of the reader / writer from the antenna, the degree of antenna coupling, and the like. For example, when a non-contact type IC card with a power consumption of 9 mW is gradually brought closer to the non-contact type reader / writer device, the IC card operates when it is brought close to a position where the received power of the IC card is 9 mW or more. In this case, assuming that there is no power loss in the IC card and all the power of 9mW is supplied, the current consumption is 1.8mA when the power supply voltage inside the IC card is 5V, and up to 5mA when it is 1.8V. can do. In other words, when the IC card consumes 1.8 mA, the power supply voltage inside the IC card is 5V, but when it consumes 5 mA, the power supply voltage drops to 1.8V.

  A CPU and a memory circuit built in an IC card usually do not always operate with a constant current consumption. The current consumption varies depending on the operation sequence and processing contents. For this reason, when the IC card is operating while receiving a certain amount of power, as described above, fluctuations in the current consumption cause fluctuations in the power supply voltage, which in turn causes electromagnetic noise. When electromagnetic noise occurs, it causes a reduction in communication quality, such as a reduction in the SN ratio when communicating with the reader / writer device. As a countermeasure against this, it is common to use a power clamp circuit such as a shunt regulator. However, these circuits usually use high voltage transistors, and stable operation may be difficult at 2 V or less. is there.

  One of the communication systems defined in ISO / IEC14443 is a 10% amplitude modulation system (Type-B). In this communication method, the received voltage and the amplitude of the communication signal are in a proportional relationship, and therefore the communication signal has a characteristic that the amplitude of the communication signal is reduced as the received voltage is lowered. Therefore, even when the IC card receives a communication signal, if the amplitude of the communication signal decreases, the SN ratio decreases and reception becomes difficult. Therefore, in order to ensure communication quality, the power supply voltage should be set to 2 V or higher. It is necessary to keep.

  From the above, when used in the non-contact mode, it is necessary to set the power-on reset setting voltage to 2 V or higher.

  On the other hand, when an IC card is connected to a contact-type reader / writer device, the power supply voltage is directly applied to the IC card via a power supply terminal or the like, so that the IC card has an allowable current value (usually several tens of mA) of the reader / writer device. Can be consumed. In this case, even if the consumption current of the IC card fluctuates, the power supply voltage is constant within the allowable current value range of the reader / writer device. In such a usage pattern, the power-on reset voltage needs to be set to a lower limit voltage or less according to the specification. For example, when CLASS-A is mounted, the power-on reset setting voltage needs to be set to 4.5 V or less. When CLASS-B is mounted, the power-on reset setting voltage is 2.7 V. It is necessary to set the following, and when CLASS-C is mounted, it is necessary to set the power-on reset setting voltage to 1.62 V or less.

  Therefore, since the appropriate reset voltage is different between the non-contact interface and the contact interface, the power-on reset setting voltage in the contact / non-contact mode is different from the conventional power-on reset circuit. If it is common, the reset setting voltage can be set only to 2 V or more, being constrained by the setting voltage at the time of non-contact. That is, although a combination card having CLASS-A, CLASS-B, and a contactless interface can be realized, there is a problem that CLASS-A, CLASS-B, CLASS-C, and a contactless interface cannot be provided. It was.

  The present invention has been made in view of the above problems, and an object thereof is to include a contact interface operable at all power supply voltages (CLASS-A, CLASS-B, CLASS-C) and a non-contact interface. A power-on reset circuit that outputs a reliable and reliable reset signal in any case for various power supply forms, and an IC card equipped with the power-on reset circuit. The point is to provide.

  In order to achieve the above object, a power-on reset circuit according to the present invention includes a non-contact interface of a combination type IC card or a reset state of the combination type IC card when a power supply voltage acquired from an external power supply source is acquired by the contact interface. Is a power-on reset circuit that outputs an internal reset signal that controls the power supply voltage and that releases the internal reset signal when it is detected that the power supply voltage has risen above a predetermined threshold value. In the case of functioning as an IC card, when the signal level of the external reset signal terminal, which is the input terminal of the external reset signal directly supplied from the external device, is the activation level and the deactivation level, the activation level is inactive. The first feature is that the predetermined threshold is set to a lower voltage than at the time of activation. That.

  Here, the external reset signal terminal used in the power-on reset circuit of the first feature corresponds to the RSTB terminal mentioned in the description of the resetting method in the contact IC card (see the description of the background art). , ISO / IEC7816-3 can be used for cold reset and warm reset. When the combination type IC card is a non-contact type IC card and acquires a power supply voltage from an external power supply source by electromagnetic induction in a non-contact manner, an external reset signal terminal (hereinafter referred to as “RSTB terminal” as appropriate). In order to avoid an open state (indefinite state) in which an external reset signal is not input from an external device, a pull-up state (high level of inactivation level) is entered in a transient state in which the power supply voltage is excited. ing. However, when a combination IC card is connected to a contact reader / writer device conforming to the ISO standard, the RSTB terminal is always fixed to a low level (activation level) by the reader / writer device when the power supply voltage is raised. A cold reset is always executed. Therefore, when the RSTB terminal is at a high level, it can be determined that the power is supplied in a non-contact state or in a contact mode that does not comply with the ISO standard, and when the RSTB terminal is at a low level. It can be determined that the power is supplied in the contact mode in conformity with the ISO standard.

  Therefore, according to the power-on reset circuit having the first feature, when the signal level of the RSTB terminal is low (activation level) and high (deactivation level), the low level is higher. Further, since the threshold of the power supply voltage level for canceling the internal reset signal is set to a low voltage, when the signal level of the RSTB terminal is low, the threshold is set to 1.62 V or less, so that CLASS-A in the ISO standard is set. , CLASS-B and CLASS-C can be reset with all the power supply voltages, and the reset operation can be reliably canceled. On the other hand, when the signal level of the RSTB terminal is high, it is in a non-contact power supply state or in a contact mode non-compliant with the ISO standard, so at least a reset procedure conforming to the ISO standard. Therefore, the reset operation in the non-contact mode can be stabilized by setting the threshold value to 2 V or higher.

  That is, according to the power-on reset circuit of the first feature, the signal level of the RSTB terminal is monitored, and the threshold value of the power supply voltage level for canceling the internal reset signal is lower at the low level than at the high level. By switching to a low voltage, it is possible to realize a power-on reset circuit that outputs a reliable and highly reliable reset signal in any power supply form, regardless of the power supply form.

  In addition to the first feature, the power-on reset circuit according to the present invention further includes a resistance voltage dividing circuit that generates a second power supply voltage by dividing the power supply voltage by a voltage dividing resistor to reduce the voltage, A comparison circuit that compares a reference voltage of a constant voltage used in a regulator circuit that converts the power supply voltage into a predetermined voltage in a combination IC card and the second power supply voltage, and a voltage dividing ratio by the voltage dividing resistor is A second feature is that the external reset signal terminal can be switched according to the signal level.

  According to the power-on reset circuit of the second feature, the internal reset signal is switched by switching the voltage dividing ratio by the voltage dividing resistor according to the signal level of the external reset signal terminal and, as a result, switching the voltage level of the second power supply voltage. It is possible to substantially switch the setting of the threshold value of the power supply voltage level to be released, and the power-on reset circuit having the first feature is used by using a constant voltage reference voltage used in the regulator circuit in the combination type IC card. Can be realized concretely.

  In the power-on reset circuit according to the present invention, in addition to the first feature, when the signal level of the external reset signal terminal is an inactive level, the predetermined reset signal is released when the internal reset signal is released. A third feature is that the set value of the threshold value decreases.

  In addition to the second feature, the power-on reset circuit according to the present invention further has a voltage dividing ratio of the voltage dividing resistor when the signal level of the external reset signal terminal is an inactive level. A fourth feature is that the setting value of the predetermined threshold is lowered when the internal reset signal is canceled by switching according to the output level.

  According to the power-on reset circuit of the third or fourth feature, when the signal level of the external reset signal terminal is at an inactive level, that is, at least in a state where power is supplied in a contact mode compliant with the ISO standard, Since the power supply voltage is likely to become unstable, it has hysteresis characteristics against fluctuations in the power supply voltage acquired from an external power supply source via a non-contact or contact interface, so the power supply voltage is the threshold value. Since the threshold value can be reset again immediately after rising beyond the threshold value, the release of the internal reset signal can be stabilized.

  On the other hand, when the signal level of the external reset signal terminal is at the activation level, the power supply voltage rises in the contact mode in conformity with the ISO standard. The threshold setting can be fixed to 1.62 V or less before and after detecting the rise, and even when the power supply voltage rises with CLASS-C, the reset by the internal reset signal can be reliably canceled. it can.

  In addition to the third feature, the power-on reset circuit according to the present invention further includes a contact mode and a non-contact mode in which the set value after the predetermined threshold is lowered after the internal reset signal is released. A fifth feature is that the mode can be switched by a mode discrimination signal for discriminating between.

  In the power-on reset circuit according to the present invention, in addition to the fourth feature, when the signal level of the external reset signal terminal is an inactive level, the voltage dividing ratio by the voltage dividing resistor is not different from the contact mode. By switching according to a mode determination signal for determining the contact mode, the set value after the predetermined threshold is lowered after the internal reset signal is released is switched by a mode determination signal for determining the contact mode and the non-contact mode. The sixth feature is that the configuration is possible.

  According to the power-on reset circuit of the fifth or sixth feature, when the signal level of the external reset signal terminal is at an inactive level, that is, at least in a state where power is supplied in a contact mode in conformity with the ISO standard, Furthermore, according to the signal level of the mode discrimination signal output from the means for discriminating between the contact mode and the non-contact mode, the hysteresis characteristic is distinguished between the case where the power supply voltage rises in the non-contact state and the case where the power supply voltage rises in the contact state. Can be switched. As a result, when the power supply voltage rises in a non-contact state, the IC card is activated with a voltage at which the non-contact communication operates sufficiently stably by setting the upper limit voltage of the threshold value in the hysteresis characteristic to 3 V or more. be able to. Thereafter, in a state in which the internal reset signal is released, the mode discrimination signal output from the means for discriminating between the contact mode and the non-contact mode is monitored. By switching the voltage dividing ratio by resistance, the lower limit voltage of the threshold value in the hysteresis characteristic can be set to 2 V or more and less than 3 V. As a result, even when operating in the non-contact mode where the power supply voltage is unstable, even if the power supply voltage fluctuates due to the consumption current of the IC card, the internal reset signal is erroneously output and the reset state is entered. Therefore, stable operation can be maintained. Furthermore, when the power supply voltage drops to 2 V or less where the operation of the high-breakdown-voltage transistor circuit becomes unstable, it is possible to surely shift to the reset state before malfunctioning.

  A combination type IC card according to the present invention includes any one of the above-described power-on reset circuits.

  According to the combination type IC card having the above characteristics, a combination type IC card capable of stable and reliable power-on reset at all the rises of various power supply voltages in the non-contact interface and all the various power supply voltages in the contact interface is realized. It becomes possible.

  Next, a power-on reset circuit according to the present invention (hereinafter appropriately referred to as “the present invention circuit”) and a combination IC card using the same will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a circuit configuration of a circuit of the present invention according to the first embodiment. The circuit of the present invention is a combination IC card at the time of rising of the power supply voltage VCC acquired from an external power supply source (not shown) by a contactless interface (not shown) or contact interface (not shown) of the combination IC card. An internal reset signal PRSTB (power-on reset signal) for controlling the reset state of the power supply, and a power-on reset circuit that cancels the internal reset signal PRSTB when detecting that the power supply voltage VCC has risen beyond a predetermined threshold Vt The resistance voltage dividing circuit 1 that generates the second power supply voltage VCC2 by dividing the power supply voltage VCC by the voltage dividing resistors R1, R2, and R3, and the power supply voltage VCC in the combination IC card. Constant voltage reference voltage VREF and second power source used in a regulator circuit (not shown) for converting the voltage The voltage dividing ratio relating to the generation of the second power supply voltage VCC2 by the comparison circuit 2 that compares the voltage VCC2 and the voltage dividing resistors R1, R2, and R3 of the resistance voltage dividing circuit 1 is the signal level of the external reset signal terminal RSTB (hereinafter, simply referred to as “reset voltage”). The voltage dividing ratio switching circuit 3 is switched based on “RSTB level” and a 2-input AND circuit 4 that generates a system reset signal SRSTB for resetting the combination IC card. The power supply voltage VCC is supplied to the regulator circuit, and the regulator circuit converts the power supply voltage VCC into a predetermined internal power supply voltage supplied by a circuit (logic circuit, nonvolatile memory, etc.) in the combination IC card. Further, in the following description, the signal levels “low level” and “high level” will be described as corresponding to the logical values “0” and “1” in positive logic, respectively.

  The resistance voltage dividing circuit 1 is composed of a series circuit of three voltage dividing resistors R1, R2, and R3. One end of the voltage dividing resistor R1 is connected to the power supply voltage VCC, and the other end of the voltage dividing resistor R1 is the voltage dividing resistor R2. One end is connected to the non-inverting input of the comparison circuit 2, the other end of the voltage dividing resistor R2 is connected to one end of the voltage dividing resistor R3, and the other end of the voltage dividing resistor R3 is connected to the ground voltage. Here, the second power supply voltage VCC2 is output from the connection point of the voltage dividing resistors R1 and R2 to the non-inverting input of the comparison circuit 2. In the first embodiment, the voltage dividing ratio for generating the second power supply voltage VCC2 is switched between the case where two voltage dividing resistors R1, R2 are used and the case where three voltage dividing resistors R1, R2, R3 are used. become.

  The comparison circuit 2 compares the second power supply voltage VCC2 input to the non-inverting input and the reference voltage VREF input to the inverting input, and if the second power supply voltage VCC2 is greater than the reference voltage VREF, the internal reset signal PRSTB On the contrary, when the second power supply voltage VCC2 is lower than the reference voltage VREF, the signal level of the internal reset signal PRSTB is set to a low level. The internal reset signal PRSTB is in an activated state (reset state) at a low level, and in an inactivated state (reset release state) at a high level.

  The voltage dividing ratio switching circuit 3 includes an inverter 5 whose input is connected to the external reset signal terminal RSTB, a 2-input NOR circuit 6 that outputs the output of the inverter 5 and the internal reset signal PRSTB, and outputs a negative logical sum of the inputs, The drain is connected to the connection point of the voltage dividing resistors R 2 and R 3, the source is connected to the ground voltage, and the gate is connected to the output of the 2-input NOR circuit 6.

  The 2-input AND circuit 4 inputs the signal of the external reset signal terminal RSTB and the internal reset signal PRSTB, and outputs the logical product as the system reset signal SRSTB. Therefore, the system reset signal SRSTB can be forcibly reset by the external reset signal terminal RSTB.

  Next, the circuit operation of the circuit of the present invention according to the first embodiment will be described in detail.

  First, when the RSTB level is low, the gate level of the NMOS transistor 7 is forcibly fixed to the low level by the inverter 5 and the NOR circuit 6 regardless of the signal level of the internal reset signal PRSTB, and the NMOS transistor 7 is in the OFF state. It becomes. Accordingly, a direct current path is formed from the power supply voltage VCC to the ground voltage via the three voltage dividing resistors R1, R2, and R3. The power supply voltage VCC is a combination of the voltage dividing resistor R1 and the voltage dividing resistors R2 and R3. Since the voltage is divided by the resistor, the second power supply voltage VCC2 input to the comparison circuit 2 is given by the following equation (1). (R2 + R3) / (R1 + R2 + R3) on the right side of Equation 1 corresponds to the voltage division ratio when the RSTB level is low.

[Equation 1]
VCC2 = VCC × (R2 + R3) / (R1 + R2 + R3)

  Next, when the RSTB level is high, the signal level of the internal reset signal PRSTB output from the comparison circuit 2 is low as will be described later when the power supply voltage VCC is equal to or lower than the predetermined threshold value Vt. The two inputs of the NOR circuit 6 are both low, the gate level of the NMOS transistor 7 is high, and the NMOS transistor 7 is turned on. Accordingly, a direct current path that flows from the power supply voltage VCC to the ground voltage via the two voltage dividing resistors R1 and R2 and the NMOS transistor 7 is formed, and the on-resistance of the NMOS transistor 7 is larger than the resistance value of the voltage dividing resistor R3. When the resistance is sufficiently low, the power supply voltage VCC is divided by the voltage dividing resistor R1 and the voltage dividing resistor R2, and therefore the second power supply voltage VCC2 input to the comparison circuit 2 is given by the following equation (2). . R2 / (R1 + R2) on the right side of Equation 2 corresponds to a voltage division ratio when the RSTB level is high and the power supply voltage VCC is equal to or lower than a predetermined threshold Vt (before power-on reset is released).

[Equation 2]
VCC2 = VCC × R2 / (R1 + R2)

  In Equations 1 and 2, if the power supply voltage VCC satisfying VCC2 = VREF is VCCL and VCCH, respectively, the voltages VCCL and VCCH are given by Equations 3 and 4 below.

[Equation 3]
VCCL = VREF × (R1 + R2 + R3) / (R2 + R3)
[Equation 4]
VCCH = VREF × (R1 + R2) / R2

  Here, the voltage VCCL and the voltage VCCH correspond to predetermined threshold values Vt when the RSTB level is a low level and a high level, respectively. In Equations 3 and 4, the magnitude relationship between the reciprocal of the voltage division ratio {(R1 + R2 + R3) / (R2 + R3)} and the reciprocal of the voltage division ratio {(R1 + R2) / R2} is always expressed by the latter as shown in Equation 5 below. Since it is larger, VCCH> VCCL.

[Equation 5]
(R1 + R2 + R3) / (R2 + R3) <(R1 + R2) / R2

  For example, when the reference voltage VREF is 1 V and the resistance ratio R1: R2: R3 of the three voltage dividing resistors R1, R2, and R3 is set to 2: 1: 1, the voltage VCCL and the voltage VCCH are expressed by the following Equation 6 And as shown in Equation 7.

[Equation 6]
VCCL = 1V × 4/2 = 2V
[Equation 7]
VCCH = 1V × 3/1 = 3V

  Next, when the power supply voltage VCC rises above VCCL when the RSTB level is low and exceeds VCCH when the RSTB level is high, the second voltage given by Equation 3 or Equation 4 is given. Since the power supply voltage VCC2 becomes larger than the reference voltage VREF, the internal reset signal PRSTB transits from the low level to the high level, and the reset state (power-on reset) is released.

  When the RSTB level is high, the signal level of the internal reset signal PRSTB output from the comparison circuit 2 becomes high when the power supply voltage VCC exceeds a predetermined threshold value Vt (= VCCH). 6, the gate level of the NMOS transistor 7 changes to a low level, and the NMOS transistor 7 is turned off. Accordingly, a direct current path is formed from the power supply voltage VCC to the ground voltage via the three voltage dividing resistors R1, R2, and R3. The power supply voltage VCC is a combination of the voltage dividing resistor R1 and the voltage dividing resistors R2 and R3. Since the voltage is divided by the resistor, the second power supply voltage VCC2 input to the comparison circuit 2 is given by the same equation 1 as when the RSTB level is low. That is, the predetermined threshold value Vt decreases from VCCH to VCCL, and has a hysteresis characteristic with respect to a change in the power supply voltage VCC. Therefore, even if a fluctuation slightly lower than VCCH occurs after the power supply voltage VCC rises above VCCH, the signal level of the internal reset signal PRSTB that has been released immediately returns to a low level and falls into a reset state carelessly. It is avoided. However, when the power supply voltage VCC drops below VCCL, the signal level of the internal reset signal PRSTB normally returns to the low level and enters the reset state.

  Therefore, the voltage VCCL corresponds to the predetermined threshold value Vt after the RSTB level is low or the RSTB level is high and the power-on reset is canceled, and the voltage VCCH is the power-on when the RSTB level is high. This corresponds to a predetermined threshold value Vt before reset release.

  From the above, at the rising of the power supply voltage VCC until it rises above the predetermined threshold Vt, VCCH> VCCL. Therefore, when the RSTB level is low, the voltage is lower than when the RSTB level is high. Thus, the internal reset signal PRSTB transits to a high level, and the power-on reset is released.

Second Embodiment
FIG. 2 is a circuit diagram showing a circuit configuration of the circuit of the present invention according to the second embodiment. As in the first embodiment, the circuit of the present invention is a power supply voltage acquired from an external power supply source (not shown) by a non-contact interface (not shown) or a contact interface (not shown) of the combination IC card. A power-on reset that outputs an internal reset signal PRSTB that controls the reset state of the combination IC card at the rise of VCC, and cancels the internal reset signal PRSTB when it is detected that the power supply voltage VCC has risen beyond a predetermined threshold Vt The circuit includes a resistance voltage dividing circuit 11, a comparison circuit 2, a voltage dividing ratio switching circuit 13, and a 2-input AND circuit 4. Since the comparison circuit 2 and the two-input AND circuit 4 are the same as those in the first embodiment, a duplicate description is omitted. The circuit configurations of the resistance voltage dividing circuit 11 and the voltage dividing ratio switching circuit 13 are different from those of the first embodiment.

  In the second embodiment, a contact / non-contact mode determination circuit 14 provided separately from the circuit of the present invention is separately required. The contact / non-contact mode determination circuit 14 is a circuit that determines whether the combination IC card is operating in a contact mode or a non-contact mode, and outputs the determination result as a mode determination signal MODE. The mode discrimination signal MODE indicates that the low level is the contact mode, and the high level indicates the non-contact mode. In the second embodiment, the specific circuit configuration of the contact / non-contact mode discriminating circuit 14 is not questioned, and it can be discriminated whether the combination type IC card is operating in the contact mode or the non-contact mode. Any circuit configuration may be used.

  The resistance voltage dividing circuit 11 is composed of a series circuit of four voltage dividing resistors R1, R2, R3, and R4, and a second voltage obtained by dividing the power supply voltage VCC by the voltage dividing resistors R1, R2, R3, and R4 to lower the voltage. This is a circuit for generating the power supply voltage VCC2. One end of the voltage dividing resistor R1 is connected to the power supply voltage VCC, the other end of the voltage dividing resistor R1 is connected to one end of the voltage dividing resistor R2 and the non-inverting input of the comparison circuit 2, and the other end of the voltage dividing resistor R2 is divided. The resistor R3 is connected to one end, the other end of the voltage dividing resistor R3 is connected to one end of the voltage dividing resistor R4, and the other end of the voltage dividing resistor R4 is connected to the ground voltage. Here, the second power supply voltage VCC2 is output from the connection point of the voltage dividing resistors R1 and R2 to the non-inverting input of the comparison circuit 2. In the second embodiment, the voltage dividing ratio relating to the generation of the second power supply voltage VCC2 is the case where two voltage dividing resistors R1, R2 are used, the case where three voltage dividing resistors R1, R2, R3 are used, and the case where 4 is used. The voltage divider resistors R1, R2, R3, and R4 are switched when used.

  The voltage division ratio switching circuit 13 includes two circuit units, and the first circuit unit is the same as the voltage division ratio switching circuit of the first embodiment. In other words, the first circuit section includes an inverter 5 whose input is connected to the external reset signal terminal RSTB, and a 2-input NOR circuit 6 that receives the output of the inverter 5 and the internal reset signal PRSTB as inputs, and outputs a negative logical sum of the inputs. And an NMOS transistor 7 having a drain connected to the connection point of the voltage dividing resistors R2 and R3, a source connected to the ground voltage, and a gate connected to the output of the two-input NOR circuit 6. The second circuit unit is a circuit unit newly added in the second embodiment, and the inverter 15 whose input is the internal reset signal PRSTB, the output of the inverter 15 and the mode discrimination signal MODE are respectively input, and each input is negated. A two-input NOR circuit 16 that outputs a logical sum; a two-input NOR circuit 17 that outputs a negative logical sum of each input by using the output of the inverter 5 and the output of the two-input NOR circuit 16 of the first circuit unit as inputs; and The drain is connected to the connection point of the voltage dividing resistors R 3 and R 4, the source is connected to the ground voltage, and the gate is connected to the output of the 2-input NOR circuit 17.

  Next, the circuit operation of the circuit of the present invention according to the second embodiment will be described in detail.

  First, when the RSTB level is low, the gate levels of the NMOS transistors 7 and 18 are forcibly fixed to a low level by the inverter 5, the NOR circuit 6 and the NOR circuit 17, regardless of the signal level of the internal reset signal PRSTB. The NMOS transistors 7 and 18 are turned off. Accordingly, a direct current path that flows from the power supply voltage VCC to the ground voltage via the four voltage dividing resistors R1, R2, R3, and R4 is formed, and the power supply voltage VCC is divided into the voltage dividing resistor R1 and the voltage dividing resistors R2, R3. Therefore, the second power supply voltage VCC2 input to the comparison circuit 2 is given by the following equation (8). (R2 + R3 + R4) / (R1 + R2 + R3 + R4) on the right side of Equation 8 corresponds to the voltage division ratio when the RSTB level is low.

[Equation 8]
VCC2 = VCC × (R2 + R3 + R4) / (R1 + R2 + R3 + R4)

  Next, when the RSTB level is high, the signal level of the internal reset signal PRSTB output from the comparison circuit 2 is low when the power supply voltage VCC is equal to or lower than the predetermined threshold Vt. The two inputs are both low, the gate level of the NMOS transistor 7 is high, and the NMOS transistor 7 is turned on. If the signal level of the internal reset signal PRSTB is low, the output of the inverter 15 is high, so that the output of the NOR circuit 16 becomes low regardless of the signal level of the mode determination signal MODE, and the NOR circuit The two inputs 17 are both low, the gate level of the NMOS transistor 18 is high, and the NMOS transistor 18 is turned on. Accordingly, a direct current path that flows from the power supply voltage VCC to the ground voltage via the two voltage dividing resistors R1 and R2 and the NMOS transistor 7 is formed, and the on-resistance of the NMOS transistor 7 is larger than the resistance value of the voltage dividing resistor R3. When the resistance is sufficiently low, the power supply voltage VCC is divided by the voltage dividing resistor R1 and the voltage dividing resistor R2, and therefore the second power supply voltage VCC2 input to the comparison circuit 2 is given by the following equation (9). . R2 / (R1 + R2) on the right side of Equation 9 corresponds to a voltage division ratio when the RSTB level is high and the power supply voltage VCC is equal to or lower than a predetermined threshold Vt (before power-on reset is released). Note that Equation 9 is the same as Equation 2 in the first embodiment.

[Equation 9]
VCC2 = VCC × R2 / (R1 + R2)

  Subsequently, when the RSTB level is high, the signal level of the internal reset signal PRSTB output from the comparison circuit 2 becomes high when the power supply voltage VCC rises beyond a predetermined threshold value Vt, and therefore the NOR circuit 6, the gate level of the NMOS transistor 7 changes to a low level, and the NMOS transistor 7 is turned off. In addition, the power-on reset is canceled, and the contact / non-contact mode determination circuit 14 determines whether the combination IC card is operating in the contact mode or the non-contact mode, and operates in the non-contact mode. If so, the mode discrimination signal MODE is at a high level. In this case, the output of the NOR circuit 16 becomes low level, and the gate level of the NMOS transistor 18 connected to the output of the NOR circuit 17 becomes high level, so that the NMOS transistor 18 is turned on. Therefore, a direct current path that flows from the power supply voltage VCC to the ground voltage through the three voltage dividing resistors R1, R2, and R3 and the NMOS transistor 18 is formed, and the NMOS transistor 18 is turned on compared to the resistance value of the voltage dividing resistor R4. When the resistance is sufficiently low, the power supply voltage VCC is divided by the combined resistance of the voltage dividing resistor R1 and the voltage dividing resistors R2 and R3. Therefore, the second power supply voltage VCC2 input to the comparison circuit 2 is It is given by the following formula 10. (R2 + R3) / (R1 + R2 + R3) on the right side of Equation 10 corresponds to the voltage division ratio when the RSTB level is high, the power supply voltage VCC exceeds a predetermined threshold value Vt, and the operation is performed in the non-contact mode.

[Equation 10]
VCC2 = VCC × (R2 + R3) / (R1 + R2 + R3)

  Further, the power-on reset is canceled, and the contact / non-contact mode determination circuit 14 determines whether the combination IC card is operating in the contact mode or the non-contact mode, and operates in the contact mode. In this case, the mode determination signal MODE is at a low level. In this case, the output of the NOR circuit 16 becomes a high level, and the gate level of the NMOS transistor 18 connected to the output of the NOR circuit 18 becomes a low level, so that the NMOS transistor 18 is turned off. Accordingly, as in the case where the RSTB level is low, a direct current path is formed from the power supply voltage VCC to the ground voltage via the four voltage dividing resistors R1, R2, R3, and R4. Since the voltage is divided by the combined resistance of the voltage resistor R1 and the voltage dividing resistors R2, R3, and R4, the second power supply voltage VCC2 input to the comparison circuit 2 is given by the above equation (8).

  In Equations 8 to 10, assuming that the power supply voltage VCC satisfying VCC2 = VREF is VCCLL, VCCH, and VCCL, the voltages VCCLL, VCCH, and VCCL are respectively given by Equations 11 to 13 below.

[Equation 11]
VCCLL = VREF × (R1 + R2 + R3 + R4) / (R2 + R3 + R4)
[Equation 12]
VCCH = VREF × (R1 + R2) / R2
[Equation 13]
VCCL = VREF × (R1 + R2 + R3) / (R2 + R3)

  Here, the voltage VCCLL corresponds to a predetermined threshold Vt when the RSTB level is low, and a predetermined threshold Vt when the RSTB level is high and the operation is performed in the contact mode after the power-on reset is released. The voltage VCCH corresponds to a predetermined threshold value Vt before the power-on reset is canceled when the RSTB level is high. VCCL corresponds to a predetermined threshold Vt when the RSTB level is high and the operation is performed in the non-contact mode after the power-on reset is canceled.

  In Equations 11 to 13, the reciprocal of the voltage division ratio {(R1 + R2 + R3 + R4) / (R2 + R3 + R4)}, the reciprocal of the voltage division ratio {(R1 + R2) / R2}, and the reciprocal of the voltage division ratio {(R1 + R2 + R3) / (R2 + R3)} Since the magnitude relationship shown in Equation 14 is obtained, the magnitude relationship among the three threshold values Vt (VCCLL, VCCH, and VCCL) is as shown in Equation 15.

[Formula 14]
RLL <RL <RH
However,
RLL = (R1 + R2 + R3 + R4) / (R2 + R3 + R4)
RH = (R1 + R2 + R3) / (R2 + R3)
RL = (R1 + R2) / R2

[Equation 15]
VCCLL <VCCL <VCCH

  For example, when the reference voltage VREF is 1 V and the resistance ratio R1: R2: R3: R4 of the four voltage dividing resistors R1, R2, R3, and R4 is set to 2: 1: 1: 2, the voltage VCCLL and the voltage VCCL The voltage VCCH is as shown in the following equations 16 to 18.

[Equation 16]
VCCLL = 1V × 6/4 = 1.5V
[Equation 17]
VCCL = 1V × 4/2 = 2V
[Equation 18]
VCCH = 1V × 3/1 = 3V

  FIG. 3 is a diagram schematically showing the relationship between the voltage level of power supply voltage VCC and the signal level of internal reset signal PRSTB when power supply voltage VCC rises (or falls).

  The internal reset signal PRSTB in the upper part of FIG. 3 shows the transition of the signal level of the internal reset signal PRSTB when the RSTB level is low. When the power supply voltage VCC rises above the threshold VCCLL, the internal reset signal PRSTB rises from the low level to the high level. When the power supply voltage VCC drops below the threshold value VCCLL, the transition is made from the high level to the low level and the reset state is entered again.

  The lower internal reset signal PRSTB in FIG. 3 shows the transition of the signal level of the internal reset signal PRSTB when the RSTB level is high and the operation after canceling the power-on reset is the non-contact mode. When the voltage rises above the threshold value VCCH, the reset state is canceled by transitioning from the low level to the high level. Conversely, when the power supply voltage VCC falls below the threshold value VCCL, the transition is made from the high level to the low level and the reset state is resumed. Become.

  As shown in Equation 15, the predetermined threshold value Vt has a relationship of VCCLL <VCCL <VCCH. Therefore, when the RSTB level is low, the internal reset signal PRSTB transitions to a high level with a voltage lower than that at the high level. The reset state is released.

  According to the configuration described above, the RSTB level is always low when connected to a contact-type reader / writer device that conforms to the ISO standard, so the threshold voltage Vt (VCCLL) is set to 1.62 V or less. By doing so, the reset operation can be performed with all power supply voltages of CLASS-A, CLASS-B, and CLASS-C in the ISO standard.

  Moreover, the power-on reset operation in the non-contact mode can be stabilized by setting the voltage VCCH and the voltage VCCL to voltages suitable for the non-contact mode operation.

  Therefore, according to the present invention, an interface of a non-contact type IC card that acquires power from an external power supply source in a non-contact manner via electromagnetic waves or the like, and a power from an external power supply source directly through a power supply terminal or the like. In combination type IC card that has the interface of the contact type IC card to be acquired, it provides a stable and reliable power-on reset circuit for all the rises of various power supply voltages in the non-contact interface and all the various power supply voltages in the contact interface. can do.

<Third Embodiment>
Next, a combination type IC card (hereinafter referred to as “the device of the present invention”) provided with the circuit of the present invention described in the first and second embodiments will be described with reference to the drawings.

  FIG. 4 is a schematic block diagram showing a circuit configuration example of the device of the present invention. As shown in FIG. 4, the device of the present invention includes an RF (Radio Frequency) unit 20 that performs communication using electromagnetic waves, a logic unit 21 that includes a plurality of logic circuits that perform various logical operations, a nonvolatile memory unit 28, and voltage control. The circuit unit 29 and the like are provided. The logic unit 21 includes a CPU (Central Processing Unit) 22 for data processing, a security processor 23 for high-speed encryption processing, a work RAM (Random Access Memory) 24 as a work area in arithmetic processing, and a boot ROM used at startup (ReadOnly Memory) 25, a protocol control circuit 26, a reset circuit 27, a bus control circuit 30, a selector circuit 31, a clock generation circuit 32, and the like are provided.

  The RF unit 20 includes an antenna coil 33 that activates electromagnetic induction, a connection terminal of the antenna coil 33, a Schottky diode, and the like, a modulation circuit 35, a demodulation circuit 36, a clock extraction circuit 37, and The power-on reset circuit 19 comprising the circuit of the present invention according to the first embodiment or the second embodiment is provided. When the power-on reset circuit 19 includes the circuit of the present invention according to the second embodiment, the contact / non-contact mode determination circuit 14 shown in FIG. 2 is provided as shown in FIG. When the power-on reset circuit 19 includes the circuit of the present invention of the first embodiment, the contact / non-contact mode determination circuit 14 can be omitted because it is not necessary for at least the operation of the power-on reset circuit 19. The device according to the present invention is characterized in that a power-on reset circuit 19 is provided.

  Next, an outline of the operation of the device of the present invention in the configuration shown in FIG. 4 will be briefly described. In the case of the operation in the non-contact mode, the electric power generated by the electromagnetic induction is rectified by the rectifier circuit 34. In the case of operation in the contact mode, the power supply voltage VCC is directly supplied from the power supply terminal. The power supply voltage VCC that has been full-wave rectified by the rectifier circuit 34 or directly supplied from the power supply voltage terminal is input to a voltage control circuit unit 29 (corresponding to a regulator circuit). Optimal voltages (for example, VDD supplied to the logic unit 21 and the nonvolatile memory unit 28 in common, VPP supplied to the nonvolatile memory unit 28) are generated and supplied to each block. In the voltage control circuit unit 29, the reference voltage VREF used to generate the voltages (VDD, VPP) supplied to each block is used in the power-on reset circuit 19. In the case of the operation in the non-contact mode, the carrier waveform from the rectifier circuit 34 is extracted by the clock extraction circuit 37, and a clock signal is generated.

  Further, data communication is performed by amplitude modulation by the modulation circuit 35 and the demodulation circuit 36. The received signal is converted into a demodulated signal by the demodulating circuit 36, input to the protocol control circuit 26 via the selector circuit 31, and processed by the CPU 2. When a transmission signal is generated in the CPU 2, the transmission signal is input from the protocol control circuit 26 to the modulation circuit 35 via the selector circuit 31, converted into a signal suitable for transmission by the modulation circuit 35, and then the antenna coil 33. Sent from

  In the circuit configuration shown in FIG. 4, except for the antenna coil 33 of the RF unit 20 and the capacitor connected in parallel thereto, it is modularized as one integrated circuit device and is used as an external terminal for operation in the contact mode. (Indicated by double circles in FIG. 4) is provided. These external terminals include a power supply terminal that receives supply of the power supply voltage VCC, a ground voltage terminal GND, signal terminals CL1 and CL2, and an external reset signal terminal RSTB. The external reset signal terminal RSTB is pulled up to a voltage level of the power supply voltage VCC via a high-resistance resistor so as not to be in an open state in the non-contact mode.

<Another embodiment>
Next, another embodiment of the circuit of the present invention will be described.

  <1> The circuit configuration of the circuit of the present invention is not limited to the circuit configuration exemplified in the first and second embodiments. The circuit configuration can change the predetermined threshold according to the signal level of the external reset signal terminal RSTB so that the voltage when the RSTB level is low (activation level) is lower than that when the RSTB level is high (activation level). It ’s fine. For example, in the first and second embodiments, the comparison circuit 2 compares the second power supply voltage VCC2 obtained by reducing the power supply voltage VCC by resistance voltage division and the constant reference voltage VREF, and the internal reset signal PRSTB is compared. In the circuit configuration for generating the second power supply voltage VCC2, the voltage dividing ratio of the resistor voltage dividing circuits 1 and 11 for generating the second power supply voltage VCC2 is changed by the voltage dividing ratio switching circuits 3 and 13, but the second power supply voltage VCC2 is The voltage level of the reference voltage VREF may be fixed and changed according to the RSTB level. In the second embodiment, the second power supply voltage VCC2 changes according to the mode determination signal MODE. Similarly, the second power supply voltage VCC2 changes according to the mode determination signal MODE. It doesn't matter. Further, the configuration for changing the second power supply voltage VCC2 side is not necessarily limited to the circuit configuration exemplified in the first and second embodiments.

  Furthermore, in the first embodiment, in the operation when the RSTB level is low (activation level), the second power supply voltage VCC2 changes according to the signal level of the internal reset signal PRSTB before and after canceling the power-on reset. Although the configuration has hysteresis characteristics with respect to the change in the power supply voltage VCC, the hysteresis characteristics need not necessarily be provided.

  <2> In the first and second embodiments, the circuit of the present invention outputs the internal reset signal PRSTB for controlling the reset state of the combination IC card at the rising of the power supply voltage VCC, and the power supply voltage VCC is a predetermined threshold value. As a configuration for canceling the internal reset signal PRSTB when it is detected that the voltage has risen beyond Vt, only the change in the power supply voltage VCC is detected. For example, the logic unit 21 (disclosed in Patent Document 1) A first reset circuit that detects a rising edge of a voltage VDD (see FIG. 4) supplied to the power supply voltage VCC (see FIG. 4) and generates a first reset signal, and a power supply voltage VCC acquired from an external power supply source (or rectifies it) A second reset circuit for generating a second reset signal by detecting the rise of the output voltage of the rectifier circuit (see FIG. 5), Also preferable to be configured to apply the present invention circuit the reset circuit.

  The present invention relates to an interface of a non-contact type IC card that acquires power from an external power supply source in a non-contact manner via electromagnetic waves, etc., converts the power source voltage into a predetermined voltage, and performs a non-contact communication operation, and a power source Non-contact / contact-combined combination that has a contact IC card interface that directly acquires power from an external power supply source via a terminal, etc., converts the power supply voltage to a predetermined voltage, and performs contact communication operation. It can be used for a type IC card and a power-on reset circuit used therefor.

1 is a circuit diagram showing a schematic circuit configuration in a first embodiment of a power-on reset circuit according to the present invention; The circuit diagram which shows the schematic circuit structure in 2nd Embodiment of the power-on reset circuit which concerns on this invention. The figure which shows typically the relationship between the change of the power supply voltage, and the signal level of an internal reset signal for demonstrating the operation | movement in 2nd Embodiment of the power-on reset circuit which concerns on this invention. Schematic block diagram showing one circuit configuration example of a combination type IC card according to the present invention Circuit block diagram showing schematic circuit configuration of conventional power-on reset circuit

Explanation of symbols

1, 11: Resistance voltage dividing circuit 2: Comparison circuit 3, 13: Voltage division ratio switching circuit 4: 2-input AND circuit 5, 15: Inverter 6, 16, 17: 2-input NOR circuit 7, 18: NMOS transistor 14: Contact / Non-contact mode discriminating circuit 19: Power-on reset circuit 20: RF unit 21: Logic unit 22: CPU
23: Security processor 24: Work RAM
25: Boot ROM
26: Protocol control circuit 27: Reset circuit 28: Non-volatile memory unit 29: Voltage control circuit unit (regulator circuit)
30: Bus control circuit 31: Selector circuit 32: Clock generation circuit 33: Antenna coil 34: Rectifier circuit 35: Modulation circuit 36: Demodulation circuit 37: Clock extraction circuit CL1, CL2: Signal terminal GND: Ground voltage terminal PRSTB: Internal reset Signal (Power-on reset signal)
R1, R2, R3, R3: Voltage dividing resistor RSTB: External reset signal terminal SRSTB: System reset signal VCC: Power supply voltage VCC2: Second power supply voltage VDD: Voltage supplied to the logic part and the non-volatile memory part VPP: Non-volatile Voltage supplied to memory VREF: reference voltage

Claims (7)

An internal reset signal for controlling the reset state of the combination IC card is output at the time of rising of the power supply voltage acquired by the contactless interface or the contact interface of the combination IC card from the external power supply source, and the power supply voltage is set to a predetermined value. A power-on reset circuit that cancels the internal reset signal when it detects that the threshold value has been exceeded.
When the combination type IC card functions as a contact type IC card, it is activated when the signal level of the external reset signal terminal which is an input terminal of the external reset signal directly supplied from the external device is the activation level and the deactivation level. The power-on reset circuit characterized in that the predetermined threshold is set to a lower voltage at the level than at the inactivation level.   2. The power-on reset according to claim 1, wherein when the signal level of the external reset signal terminal is an inactivation level, the set value of the predetermined threshold decreases when the internal reset signal is released. circuit.   The setting value after the predetermined threshold value after the internal reset signal is released is configured to be switchable by a mode determination signal for determining a contact mode and a non-contact mode. 3. A power-on reset circuit according to 2. A resistance voltage dividing circuit for generating a second power supply voltage by dividing the power supply voltage by a voltage dividing resistor to reduce the voltage;
A comparison circuit that compares the second power supply voltage with a constant voltage reference voltage used in a regulator circuit that converts the power supply voltage into a predetermined voltage in the combination IC card;
2. The power-on reset circuit according to claim 1, wherein a voltage dividing ratio by the voltage dividing resistor is configured to be switchable according to a signal level of the external reset signal terminal.   When the signal level of the external reset signal terminal is an inactivation level, the voltage dividing ratio by the voltage dividing resistor is switched according to the output level of the comparison circuit, so that when the internal reset signal is released, the predetermined threshold value The power-on reset circuit according to claim 4, wherein the set value is reduced.   When the signal level of the external reset signal terminal is an inactivation level, the voltage dividing ratio by the voltage dividing resistor is switched by a mode determination signal for determining a contact mode and a non-contact mode, thereby releasing the internal reset signal. 6. The power-on reset circuit according to claim 5, wherein a setting value after the predetermined threshold value is lowered can be switched by a mode discrimination signal for discriminating between a contact mode and a non-contact mode. . A combination-type IC card comprising the power-on reset circuit according to claim 1.

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