JP4267566B2 - Method for manufacturing gate electrode - Google Patents

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to separate a thin film structure in which a polycrystalline layer divided into a thickness less than or equal to a thickness determined according to a failure event, or a polycrystalline layer, and each polycrystalline layer. A semiconductor device having a thin film structure in which material layers different in main component from the polycrystalline layer are laminated, a method and apparatus for manufacturing the semiconductor device, and a film thickness of the polycrystalline layer for preventing a defective event of the semiconductor device It relates to the decision method.

  In recent years, amorphous materials have been used in various applications as semiconductor device materials and magnetic materials, taking advantage of the fact that isotropic and homogeneous materials can be obtained. As a material for semiconductor devices, amorphous silicon is often used for the purpose of easily obtaining a uniform impurity concentration.

  When a silicon thin film is formed as a polycrystalline silicon layer on the surface of a semiconductor substrate, the stress generated in the film is sufficiently low at several hundred MPa or less, but after forming an amorphous layer on the surface of the semiconductor substrate, other materials are formed. The previously deposited amorphous material is crystallized for the purpose of filming, heat treatment to relieve stress generated in other layers, or crystallizing the deposited amorphous material. When exposed to a temperature higher than the temperature, the film volume shrinks with the crystallization of the amorphous material, so that a very large tensile stress reaching 1000 MPa may be generated in the film.

  The reliability of the product may be significantly deteriorated due to warpage deformation of the semiconductor substrate caused by this stress generation, film peeling in the semiconductor device, cracks in the film, crystal defects (dislocations, etc.), etc. . In order to prevent these defects, for example, as described in JP-A-63-260052, a film in which a compressive stress is generated in the film and a film in which a tensile stress is generated in the film are laminated, There has been a method of reducing the stress of the material.

  In addition, there are techniques described in Japanese Patent Application Laid-Open No. 63-29954 and Japanese Patent Application Laid-Open No. 3-3326 regarding the formation of stacked polycrystalline silicon films in semiconductor devices. These techniques are techniques for laminating different types of materials.

JP 63-260052 A JP-A 63-29954 JP-A-3-3326

  However, when an amorphous layer is formed on the surface of a semiconductor substrate and crystallized into a polycrystalline phase, the thicker the film, the larger the crystal grains and the greater the volume shrinkage. Depending on the film thickness, the tensile strength generated in the crystallized amorphous material layer may be larger than the adhesion strength between the respective film-forming layers or the material strength of the film-forming layer, and the interlayer peeling, cracks in the layer, etc. Defects occur.

  In addition, even when the defect does not occur in the semiconductor device, warping deformation that causes trouble during exposure occurs in the wafer, or the dislocation density increases due to increased strain at the film interface of the amorphous material. Therefore, in order to control the generated stress, it is necessary to limit the film thickness at the time of film formation, such as causing deterioration of electric characteristics in the semiconductor device such as increase in electric conductivity and wiring resistance.

  In the present specification, various failures caused by an increase in stress generated in the semiconductor device are collectively referred to as “semiconductor device failure events”. In addition, the allowable stress value that does not cause these failure events varies depending on the difference in the manufacturing process of the semiconductor device, the difference in the portion where the laminated film is used in the semiconductor device, the material properties, and the corresponding failure event. An allowable stress value that does not cause a failure event of the semiconductor device is referred to as a “critical stress value”.

  When the film thickness of the polycrystalline material phase film obtained by crystallizing the amorphous material phase film is thin, the crystal grains are refined and the generated stress is reduced, and the above-mentioned defects do not occur, but can flow in the film. The polycrystalline material phase film obtained by crystallizing the amorphous material phase film to an appropriate thickness may cause a failure such as electromigration caused by excessive current in the film when current is limited It was difficult to form a film.

The objects of the present invention are as follows.
(1) In a thin film manufacturing method including an amorphous layer deposition step and a crystallization step of the amorphous material, the film thickness of a conductive thin film structure including an amorphous layer crystallized in a later step Can be formed to a thickness required for the design specifications, and the semiconductor device is free from deterioration of electrical characteristics of the manufactured semiconductor device, delamination, cracks in the layer, crystal defects, etc. It is in providing the manufacturing method of.
(2) Another object of the present invention is to provide a highly reliable semiconductor device in which defects are prevented from occurring by the semiconductor device manufacturing method provided for the problem (1).
(3) Or, in a thin film manufacturing apparatus capable of performing an amorphous layer deposition step and a crystallization step of the amorphous material, a step of forming an amorphous layer and a step of crystallizing the amorphous material, An object of the present invention is to provide a thin film manufacturing apparatus which is performed in a consistent process without automatically releasing a thin film being manufactured to the atmosphere by automatic control.
In order to achieve the object of the present invention of (4) or (1) to (3) above, the upper limit of the thickness of the amorphous layer that can be deposited at one time is reliably prevented rather than empirically. It is to provide a method for determining a value.

In order to achieve the above object, the present invention has the following features.
The semiconductor device of the present invention has a conductive thin film, (1) at least a part of the thin film has a laminated structure divided in the film thickness direction, and the main component of each layer by division is the same element or (2) At least part of the thin film is the same compound (especially effective when the main component is a material containing silicon atoms or metal silicide. The material of each layer may be different depending on the doping). The layered structure is divided in the film thickness direction, and the average crystal grain size in each layer is about ½ to about 10 times the divided layer thickness (for example, the divided film thickness and And / or (3) at least a part of the thin film has a laminated structure divided in the film thickness direction, and each layer. Thickness depends on semiconductor device failure event Or less thick which is defined by a constant to be critical stress value, characterized by.

  In any case, the semiconductor device has a thin film structure made of the same conductive material, and is preferably divided at least once in the film thickness direction. The thin film is preferably composed of two or more polycrystalline layers, and is applied to a portion selected from the group of an electrode (particularly desirably a gate electrode) and a wiring layer. It is also effective to have a layer made of a material different from that of the polycrystalline layer at a position separating the layers of the polycrystalline layer. Further, it is also effective that the impurity concentration in each divided layer of the thin film divided in the film thickness direction differs between at least one adjacent layer.

  Alternatively, the semiconductor device of the present invention has a groove or an uneven portion on the surface of the semiconductor substrate, and at least an angle formed by the surface of the semiconductor substrate and the groove or the uneven portion on a part or all of the groove or the uneven portion on the surface of the semiconductor substrate. A conductive multilayer thin film is formed so as to cover the part, and the main component of each layer is the same element or the same compound. In this case, the conductive multilayer thin film is preferably in a polycrystalline phase, and the thickness of each layer constituting the thin film is preferably equal to or less than the thickness defined by the critical stress value determined according to the failure event of the semiconductor device.

  It is also effective to have a layer made of a material different from that of the polycrystalline layer at a position separating the layers of the polycrystalline layer. Further, it is also effective that the impurity concentration in each divided layer of the thin film divided in the film thickness direction differs between at least one adjacent layer.

  Alternatively, the semiconductor device of the present invention is characterized in that the metal silicide thin film has a laminated structure divided at least once in the film thickness direction.

Furthermore, embodiments of the semiconductor device of the present invention are as follows.
[1] A polycrystalline layer obtained by an amorphous layer deposition step and an amorphous material crystallization step, wherein at least two or more polycrystalline layers made of the same material are continuously laminated. Yes. [2] The thickness of each of the stacked polycrystalline layers is equal to or less than the thickness defined by the critical stress value determined according to the failure event of the semiconductor device. [3] In a semiconductor device having a gate electrode, at least two or more polycrystalline layers composed of the same material as a main component are continuously stacked on all or part of a gate electrode structure on a semiconductor substrate.

  The method for manufacturing a semiconductor device of the present invention includes a step of depositing an amorphous layer on a semiconductor substrate and a step of crystallizing the deposited amorphous material. (1) A step of depositing an amorphous layer Dividing into a plurality of times, and performing the crystallization step for each amorphous layer deposition step, or (2) dividing the amorphous layer deposition step into a plurality of times to deposit each amorphous layer. In order to separate the amorphous layers from one another, a material whose main component is different from the amorphous material is deposited, and the deposited amorphous material is crystallized at least after the completion of all the steps.

  In the case of (2), it is preferable that the amorphous material is silicon, and a material whose main component for separating each amorphous layer is different from the amorphous material is a metal that causes a silicide reaction.

  In any case, in the method of manufacturing a semiconductor device according to the present invention, the impurity concentration in the amorphous layer deposited by dividing into a plurality of times is different between at least one of the adjacent deposited layers, or is amorphous. It is preferable that the step of crystallizing the material is a step of crystallizing the amorphous material by laser irradiation of the entire surface of the amorphous layer or selectively only a local portion of the amorphous layer.

  The method for producing a thin film of the present invention is a method having an amorphous layer deposition step and an amorphous material crystallization step, wherein (1) the amorphous layer deposition step is divided into a plurality of times, Performing the crystallization step for each deposition step of the amorphous layer, and (2) the impurity concentration in the amorphous layer deposited in a plurality of times is divided between at least one of the adjacent deposited layers. (3) A material whose main component is different from an amorphous material in order to divide the amorphous layer deposition process into a plurality of times and to separate each amorphous layer for each amorphous layer deposition process And (4) the step of crystallizing the amorphous material is performed on the entire surface of the amorphous layer or selectively amorphous. It is characterized in that it is a crystallization process of an amorphous material by laser irradiation only in a local portion of the porous layer.

  Alternatively, the thin film manufacturing method of the present invention is a method of obtaining a metal silicide thin film by laminating a silicon thin film and a metal thin film, wherein the metal thin film and the silicon thin film are laminated at least twice each. Each of the stacked film thicknesses is equal to or less than the film thickness defined by the failure event, and a metal silicide thin film is produced by causing a silicide reaction.

  In any case, in the thin film manufacturing method of the present invention, it is preferable that the thickness of each amorphous layer deposited at one time is equal to or less than the thickness defined by the critical stress value determined in accordance with the failure event. .

  A semiconductor device manufacturing apparatus of the present invention is an apparatus for performing an amorphous layer deposition step and an amorphous material crystallization step, a chamber in which a semiconductor substrate is placed, and a jig for supporting the semiconductor substrate A heating device for adjusting the temperature in the chamber and the substrate temperature, a device for adjusting the inflow amount of the gas corresponding to the type of gas flowing in the chamber, a device for adjusting the pressure of the gas in the chamber, and the chamber It has an exhaust device for exhausting from the inside, and a chamber, a heating device, an inflow control device, a gas pressure control device, and a device that automatically controls the exhaust device, and is continuously or intermittently without opening to the atmosphere. A multilayer thin film structure is formed on a semiconductor substrate while controlling a process for depositing and crystallizing a plurality of amorphous films by a control device.

  In this apparatus, at least one laser irradiation apparatus and an apparatus for automatically controlling the laser irradiation apparatus are provided, and the semiconductor device manufacturing process is automatically controlled to crystallize the entire surface of the amorphous layer. It is possible to perform local crystallization.

  Further, the film thickness determining method of the present invention is a method for determining the deposited film thickness of a thin film for performing the amorphous layer deposition step and the amorphous material crystallization step, Relationship between the average crystal grain size generated in the polycrystalline layer obtained by crystallization of the amorphous material and the thickness of the polycrystalline layer obtained by crystallization of the amorphous material and the resulting stress From the above, it is characterized in that the film thickness of the amorphous layer deposited at one time is determined below the critical stress value determined according to the failure event.

Here, the terms used in the present specification will be supplementarily described.
Main component: Impurities for active doping, impurities originally contained in raw materials such as gases and targets, and impurities that are inevitably mixed in during the manufacturing process are excluded. To tell.

Conductivity (of thin film); refers to conductivity exhibited by metals and semiconductors. The volume resistivity of the semiconductor at room temperature intermediate 10 metal and an insulator ^- a ^{5~108Ω · m (10 -5 ~10 8} ) Ω · about m. The volume resistivity is lower as the impurity concentration is higher, and shows a value close to 0 at absolute zero. Therefore, in the present invention, when the volume resistivity of the thin film is 10 ⁸ Ω · m (10 ⁸ Ω · m) or less, it is said to be conductive.

  Average crystal grain size (in the in-plane direction of the deposited film); crystal nucleus generation density varies depending on the impurity concentration of the deposited film and heating conditions, and is about ½ times to about 10 times depending on conditions under which crystallization occurs. That is, in the present invention, crystallization (reaction) having a particle size of about 1/2 to 10 times the thickness of each divided layer is desirable.

  Layer by silicide reaction; when laminated, it may be amorphous or polycrystalline, and the final film may be polycrystalline.

  A failure event of a semiconductor device; a generic term for various failures caused by an increase in stress generated in a semiconductor device such as delamination, inter-layer cracking, or crystal defect.

  Critical stress value: An allowable stress value that does not cause a semiconductor device failure event. The allowable stress value that does not cause a failure event varies depending on the difference in the manufacturing process of the semiconductor device, the difference in the portion where the laminated film is used in the semiconductor device, the material properties, and the corresponding failure event.

  Trench capacitor; a capacity used for a DRAM memory cell having a storage capacity exceeding 1 Mbit. When the area is increased by creating a capacity in the side wall of a deep groove dug in the silicon substrate, a large capacity can be obtained even with a small occupied area as the miniaturization and higher integration progress.

LOCOS: A silicon oxide film for element isolation.
Primary recrystallization (primary recrystallization): If the range in which atoms are regularly arranged is considered as a crystal, it can be considered that a crystal exists microscopically in a substance in an amorphous state. The primary recrystallization referred to in the present specification means that an amorphous substance undergoes phase transformation into an aggregate of crystals, that is, crystallization (reaction). Generally speaking, if it is called primary recrystallization, the crystal grains become coarse due to cold working, etc., and when the member containing many crystal defects is heated, the coarse grains become finer. In this application, however, the average grain size is such that it is generated by primary recrystallization, as distinguished from secondary recrystallization in which microcrystals become coarse at the temperature at which atoms are activated. I emphasized that and used this phrase.

  In the manufacture of a semiconductor device, when the crystallization step of the amorphous material is performed at a temperature that causes a primary recrystallization reaction after the film formation step of the amorphous layer, the crystal of the film obtained by crystallization of the amorphous material It is generally known that the size of the grain size is on the order of the film thickness, and a film having almost no crystal grain boundary in the film thickness direction is formed.

  In addition, since the crystal grain boundary is a mismatched portion between crystal grains having different atomic arrangement directions, it is a region where many defects (dislocations, atomic vacancies, etc.) exist locally.

  In the process of crystallizing an amorphous material by heat treatment, when the film thickness is large, the crystal grains are large, and the ratio of the crystal grain boundary (region having a high defect density) to the entire film is small. Therefore, the contraction ratio of the film volume increases, and the tensile stress generated in the film increases. On the other hand, when the film thickness is small, the generated crystal grains are small, and the ratio of the crystal grain boundary to the entire film is large. Therefore, the contraction ratio of the film volume is reduced, and the tensile stress generated in the film can be kept low. it can.

  The crystal grain size described here is the average value of the distance between crystal grain boundaries adjacent in the direction parallel to the film surface in an arbitrary cross section of the polycrystalline thin film for which the crystallization reaction has been completed.

  FIG. 15 shows a measurement example of stress (crystallization stress) generated along with the crystallization reaction in the film when an amorphous silicon thin film is actually deposited by changing the film thickness to cause a crystallization reaction. Show. The horizontal axis in the figure is the deposited film thickness, and the vertical axis is the stress generated in the film due to the crystallization reaction when the entire deposited film is crystallized at once. Thus, it can be seen that as the deposited film thickness increases, the stress generated during the crystallization reaction increases.

  Therefore, in order to prevent the peeling and cracking of the thin film or the occurrence of dislocations inside the single crystal substrate, the film thickness is controlled so that the stress generated by the crystallization reaction is less than the critical stress value specified by each failure event. It is effective to do.

  According to the present invention, in the manufacturing process of a semiconductor device including a film forming process of an amorphous layer, the thickness of the amorphous layer deposited at a time is determined as a critical stress value determined according to a failure event. The crystal grain size of the amorphous layer formed in the polycrystalline layer obtained by the first recrystallization is limited by performing the step of crystallizing the amorphous material by limiting the thickness to a thickness defined by The size is limited to the order of thickness of the deposited amorphous layer.

  Accordingly, since the size of the crystal grain size formed in the obtained polycrystalline layer is limited, the stress generated in the polycrystalline layer can be reduced to a critical stress value that does not cause a defective event.

  By laminating the low-stressed polycrystalline layer, the film thickness of the thin film structure can be formed as required by the design specifications, and the electrical characteristics of the semiconductor device to be manufactured are deteriorated. In addition, it is possible to prevent defects due to stress such as delamination, cracks in the layer, and crystal defects. Accordingly, it is possible to obtain high product reliability and high product yield of the semiconductor device to be manufactured.

  Further, in a thin film manufacturing apparatus that can perform an amorphous layer deposition process and a crystallization process of the amorphous material, the process of forming the amorphous layer and the process of crystallizing the amorphous material are automatically controlled. Therefore, the thin film in the middle of manufacture can be performed in a consistent process without opening it to the atmosphere.

  As described above, by using the semiconductor device manufacturing method according to the present invention, the thickness of the amorphous layer deposited at one time is determined by the critical stress value determined according to the failure event. By performing crystallization (primary re) as described below, it is possible to reduce the stress generated in the polycrystalline layer by crystallization.

  In addition, by laminating this low-stress thin film until the cross-sectional area does not result in excessive electrical resistance, it eventually prevented defects caused by stress, resulting in deterioration of electrical characteristics, delamination, and cracks in the layer. Thus, a semiconductor device with high reliability and yield can be obtained.

  Furthermore, by using the thin film manufacturing apparatus according to the present invention, the process of depositing the amorphous layer and the process of crystallizing the amorphous material are controlled by the automatic control apparatus to control the entire thin film manufacturing process. Can be performed in a consistent process without opening to the atmosphere.

  In addition, by using the method for determining the thickness of the amorphous layer that can be deposited at one time determined according to the failure event based on the present invention, the amorphous material that can be deposited at once to obtain the above-described effect. Rather than empirically determining the thickness of the layer, it is possible to determine a thickness that can reliably prevent defective events.

Embodiments of the present invention will be described below with reference to the drawings.
Example 1
An embodiment relating to a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be described with reference to FIGS.

  FIG. 1 is a cross-sectional perspective view showing the structure of a semiconductor device 1 according to an embodiment of the present invention. The semiconductor device 1 has completed LOCOS formation, gate oxidation, gate electrode film formation and etching process, and one of the present invention is used as a gate electrode structure of a MOS transistor.

  In this embodiment, the gate electrode 2 includes a silicon oxide film 5 formed by a thermal oxidation process on the surface of a p-type silicon semiconductor substrate 4 electrically isolated from an adjacent element by the LOCOS 3, and the silicon oxide film 5. It has a structure in which a divided polycrystalline silicon layer 6 into which impurities such as phosphorus (P) that electrically activates silicon are introduced at a high concentration and a uniform concentration is laminated on the surface. Since each divided polycrystalline silicon layer 6 is formed by primary recrystallization, it mainly has a columnar crystal structure.

  The manufacturing method of the semiconductor device 1 will be described with reference to the manufacturing process sectional views of FIGS. 2 to 14, taking as an example the case of manufacturing a CMOS on the p-type silicon semiconductor substrate 4.

  The first step is shown in FIG. The surface of the p-type silicon semiconductor substrate 4 is thermally oxidized to form a silicon oxide film 5a. Next, a silicon nitride film 11a is formed on the surface of the silicon oxide film 5a by a CVD (chemical vapor deposition) method or the like.

The subsequent second step is shown in FIG. The photoresist 12a is uniformly applied to the surface of the silicon nitride film 11a formed in the process of FIG. 2, the photoresist 12a is patterned, and the silicon nitride film 11a is etched. While controlling the flow rate of phosphine (PH ₃ ), phosphorus (P) is ionized by discharge, and using the patterned silicon nitride film 11 a as a mask, phosphorus (P) is etched by etching the silicon nitride film 11 a of the silicon semiconductor substrate 4. Introduce into the removed part. In the case of phosphorus (P), ions are implanted using phosphine, but arsenic (As) ions may be implanted using arsine (AsH ₃ ) or the like. The reason why such ion implantation is performed is to make the insulation between devices more complete by using the LOCOS portion as a reverse bias.

  In the third step (FIG. 4) after the second step, the silicon oxide film 5a is formed thick only in a region where ion implantation is prevented by thermal oxidation or the like in the next ion implantation step.

FIG. 5 shows the fourth step. Here, only the silicon nitride film 11a in the step of FIG. 4 is selectively etched and removed. Next, boron ions are generated by discharge from boron triboride (BF ₃ ), and boron ions are introduced into the p-type silicon semiconductor substrate 4. If the p-type silicon semiconductor substrate 4 is left as it is, it is amorphous due to damage caused by the implantation of ions, or even a single crystal is not electrically activated because there are many lattice defects. Volume resistivity is shown. Therefore, heat treatment is performed to diffuse the introduced impurities and to recover the p-type silicon semiconductor substrate 4.

  FIG. 6 shows a fifth step. A silicon nitride film 11b is formed by a CVD method or the like, and a portion where LOCOS 3 is to be formed is patterned to serve as a mask for LOCOS 3 formation. After removing the remaining photoresist 12b, LOCOS 3 is formed by wet oxidation or the like.

  Subsequently, in a sixth step shown in FIG. 7, the silicon nitride film 11b used for forming the LOCOS 3 is removed using hot phosphoric acid or the like, and the silicon oxide film 5a other than the LOCOS 3 is also removed by etching. On the exposed surface of the p-type silicon semiconductor substrate 4, a new thin silicon oxide film 5 is formed again as a gate electrode oxide film by thermal oxidation.

  After this step, a step of forming a gate electrode material is performed. Hereinafter, a method for manufacturing the gate electrode 2 of FIG. 1 in which the respective divided polycrystalline silicon layers 6 are laminated, in which impurities for electrically activating silicon are introduced at a high concentration and a uniform concentration, will be described with reference to FIG. explain.

  FIG. 14 shows a manufacturing process of the semiconductor device gate electrode 2 of FIG. 1 having a divided polycrystalline silicon layer 6 laminated structure in which impurities for electrically activating silicon are introduced at a high concentration and a uniform concentration according to the present invention. It is sectional drawing.

First, step (1) in FIG. 14 will be described. For example, a gas such as disilane (Si ₂ H ₆ ) and phosphine (PH ₃ ) reacts in a gas phase to control the temperature of the semiconductor substrate so that amorphous silicon is deposited, and a silicon oxide film is formed by gate oxidation in the previous step. 5 is formed on the surface of the p-type silicon semiconductor substrate 4 on the surface of the p-type silicon semiconductor substrate 4 by a CVD (chemical vapor deposition) method or the like. The deposition is performed so that the thickness is equal to or less than the thickness defined by the determined critical stress value. At this time, the impurity phosphorus (P) concentration in the divided amorphous silicon layer 13 is uniform.

Although the semiconductor substrate temperature is used as an example of the factor for controlling the silicon deposition state, other factors such as the pressure and flow rate of the gas to be flowed may be controlled. In addition, when depositing an amorphous silicon thin film, monosilane (SiH ₄ ) may be used.

  Next, steps (2) to (3) in FIG. 14 will be described. By maintaining the semiconductor substrate temperature at 600 ° C. or higher, the amorphous silicon is crystallized and the divided polycrystalline silicon layer 6 is formed. The stress generated in the divided polycrystalline silicon layer 6 is less than the critical stress value because the film thickness of the divided amorphous silicon layer 13 is deposited below the thickness defined by the critical stress value determined according to the failure event. Can be suppressed. Crystallization of the amorphous material may be performed by controlling the temperature of the semiconductor substrate, but the amorphous material may be crystallized by laser irradiation. Crystallization of the amorphous material by this laser irradiation can also crystallize the entire surface of the divided amorphous silicon layer 6 formed on the semiconductor substrate 4, but local crystallization is performed by laser irradiation to the local portion. It doesn't matter.

  In steps (4) to (5) of FIG. 14, the steps of FIGS. 3 (1) to (3) are repeated until the total thickness of the laminated divided polycrystalline silicon layers 6 reaches a required thickness. By repeating this, a divided polycrystalline silicon layer laminated film 14 having a structure with reduced stress is formed.

  After the process of FIG. 14, a photoresist 12c (see FIG. 7) is applied to the surface of the divided polycrystalline silicon layer laminated thin film 14, patterned, and etched to obtain a final structure. As shown in FIG. 8, the stacked gate electrode 2 having a structure in which the divided polycrystalline silicon layers 6 are stacked can be formed.

  Therefore, by stacking the divided polycrystalline silicon layers 6 into which impurities such as phosphorus (P) for electrically activating silicon are introduced at a high concentration and a uniform concentration, a cross-sectional area that does not cause an excessive electric resistance. In other words, it is possible to obtain a film thickness in which the electrical resistance is less than the design value, and because the average crystal grain size of the formed polycrystalline silicon is small, the stress generated in the film is suppressed to a critical stress value or less. It becomes possible to obtain the gate electrode 2 having a structure in which the polycrystalline silicon layers 6 are laminated.

  Here, a silicon (Si) film and a cobalt (Co) film are alternately deposited in an amorphous state to cause a primary recrystallization reaction, thereby dividing a polycrystalline (cobalt silicide) layer having a columnar crystal structure. The photograph (FIG. 27) which observed the thin film used as the crystal | crystallization laminated structure with the electron microscope is shown. The magnification is about 180,000 times.

  Also in the divided polycrystalline silicon layer laminated film 14 described with reference to FIG. 14, in order to deposit the next amorphous silicon layer after crystallization of each amorphous silicon layer, the divided polycrystalline silicon layer laminated film 14 is used by using an electron microscope. However, like FIG. 27, it can be observed that it has a laminated cross-sectional structure. From this, the structure in which the polycrystalline material is deposited from the beginning to the required thickness is clearly different from the structure of the present invention in that a clear boundary between the divided layers is recognized.

  The following eighth step will be described with reference to FIG. A photoresist 12d is applied to the p-type silicon semiconductor substrate 4 and patterned. Using the remaining photoresist 12d as a mask, ions such as phosphorus (P) or arsenic (As) are implanted to form the source and drain of the n-channel MOS transistor.

  FIG. 10 shows the ninth step. First, the photoresist used in the process of FIG. 9 is removed, and a photoresist 12e is newly applied to the p-type silicon semiconductor substrate 4 to perform patterning, and ions such as boron (B) are implanted to form the source of the p-channel MOS transistor, A drain is formed. A heat treatment is applied to diffuse the introduced ions.

  In the subsequent tenth step of FIG. 11, the photoresist 12e used in the step of FIG. 10 is removed, and the p-type silicon semiconductor substrate 4 is covered with an interlayer insulating film 16 such as phosphorous glass. A hole 20 for obtaining electrical contact with the semiconductor substrate 4 is obtained by etching.

  In FIG. 12 (11th step) and FIG. 13 (12th step), a wiring material such as an aluminum alloy is formed on the surface of the p-type silicon semiconductor substrate 4 by sputtering and patterned to obtain the aluminum alloy wiring layer 17. In order to protect the finally formed semiconductor device, the entire surface of the substrate is covered with an insulating film (passivation film) 18 and the whole process is completed. In the case of a semiconductor device having a multilayer wiring, after this twelfth step, a hole for obtaining further electrical contact is formed and the next wiring is applied. Although the wiring to the gate electrode 2 is not shown in the drawing, this wiring is formed by a known technique.

In the first embodiment, the p-type silicon semiconductor substrate 4 is used as the semiconductor substrate. However, the p-type silicon semiconductor substrate is not necessarily required and may be an n-type silicon semiconductor substrate. In that case, the manufacturing process requires some changes. Further, a gallium arsenide semiconductor substrate or the like may be used. Polycrystalline silicon is used as the material of the gate electrode 2, but other materials that can be deposited in an amorphous state and have conductivity when crystallized may be used. Further, although phosphorus (P) is used as an impurity, other impurities such as boron (B) and arsenic (As) may be used.
(Example 2)
Another embodiment relating to a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be described with reference to FIGS.

  FIG. 16 is a cross-sectional perspective view showing the structure of the semiconductor device 7 according to the embodiment of the present invention. The semiconductor device 7 is a diagram in which the steps up to LOCOS formation, gate oxidation, gate electrode film formation and etching are completed, and the semiconductor device manufacturing method according to the present invention is used as the gate electrode structure of the MOS transistor as in the first embodiment. is doing.

  The gate electrode 8 according to an example of the manufacturing method of the present invention is formed on the surface of the silicon oxide film 5 formed by thermal oxidation on the surface of the p-type silicon semiconductor substrate 4 electrically isolated from the adjacent element by the LOCOS 3. The divided polycrystalline silicon layer 6 having a high concentration and a uniform concentration of impurities that electrically activate silicon such as (P) is different from the polycrystalline silicon mainly composed of silicon, for example, The aluminum alloy layers 9 are alternately stacked.

  Since this semiconductor device 7 can be obtained by a manufacturing method similar to the manufacturing method of the semiconductor device 1 shown in the first embodiment except for the gate electrode 8, the manufacturing method of only the gate electrode 8 is the process shown in FIG. This will be described with reference to FIG.

  The manufacturing process of the semiconductor device 7 is the same as that of the first embodiment up to the middle of the process of FIG. After the process of FIG. 6 is completed, the silicon nitride film 11b used for forming the LOCOS 3 in the process of FIG. 7 is removed using hot phosphoric acid or the like, and the silicon oxide film 5a other than the LOCOS 3 is also removed by etching. On the exposed surface of the p-type silicon semiconductor substrate 4, a new thin silicon oxide film 5 is formed again as a gate electrode oxide film by thermal oxidation.

  After this step, a step of forming a gate electrode material is performed. Hereinafter, a material in which an impurity (for example, P) for electrically activating silicon is introduced at a high concentration and a uniform concentration is different from the polycrystalline silicon in which the divided polycrystalline silicon layer 6 laminated thin film is mainly composed of silicon. A method for manufacturing the gate electrode 8 having a structure divided by the aluminum alloy layer 9 will be described with reference to FIG.

  FIG. 17 is a process sectional view showing a method of manufacturing the gate electrode 8 of the semiconductor device 7 according to the second embodiment of the present invention.

Step (1) in FIG. 17 will be described. After the formation of the silicon oxide film 5 for the gate electrode, a gas containing an impurity element to be doped such as disilane (Si ₂ H ₆ ) and phosphine (PH ₃ ) is supplied to the surface of the silicon oxide film 5 to cause a vapor phase decomposition reaction. Then, the divided amorphous silicon layer 13 is formed to a thickness not more than a thickness defined by a critical stress value determined according to a failure event by a CVD (chemical vapor deposition) method or the like. Monosilane (SiH ₄ ) may be used for depositing the amorphous silicon thin film.

  Step (2) in FIG. 17 will be described. For example, an aluminum alloy layer 9 which is a material different from the film deposited in the step (1) is deposited by a method such as sputtering. The material deposited by sputtering may be another conductive material or a silicide compound. The thickness of the aluminum alloy layer 9 to be deposited is such that the atoms in each divided amorphous silicon layer hardly move to other divided amorphous silicon layers by thermal diffusion in the subsequent step of crystallizing the divided amorphous silicon layer. To do.

  In step (3) of FIG. 17, steps (1) to (2) are repeated until the total thickness of the divided amorphous silicon layer 13 and polycrystalline aluminum alloy layer 9 becomes larger than the required thickness.

  Step (4) in FIG. 17 will be described. When the total thickness of the divided amorphous silicon layer 13 and the polycrystalline aluminum alloy layer 9 reaches a required thickness, the temperature of the semiconductor substrate is controlled to a temperature at which the amorphous silicon crystallizes, for example, 600 ° C. The silicon layer 13 is crystallized.

  After the manufacturing step of FIG. 17, the laminated thin film of the divided amorphous silicon layer 13 and the polycrystalline aluminum alloy layer 9 is patterned, thereby dividing the divided polycrystal having a high concentration and a uniform concentration of impurities such as phosphorus (P). A gate electrode 8 having a structure in which a silicon layer 6 and an aluminum alloy layer 9 which is a material different from polycrystalline silicon containing only silicon as a main component can be obtained. Reference numeral 15 denotes a thin film having an alternately laminated structure of polycrystalline silicon and another material.

  In this manufacturing process, it is not necessary to perform the crystallization process of the amorphous material every time after the film formation process of the amorphous layer as in the first embodiment. The gate electrode 8 structure based on the embodiment of the present invention can be obtained by only the process, which leads to shortening of the process.

  Further, for a material different from the amorphous silicon deposited in the step (2) of FIG. 17, a metal that undergoes a silicide reaction such as tungsten or cobalt may be used instead of the aluminum alloy. The silicide reaction proceeds at the interface between each of the metal layers that react with the silicide, and a thin film having a structure in which the silicide layers are stacked is formed.

  Therefore, by making the film thickness of each divided silicide layer obtained here equal to or less than the film thickness defined by the critical stress value determined according to the failure event, the stress generated in each divided polycrystalline silicide layer is It can be suppressed below the critical stress value.

  In this way, by sandwiching another material layer between them and dividing the film thickness of each amorphous material layer to a prescribed thickness or less, the process of crystallizing the amorphous material is performed only once. That is, it can be performed only at the end of the entire process.

  However, since the stress generated is generally lower when the surface of the amorphous material layer is crystallized and contracted in a state where there are no constraint conditions, the crystal is generated at the completion of the film formation of each divided amorphous material layer. There is no problem even if it is made. In addition, laser irradiation may be performed on the local portion of the divided amorphous material layer, and the local portion may be selectively reduced in stress, and the portion that does not directly lead to a defect may be crystallized at the end of the entire process. .

  By using the semiconductor device manufacturing method described above, as in the first embodiment, the stress generated in the gate electrode film does not exceed the critical stress value corresponding to the failure event, and the target thickness is uniform. Thus, a highly reliable gate electrode with a low resistance can be manufactured, and a highly reliable product can be provided.

In the second embodiment, the p-type silicon semiconductor substrate 4 is used as the semiconductor substrate. However, the p-type silicon semiconductor substrate 4 is not necessarily required and may be an n-type silicon semiconductor substrate. Further, a gallium arsenide semiconductor substrate or the like may be used. Polycrystalline silicon is used as the material of the gate electrode 8, but other materials that can be deposited in an amorphous state and have conductivity when crystallized may be used. Further, although phosphorus (P) is used as an impurity, other impurities such as boron (B) and arsenic (As) may be used.
(Example 3)
An embodiment of a semiconductor device structure manufactured by using the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

  18 to 24 are cross-sectional views in the embodiment of the semiconductor structure according to the present invention. The present invention is used to fill the groove (concave portion) formed in the surface of the p-type silicon semiconductor substrate 4 with the polycrystalline silicon layer 6. One example used is shown.

  The example of FIG. 18 is an example used for a trench type memory cell. After a silicon oxide film 5 is formed as an insulating film in the trench groove on the surface of the p-type silicon semiconductor substrate 4, a polycrystalline silicon layer 6 is laminated to form a groove. Is buried. As shown in FIG. 19, this groove does not necessarily need to be completely filled with the polycrystalline silicon layer 6.

  The example of FIG. 20 shows the surface of the p-type silicon semiconductor substrate 4 in which the corners are rounded by isotropic etching or the like, or the corners are removed by applying an interlayer insulating film for planarization. 5 shows a case where a polycrystalline silicon layer 6 is formed. The example of FIG. 21 shows a case where the side surfaces of the groove and the uneven portion are tapered. The example of FIG. 22 shows a case where there are irregularities on the side surfaces of the grooves and the irregularities. As the corner is less round and the corner is sharper, the stress is concentrated and the structure becomes severe.

  23, 24, and 25 show an example in which a polycrystalline silicon layer 6 as a wiring layer is formed on the concavo-convex portion, and p-type silicon after covering the gate electrode 2 and the like with the interlayer insulating film 16 is shown. The wiring layer 6 is formed along the irregularities on the surface of the semiconductor substrate 4 and is used for the purpose of making electrical contact with the substrate.

  When amorphous silicon is deposited and crystallized, the corners of the concavo-convex parts become stress concentration points accompanying the volumetric shrinkage of the layer due to crystallization of the amorphous material, so that the flat part as in Example 1 and Example 2 A large stress is locally generated as compared with the film formed on the substrate.

  Therefore, using this example, the film thickness of the amorphous layer such as amorphous silicon formed at one time is set so that the stress concentration value does not exceed the critical stress value. If the film forming process is repeated until the necessary film thickness is reached as in the first and second embodiments, when the polycrystalline silicon layer 6 is embedded in the groove formed on the surface of the p-type silicon semiconductor substrate 4, the polycrystalline structure is formed in the uneven portion. It is possible to prevent a defect from occurring when the silicon layer 6 is formed.

The shape of the side wall and the corner of the concavo-convex portion as shown in FIGS. 23, 24, and 25 may be shapes shown in FIGS. 20 to 22 or a combination thereof.
As the amorphous material is deposited in such grooves and irregularities, the thickness of the deposited amorphous layer does not exceed the critical stress value according to the present invention. The effect of the manufacturing method of setting and laminating is exhibited.

The same effect can be obtained even if the structure and manufacturing method in which each amorphous layer is divided into other material layers as in the second embodiment are used in this embodiment.
In the third embodiment, another material such as a tantalum oxide film may be used as the material of the insulating film of the trench type memory cell. Although amorphous silicon is used for the laminated material, other amorphous materials may be used.
(Example 4)
Next, examples relating to the thin film manufacturing method of the present invention will be described with reference to FIGS. 26, 27, 28, and 29. FIG. FIG. 26 illustrates the flow of the method for manufacturing the metal silicide thin film of this example. In this thin film manufacturing method, a metal silicide thin film having a composition MSix (M is a metal element, Si is a silicon element, and x is a stoichiometric ratio)
M + xSi = MSix (1)
The chemical reaction of

After a base film (silicon oxide film) 5 is formed on the substrate 4, a silicon thin film 6 having a thickness of 1/2 tSi is first deposited. Here, the film thickness tSi is such that when the composition of the finally obtained metal silicide film is MSix (M is a metal element), the atomic ratio is
M: Si = 1: x (2)
The thickness ratio (1: y) between the metal thin film 20 and the silicon thin film 6 is determined from the density ratio of each element. That is, tM: tSi = 1: y (3)
It becomes.

The film thickness tMSi that is twice the film thickness calculated from the thickness of the metal silicide thin film per layer defined by the finally obtained failure event, and the sum of the initial silicon thin film thickness tSi and the metal thin film thickness tM Ratio (1: z)
tMSi: (tSi + tM) = 1: z (4)
Is taken into account, the tM is eliminated from the equations (1) and (2),
tSi = (yz) tMSi / (1 + y) (5)
Is determined.

Next, as the second layer film, film thickness tM = ztMSi / (1 + y) (6)
A metal thin film determined by the above is deposited.

As the third layer, a silicon thin film having a thickness of tSi is deposited. Thereafter, the metal thin film 20 with the required number of layers (N layers), the film thickness tM, and the silicon thin film 6 with the film thickness tSi are alternately deposited. The number of layers required for deposition (considering a pair of a metal thin film and a silicon thin film as one layer) is, when the thickness of the metal silicide thin film to be finally obtained is tM,
N = TM / tMSi (7)
An integer satisfying. However, tMSi is adjusted to be equal to or less than the limit film thickness defined by the failure event so that N is an integer.

  The film thickness of the uppermost layer is set to 1/2 tSi or 1/2 tM. The reason why the thickness of the lowermost layer and the uppermost layer is ½ is as follows. That is, since the chemical reaction starts from the interface between different materials, the chemical reaction proceeds from both the upper and lower interfaces of each film in either the silicon thin film 6 or the metal thin film 20.

  Accordingly, a film thickness equivalent to exactly half of each film is consumed by the reaction from the upper interface and the lower interface. That is, for the uppermost layer or the lowermost layer film, there is only one reaction interface, so the required film thickness is ½.

  In the present embodiment, the uppermost layer material is the same silicon thin film as the lowermost layer, but it is not necessarily a silicon thin film, and may be a metal thin film. Furthermore, the lowermost film is not necessarily a silicon thin film, and deposition may be started from a metal thin film. Also, the deposition method of each film is not particularly limited.

After completing the deposition of a predetermined number of layers, the entire substrate is heated to a temperature sufficient for the silicidation reaction to proceed to complete the silicidation reaction. An example of the observation of the crystal state of the film after completion of the reaction is shown in FIG. In FIG. 27, a Co thin film is used as a metal thin film, and a film in which the atomic ratio is set so as to be Co: Si = 2: 1 is heat-treated at a temperature equal to or higher than the temperature at which the silicide reaction is completed (for example, 700 ° C.). 27 is an example of observing the crystal structure of the film using a transmission electron microscope, where layer i is an adhesive for preparing a transmission electron microscope sample, and layer ii is a cobalt silicon alloy laminate comprising about 10 layers in the photograph of FIG. A film (Co ₂ Si), a layer iii represents a silicon oxide film, and a layer iv represents a silicon substrate. A layered state in which the portion of layer ii is divided is shown, but since the crystal orientation is different, the color tone of each crystal looks different.

When the reaction is completed, it can be seen that the structure is formed by laminating films in which crystal grains are substantially penetrated in the film thickness direction and continuous in the horizontal direction. The thickness of each layer is a silicide film thickness determined by half the sum of the film thickness of the metal thin film and silicon thin film laminated before the reaction. TMSi = 1/2 (tM + tSi) / z (8)
It corresponds to.

  In this way, when a silicide reaction is caused after a metal thin film and a silicon thin film are divided into a plurality of times and laminated, the silicide thin film having a predetermined film thickness has a small crystal grain size, that is, low stress that does not cause a defective event. It can be obtained in the state (stress due to volume change when the silicide reaction proceeds).

  FIG. 28 shows a cross-sectional view of a MOS (Metal-Oxide-Semiconductor) transistor structure manufactured by applying this manufacturing method, in which a silicide alloy is used for the gate electrode of the transistor.

  In this embodiment, since the gate electrode having a predetermined thickness is formed of a laminated film made of small crystal grains, it is possible to control the stress during the formation of the silicide film below the occurrence of a defective event.

  FIG. 29 shows a cross-sectional view of an apparatus using the silicide thin film 19 as a wiring material using this manufacturing method. Also in this embodiment, since the wiring film having a predetermined thickness can be formed of a laminated film having small crystal grains, the wiring film can be manufactured in a low stress state that does not cause a defective event.

  Suitable metals for forming the metal silicide thin film include titanium Ti, vanadium V, chromium Cr, manganese Mn, iron Fe, cobalt Co, nickel Ni, tantalum Ta, tungsten W, zirconium Zr, niobium Nb, molybdenum Mo, Any of palladium Pd, rhodium Rh, iridium Ir, platinum Pt, hafnium Hf, terbium Tb, erbium Er, and yttrium Y can be selected.

In addition, the thin film targeted in the present invention is a wiring in an optical device, an optical disk, a magnetic disk, a superconducting element, and the like.
(Example 5)
Next, an embodiment relating to a manufacturing apparatus according to the present invention will be described with reference to FIGS. 30, 31, 32, 33, and 34. FIG.

  30 and 31 show an embodiment of a manufacturing apparatus using chemical vapor deposition according to the present invention. FIG. 30 shows an example of a diffusion furnace type manufacturing apparatus, and FIG. 31 shows an example of a vertical type manufacturing apparatus.

  The semiconductor device manufacturing apparatus according to the present embodiment is characterized by a control device that automatically controls a repetition process of a combination of a plurality of processes of forming an amorphous thin film and crystallizing the thin film. There is no problem.

  The manufacturing apparatus shown in FIGS. 30 and 31 includes a chamber 31 that provides a place for a film forming process on a semiconductor substrate 38 and a process for crystallizing an amorphous material, a jig 32 that supports the semiconductor substrate 38, and a semiconductor. A heating device 33 for adjusting the substrate temperature and the atmosphere in the chamber 31, a plurality of gas controllers 34 for supplying a source gas, an exhaust device 35 for controlling the pressure in the chamber and exhausting the chamber, the chamber, the heating device, The inflow amount adjusting device, the gas pressure adjusting device, and the automatic control device 36 for automatically controlling the exhaust device are configured. By using this manufacturing apparatus, it is possible to carry out the manufacturing method based on this embodiment continuously or intermittently with a single manufacturing apparatus while automatically controlling the manufacturing process without opening to the atmosphere. is there.

  The automatic control device 36 controls the heating device 33, the plurality of gas controllers 34, the exhaust device 35, and the film forming conditions such as the semiconductor substrate temperature and the chamber internal pressure. Further, since laser irradiation is selectively performed on the entire surface or a local portion of the semiconductor substrate 38, a laser irradiation device 37 may be attached as shown in FIG.

  FIG. 32 shows an example of a flowchart in which the automatic control device 36 performs processing in the semiconductor device manufacturing apparatus shown in FIGS. 30 and 31. This flowchart is for automatically controlling the process shown in FIG. 14 of the first embodiment. FIG. 33 shows an example of a temperature process in which the control of the semiconductor substrate temperature and the atmospheric temperature in the chamber as film forming conditions is automatically controlled according to the flowchart of FIG. 33, the horizontal axis represents time, the vertical axis represents the semiconductor substrate temperature, and Tcr represents the critical temperature at which the amorphous material deposited on the semiconductor substrate 38 is crystallized.

  This will be described with reference to the flowchart of FIG. In the figure, □ represents processing, and diamond represents judgment. The process start temperature is assumed to be 20 ° C., for example. The manufacturing process control of the semiconductor device is started from (100) in FIG.

  In the process (101), the semiconductor substrate 38 on which an insulating film such as a silicon oxide film is deposited by the sixth process shown in FIG. 7 is installed in the chamber of the manufacturing apparatus, and the manufacturing process is started (FIG. 33). Corresponds to A). When the inside of the chamber does not reach a degree of vacuum suitable for the film forming environment, the vacuum is exhausted using a vacuum exhaust device. In the process (102), the semiconductor substrate 38 is heated using the heating device 33 shown in FIG.

  In the determination (103), it is determined whether or not the semiconductor substrate temperature has reached a temperature at which an amorphous material can be formed. If the temperature has not reached the temperature at which a film can be formed (if determined as No in the determination (103)). ), Returning to the processing (102), heating of the semiconductor substrate is continued. The loop of the processing (102) and the determination (103) is repeated until the semiconductor substrate temperature reaches a temperature at which an amorphous material can be formed (until determined as Yes in the determination (103)) (A- in FIG. 33). Corresponds to step B). However, when the judgment (103) is controlled by the heating time, heating is performed until a predetermined heating time is reached.

  After it is determined Yes in the determination (103), the processing (104) is performed while maintaining the film forming temperature. In the process (104), the supply of the source gas from the gas controller into the chamber and the pressure control of the source gas in the chamber are performed. In this process, the first divided amorphous material layer is formed by chemical vapor deposition or the like. In judgment (105), the thickness of the first divided amorphous material layer formed at one time has reached a predetermined value equal to or less than the thickness defined by the critical stress value determined according to the failure event. If the predetermined thickness is not reached (No is determined in the determination (105)), the process returns to the process (104), and the supply of the source gas into the chamber and the supply of the source gas in the chamber are performed. Continue pressure control. The loop of the process (104) and determination (105) is repeated until the thickness of the first divided amorphous material layer reaches a predetermined thickness (until determined as Yes in determination (105)) (FIG. 33). Corresponds to the step B-C). However, when the judgment (105) is controlled by the film formation time, the processing (104) is continued until the predetermined film formation time is reached.

  When the deposited film thickness reaches a predetermined value equal to or less than the thickness defined by the critical stress value determined according to the failure event, it is determined as Yes in the determination (105), and the supply of the source gas is performed. Is stopped and the process proceeds to processing (106). In the processing (106), the semiconductor substrate 38 is heated by the heating device 33 shown in FIG. 30 or 31 until the temperature at which the amorphous material is crystallized. In determination (107), it is determined whether or not the semiconductor substrate temperature has reached a temperature at which the amorphous material crystallizes. In the processing (106) and determination (107) loops, as in the processing (102) and determination (103) loops, the determination (107) and the processing (106) are determined as Yes in the determination (107). The process is repeated (corresponding to the step CD in FIG. 33). However, when the judgment (107) is controlled by the heating time, heating is performed until a predetermined heating time is reached.

  The next process is started when the temperature of the semiconductor substrate reaches the temperature at which the amorphous material crystallizes. In the process (108), at least the time required for the entire first divided amorphous material layer to crystallize, This temperature is maintained (corresponding to the step D-E in FIG. 33).

  After the process (108) is completed, in the decision (109), it is judged whether or not the thickness of the whole layer in which the amorphous material is crystallized has reached the thickness required for the design. However, when the judgment (109) is controlled by the number of times of forming the amorphous material layer, it is judged as Yes until reaching the predetermined number of times, and when reaching the number of times, No and Judgment will be made.

  If the thickness of the entire layer where the amorphous material is crystallized does not reach the thickness required for the design, the amorphous material deposition step and the crystallization step are repeated again. And the loop of judgment (111) is performed, and the semiconductor substrate is cooled until it reaches a temperature at which an amorphous material can be formed (corresponding to the step EF in FIG. 33).

  When the temperature of the semiconductor substrate reaches a temperature at which an amorphous material can be formed, the process moves from the determination (111) to the process (104). In the loop of the process (104) and the determination (105), the temperature of the semiconductor substrate 38 is increased. While holding, the source gas is supplied into the chamber and the pressure of the source gas in the chamber is controlled to start the film formation of the second divided amorphous material layer. Thereafter, the processing and determinations (104) to (111) are repeated until the total thickness of the divided amorphous material layer reaches the thickness required for the design. In the repetition of the processing and judgments (104) to (111), if the judgment (109) is No (the thickness of the entire layer in which the amorphous material is crystallized reaches the thickness required for the design. In this case, a loop of processing (112) and determination (113) (corresponding to YZ in FIG. 33) is started. In the processing (112), the semiconductor substrate 38 is cooled at a cooling rate that does not cause defects in the semiconductor device being manufactured due to thermal stress or the like. In the determination (113), the semiconductor substrate temperature is the substrate take-out temperature, for example, semiconductor substrate storage. It is determined whether or not the temperature has reached 20 ° C.

  When it is determined in the determination (113) that the semiconductor substrate temperature has reached the substrate removal temperature, the process proceeds to the processing (114), and the semiconductor substrate 38 is removed from the manufacturing apparatus chamber. All the steps controlled by the automatic control device 36 using the manufacturing apparatus according to this embodiment are completed by this substrate removal step (corresponding to Z in FIG. 33).

  The process start temperature or the substrate take-out temperature does not have to be 20 ° C., and any temperature below the crystallization temperature may be used. Further, the temperature may be higher than the crystallization temperature. In this case, however, the process (102) in FIG. 32 is not heating but cooling the semiconductor substrate during film deposition. In the process (112) in FIG. Will do.

  FIG. 34 shows another embodiment of a flowchart in which the automatic control device 36 performs processing using the semiconductor device manufacturing apparatus shown in FIGS. 30 and 31. This flowchart is for automatically controlling the process shown in FIG. 17 of the second embodiment. The flowchart of FIG. 34 is combined with the process of forming another material layer for dividing the amorphous material layer in the flowchart of FIG.

  This will be described with reference to the flowchart of FIG. The □ process indicated by the dotted line in the figure indicates that the process is not necessarily performed but is performed as necessary. Details will be described later. The process start temperature is assumed to be 20 ° C., for example. The manufacturing process control of this semiconductor device is started from (200) of FIG.

  Processes and determinations (201) to (205) are the same as the processes and determinations (101) to (105) in FIG. 32. In this step, the film formation process for the amorphous material α is performed. The next process (206) may or may not be performed at this time. In the determination (207), it is determined whether or not the total film thickness of the layer obtained by crystallizing the amorphous material α and the layer of the material β different from α has reached the design film thickness. If there is a layer in which the amorphous material α has not yet been crystallized, it is determined whether the total thickness of the α and β layers has not reached the designed thickness when the layer is crystallized. .

  In the next process (208), first, the temperature of the semiconductor substrate is set to a condition that allows the material β to be formed, and while maintaining the environment, the raw material gas of the material β is supplied to form the β layer. When the β layer is formed by chemical vapor deposition or the like, the source gas is supplied as described above. However, when the film is formed by sputtering or the like, ions such as argon gas are used instead of the source gas. The gas for accelerating and colliding with the target is supplied. Further, the β layer may be formed in an amorphous state or a crystalline state. In the determination (209), it is determined whether or not the β layer has reached the thickness to be formed at one time, and the loop of the processing (208) and the determination (209) is repeated until the thickness is reached. The next process (210) may or may not be performed at this time.

  In the determination (211), as in the determination (207), it is determined whether the total film thickness of the layer obtained by crystallizing the amorphous material α and the layer of the material β different from α has reached the designed film thickness. . If there is a layer in which the amorphous material α has not yet been crystallized, it is determined whether the total thickness of the α and β layers has not reached the designed thickness when the layer is crystallized. .

  In the determination (211), it is determined as No (determined that the total thickness of the α and β layers has reached the design value), and when the crystallization of all the amorphous materials has been completed, Proceed to the process (212), but if the judgment (211) is No, and there is still a layer that has not been crystallized, the layer that has not been crystallized before proceeding to the next process (212). Crystallize.

  That is, the treatment (206) and the treatment (210) are not necessarily performed every time because the layer of the amorphous material α is divided and deposited with the other material β layer, but the entire amorphous material is crystallized. In order to proceed to the process (212), the time of the last process (206) before moving to the process (212), the time of the last process (210) before moving to the process (212), or the process ( A step of crystallizing must be provided at least once immediately before 212).

  Even if the step of crystallizing the amorphous material described above is performed after each step of forming each divided amorphous material layer as shown in Example 2, the divided amorphous material layer by laser irradiation is used. Even if the local crystallization process is performed, it may be performed after the completion of the entire film formation process for reasons such as shortening the manufacturing process.

  Subsequent steps, processing (212), processing (213), and processing (214) are the same as the processing (112), processing (113), and processing (114) described in FIG. These processes, semiconductor substrate take-out temperature, for example, cooling to reach 20 ° C., and take-out from the semiconductor substrate manufacturing apparatus chamber, are all controlled by the automatic controller 36 using the manufacturing apparatus according to this embodiment. The process will be terminated.

  The process start temperature or the substrate take-out temperature does not have to be 20 ° C., and any temperature below the crystallization temperature may be used. Further, the temperature may be higher than the crystallization temperature. In this case, however, the process (202) in FIG. 34 cools the semiconductor substrate instead of heating at the time of film deposition. In the process (212) in FIG. Will do.

When the semiconductor device manufacturing apparatus described above is used, the manufacture of the semiconductor device having the low stress structure described in the first embodiment, the second embodiment, and the third embodiment according to the present invention can be performed in the same chamber. Since a consistent process can be performed by automatic control, a semiconductor device being manufactured can be efficiently performed without opening it to the atmosphere.
(Example 6)
Next, an embodiment relating to the manufacturing apparatus of the present invention will be described with reference to FIGS. FIG. 35 is a cross-sectional configuration diagram of a bipolar sputtering apparatus when a sputtering method is employed as a thin film forming method. The material target 41 to be deposited and the substrate 38 on which the film is deposited are opposed to each other, a DC or AC voltage is applied from the power source 39 between the target 41 and the substrate 38, and a discharge gas (for example, argon gas) introduced through the gas controller 34 is applied. Ar gas) is discharged.

  The substrate 38 is held by a holding unit (semiconductor substrate jig) 32 having a heating function. The temperature of the holding unit 32 is controlled by the temperature controller 40. The thin film deposition rate is adjusted by controlling the introduced gas pressure, the applied voltage, the substrate temperature, or the like by the controller 36.

  A method of controlling the thin film deposition rate and the substrate temperature in the controller 36 will be described with reference to FIG. FIG. 36 shows an example of time control of the thin film deposition rate V and the substrate temperature Ts when a thin film is deposited using the control device 36. At the start of thin film deposition, the substrate temperature Ts is kept sufficiently lower than the crystallization temperature.

  In this temperature state, the first film is deposited in a predetermined film thickness range defined by the failure event (L1). Thereafter, thin film deposition is stopped, and the substrate temperature Ts is raised to the crystallization temperature Tc or higher to complete the crystallization reaction of the deposited film (C1). However, in this crystallization, the temperature is controlled so that the growth is in the range of the primary recrystallization reaction, that is, the average grain size of the grown grains is about the deposited film thickness.

  After completion of the crystallization reaction, the substrate temperature Ts is lowered again to the crystallization temperature Tc or less, and the film deposition is resumed (L2). When the predetermined film thickness is reached, film deposition is stopped, and the substrate temperature Ts is raised to crystallize the second deposited film (C2). Stopping the deposition of the thin film can be achieved by stopping the application of the discharge voltage or reducing the voltage below the discharge critical voltage, stopping the introduction of the discharge gas, or controlling the gas pressure outside the discharge region. Further, the substrate heating can be realized by incorporating a heater or the like in the holding unit 32.

  In this embodiment, the film is deposited twice (L1 and L2). However, the number of times of film deposition is not necessarily limited to two, and may be performed as many times as necessary.

According to the present embodiment, in a manufacturing apparatus for depositing a thin film having a predetermined film thickness, a plurality of times of film deposition of a film thickness equal to or less than the maximum film thickness defined by the failure event and crystallization of each deposited film are performed. Since an apparatus that can continuously perform the process without taking the substrate out of the apparatus can be provided, there is an effect that it is possible to provide a manufacturing apparatus that deposits a thin film having a predetermined thickness with low stress without causing a failure event.
(Example 7)
Next, another embodiment of the thin film manufacturing method of the present invention will be described with reference to FIGS. 37, 38, 39, and 40. FIG. FIG. 37 shows a method for producing a laminated thin film according to this example.

  First, a base film (silicon oxide film) 5 is formed on the surface of the silicon substrate 4, an amorphous film into which an impurity of a predetermined concentration is introduced, for example, an amorphous silicon film is deposited in a film thickness range that does not cause a defective event, and then the crystal The chemical reaction is completed to obtain a polycrystalline silicon film 6 (first layer).

  In the amorphous silicon thin film of the second layer, as shown in FIG. 38, an impurity having a higher concentration than that of the first layer is introduced to complete the crystallization reaction, and the polycrystalline silicon film into which the high concentration of impurity is introduced. 6a is obtained. The impurity concentration in the third layer film is also set in the same manner as in the second layer, the film deposition and the crystallization reaction are completed, and the polycrystalline silicon film 6a into which the high concentration impurity is introduced is obtained. The fourth layer introduces impurities having the same concentration as the first layer, completes film deposition and crystallization reaction, and obtains a polycrystalline silicon film 6.

  According to this embodiment, a polycrystalline silicon thin film having a predetermined film thickness is obtained as a laminated thin film having a small grain size, so that a film can be formed in a low stress state and an impurity concentration gradient is formed in the film thickness direction. can do. Note that the number of films to be stacked is not necessarily four layers as described in this embodiment.

  Furthermore, the profile of the impurity introduced into each layer is not necessarily the profile as shown in FIG. 38, and an arbitrary profile can be formed according to the purpose.

  FIG. 39 shows a cross-sectional structure of a MOS transistor manufactured by applying the thin film manufacturing method of this embodiment. A case where phosphorus (P) is used as an impurity to reduce the electrical resistance may be considered. In this case, the P concentration of the first layer is controlled to a low concentration as shown in FIG. 38 in order to prevent phosphorus (P) from diffusing into the oxide film and causing deterioration of the oxide film quality as much as possible. Yes.

  In this embodiment, it is possible to reduce the stress by obtaining a polycrystalline silicon thin film as a gate electrode as a laminated thin film having a small crystal grain size, and the impurity concentration profile in the film thickness direction can be controlled according to the purpose. There is also an effect. Note that the number of stacked gate electrode films shown in this embodiment is not necessarily four. Also, the impurity profile may be other than that shown in FIG.

  FIG. 40 shows an example of a cross-sectional structure of a wiring thin film of a semiconductor device in which the thin film manufacturing method of this embodiment is applied to wiring film manufacturing. For example, when the impurity profile as shown in FIG. 38 is given, the electric resistances of the second layer and the third layer having a high impurity concentration are lower than those of the first layer and the fourth layer, and the current is selectively applied to the first layer. It will flow through the second and third layers. In this case, since Joule heat is mainly generated in these two layers, the temperature of the first layer or the fourth layer becomes relatively low, and surface diffusion of atoms considered to be a cause of electromigration is suppressed. As a result, the effect of prolonging the electromigration life can be expected.

Also in the present embodiment, the number of laminated film thicknesses in the film thickness direction is not necessarily four, and the impurity concentration profile may be other than that shown in FIG. Also in this embodiment, since a thin film having a film thickness direction impurity concentration profile controlled for a predetermined purpose can be obtained as a laminated thin film having a small particle size, there is an effect that a thin film structure can be provided in a low stress state that does not cause a failure event. is there.
(Example 8)
Next, an embodiment of the film thickness determination method of the present invention will be described with reference to FIGS. 41, 42, and 43. FIG. FIG. 41 shows a flowchart of the film thickness determination method of the present invention. The initial value of the film division number N is 1.

  Since there is a critical stress in each of the peeling and cracking of the film, which is a mechanical failure event caused by the stress of the film, and in the occurrence of dislocations in the single crystal substrate, in the process (300), the mechanical that occurs in the target process The critical stress σc corresponding to the failure event is determined. In the process (301), the required total film thickness Tt is determined from the cross-sectional area of the wiring or the like that satisfies the resistance value necessary for design, or the surface area that satisfies the capacitance value or the like.

  In the crystallization reaction or silicide reaction, as shown in FIG. 42, there is a correlation between the crystal grain size L after completion of the reaction and the stress σ generated in the film. The function f representing the relationship between the two is a function of the crystal grain size before and after the reaction, the Young's modulus of the film, and the like. In the process (302), the relationship σ = f (L) between the particle size and the film stress is grasped. Since there is a critical stress σc for film peeling and cracking, which is a mechanical failure event due to the stress of the film, or for the occurrence of dislocations in a single crystal substrate, the critical crystal grain size Lc depends on each failure event. Determined.

  In general, it is known that when a primary recrystallization reaction is caused in a thin film by heat treatment, the generated crystal grain size is about the film thickness. Therefore, considering this primary recrystallization reaction, the relationship between the film thickness and the generated stress can be known as shown in FIG. In the process (303), the relationship σ = g (T) between the film thickness and the generated stress is grasped. Similarly, the critical film thickness Tc corresponding to the critical stress σc of the mechanical failure event can be determined in accordance with each failure event. When the film thickness Tu per layer to be deposited is determined, the film generation stress σu per layer when an amorphous material layer having the film thickness is caused to undergo crystallization reaction or silicide reaction at a time is shown in FIG. Since it can be read immediately, it can be determined whether or not the generated stress σu causes a defective event.

  In judgment (304), it is judged whether the stress generated in the film is not more than the critical stress σc. When the generated stress is equal to or lower than the critical stress value of the failure event (when judged Yes in judgment (304)), the film may be deposited as it is to complete the crystallization reaction. In this case, the film thickness that can be formed at one time finally determined in the process (305) is Tu = Tt. However, when the generated stress is larger than the critical stress value at which the defective event occurs (when determined No in the determination (304)), it is necessary to consider the division of the film.

  When it is determined No in the determination (304), the process proceeds to the processing (306), and the number of film divisions is set to N = N + 1. In the process (307), the new film thickness Tu per layer is determined as Tu = Tt / N using the film division number N newly determined in the process (306). In the process (308), the film thickness and the occurrence of the film generation stress σu generated when the amorphous material layer having the film thickness Tu newly determined in the process (307) is crystallized are grasped in the process (303). It is obtained from the stress relationship σ = g (T).

  In the determination (309), it is determined whether or not the occurrence of a mechanical failure event is determined by the final residual stress of the film. If the occurrence of a defective event is determined by the final residual stress of the film (when it is determined Yes in the process (309)), the film generation stress = Nσu is determined and processed in the process (311). By repeating the loops (304) to (309) and (311), a condition (number of divisions) is obtained such that the sum Nσu of the stresses generated by the film divided into N layers does not exceed the critical stress value σc of the failure event. Repeat splitting until.

  In the case where the presence or absence of a defective event is not determined by the final residual stress of the film but is determined by the stress fluctuation per crystallization reaction or silicide reaction (determined as No in the processing (309)) In the process (310), the film generation stress = σu is repeated, and the loops of the determination and the processes (304) to (310) are repeated, and the generated stress σu for each film thickness divided into N layers is the critical stress for the occurrence of a defective event. A condition (number of divisions) that does not exceed the value σc may be selected.

  The loop of judgment and processing (304) to (309), (311) or the loop of judgment and processing (304) to (310) is terminated when the film generation stress <σc is judged in judgment (304). In the process (305), the final film thickness Tu per layer is determined (the Tu determined when the process (307) was last performed is applied as it is).

  In any case, the thickness of each divided film is not necessarily constant, and may be different. The optimum deposited film thickness can be determined by the above method. However, although not shown in FIG. 41, if the finite number of divisions N cannot be obtained or the number of divisions is not practical (for example, N = 10 or more), the required film thickness Tt is reviewed. Need to do.

  In this embodiment, when a thin film having a predetermined film thickness is obtained as a laminated structure by dividing the number of times of deposition in a low stress state that does not cause a failure event, the effect of easily determining the deposited film thickness per time is obtained. There is. The optimum range of particle diameter is 10 nm (nanometer) to 5 μm (micron), and the optimum range of film thickness is 10 nm to 1 μm.

1 is a cross-sectional perspective view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing of the 1st manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 2nd manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 3rd manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 4th manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 5th manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 6th manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 7th manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 8th manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 9th manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 10th manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 11th manufacturing process of the semiconductor device which concerns on 1st Example of this invention. It is sectional drawing of the 12th manufacturing process of the semiconductor device which concerns on 1st Example of this invention. FIG. 7 is an explanatory diagram of a manufacturing process of the semiconductor device according to the first example of the invention. It is a characteristic view which shows the example of a measurement of the relationship between the film thickness and crystallization stress in the amorphous silicon thin film explaining the effect | action of this invention. It is a cross-sectional perspective view of the semiconductor device based on 2nd Example of this invention. It is manufacturing process explanatory drawing of the semiconductor device which concerns on 2nd Example of this invention. It is sectional drawing of the semiconductor device which concerns on 3rd Example of this invention. It is sectional drawing of the semiconductor device which concerns on 3rd Example of this invention. It is sectional drawing of the semiconductor device which concerns on 3rd Example of this invention. It is sectional drawing of the semiconductor device which concerns on 3rd Example of this invention. It is sectional drawing of the semiconductor device which concerns on 3rd Example of this invention. It is sectional drawing of the semiconductor device which concerns on 3rd Example of this invention. It is sectional drawing of the semiconductor device which concerns on 3rd Example of this invention. It is sectional drawing of the semiconductor device which concerns on 3rd Example of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on 4th Example of this invention. It is a transmission electron micrograph which shows the structure of the crystal | crystallization in the cross section of the semiconductor device based on 4th Example of this invention. It is sectional drawing of the semiconductor device which concerns on 4th Example of this invention. It is sectional drawing of the semiconductor device which concerns on 4th Example of this invention. FIG. 10 is an explanatory diagram of a configuration of a semiconductor manufacturing apparatus according to a fifth embodiment of the present invention. FIG. 10 is an explanatory diagram of a configuration of a semiconductor manufacturing apparatus according to a fifth embodiment of the present invention. It is a flowchart explaining the control method of the semiconductor manufacturing apparatus which concerns on 5th Example of this invention. It is explanatory drawing of the temperature control method example of the semiconductor manufacturing apparatus which concerns on 5th Example of this invention. It is a flowchart explaining the manufacturing process control of the semiconductor manufacturing apparatus based on 5th Example of this invention. It is structure explanatory drawing of the semiconductor manufacturing apparatus based on 6th Example of this invention. It is explanatory drawing regarding the control method of the semiconductor manufacturing apparatus which concerns on 6th Example of this invention. It is sectional drawing in the manufacturing process of the semiconductor device based on 7th Example of this invention. It is explanatory drawing of the impurity concentration control method in the manufacturing method of the semiconductor device which concerns on 7th Example of this invention. It is sectional drawing of the semiconductor manufacturing apparatus based on 7th Example of this invention. It is sectional drawing of the semiconductor manufacturing apparatus based on 7th Example of this invention. It is a flowchart explaining the division | segmentation film thickness determination method of the laminated film in the manufacturing method of the semiconductor device which concerns on 8th Example of this invention. It is a characteristic view explaining the relationship between the crystal grain diameter and generated stress of the thin film which concerns on 8th Example of this invention. It is a characteristic view explaining the relationship between the laminated film thickness of the thin film which concerns on 8th Example of this invention, and generated stress.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,7 ... Semiconductor device, 2,8 ... Laminated structure gate electrode, 3 ... LOCOS, 4 ... p-type silicon semiconductor substrate, 5, 5a ... Silicon oxide insulating film, 6, 6a ... Divided polycrystalline silicon layer, 9 ... Divided Layers of materials different from the polycrystalline silicon layer, 11, 11a, 11b ... silicon nitride film, 12a, 12b, 12c, 12d, 12e ... photoresist, 13 ... divided amorphous silicon layer, 14 ... divided polycrystalline silicon layer laminated structure thin film 15 ... Alternately laminated thin films of polycrystalline silicon and other materials, 16 ... interlayer insulating film, 17 ... Al wiring layer, 18 ... insulating film, 19 ... metal silicide layer, 20 ... metal thin film layer, 31 ... chamber, 32 ... Semiconductor substrate jig, 33 ... Heating device, 34 ... Gas controller, 35 ... Exhaust device, 36 ... Automatic control device, 37 ... Laser irradiation device, 38 ... Semiconductor substrate, 39 Power, 40 ... temperature controller, 41 ... sputtering target.

Claims (4)

In a method for manufacturing a gate electrode having a conductive thin film on a semiconductor substrate,
Forming the conductive thin film of the gate electrode by repeating the step of depositing an amorphous layer and the step of crystallizing the deposited amorphous material a plurality of times in succession;
The method of manufacturing a gate electrode , wherein the step of depositing the amorphous layer uses a gas containing impurities to be included in the deposited amorphous material. In the manufacturing method of the gate electrode according to claim 1 ,
The method for manufacturing a gate electrode, characterized in that the gas disilane (Si 2 _{H 6)} and phosphine (PH ₃₎ in which vapor phase reaction of depositing the amorphous layer. In the manufacturing method of the gate electrode according to claim 1 or 2,
A method of manufacturing a gate electrode , characterized in that the impurity concentration in the amorphous layer deposited by being divided into a plurality of times is different between at least two layers of adjacently deposited layers. In the manufacturing method of the gate electrode according to any one of claims 1 to 3 ,
The step of crystallizing the amorphous material is a step of crystallizing the amorphous material by laser irradiation over the entire surface of the amorphous layer or selectively only in a local portion of the amorphous layer. A manufacturing method of a gate electrode .

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