JP4261845B2 - Load drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a load driving technique, and further to a technique for reducing power loss in a circuit for driving a capacitive load, for example, a technique effective when applied to a piezoelectric element driving circuit in an inkjet head.
[0002]
[Prior art]
In an ink jet head using a piezoelectric element (piezo element), a voltage is applied to the piezoelectric element to distort the piezoelectric element toward the pressure generating chamber, and ink is ejected from the nozzle hole by the pressing force.
[0003]
Piezoelectric elements are capacitive loads, and charge and discharge are repeated as many times as ink is ejected. However, the energy conversion efficiency of ejection is not necessarily high, and almost the same amount of energy may be lost as heat in one ejection. There is a forced rise in the package temperature.
[0004]
As a method of suppressing heat generation, energy recovery (power recovery) and loss energy suppression (power loss reduction) can be considered.
[0005]
In the power recovery, when the electric charge stored in the capacitive load is discharged, the electric charge is transferred to another capacitor (capacitor), and this electric charge is reused at the next charging time. Examples of documents describing this system include “Latest Plasma Display Technology” (published in 1996, published by ED Research, pages 107 to 111) and JP-A-11-170529.
[0006]
On the other hand, as a method for reducing power loss, in a printer head driving device using a piezo element, the back electromotive force of a coil is used to reduce the voltage applied to a charge or discharge switch to suppress loss energy. Japanese Patent Laid-Open No. 2001-63040 is an example of a document describing this.
[0007]
[Problems to be solved by the invention]
Piezoelectric elements are capacitive loads, and charge and discharge are repeated as many times as ink is ejected. However, the energy conversion efficiency of ejection is not necessarily high, and almost the same amount of energy may be lost as heat in one ejection. There is. For example, as shown in FIG. 2, a case is considered in which charging is performed by applying a rectangular wave voltage V to a series circuit of a capacitance C that is a capacitance of a piezoelectric element and a switch M formed by a p-channel MOS transistor. The value of the switch M using a p-channel MOS transistor varies depending on the gate voltage, but can be approximated by a resistor R as shown in FIG. In this specification, when multiplication is indicated by “*”, the energy stored in the capacity C during charging is (1/2) * C * V. ² However, the energy consumed by the resistor R is the same amount (1/2) * C * V ² It is. Even when the applied voltage V is set to the ground level and the capacitor C is discharged after charging the capacitor C, the energy consumed by the resistor R is (1/2) * C * V ² Therefore, the energy consumed by the resistor R through charging / discharging is not related to the resistance value but CV ² And lost as heat.
[0008]
As a means for suppressing this loss energy, there is power recovery used in a plasma display (PDP) that can be regarded as a capacitive load in the same way as a piezoelectric element of a printer. In a PDP adopting a system called AC type, it is necessary to charge and discharge a capacitor C that is regarded as a capacitance of the panel from 0 to Vo volts within a time period called a sustain period. At that time, power is collected. That is, a capacitor Css and an inductance L are provided separately from the capacitor C, the capacitor Css is charged in advance to a voltage of (1/2) * Vo, and the charge of the capacitor Css is obtained by using the natural vibration of the inductance L and the capacitor C. The charge is transferred from the capacitor C to the capacitor Css when the charge is transferred to the capacitor C and discharged. In this method, power recovery for reusing electric charges and power loss reduction using natural vibration are performed. By utilizing the natural vibration, the terminal voltage of the capacitor Css can be set to (1/2) Vo which is half of the voltage Vo to be applied to the capacitor C. Therefore, the current flowing through the line from the capacitor Css to the capacitor C through the inductance L can be obtained. The power loss can be reduced by the resistance component.
[0009]
As another means for suppressing the loss energy, there is a method of reducing the voltage across the resistor including the switch by using the back electromotive force of the inductance. Considering the case where the inductance L is inserted between the resistor R and the capacitor C as shown in FIG. 4, a back electromotive force is generated in the inductance L immediately after the start of charging, and the voltage across the resistor R is divided by the back electromotive force. Can only be made smaller. As a result, the loss energy, which is the time integral value of the product of the current flowing through the resistor R and the voltage applied to both ends, can be reduced. The power loss reduction in the power recovery described above is a special case of this method.
[0010]
The power recovery, the method for reducing power loss using natural vibration, and the method for reducing power loss using back electromotive force of inductance need to implement the inductance L, but manufacture an appropriate inductance inside the IC. Is difficult and needs to be provided outside. When the inductance L is externally mounted, if the number of channels of the print head is large, many mounting parts are required and it is difficult to realize the mounting. In addition, if the line resistance including the switch is large, the inductance L must be a large value, which increases the mounting component price.
[0011]
Further, in the power recovery, the power recovery capacity Css is approximately twice the capacity C (C * Vo = (1/2) * Css * Vo, ∴Css = 2C considering the movement of electric charge during discharge). When used for an inkjet head, about 2000 pF per channel is required. Even if a power recovery circuit can be realized by collecting a large number of channels and having one power recovery capacity ΣCss, the capacity ΣCss is placed outside the IC. When the charge is transferred from the external capacitor ΣCss to the capacitor C through the IC when necessary, the IC causes a power loss, which does not reduce the IC power loss.
[0012]
Furthermore, when the inventors of the present application have studied a load driving circuit that drives a capacitive load such as a piezoelectric element, when a voltage fluctuation occurs in the power supply line, noise is generated at the terminal of the capacitive load that is being driven. It has been found that capacitive loading results in an undesirable state. For example, in an ink jet printer using a piezoelectric element, if the terminal voltage of the piezoelectric element fluctuates while the piezoelectric element is being driven, the ink was suddenly changed to an ink-sucking state even though it was in an ink-discharging state until then. In such a case, the printing accuracy may be deteriorated.
[0013]
An object of the present invention is to provide a technique for reducing power loss.
[0014]
Another object of the present invention is to provide a technique for avoiding an undesired state caused by a power supply voltage fluctuation of a capacitive load.
[0015]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0017]
That is, the operation is enabled by supplying the power supply voltage, and the drive element for driving the capacitive load according to the input signal is compared with the terminal voltage of the capacitive load and the power supply voltage. A load driving circuit is configured to include a control logic for detecting fluctuations in the power supply voltage and controlling the driving element in a non-conducting state in accordance with the detection result.
[0018]
The drive of the capacitive load is stopped when the drive element is turned off through the control logic. This avoids undesired conditions due to power supply voltage fluctuations of the capacitive load.
[0019]
At this time, in order to reduce the power loss in the driving element, from the change curve of the terminal voltage of the capacitive load when a rectangular voltage waveform is applied to the series connection circuit of the capacitive load and the driving element. Voltage control means for controlling the power supply voltage waveform of the drive element when charging the capacitive load and the power supply voltage waveform of the drive element when discharging from the capacitive load. By providing, the power loss of the driving element, for example, the charging or discharging transistor is reduced as follows.
[0020]
In a series circuit of a capacitive load and a resistor, when charging a capacitor with a rectangular wave of voltage V, the loss energy of a resistor R (including a switch and a line resistor) connected in series to the capacitor C is (1 / 2) * C * V ² It is. If the charging voltage is divided into two voltage levels, a rectangular wave of 0 to (1/2) * V and a rectangular wave of (1/2) * V to V, the loss energy of the resistance is ( 1/2) * C * (1/2 * V) ² + (1/2) * C * (1/2 * V) ² = (1/4) * C * V ² And half of the previous. Further, when the applied voltage is divided into three stages, the energy loss is 1/3, and when the applied voltage is divided into four stages, it becomes 1/4. This reduction in power loss is obtained by reducing the current that flows when the applied voltage value is divided. In other words, it is obtained by reducing the voltage across the resistor.
[0021]
Furthermore, the voltage to be applied is divided innumerably into a linear voltage (when the horizontal axis is time and the vertical axis is voltage), the voltage rises diagonally from 0 to V volts and then maintains V volts. In some cases, significant loss energy loss can be expected. When a voltage is applied in a straight line, the approximate expression integrating the loss energy at the resistor R up to infinite time is (1/2) * C * V ² -(1/6) * V ² * (T / R) + O (T ² ). Here, T is the time until the linear voltage reaches 0 V to V volts, and the third term is T ² This is the approximate error term. As is apparent from this approximate expression, as the linear voltage time T is increased and R is decreased, the loss energy decreases. When T = 3 * R * C, the first term and the second term are offset, and the error term. The loss energy becomes very small. When T exceeds 3 * R * C, the sum of the first and second terms becomes negative, is subtracted from the error term, and approaches zero as much as possible. The current when this linear voltage is applied is (1 / T) * C * V * [1-exp (−t / (R * C))], and reaches a maximum value at t = T. That is, the resistance R does not exist in the coefficient representing the maximum value of current. This is because, by applying a gentle voltage with a slow rise from the charging curve of the capacity C when a rectangular wave is applied to the series circuit of R and C, the capacity is relatively increased (with respect to a gradual voltage rise). Is charged instantaneously, the voltage applied to both ends of the resistor becomes minute, and it is considered that the resistor R does not exist in the coefficient representing the maximum value of the current. Therefore, the reduction in power loss is caused by the decrease in current value, and the decrease in current value is considered to be caused by the decrease in voltage across the resistor R.
[0022]
What is required in the circuit according to the present invention is to gently increase the voltage applied to the series circuit of the capacitor C and the resistor R. Specifically, as described above, when the voltage waveform is applied in a rectangular shape to the series connection circuit of the capacitive load and its drive element, it becomes more gradual than the change curve of the terminal voltage of the capacitive load. Controlling the power supply voltage waveform of the drive element when charging the capacitive load and the power supply voltage waveform of the drive element when discharging from the capacitive load. If such a circuit is used, the power consumption of the IC can be reduced, and the heat radiation design of the printer head mounted with the IC, which has been required in the past, becomes easy. Since the motor output for operating the head can be reduced, the cost of the system can be reduced.
[0023]
Further, it is possible to provide a transistor capable of supplying the capacitive load with a voltage before being voltage-controlled by the voltage control means during a period when the driving element is non-conductive.
[0024]
Further, the power supply voltage is supplied to enable operation, and a drive element for driving a capacitive load according to an input signal and a series connection circuit of the capacitive load and the drive element have a rectangular voltage. A waveform of the power supply voltage of the drive element when charging the capacitive load and a discharge from the capacitive load so as to be gentler than the change curve of the terminal voltage of the capacitive load when the waveform is given. When the load drive circuit is configured to include a voltage control means for controlling the power supply voltage waveform of the drive element, the drive element can be a bipolar transistor. Since the bipolar transistor can be made non-conductive due to fluctuations, as in the case where the control logic is provided, undesired due to fluctuations in the power supply voltage of the capacitive load. To avoid the state, to achieve the object of the present invention that.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 5 shows a circuit to be compared with the load drive circuit according to the present invention.
[0026]
This circuit is configured to perform load driving for two piezoelectric elements in the printer head, and is not particularly limited. However, the printer print head IC 1 and a voltage control circuit 6 for controlling the voltage supplied to the printer print head IC 1 are provided. including.
[0027]
The printer printhead IC 1 includes load charging p-channel MOS transistors M1 and M3, a charge-side controller 2 for controlling the operation thereof, load discharge n-channel MOS transistors M2 and M4, and an operation thereof. And a discharge-side controller 3 for controlling. The MOS transistors M1 to M4 are examples of driving elements for driving the capacitive loads (CL1, CL2).
[0028]
A p-channel MOS transistor M1 and an n-channel MOS transistor M2 are connected in series, and the series connection node is coupled to the piezoelectric element CL1. A p-channel MOS transistor M3 and an n-channel MOS transistor M4 are connected in series, and the series connection node is coupled to the piezoelectric element CL2.
[0029]
The sources of the p-channel MOS transistors M1 and M3 are coupled to the input line LC3, and the high-potential power supply voltage is supplied to the p-channel MOS transistors M1 and M3 via the input line LC3. A control signal from the charging controller 2 is input to the gates of the p-channel MOS transistors M1 and M3, and the operations of the p-channel MOS transistors M1 and M3 are controlled by this control signal.
[0030]
The sources of the n-channel MOS transistors M2 and M4 are coupled to the input line LD3, and the low-potential-side power supply voltage is supplied to the n-channel MOS transistors M2 and M4 via the input line LD3. A control signal from the discharge-side controller 3 is input to the gates of the n-channel MOS transistors M2 and M4, and the operations of the n-channel MOS transistors M2 and M4 are controlled by this control signal.
[0031]
The voltage control circuit 6 includes a charge side voltage control circuit 61, a discharge side voltage control circuit 62, and a potential determining resistor Ra.
[0032]
The charging-side voltage control circuit 61 includes a charging reference voltage circuit 4 for forming a charging reference voltage, and an operational amplifier A1 for comparing the charging reference voltage formed by the charging reference voltage circuit 4 with the voltage of the line LC3. And a p-channel MOS transistor M9 controlled by the output of the operational amplifier A1. Power supply Vdd2 is coupled to line LC3 via p-channel MOS transistor M9. The output voltage of the charging reference voltage circuit 4 is transmitted to the inverting input terminal (−) of the operational amplifier A1 via the line LC2. When the output voltage of the charging reference voltage circuit 4 is changed so as to gradually increase with time, the on-resistance of the p-channel MOS transistor M9 is changed in accordance with the output signal of the operational amplifier A1, thereby causing the line The voltage level of the LC 3 is also gradually raised in response to the change with time of the output voltage of the charging reference voltage circuit 4.
[0033]
The discharge side voltage control circuit 62 includes a discharge reference voltage circuit 5 for forming a discharge reference voltage, and an operational amplifier A2 for comparing the discharge reference voltage formed by the discharge reference voltage circuit 5 with the voltage of the line LD3. And an n-channel MOS transistor M10 controlled by the output of the operational amplifier A2. The ground GND (low potential side power supply voltage) is coupled to the line LD3 via the n-channel MOS transistor M10. The output voltage of the discharge reference voltage circuit 5 is transmitted to the inverting input terminal (−) of the operational amplifier A2 via the line LD2. When the output voltage of the discharge reference voltage circuit 5 is changed so as to gradually decrease with time, the on-resistance of the n-channel MOS transistor M10 is changed in accordance with the output signal of the operational amplifier A2, whereby the line The voltage level of the LD 3 is also gradually lowered in response to the change with time of the output voltage of the discharge reference voltage circuit 5.
[0034]
By disposing a charging MOS switch in parallel with the MOS transistors M1 and M3 and disposing a discharging MOS switch in parallel with the MOS transistors M2 and M4 (both not shown), it is possible to drive a piezoelectric element exceeding two channels. It is possible.
[0035]
The voltage level of the power supply Vdd2 is not particularly limited, but is about 30V. In FIG. 5, a single power source of Vdd2 is used, but a configuration in which Vdd2 is the highest potential and the ground GND potential in the drawing is the lowest potential as two power sources is also conceivable.
[0036]
The printer print head IC 1 is controlled by a one-chip microcomputer. As input signals, there are a waveform signal of a low voltage Vdd 1 (3.3 V to 5 V) level and a waveform selection signal for each piezoelectric element (not shown). The waveform signal and the waveform selection signal for each piezoelectric element generate a charge / discharge timing control signal for each piezoelectric element as indicated by signals S1 and S2 in the figure by a logic circuit (not shown). Here, when the signals S1 and S2 change from the low level to the high level, the charging start timing is set, and when the signals S1 and S2 change from the high level to the low level, the discharge start timing is set.
[0037]
In order to reduce the number of external circuits of the IC, it is conceivable to use one external circuit for a plurality of piezoelectric elements. However, to charge n piezoelectric elements, one piezoelectric element is charged. N times the current is required. When charging, the line LC2 whose voltage is gradually boosted is directly connected to the sources of the p-channel MOS transistors M1 and M3, so that a power reduction effect can be obtained, but the operational amplifier A1 can obtain a current corresponding to a change in load. And the configuration of the p-channel type MOS transistor M9. The operational amplifier A1 and the p-channel MOS transistor M9, and the operational amplifier A2 and the n-channel MOS transistor M10 are so-called current amplification circuits.
[0038]
Focusing on the charging circuit of the piezoelectric element CL1, the drain of the p-channel MOS transistor M9 is connected to the source of the p-channel MOS transistor M1 intended to reduce power loss, and the drain of the MOS transistor M1 is connected to the piezoelectric element. By connecting to CL1, power loss in the p-channel MOS transistor M1 is reduced. Focusing on the discharge circuit, the drain of the MOS transistor M10 is connected to the source of the n-channel MOS transistor M2 intended to reduce power loss, and the drain of the MOS transistor M2 is connected to the piezoelectric element CL1. As a result, the power loss of the MOS transistor M2 can be reduced.
[0039]
By configuring the charging circuit and discharging circuit of the piezoelectric element CL2 in the same manner as described above, the power loss of the p-channel MOS transistor M3 and the n-channel MOS transistor M4 can be reduced.
[0040]
FIG. 6 shows the operation timing of the main part in the circuit shown in FIG.
[0041]
When the signals S1 and S2 change from the low level to the high level at time t1 in FIG. 6, the charging-side controller 2 changes the line LC1 signal from the high level to the low level, and also charges the p-channel MOS transistor for charging the piezoelectric element CL1. The p-channel MOS transistor M3 for charging M1 and the piezoelectric element CL2 is turned on. The discharge-side controller 3 changes the line LD1 from high level to low level and turns off the discharge n-channel MOS transistor M2 of the piezoelectric element CL1 and the discharge n-channel MOS transistor M4 of the piezoelectric element CL2.
[0042]
The charging reference voltage circuit 4 rises the voltage of the line LC2 in a straight line in response to the change of the signal of the line LC1. Here, assuming that the rise time of the line LC2 from 0 to 0.9 * Vdd2 volts is T, there is a relationship of T ≧ 3 * R * CL. Here, R is a resistance value obtained by converting the on state of the charging p-channel MOS transistor M1 or the p-channel MOS transistor M3, and CL is a capacitance value of the piezoelectric element CL1 or CL2. When M1 and M3 are simultaneously turned on as described here, R is a parallel combined resistance value of resistances obtained by converting the on states of the two MOSs, and CL is the piezoelectric element CL1 and the piezoelectric element CL2. Although it is a parallel composite capacity value, the value of 3 * R * CL is the same as when only M1 is turned on.
[0043]
The discharge reference voltage circuit 5 sets the line LD2 to high level in response to the line LD1 becoming low level. When the line LD2 becomes high level, the potential of the line LD2 becomes higher than the potential of the line LD3, so the output of the operational amplifier A2 decreases, the line LD3 also becomes high level, and M10 is turned off.
[0044]
When the line LC2 starts to rise linearly, the potential of the LC2 is higher than the potential of the line LC3, so the output of the operational amplifier A1 falls and the M9 is turned on, and the line LC3 rises linearly so as to have the same potential as the line LC2. Here, due to the response speed of the operational amplifier A1 and the presence of Vth of the p-channel MOS transistor M9, the voltage rise start of the line LC3 is delayed from that of the line LC2, and immediately rises to the voltage of the LC2 immediately after the M9 is turned on. Thereafter, it rises linearly following the trajectory of the line LC2.
[0045]
When the voltage of the line LC3 rises linearly, the piezoelectric element CL1 and the piezoelectric element CL2 are charged, and between the time t1 and the time t2, the p-channel MOS transistor M1 for charging the piezoelectric element CL1 and the piezoelectric element as described above. The power loss of the charging p-channel MOS transistor M3 for CL2 can be reduced.
[0046]
When the signals S1 and S2 change from the high level to the low level at time t2, the charging side controller 2 changes the line LC1 from the low level to the high level and turns off the p-channel MOS transistors M1 and M3. Further, the discharge-side controller 3 changes the line LD1 from the low level to the high level and turns on the n-channel MOS transistors M2 and M4.
[0047]
The charging reference voltage circuit 4 sets the line LC2 to low level in response to the line LC1 becoming high level. When the line LC2 becomes low level, the output of the operational amplifier A1 rises because the potential of LC2 is lower than the potential of line LC3, the line LC3 also becomes low level, and M9 is turned off.
[0048]
In response to the fact that the line LD1 becomes high level, the discharge reference voltage circuit 5 drops the line LD2 linearly.
[0049]
When the line LD2 falls linearly, the potential of LD2 becomes lower than the potential of LD3, the output of the operational amplifier A2 increases, M10 turns on, M2 and M4 turn on, and the piezoelectric elements CL1 and CL2 have almost the same potential. The line LD3 falls linearly so as to have the same potential as LD2. Also here, due to the response speed of the operational amplifier A2 and the presence of Vth of the p-channel MOS transistor M10, the voltage falling start of the line LD3 is delayed from that of the line LD2, and immediately falls to the voltage of the LD2 immediately after M10 is turned on. Thereafter, it falls linearly following the locus of the line LD2.
[0050]
When the voltage of the line LD3 falls, the piezoelectric elements CL1 and CL2 are discharged, and the power loss of M2 and M4 can be reduced as described above from time t2 to time t3.
[0051]
At time t3, the signals S1 and S2 change from low level to high level, and the same operation as at time t1 is performed.
[0052]
In the circuit configuration shown in FIG. 5, regardless of whether the piezoelectric elements CL1 and CL2 are charged or discharged at the same timing, when the piezoelectric elements CL1 and CL2 are charged or discharged at different timings, Fluctuation of the power supply voltage of the printer print head IC 1 is likely to occur, and if this occurs, noise is generated at the terminal of the piezoelectric element being driven, which may cause the piezoelectric element to be in an undesired state. For example, in FIG. 7, between time t1 and time t2, the piezoelectric elements CL1 and CL2 are charged or discharged at the same timing, and in such a case, normal operation is performed as in the case shown in FIG. However, after time t2 in FIG. 7, the timing at which the signals S1 and S2 rise from the low level to the high level is different, and the MOS transistor M1 is turned on faster than the MOS transistor M3, so that the piezoelectric element CL1. When the charging of the piezoelectric element CL2 starts thereafter, the operational amplifier A1 and the MOS transistor M9 cannot fully respond to such a load change, and the voltage level of the line LC1 is temporarily Noise is generated by being lowered. This phenomenon is called “charge sharing”. Such charge sharing, for example, causes an undesired state of sucking ink when the piezoelectric element is in a state of ejecting ink in an ink jet printer, and the ink dot diameter when performing gradation printing. The printing accuracy is deteriorated by affecting the print quality.
[0053]
Therefore, in order to prevent the charge sharing from occurring, the printer print head IC 1 is configured as follows.
[0054]
FIG. 1 shows a configuration example of a load driving circuit according to the present invention.
[0055]
The load driving circuit shown in FIG. 1 is greatly different from that shown in FIG. 5 in that control logic 11, 12, 13, 14 is provided in the printer print head IC1. The control logic 11, 12, 13, 14 compares the terminal voltage of the piezoelectric elements CL1, CL2, which is an example of a capacitive load, with the power supply voltage to the printer print head IC 1 (the voltages of the lines LC3, LD3). Thus, the fluctuation of the power supply voltage is detected, and the corresponding MOS transistors M1 to M4 are controlled to be in a non-conductive state according to the detection result.
[0056]
The control logic 11 is not particularly limited, but the comparator CO1 for comparing the terminal voltage of the piezoelectric element CL1 and the voltage of the line LC3, the output signal of the comparator CO1 and the signal from the charging controller 2 (in FIG. 5) OR gate OR1 for obtaining an OR logic with respect to the driving signal of M1).
[0057]
The control logic 12 is not particularly limited, but includes a comparator CO2 for comparing the terminal voltage of the piezoelectric element CL1 and the voltage of the line LD3, an inverter I1 for inverting the logic of the output signal of the comparator CO2, and this And an AND gate AN1 for obtaining an AND logic between the output signal of the inverter I1 and the signal from the charging controller 3 (corresponding to the drive signal of M2 in FIG. 5).
[0058]
The control logic 13 is not particularly limited, but the comparator CO3 for comparing the terminal voltage of the piezoelectric element CL2 and the voltage of the line LC3, the output signal of the comparator CO3, and the signal from the charging side controller 2 (in FIG. 5) OR gate OR2 for obtaining an OR logic with respect to the drive signal of M3).
[0059]
The control logic 14 is not particularly limited, but includes a comparator CO4 for comparing the terminal voltage of the piezoelectric element CL2 and the voltage of the line LD3, an inverter I2 for inverting the logic of the output signal of the comparator CO4, And an AND gate AN1 for obtaining an AND logic between the output signal of the inverter I2 and the signal from the charging controller 3 (corresponding to the drive signal of M4 in FIG. 5).
[0060]
The comparators CO1 to CO4 output a high level when the input potential of the non-inverting input terminal (+) is higher than the input potential of the inverting input terminal (−), on the contrary, the input of the non-inverting input terminal (+). A low level is output when the potential is lower than the input potential of the inverting input terminal (−) and when the input potentials of both input terminals are equal to each other. Accordingly, the MOS transistors M1 and M3 are turned on when the line from the charge side control 2 to the OR gates OR1 and OR2 is at a low level and the potential of the line LC3 exceeds the potential of the piezoelectric elements CL1 and CL2. The MOS transistors M2 and M4 are turned on when the line from the discharge side control 3 to the AND gates AN1 and AN2 is at a high level and the potential of the line LD3 is lower than the potentials of the piezoelectric elements CL1 and CL2.
[0061]
The operation of the above configuration will be described.
[0062]
First, the operation on the charging side will be described.
[0063]
The piezoelectric elements CL1 and CL2 are both discharged. When the potential of the line LC3 in FIG. 1 starts to rise, the output of the comparator CO1 becomes low level, and if the line from the charging controller 2 to the OR gate OR1 is low level, the MOS transistor M1 is turned on. If the line from the charge-side controller 2 to the OR gate OR2 is at a high level, the MOS transistor M3 is turned off. In this state, charging of the piezoelectric element CL1 is started, and the potential of the line LC3 is higher than the potential of the piezoelectric element CL1.
[0064]
During the charging of the piezoelectric element CL1, when the line from the charging controller 2 to the OR gate OR2 becomes low level, the MOS transistor M3 is turned on, and the charging of the line CL2 is started, the voltage of the line LC3 is changed to the MOS transistor M1, The piezoelectric elements CL1 and CL2 are supplied to the piezoelectric elements CL1 and CL2 through M3, so that they are charged. However, the operational amplifier A1 and the MOS transistor M9 cannot immediately respond to the increase in load, and therefore, the line The potential of LC3 is temporarily lowered.
[0065]
On the other hand, before the MOS transistor M3 is turned on, the electric charge stored in the piezoelectric element CL1 tends to move to CL2 via the MOS transistor M1, the line LC3, and the MOS transistor M3. In this case, the relationship among the potentials of the piezoelectric element CL1, the line LC3, and the piezoelectric element CL2 is as follows.
CL1 potential> Line LC3 potential> CL2 potential
[0066]
At this time, since the potential of the non-inverting input terminal of the comparator CO1 exceeds the potential of the inverting input terminal, the output of the comparator CO1 becomes high level and the MOS transistor M1 is turned off. Thereby, charging to the piezoelectric element CL1 is stopped. The piezoelectric element CL2 continues to be charged.
[0067]
When the potential of the line LC3 exceeds the potential of the piezoelectric element CL1, that is, when the terminal voltages of the piezoelectric elements CL1 and CL2 are substantially the same, the potentials of both input terminals of the comparator CO1 are the same. The output of the comparator CO1 becomes low level, the MOS transistor M1 is turned on, and charging of the piezoelectric element CL1 is resumed.
[0068]
Next, the operation on the discharge side will be described.
[0069]
The piezoelectric elements CL1 and CL2 are both charged. When the potential of the line LD3 starts to fall in this state, the output of the comparator CO2 becomes low level, and the MOS transistor M2 is turned on if the line from the discharge side controller 3 to the AND gate AN1 is high level. If the line from the discharge-side controller 3 to the AND gate AN2 is at a low level, the MOS transistor M4 is turned off. In this state, the discharge of the piezoelectric element CL1 is started, and the potential of the line LD3 becomes lower than the potential of the piezoelectric element CL1.
[0070]
During the discharge of the piezoelectric element CL1, the line from the discharge-side controller 3 to the AND gate AN2 is set to the high level to turn on the MOS transistor M4, and when the discharge of the piezoelectric element CL2 is started, the MOS transistor M2 and M4 are passed through. As a result, the accumulated charge in the piezoelectric elements CL1 and CL2 tends to be discharged to the line LD3. However, the operational amplifier A2 and the MOS transistor M10 cannot immediately respond to the increase in load, and the potential of the line LD3 is temporarily raised. .
[0071]
On the other hand, there is a potential difference between the piezoelectric elements CL1 and CL2, and the electric charge of the piezoelectric element CL2 tends to move to the piezoelectric element CL1 via the MOS transistor M4, the line LD3, and the MOS transistor M2. At this time, the relationship among the potentials of the piezoelectric element CL1, the line LD3, and the piezoelectric element CL2 is as follows.
CL1 potential <line LD3 potential <CL2 potential
[0072]
At this time, since the potential of the inverting input terminal of the input of the comparator CO2 is lower than the potential of the non-inverting input terminal, the output of the comparator CO2 becomes high level and the MOS transistor M2 is turned off. Thereby, the discharge from the piezoelectric element CL1 is stopped. The piezoelectric element CL2 continues to be discharged.
[0073]
When the potential of the line LD3 falls below the potential of the piezoelectric element CL1, that is, when the terminal voltages of the piezoelectric elements CL1 and CL2 become substantially the same potential, both input terminals of the comparator CO2 have the same potential, so that the comparator CO2 output Becomes low level, the MOS transistor M2 is turned on, and the discharge from the piezoelectric element CL1 is resumed.
[0074]
As a result of this operation, when the potentials of the lines LC3 and LD3 become undesired levels, the corresponding MOS transistors M1 to M4 are made non-conductive by the control logics 11 to 14, whereby the piezoelectric element CL1. , CL2 charging or discharging is temporarily stopped, for example, in an inkjet printer using a piezoelectric element, when the terminal voltage of the piezoelectric element is fluctuated during driving of the piezoelectric element Thus, it is possible to avoid an undesirable state of the piezoelectric elements CL1 and CL2, such as sudden ink suction state, which has been in the ink ejection state until then.
[0075]
FIG. 8 shows a configuration example of the charging reference voltage circuit 4.
[0076]
Since the p-channel MOS transistor MC1 and the resistor RC1 are a bias circuit, and the p-channel MOS transistor MC2 has the same gate potential as the p-channel MOS transistor MC1, the p-channel MOS transistor MC3 is turned on and n When the channel type MOS transistor MC4 is turned off, the same current as the p channel type MOS transistor MC1 flows through the p channel type MOS transistor MC2. First, when the input line LC1 is set to the high level, the p-channel MOS transistor MC3 is turned off, the n-channel MOS transistor MC4 is turned on to set the initial voltage of the capacitor CC1 to zero, and the input line LC1 becomes low level. The p-channel MOS transistor MC3 is turned on, the n-channel MOS transistor MC4 is turned off, and the capacitor CC1 is charged. The terminal voltage of the capacitor CC1 and the output line LC2 are boosted linearly from 0 volt to Vdd2.
[0077]
FIG. 9 shows a configuration example of the discharge reference voltage circuit 5.
[0078]
When a constant current circuit is formed by the n-channel MOS transistor MD1, the n-channel MOS transistor MD2, and the resistor RD1, the n-channel MOS transistor MD4 is turned on and the p-channel MOS transistor MD3 is turned off. The same current as that of the n-channel MOS transistor MD1 flows through MD2. First, the input line LD1 is set to low level, the n-channel type MOS transistor MD4 is turned off, the p-channel type MOS transistor MD3 is turned on to charge the capacitor CD1 to the power supply voltage Vdd2, and the input line LD1 becomes high level. At this time, the n-channel MOS transistor MD4 is turned on, the p-channel MOS transistor MD3 is turned off, and the capacitor CD1 is discharged. The terminal voltage of the capacitor CD1 and the output line LD2 are dropped linearly from Vdd2 to 0 volts.
[0079]
Next, another configuration example will be described.
[0080]
10 and 11 show another configuration example of the charging reference voltage circuit 4.
[0081]
If the output LC2 of the charging reference voltage circuit 4 generates a gentle curve from the charging voltage curve when a rectangular wave is input to the series circuit of the charging MOS and the piezoelectric element, the power loss reduction effect can be obtained. Therefore, the circuit shown in FIG. 10 is formed by combining the p-channel MOS transistor MC5, the n-channel MOS transistor MC6, the resistor RC2, and the capacitor CC2. An RC series circuit in which the capacitor CC2 is the same as the equivalent capacitance values of the piezoelectric elements CL1 and CL2, and the resistor RC2 is equal to or greater than the on-resistance value of the charging MOS transistor M1. The line LC1 is set to a high level in advance to turn on the n-channel MOS transistor MC6 and the capacitor CC2 is discharged. When the line LC1 goes to a low level, the p-channel MOS transistor MC5 is turned on and the capacitor CC2 is charged. A voltage is output from the line LC2.
[0082]
The circuit shown in FIG. 11 includes a p-channel MOS transistor MC6, n-channel MOS transistors MC7 and MC8, resistors RC3 and RC4, and capacitors CC3 and CC4. By charging the series circuit of the resistor RC4 and the capacitor CC4 with the voltage at the connection point between the resistor RC3 and the capacitor CC3, the RC2 stage circuit is used in order to bring it closer to a linear voltage as compared with the series circuit of the resistor RC. Yes. The capacitance CC4 is the same as the equivalent capacitance value of the piezoelectric element, the capacitance CC3 is equal to or greater than the equivalent capacitance value, and the combined resistance of the resistor RC3 and the resistor RC4 is equal to or greater than the on-resistance value of the charging MOS transistor M1 and approaches a linear voltage. . When the input LC1 is set to the high level in advance, the n-channel MOS transistor MC7 and the n-channel MOS transistor MC8 are turned on, the capacitors CC3 and CC4 are discharged, and when the line LC1 becomes the low level, the p-channel MOS The transistor MC6 turns on, charges the capacitors CC3 and CC4, and outputs a voltage from the line LC2.
[0083]
12 and 13 show another configuration example of the discharge reference voltage circuit 5.
[0084]
In FIG. 12, an RC series circuit is used, and in FIG. 13, an RC two-stage circuit is used. The capacitance value and resistance value are the same as those shown in FIGS.
[0085]
The configuration shown in FIG. 12 includes a p-channel MOS transistor MD5, an n-channel MOS transistor MD6, a resistor RD2, and a capacitor CD2. When the input line LD1 is set to a low level in advance, the p-channel MOS transistor MD5 is turned on to charge the capacitor CD2, and when the input line LD1 becomes a high level, the n-channel MOS transistor MD6 is turned on and the capacitor CD2 is turned on. The voltage at that time is discharged, and the voltage at that time is output from line LD2.
[0086]
The configuration shown in FIG. 12 includes p-channel MOS transistors MD7 and MD8, an n-channel MOS transistor MD6, resistors RD3 and RD4, and capacitors CD3 and CD4. When the input line LD1 is set to a low level in advance, the p-channel MOS transistor MD7 and the p-channel MOS transistor MD8 are turned on, the capacitors CD3 and CD4 are charged, and when the input line LD1 becomes a high level, n Channel type MOS transistor MD6 is turned on, capacitors CD3 and CD4 are discharged, and the voltage at that time is output from line LD2.
[0087]
In the circuit configuration shown in FIG. 1, when the on-timing of the MOS transistor M3 at the time of charging is just before the end of the charging period, the potentials of the piezoelectric elements CL1 and CL2 may not reach the voltage level of the power supply Vdd2. is there. This is also true for discharge.
[0088]
FIG. 14 shows a circuit configuration in which the potentials of the piezoelectric elements CL1 and CL2 reach the voltage level of the power supply Vdd2.
[0089]
The printer print head IC 1 shown in FIG. 14 differs greatly from that shown in FIG. 1 in that it includes a p-channel MOS transistor M 5, an n-channel MOS transistor M 6, and control logic 15 and 16. .
[0090]
The p-channel MOS transistor M5 has a source coupled to the power supply Vdd2, a drain coupled to the terminal of the piezoelectric element CL1, and a gate coupled to the control logic 15.
[0091]
The n-channel MOS transistor M6 has a drain coupled to the terminal of the piezoelectric element CL1, a source coupled to the ground GND, and a gate coupled to the control logic 16.
[0092]
The control logic 15 includes inverters N1 and N2 for inverting the output signal from the charge-side controller 2, an AND gate for obtaining an AND logic between the output signal of the OR gate OR1 and the inverter N1, and the output signal and the inverter N2. A combination gate ANR1 with a NOR gate that obtains a NOR logic with the output signal. The operation of the MOS transistor M5 is controlled by the output signal of the combination gate ANR1.
[0093]
The control logic 16 includes an inverter N3 for inverting the output signal of the AND gate AN1, an AND gate for obtaining an AND logic of the output signal of the inverter N3 and the output signal from the discharge controller 3, and the AND It includes a combination gate ANR2 of a NOR gate that obtains a NOR logic of the gate and the output signal from the discharge side controller 3, and an inverter N4 for inverting the output signal. The operation of the MOS transistor M6 is controlled by the output signal of the inverter N4.
[0094]
In FIG. 14, only the piezoelectric element CL1 is shown for convenience of explanation, but the piezoelectric element CL2 can be similarly realized.
[0095]
Next, the operation of the above configuration will be described.
[0096]
FIG. 15 shows the operation timing of the main part in FIG.
[0097]
When charging of the piezoelectric element CL2 is started during the charging of the piezoelectric element CL1, the input terminal of the inverter N1 is set to the low level, the input terminal of the inverter N2 is set to the high level, and the output signal of the OR gate OR1 turns off the MOS transistor M1. High level while doing. Only when the output signal of the OR gate OR1 is at a high level, the output signal of the combination gate ANR1 is at a low level, thereby turning on the MOS transistor M5.
[0098]
Next, when the charge-side controller 2 sets the input terminal of the inverter N1 to the high level and the input terminal of the inverter N2 to the low level, the MOS transistor M1 is turned off and the output signal of the combination gate ANR1 is set to the low level. As a result, the MOS transistor M5 is turned on. Thereby, the power supply voltage Vdd2 before voltage control by the charging side voltage control circuit 61 can be supplied to the piezoelectric element CL1.
[0099]
Similarly, when the discharge of the piezoelectric element CL2 is started during the discharge of the piezoelectric element CL1, the signal input from the discharge-side controller 3 to the AND gate of the combination gate ANR2 is high level, and the combination from the discharge-side controller 3 is the same. The signal input to the NOR gate of the gate ANR2 is set to the low level, and the output of the AND gate AN1 is set to the low level while the MOS transistor M2 is turned off. Only when the output signal of the AND gate AN1 is at the low level, the output of the combination gate ANR2 is at the low level, and the MOS transistor M6 is turned on.
[0100]
Next, when the signal input from the discharge-side controller 3 to the AND gate of the combination gate ANR2 is set to low level and the signal input from the discharge-side controller 3 to the NOR gate of the combination gate ANR2 is set to high level, the MOS transistor M2 is turned off, the output of the combination gate ANR2 is set to low level, and the MOS transistor M6 is turned on. Thereby, the power supply voltage (GND level) before the voltage control by the discharge side voltage control circuit 62 can be supplied to the piezoelectric element CL1.
[0101]
Since the MOS transistor M5 is thus conducted, the terminal potential of the piezoelectric element CL1 is made to reach the voltage level of the power supply Vdd2 even when the on-timing of the MOS transistor M3 is just before the end of the charging period during charging. Can do. Similarly, since the MOS transistor M6 is turned on, the terminal potential of the piezoelectric element CL1 can reach the ground GND level even when the on-timing of the MOS transistor M4 is just before the end of the charging period during discharging. it can.
[0102]
FIG. 16 shows another configuration example of the printer print head IC 1.
[0103]
The printer printhead IC 1 shown in FIG. 16 is largely different from that shown in FIG. 5 in that a p-channel MOS transistor M11 and an npn-type bipolar transistor coupled thereto are used instead of the p-channel MOS transistor M1. T1 is provided; instead of the n-channel MOS transistor M2, an n-channel MOS transistor M12 and a pnp bipolar transistor T2 coupled thereto are provided; instead of the p-channel MOS transistor M3, p A channel-type MOS transistor M13 and an npn-type bipolar transistor T3 coupled thereto are provided. Instead of the n-channel type MOS transistor M4, an n-channel-type MOS transistor M14 and a pnp-type bipolar transistor T4 coupled thereto are provided. Point A.
[0104]
By interposing the bipolar transistor in this way, even when the potential of the line LC3 is temporarily lowered during charging, no current flows from the piezoelectric element to the LC3, and charge sharing does not occur.
[0105]
When charging the piezoelectric element CL1, the MOS transistor M11 is turned on when the line from the charging controller 2 to the MOS transistor M11 is set to a low level. The relationship of the potential at this time is as follows.
LC3 potential> T1 base potential> CL1 potential
[0106]
As a result, the base current of the bipolar transistor T1 flows from the line LC3. As a result, the bipolar transistor T1 is turned on and the piezoelectric element CL1 is charged.
[0107]
When the potential of the line LC3 is temporarily lowered during this charging, the potential relationship is as follows.
LC3 potential = base potential of T1 <CL1 potential
[0108]
Because of this relationship, since the base current of the bipolar transistor does not flow, the bipolar transistor T1 is turned off, and therefore charge sharing between the piezoelectric elements CL1 and CL2 can be avoided.
[0109]
Further, the discharge operates as follows.
[0110]
When the line from the discharge-side controller 3 to the MOS transistor M12 is set to the high level, the MOS transistor M12 is turned on. The relationship of the potential at this time is as follows.
LD3 potential <T2 base potential <CL1 potential
[0111]
Accordingly, the base current of the bipolar transistor T2 flows from the piezoelectric element CL1, and as a result, the bipolar transistor T2 is turned on and the piezoelectric element CL1 is discharged. When the potential of the line LD3 rises temporarily during the discharge, the potential relationship is as follows.
LD3 potential = base potential of T2> CL1 potential
[0112]
Thereby, since the base current of the bipolar transistor does not flow, the bipolar transistor T2 is turned off, and charge sharing between the piezoelectric elements CL1 and CL2 is avoided.
[0113]
FIG. 17 shows another configuration example of the voltage control circuit 6.
[0114]
In the configuration example shown in FIG. 17, in the voltage control circuit 6, the power supply voltage supplied to the printer print head IC 1 is changed stepwise.
[0115]
From each tap of the voltage dividing resistor 18 formed by connecting a plurality of resistors R1 to Rn in series, a voltage obtained by dividing the voltage Vdd2 according to the resistance ratio is obtained. By sequentially selecting the tap voltage by the selection circuit 17, the voltage on the line LC3 can be changed so as to increase stepwise. Operation control of the selection circuit 17 is performed by a control circuit 19. In addition, the discharge side circuit can also be configured to sequentially decrease the voltage of the line LD3 stepwise by configuring as shown in FIG. Even if it does in this way, the effect similar to said example can be acquired.
[0116]
According to the above example, the following effects can be obtained.
[0117]
(1) When the output voltage of the charging reference voltage circuit 4 is changed so as to gradually increase with time, the on-resistance of the p-channel MOS transistor M9 is changed according to the output signal of the operational amplifier A1. Thus, the voltage level of the line LC3 is also gradually increased in response to the change with time of the output voltage of the charging reference voltage circuit 4. Further, when the output voltage of the discharge reference voltage circuit 5 is changed so as to gradually decrease with time, the on-resistance of the n-channel MOS transistor M10 is changed according to the output signal of the operational amplifier A2. The voltage level of the line LD3 is also gradually lowered in response to a change with time of the output voltage of the discharge reference voltage circuit 5. Since the voltage levels of the lines LC3 and LD3 are gradually changed in this way, it is possible to reduce the energy loss due to the resistance component connected in series with the capacitive load, thereby enabling the load drive circuit to Power loss can be reduced.
[0118]
(2) By detecting the fluctuation of the power supply voltage by comparing the terminal voltage of the piezoelectric elements CL1 and CL2 with the power supply voltage, and controlling the MOS transistors M1 to M4 to be in a non-conductive state according to the detection result, The driving of the piezoelectric elements CL1 and CL2 is stopped. Thereby, it is possible to avoid an undesired state caused by fluctuations in the power supply voltage of the piezoelectric elements CL1 and CL2.
[0119]
(3) By providing the MOS transistor M5 and making it conductive, the terminal potential of the piezoelectric element CL1 can reach the voltage level of the power supply Vdd2. Similarly, by providing the MOS transistor M6 and making it conductive, the terminal potential of the piezoelectric element CL1 can reach the ground GND level.
[0120]
Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.
[0121]
In the above description, the case where the invention made mainly by the present inventor is applied to the inkjet head which is the field of use behind the invention has been described. However, the present invention is not limited to this and is widely applied as a load driving circuit. can do.
[0122]
The present invention can be applied on condition that at least a drive element for driving a capacitive load is included.
[0123]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0124]
That is, when the power supply voltage is fluctuated, the drive of the capacitive load is stopped by turning the drive element into a non-conducting state, thereby avoiding an undesired state caused by the fluctuation of the power supply voltage of the capacitive load. Can do.
[0125]
Further, the capacitive load is charged so as to be more gradual than the change curve of the terminal voltage of the capacitive load when a rectangular voltage waveform is applied to the series connection circuit of the capacitive load and its drive element. By controlling the power supply voltage waveform of the drive element at the time of discharge and the power supply voltage waveform of the drive element at the time of discharging from the capacitive load, the loss energy of the resistance component connected in series to the capacitive load is reduced. Reduction can be achieved, thereby reducing power loss in the load drive circuit.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a configuration example of a load driving circuit according to the present invention.
FIG. 2 is a circuit diagram of a configuration example of a capacity charging circuit using a switch.
FIG. 3 is a circuit diagram of a configuration example of a capacity charging circuit in which the switch is regarded as a resistor.
FIG. 4 is a circuit diagram of a configuration example of a capacity charging circuit using a resistor and an inductance.
FIG. 5 is a circuit diagram of a configuration example of a circuit to be compared with a load driving circuit according to the present invention.
6 is an operation timing chart of the main part of the circuit shown in FIG. 5. FIG.
FIG. 7 is a timing chart showing a case where noise is generated at the terminal of the piezoelectric element being driven in the circuit configuration shown in FIG. 5;
FIG. 8 is a circuit diagram of a configuration example of a charging reference voltage circuit in the load driving circuit.
FIG. 9 is a circuit diagram illustrating a configuration example of a discharge reference voltage circuit in the load driving circuit.
FIG. 10 is a circuit diagram showing another configuration example of the charging reference voltage circuit.
FIG. 11 is a circuit diagram showing another configuration example of the charging reference voltage circuit.
FIG. 12 is a circuit diagram showing another configuration example of the discharge reference voltage circuit.
FIG. 13 is a circuit diagram showing another configuration example of the discharge reference voltage circuit.
FIG. 14 is a circuit diagram showing another configuration example of a printer print head IC in the load driving circuit.
FIG. 15 is an operation timing chart of the main part of the circuit shown in FIG. 14;
FIG. 16 is a circuit diagram showing another configuration example of the printer print head IC in the load driving circuit.
FIG. 17 is a circuit diagram illustrating a detailed configuration example of a main part in the load drive circuit.
[Explanation of symbols]
1 IC for printer print head
2 Charge-side controller
3 Discharge controller
4 Charge reference voltage circuit
5 Discharge reference voltage circuit
6 Voltage control circuit
11, 12, 13, 14 Control logic
15,16 Control logic
61 Charge side voltage control circuit
62 Discharge side voltage control circuit
CL1, CL2 Piezoelectric element

Claims (7)

A first drive element connected between the power supply line and the capacitive load;
A second drive element connected between the capacitive load and a current discharge line;
Control logic for controlling the operation of the first and second driving elements in response to an input signal,
The control logic controls the first driving element to be in a non-conductive state when the terminal voltage of the capacitive load is higher than the voltage of the current supply line during charging, and the terminal of the capacitive load during discharging. A load driving circuit configured to control the second driving element to a non-conducting state when a voltage is lower than a voltage of the current discharge line . A first drive element connected between the current supply line and the capacitive load so as to form a first series connection circuit with respect to the current supply line ;
A second drive element connected between the capacitive load and the current discharge line so as to form a second series connection circuit with respect to the current discharge line ;
Voltage control means for respectively controlling the voltage waveform of the current supplied to the current supply line and the current discharged from the current discharge line;
Control logic for controlling the operation of the first and second driving elements in response to an input signal,
Said voltage control means, when charging the capacitive load, the first series connection circuit increases slowly than rectangular variation curve of the voltage wave form of current supplied to be so that the said current When the voltage waveform of the current supplied to the supply line is controlled and discharged from the capacitive load , the change curve of the voltage waveform of the current discharged from the second series connection circuit is more gradual than the inverted rectangular shape. Is configured to control the voltage waveform of the current flowing in the current discharge line so as to decrease to
The control logic, when the terminal voltage of the capacitive load is higher than the voltage of the current supply line controls the first drive element non-conductive at the time of charge, the capacitive load of the terminal at the time of discharge A load drive circuit configured to control the second drive element to a non-conductive state when the voltage is lower than the voltage of the current discharge line . A third driving element connected between the power source and the capacitive load so as to form a third series connection circuit with respect to the power source as an input of the power source control unit; and an input of the power source control unit. A fourth drive element connected between the capacitive load and the ground so as to form a fourth series connection circuit with respect to a certain ground;
The control logic is configured such that, during charging , the third drive element is turned on and the terminal voltage of the capacitive load reaches a predetermined voltage of the power supply during a period in which the first drive element is turned off. In addition, during the discharge, the fourth drive element is turned on and the terminal voltage of the capacitive load is controlled to reach the ground potential during the period in which the second drive element is turned off. The load driving circuit according to claim 2, wherein the load driving circuit is configured as described above. A load driving circuit for controlling the charging and discharging current for the capacitive load in response to the input signal,
A first drive element including a bipolar transistor connected between the current supply line and the capacitive load so as to form a first series connection circuit with respect to the current supply line ;
A second drive element including a bipolar transistor connected between the capacitive load and the current discharge line so as to form a second series connection circuit with respect to the current discharge line;
Voltage control means for controlling a voltage waveform of a current supplied to the current supply line and a current waveform flowing in the current discharge line, respectively,
Said voltage control means, when charging the capacitive load, the first series connection circuit increases slowly than rectangular variation curve of the voltage wave form of current supplied to be so that the said current When the voltage waveform of the current supplied to the supply line is controlled and discharged from the capacitive load , the change curve of the voltage waveform discharged from the second series connection circuit is gradually lowered than the inverted rectangular shape. load driving circuit characterized by comprising configured to control the voltage waveform of the current flowing through the current discharge line to. A load driving circuit for controlling a charge / discharge operation performed through a common current supply line and a current discharge line for at least the first and second drive elements operating as a capacitive load,
A first charging drive element connected between the current supply line and the first drive target element, the current supply line, and the A second charge / discharge drive element connected between the second drive element;
A first discharge driving element connected between the current discharge line and the first drive target element, the current discharge line, and the A second discharge drive element connected between the second drive target element;
First control means for controlling currents flowing in the current supply line and the current discharge line, respectively;
Second control means for controlling the conduction state of each of the drive elements,
The first control means controls the voltage waveform of the current supplied to the current supply line so that the potential gradually rises over time during charging and changes to a predetermined high potential, and over time during discharging. It is configured to control the voltage waveform of the current discharged from the discharge current line so that the potential gradually decreases and reaches a predetermined low potential,
The second control means includes
In the operation in which charging for one of the first and second driving targets is started first and charging for the other driving target element is started with delay, the driving target element on the side that has started charging first When a state in which the terminal voltage is higher than the voltage of the current supply line is detected, the charging drive element on the side that has started charging is turned off to charge the drive target element that has started charging first. When the state where the terminal voltage of the driving target element on the side that has started charging first is lower than the voltage of the current supply line is detected, the charging to the driving target element that started charging first is detected. Configured to resume charging,
In the operation in which the discharge to one of the first and second drive target elements is started first and the discharge to the other drive element is started with a delay, the drive target element on the side that started the discharge first When a state in which the terminal voltage is lower than the voltage of the current discharge line is detected, the discharge drive element on the side where the discharge is started first is made non-conductive, and the discharge from the drive target element that started the discharge first is performed. Discharge to the drive element that started discharge first when it is detected that the terminal voltage of the drive target element on the side that has started discharge first is higher than the voltage of the current discharge line. A load driving circuit configured to resume the operation. 6. The load according to claim 5, wherein the first and second charging drive elements are constituted by p-channel MOS transistors, and the first and second discharge drive elements are constituted by n-channel MOS transistors. Driving circuit. During the period in which the first or second driving element is non-conductive, charging or discharging of the capacitive load is temporarily stopped,
The control logic further turns on the first driving element to resume charging to the capacitive load when the terminal voltage of the capacitive load becomes lower than the voltage of the current supply line during charging. In the discharge, when the terminal voltage of the capacitive load becomes higher than the voltage of the current discharge line, the second drive element is turned on to resume the discharge from the capacitive load. 3. The load driving circuit according to claim 1, wherein the load driving circuit is configured to control the load driving circuit.

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