JP4256745B2 - Optical information reader - Google Patents

Description

Detailed Description of the Invention

  The present invention relates to an optical information reading apparatus that reads information to be read, which is composed of portions having different light reflectivities such as bar codes and two-dimensional codes.

As is well known, an optical information reader, such as a barcode scanner, projects a laser beam or the like on a barcode image composed of a black bar (or simply a bar) and a white bar (or space) and reflects the laser beam. The code information is read by receiving light and applying electrical processing. During the electrical processing, a binarization processing circuit that converts an initial signal, which is an electrical analog signal photoelectrically converted by the light receiving element, into a digital signal greatly affects the reading accuracy of the scanner.
As the binarization processing circuit, a tracking method using a diode and a differentiation method using a differentiation circuit are generally used.
<Conventional example of follow-up method>

An example of a binarization processing circuit using a diode slice circuit will be described as the tracking method. FIG. 25 is a circuit diagram showing a configuration example thereof, and FIG. 26 is a waveform diagram showing the operation thereof. This is disclosed in Patent Document 1.
In this example, as shown in FIG. 41, the binarization processing circuit 100 that converts an electrical analog signal from a line image sensor (not shown) into a digital signal is the reverse of the analog signal being input to the connection point No. A peak rectification hold circuit 101 composed of a series circuit of a pair of diodes D1, D2 and a peak hold capacitor C1 connected in parallel and a gamma correction capacitor C2 are connected in parallel with the pair of diodes D1, D2. A gamma correction circuit 102, a series circuit of a resistor R1 and a capacitor C3, an injection component adjustment circuit 103 connected in parallel to the peak hold capacitor C1, a comparator 104 connected to a feedback resistor R4, and the comparator 104 A resistor R2 for applying a DC offset voltage to the non-inverting input terminal (+) and a DC power source Vcc Consisting of that DC offset circuit 105 Metropolitan.

The inverting input terminal (−) of the comparator 104 is connected to a connection point N1 on the input side of the pair of diodes D1 and D2 via the resistor R3, and the inverting input terminal (+) is connected to the pair of diodes D1 and D2. It is connected to a connection point N ₁ with the peak hold capacitor C ₁ , receives an analog signal Si, and outputs a binarized signal Do from the output terminal of the comparator 104.
A waveform CH1 shown in FIG. 26 is an actual measurement value (voltage) of the analog signal to be sliced, that is, an actual measurement value of the analog signal Si input to the connection point No in FIG.

The waveform CH2 is a signal that follows the input analog signal CH1, and is a slice signal generated by the wideband wide dynamic range slice signal generation unit that includes each circuit excluding the comparator 104 in FIG. 25 based on the input analog signal CH1. Sc.
The waveform CH4 is a binary signal (voltage) Do that is the output of the comparator 104 shown in FIG. 25, that is, a digital signal obtained by slicing the input analog signal Si of the waveform CH1 with the slice signal Sc of the waveform CH2 and binarizing it. It is. Each time the input analog signal Si (waveform CH1) and the slice signal Sc (waveform CH2) are interlaced and the magnitude relationship between the two is reversed, the binary signal Do (waveform CH4) that is the output signal of the comparator 104 is displayed. ) Is inverted from the low level to the high level or from the high level to the low level.
<Conventional example of differential expression>

An example of the differential binarization processing circuit is disclosed in Patent Document 2.
FIG. 27 is a block circuit diagram showing the configuration of the binarization processing circuit. In the binarization processing circuit 200, a photodiode 202 that converts reflected light from the barcode 201 illuminated by a laser beam or the like into an analog electrical signal, an amplification unit 203 that amplifies the electrical signal, and an amplification thereof. A differential unit 204 for differentiating the received signal to detect its change point, a peak hold circuit 205 for separating the noise of the differential signal and the signal, and the amplitude of the differential signal output from the peak hold circuit 205 by a predetermined ratio The voltage dividing circuit 206 that outputs the slice level for binarization and the output signal of the differentiation unit 204 and the slice level output from the voltage dividing circuit 206 are compared, and the white gate signal (W− GATE), the output signal of the differentiation unit 204, and the slice level output from the voltage dividing circuit 206. Compared with shift circuit 208 with an amount shifted slice level, a comparator 209 for outputting a black gate signal (B-GATE).

  Here, the case where the output signal of the differentiating unit 204 is equal to or higher than the slice level is valid, and the signal equal to or lower than the slice level is determined as noise. In this example, an additional peak hold circuit 210 that varies the slice ratio in correlation with the magnitude of the signal amplitude is connected in parallel with the peak hold circuit 205.

          JP 2000-306085 A           JP 2001-28045 A

Problems to be solved by the invention

  Here, in the former binarization processing circuit of the follow-up method, the binarized signal changes at the apex from the rise to the fall of the waveform of the output signal or at the apex from the fall to the rise. In the waveform CH1 shown in FIG. 26, the raised portion like the shoulder corresponds to it. If the waveform of the bar code bar to space or the part from space to bar is symmetrical, the ratio of bar to space will not be affected, but if the waveform is distorted due to signal sag or noise superimposition, the binarized signal Since the change point becomes asymmetrical, the bar becomes thicker or conversely thinner, which may cause a problem that reading cannot be performed normally.

  Also, in the latter differential processing binarization processing circuit, different from the tracking method, attention is paid to the fact that the bar and space change points of the barcode signal correspond to the peak value of the differential waveform of the barcode signal. . However, this differentiation method is easily affected by noise, and an abnormal binarized signal may occur due to the noise, and may not be read normally.

  The present invention has been made to solve such a problem in the optical information reading apparatus, and removes the influence of noise by the binarization processing means not based on the two conventional methods described above. The object of the present invention is to improve the reproducibility of the space ratio so that the information can be read accurately even if the object to be read is a low PCS barcode or a high-definition barcode with a small signal level.

Means for solving the problem

  An optical information reading apparatus according to the present invention includes a light receiving unit that irradiates a reading target composed of portions having different light reflectances, receives the reflected light, and performs photoelectric conversion, and a current signal photoelectrically converted by the light receiving unit. Is converted into a voltage signal, an electrical filter that passes and outputs a signal in the required frequency band of the voltage signal, a differentiation unit that differentiates the output signal of the electrical filter, and a differential signal ( In order to achieve the above object, in the optical information reading apparatus comprising a binarization processing unit that performs signal processing based on Vdef) and outputs a binarized signal, the binarization processing unit is as follows: It is configured.

That is, the differential signal (Vdef) and positive and negative slice levels (Vws, Vbs) for removing a noise signal having a predetermined amplitude or more are compared, and the positive transition in which the voltage signal shifts from the negative level to the positive level. Edge candidate area signal generation unit that generates edge candidate areas signals (Vwe, Vbe) for positive transition and negative transition indicating ranges including edge candidates and negative transition edge candidates that shift from a positive level to a negative level. (21, 22),
Each slice level (Vwps, Vbps) obtained by dividing a signal obtained by peak-holding each edge candidate area signal (Vwe, Vbe) is compared with the differential signal (Vdef), and the positive transition edge and Edge candidate signal detection units (23, 24) for detecting edge candidate signals (Vwe2, Vbe2) that are candidates for negative transition edges;
The rising edge of the positive transition edge candidate signal (Vwe2) within the valid period of the positive transition edge candidate area signal (Vwe) and the negative transition within the valid period of the negative transition edge candidate area signal (Vbe). A binarization signal generating unit that generates a binarized signal by determining a falling edge of the edge candidate signal (Vbe2) as an edge of a negative level and a positive level of the voltage signal. Constitute.

Further, an integration circuit that integrates the differential signal (Vdef) for each valid period of the edge candidate area signals (Vwe, Vbe) of the positive transition and the negative transition and outputs an integral signal; A positive / negative slice level (Vs5, Vb6) for removal is compared with each other, and a acceptance / rejection determination signal generation unit that generates acceptance / rejection determination signals (Vdw, Vdb) for positive transition and negative transition is provided.
When the binary signal generation unit determines that the rising edge of the positive transition edge candidate signal (Vwe2) and the falling edge of the negative transition edge candidate signal (Vbe2) are the negative level and positive level edges of the voltage signal. In addition, the determination state of the positive / negative transfer acceptance / rejection determination signals (Vdw, Vdb) may be added as a condition.

Further, the differential signal (Vdef) is detected and its level is measured, and the positive and negative slice levels (Vws, Vbs) used in the edge candidate area signal generation unit are changed according to the level. A slice level control signal generation unit that generates a level control signal may be provided.
The slice level control signal generation unit detects a differential signal (Vdef), performs A / D conversion on the signal to obtain a digital value, and performs sampling from a higher level for each predetermined number of samplings during the A / D conversion. The n values are stored, the average value Vave of the n values is taken, and compared with the specified value Vsre. When the specified value Vsre> the average value Vave, the control signal for increasing the slice level is set to the specified Vsre. In the case of ≦ average value Vave, the control signal for lowering the slice level can be configured by means for generating each control signal.

Furthermore, in these optical information readers, a gain control amplifier that is inserted on the input side of the differentiation unit and amplifies the voltage signal, and the gain control according to the amplitude of the differentiation signal (Vdef). It is more preferable to provide an amplifier gain control unit that generates a control signal for controlling the gain of the amplifier.
The amplifier gain control unit may generate a control signal for controlling the gain of the gain control amplifier according to the level of the differential signal (Vdef) measured by the slice level control signal generation unit.

Preferred embodiments of the present invention will be described below with reference to the drawings.
[First embodiment]
First, a first embodiment of the optical information reading apparatus according to the present invention will be described. FIG. 1 is a block diagram showing the circuit configuration.
The optical information reading apparatus shown in FIG. 1 includes a front part 10 and a rear part 20.

  The front-stage unit 10 receives a reflected light when a light beam is projected onto a reading target composed of portions having different light reflectivities such as a bar code, and the like. Connected to the I / V amplifier 12 that is a signal conversion unit that converts the photoelectric current photoelectrically converted into a voltage signal, and the I / V amplifier 12 that is connected to the I / V amplifier 12 and has a predetermined frequency band in the converted voltage signal. A low-pass filter 13 that is an electrical filter for passing only a signal and removing unnecessary high-frequency noise, and a differentiation circuit 14 that is a differentiation unit for differentiating a voltage signal that has passed through the low-pass filter 13. It is configured.

The differentiating circuit 14 is a simple CR differentiating circuit comprising a capacitor C10 and a resistor R10 as shown in FIG. 2 (a), or an operational amplifier OP as shown in FIG. 2 (b) and its inverting input terminal in series. What is necessary is just to use the differentiation circuit etc. which consist of the connected capacitor | condenser C11, input resistance R11, and feedback resistance R12 connected between the non-inverting input terminal and output terminal of operational amplifier OP.
Here, an example of an actual signal waveform in the pre-stage unit 10 is shown. FIG. 3 shows the waveform of a signal that has been subjected to photoelectric conversion by the I / V amplifier 12 and from which noise has been removed by the low-pass filter 13. A differential signal Vdef obtained by differentiating this signal by the differentiation circuit 14 has a waveform as shown in FIG. The differential signal Vdef is input to the rear stage unit 20.

Next, the rear stage 20 will be described. The post-stage unit 20 is a binarization processing unit that performs signal processing based on the differential signal def that is an output signal of the differentiation circuit 104 and outputs a binarized signal.
1 includes a white side (positive transition) edge candidate area signal generation unit 21, a black side (negative transition) edge candidate area signal generation unit 22, a white side (positive transition) edge candidate signal detection unit 23, and A black side (negative transition) edge candidate signal detection unit 24 and a binarized signal generation unit 25 to which output signals of these units are input.

Here, in order to accurately binarize the voltage signal having the waveform shown in FIG. 3 that has been photoelectrically converted by the I / V amplifier 12 and from which noise has been removed by the low-pass filter 13, the amplitude of the voltage signal is changed. “Positive transition edge” that shifts from the negative level (corresponding to the black bar part of the barcode) to the positive level (corresponding to the white space part of the barcode) with the center as 0 level, and transition from the positive level to the negative level It is necessary to accurately detect the “negative transition edge”. For this purpose, this voltage signal is differentiated to generate a differential signal Vdef shown in FIG. However, although the differential signal includes candidates for the positive transition edge and the negative transition edge, it is not possible to accurately extract each edge with this differential signal alone.
Therefore, in each embodiment of the present invention, each signal generation unit as described above is provided. However, as shown in FIGS. 3 and 4, the positive level side of the voltage signal or the differential signal is set to “white side”, and the negative side is set to negative. The level side is referred to as “black side”, the positive transition edge is referred to as “white side edge”, and the negative transition edge is referred to as “black side edge”. This designation will be used in the following description.
<Edge candidate area signal generation units 21 and 22>

The white side edge candidate area signal generation unit 21 includes a comparator 211 and a slice level generation circuit 212, and the black side edge candidate area signal generation unit 22 includes a comparator 221 and a slice level generation circuit 222.
The differential signal output from the differentiation circuit 104 is input to the comparator 211 of the white side edge candidate area signal generation unit 21 and the comparator 221 of the black side edge candidate area signal generation unit 22.

The white side comparator 211 compares the input differential signal with the white side slice level (constant voltage: 2.8 V, for example) from the slice level generation circuit 212, and outputs a white side edge candidate area signal. The black-side comparator 221 compares the input differential signal with the black-side slice level (constant voltage: for example, 2.3 V) from the slice level generation circuit 222, and outputs a black-side edge candidate area signal. Each of these edge candidate area signals is input to the binarized signal generation unit 25.
The relationship between these signals is shown in FIG. Vdef is a differential signal, Vws is a white side slice level output from the white side slice level generation circuit 212, and Vbs is a black side slice level output from the black side slice level generation circuit 222. Vwe represents the output signal of the white-side comparator 211, and Vbe represents the output signal of the black-side comparator 221.

  Here, the slice level is set to a constant voltage, and Vws = 2.8V and Vbs = 2.3V. Also, in order to binarize the differential signal for reading the barcode, the edge position of the barcode must be obtained. It can be considered that the steepest rising edge of the waveform of the output signal of the low-pass filter 13 shown in FIG. 3 shows the boundary between the bar and the space well. Since the position with the steepest inclination corresponds to the maximum position of the waveform of the differential signal Vdef shown in FIG. 5, if a binarized signal that changes at this maximum position is generated, the differential signal for reading the barcode can be accurately converted into two. It can be priced.

When the differential signal Vdef is greater than the white slice level Vws and may include a change point from white to black, the white side comparator 211 sets the output signal, that is, the white side edge candidate area signal Vwe to “1”. On the other hand, when the differential signal Vdef is smaller than the white side slice level Vws and there is no possibility of including a change point from white to black, an operation of setting the output signal Vwe to “0” is performed.
When the differential signal Vdef is smaller than the black slice level Vbs and may include a change point from black to white, the black-side comparator 221 outputs the output signal, that is, the black-side edge candidate area signal Vbe. Conversely, when the differential signal Vdef is larger than the black slice level Vbs and there is no possibility of including a change point from white to black, the operation of setting the output signal Vbe to “1” is performed. .

Furthermore, the white side edge candidate area signal Vwe output from the white side comparator 211 is also sent to the peak hold circuit 232 of the white side edge candidate area signal detection unit 23 as the black side edge candidate output from the black side comparator 221. The area signal Vbe is also input to the peak hold circuit 242 of the black edge candidate signal detection unit 24, respectively.
<Edge candidate signal detectors 23 and 24>

  The white-side edge candidate signal detection unit 23 includes a comparator 231, a peak hold circuit 232, and a slice level generation circuit 233. The black edge candidate signal detection unit 24 includes a comparator 241, a peak hold circuit 242, and a slice level generation circuit 243.

  The differential signal Vdef output from the differentiating circuit 14 is also input to the comparator 231 and the peak hold circuit 232 of the white side edge candidate area signal detecting unit 23. The peak hold circuit 232 holds the peak of the differential signal Vdef, and inputs the peak hold signal Vwph to the slice level generation circuit 233. The slice level generation circuit 233 obtains the slice level of the peak hold signal Vwph and inputs the slice level Vwps to the comparator 231. The comparator 231 compares the differential signal Vdef and the slice level Vwps, and inputs the white-side edge candidate signal Vwe2 that is the comparison output signal to the binarized signal generation unit 25.

Here, the peak hold circuit 232 is a circuit as shown in FIG. 11A, and includes two operational amplifiers X1 and X2, two diodes D3 and D4, a switch circuit SW1, and two resistors. R21, R22, a capacitor C21, and a power source E1.
The white-side peak hold circuit 232 operates as follows.
First, the white edge candidate area signal Vwe is applied to the switch circuit SW1. At this time, when the white side edge candidate area signal Vwe becomes “H”, the switch circuit SW1 is turned OFF, and when the white side edge candidate area signal Vwe becomes “L”, the switch circuit SW1 is turned ON.

The capacitor C21 is a capacitor for holding the white-side peak hold signal voltage, and this peak-hold voltage is output as a white-side peak hold signal via the operational amplifier X2 and at the negative input terminal of the operational amplifier X1 via the resistor R21. Is input.
When the differential signal Vdef becomes larger than the slice level for the white side differential signal and the white side edge candidate area signal Vwe becomes “H”, the switch circuit SW1 is turned OFF, the diode D3 is activated, and the peak detection mode is set. .
In this peak detection mode state, when the voltage of the differential signal Vdef becomes larger than the white peak hold signal voltage, the output of the operational amplifier X1 rises, so that the diode D3 becomes conductive, and as a result, the capacitor C1 is charged by the operational amplifier X1. As a result, the terminal voltage rises.

The terminal voltage of the capacitor C1 is fed back to the negative input terminal of the operational amplifier X1 via the buffer amplifier X2 and the resistor R21, and is always compared with the positive input terminal to which the differential signal Vdef is input. Follows the rise in the voltage of the differential signal Vdef.
On the contrary, when the voltage of the differential signal Vdef becomes smaller than the white side peak hold signal voltage, the output of the operational amplifier X1 falls and the diode D3 is turned OFF. As a result, the terminal voltage of the capacitor C21 is maintained as it is. The diode D4 is for preventing the operational amplifier X1 from being saturated at this time.
In this way, the capacitor C21 holds the peak value of the differential signal Vdef during the peak detection mode period (in the white edge candidate area).

On the other hand, when the differential signal Vdef becomes smaller than the white differential signal slice level and the white edge candidate area signal Vwe becomes “L”, the switch circuit SW1 is turned ON, the diode D3 is short-circuited, and the peak hold circuit follows. It becomes a mode.
In this mode, since the diode D3 is short-circuited, the output of the operational amplifier X1 is directly applied to the input of the operational amplifier X2, and the operational amplifier X2 outputs a signal having the same voltage waveform as that of the differential signal Vdef.
Thus, the peak value of the differential signal Vdef with respect to the white side edge candidate signal Vwe is output as the white side peak hold signal Vwph. The waveform is shown in FIG.

The slice level generation circuit 233 includes a voltage dividing circuit including two voltage dividing resistors Ra and Rb as shown in FIG.
In the white side edge candidate signal detection unit 23, the comparator 231 obtains the maximum value of the differential signal Vdef. The maximum value of the differential signal is defined as “the position where the differential signal level is 90% or less of the peak hold signal level, for example, where the maximum value of the differential signal level is given”. The same applies to the black edge candidate signal detection unit 24 described later. Even in this case, the white side and black side positions have the same amount of delay, and the relative positions of the white / black edge positions do not change, so they may be used instead of the true maximum positions.

The white-side peak hold signal Vwph output from the white-side peak hold circuit 232 is sent to the slice level generation circuit 233, and a voltage of 90% of the peak hold signal level is output as the white-side peak position detection slice level Vwps. .
The slice level Vwps is input to the peak position detection comparator 231 and compared with the differential signal Vdef. The white edge candidate signal Vwe2 is output from the comparator 231 and input to the binarized signal generator 25.
FIG. 8 shows the relationship between the white-side peak position detection slice level Vwps and the white-side edge candidate signal Vwe2. The rising edge of the white side edge candidate signal Vwe2 corresponds to the edge position from black to white of the barcode pattern.

  The differential signal Vdef is also input to the peak position detection comparator 241 and the peak hold circuit 242 of the black edge candidate signal detection unit 24. The peak hold circuit 242 holds the peak of the differential signal Vdef, and inputs the peak hold signal Vbph to the slice level generation circuit 243. The slice level generation circuit 243 obtains the slice level of the peak hold signal Vbph, and inputs the slice level Vbps to the comparator 241. As a result, the comparator 241 compares the differential signal Vdef with the slice level Vbps, and inputs the black side edge candidate signal Vbe2 as a comparison output signal to the binarized signal generator 25.

  The black side peak hold circuit 242 is configured as shown in FIG. In this circuit, the diode D3 and the diode D4 are connected in the opposite polarity to the case of the white-side peak hold circuit 232 shown in FIG. 5A, and the capacitor C21 has a negative signal peak value. Since the same operation is performed with the same configuration as that of the white-side peak hold circuit 232, the same reference numerals are given to the portions corresponding to (a) of FIG. Is omitted.

The black edge candidate area signal Vbe described above is input to the black peak hold circuit 242 so that the minimum value of the differential signal Vdef in the black edge candidate area is held. The waveform of the black side peak hold signal Vbph is shown in FIG. The black peak position detection comparator 241 obtains the minimum value of the differential signal Vdef.
The black-side peak hold signal Vbph output from the black-side peak hold circuit 242 is sent to the slice level generation circuit 243, and a voltage of 90% of the peak hold signal level is output as the slice level Vbps. The slice level Vbps is input to the peak position detection comparator 241 and compared with the differential signal Vdef, whereby the black side edge candidate signal Vbe2 is output from the comparator 241 and input to the binarized signal generator 25. The
FIG. 9 shows the relationship between the black-side peak position signal slice level Vbps and the black-side edge candidate signal Vbe2. The falling edge of the black edge candidate signal corresponds to the position of the black to white edge of the barcode pattern.
<Binary signal generator 25>

As a result of the above processing, the binarized signal generation unit 25 receives four signals of the white edge candidate area signal Vwe, the black edge candidate area signal Vbe, the white edge candidate signal Vwe2, and the black edge candidate signal Vbe2. The
Further, as shown in FIG. 13, for example, the binarized signal generation unit 25 includes two AND circuits 251 and 252, a rising detection circuit 253 and a falling detection circuit 254, and a flip-flop circuit 256.

The rising edge detection circuit 253 detects the rising edge signal of the white edge candidate signal Vwe2, and the AND circuit 251 takes the AND of the rising edge detection signal and the white edge candidate area signal Vwe, and outputs the output pulse to the flip-flop circuit 256. Input to the set terminal. The black edge candidate signal Vbe is detected by the falling detection circuit 254. The AND circuit 252 takes the AND of the falling detection signal and the black edge candidate area signal Vbe and flips the output pulse. Is input to the reset terminal of the circuit 256.
The waveform of each signal related to the operation of the binarized signal generation circuit 25 is shown in FIG.

The white-side edge candidate signal Vwe and the black-side edge candidate signal Vbe each generate a large number of pulses. Thus, the white-side edge candidate signal Vwe2 while the white-side edge candidate area signal Vwe is “H”. The flip-flop circuit 256 is set by the rising differential pulse of, and the flip-flop circuit 256 is reset by the falling differential pulse of the black-side edge candidate area signal Vbe2 while the black-side edge candidate area signal Vbe is “H”. As the output of the loop circuit 256, a binarized signal accurately corresponding to the array pattern of the white bar and black bar of the barcode can be obtained.
<Effect of the first embodiment>

  In the first embodiment, the slice level generation circuits 212 and 222 of the white / black edge candidate area signal generation units 21 and 22 respectively output a constant voltage as a slice level. These are set to voltages larger in the positive and negative directions than noise signals that tend to occur in advance. Since a signal obtained by comparing these slice levels with the differential signal Vdef is used as a white / black edge candidate area signal, a region including a noise signal is not erroneously recognized as a binarized signal. .

Further, the white side / black side edge is compared with the slice level generated based on the signal that holds the peak of the differential signal within the period in which the white / black edge candidate area signal is at the high level. Since the candidate signal is obtained, the edge of the binarized signal is reliably obtained and processed as described above by the binarized signal generating unit 25 having a simple configuration, so that the binarized signal accurate to the barcode pattern to be read is obtained. Can be generated.
[Second Embodiment]

Next, a second embodiment will be described. In this embodiment, the influence of noise is further reduced, and binarization processing with higher accuracy can be performed.
FIG. 14 is a block diagram showing only the rear stage portion 20 of the second embodiment of the optical information reading apparatus according to the present invention, and the front stage portion 10 is the same as the first embodiment shown in FIG. Is omitted.

Also in the rear stage portion 20 shown in FIG. 14, the same reference numerals are given to the portions corresponding to those in the first embodiment shown in FIG. 1, and their configuration and functions are different from those in the first embodiment. Only the point will be described.
The rear stage unit 20 also includes a white side edge candidate area signal generation unit 21, a black side edge candidate area signal generation unit 22, a white side edge candidate signal detection unit 23, a black side edge candidate signal detection unit 24, and a binarized signal generation. The point that the portion 25 is provided is the same as that of the first embodiment.

In the second embodiment, an integration circuit 26, a white-side acceptance / rejection determination signal generation unit 27, and a black-side acceptance / rejection determination signal generation unit 28 are further provided.
The integrating circuit 26 includes a differential signal Vdef from the preceding differentiation circuit 14 (see FIG. 1) (not shown), a white side edge candidate area signal Vwe from the white side edge candidate area signal generation unit 21, and a black side. The black-side edge candidate area signal Vbe from the edge candidate area signal generation unit 22 is input.
<Integration circuit 26>

As the integration circuit 26, a well-known general integration circuit as shown in FIG. 15 can be used. Then, by inputting a comparison signal between the white edge candidate area signal Vwe and the black edge candidate area signal Vbe, control is performed so that the DC component of the differential signal Vref is not reproduced.
Specifically, the differential signal Vdef flows through the resistor R31, and the white side edge candidate signal Vwe input to the OR circuit U1 is “1” or the black side edge candidate signal Vbe is “0” (a signal inverted by the inverter IN). Is "1"), the output of the OR circuit U1 is "1". At this time, since the analog switch SW2 is turned OFF, a signal level in the edge candidate area is generated in the integration capacitor C31 and is output from the operational amplifier X3. In a section that is not an edge candidate area on either the white side or the black side, the analog switch SW2 is turned on. Therefore, the voltage of the integration capacitor C31 is reset, and the level waveform from which the DC component is removed is output from the operational amplifier X3. . In this way, the output of the integrating circuit 26 becomes an integrated waveform from which the DC component has been removed.
<Acceptance determination signal generators 27 and 28>

The integration signal Vint output from the integration circuit 26 is input to the comparator 271 of the white side acceptance / rejection determination signal generation unit 27 and the comparator 281 of the black side acceptance / rejection determination signal generation unit 28.
The white-side comparator 271 compares the differential signal Vdef with the slice level (for example, 2.7 V) Vs5 output from the slice level generation circuit 272, and determines whether the white-side edge candidate area signal Vwe or the noise signal.

That is, when the integration signal Vint is greater than the slice level Vs5, it is determined that a barcode signal exists and the white-side acceptance / rejection determination signal Vdw is set to “1”. Conversely, when the integration signal Vint is smaller than the slice level Vs5, it is regarded as noise and the white-side acceptance / rejection determination signal Vdw is set to “0”.
The black-side comparator 281 compares the differential signal Vdef with an output signal (for example, 2.3 V) Vs6 of the slice level generation circuit 282, and determines whether the black-side edge candidate area signal Vbe is a noise signal. Therefore, similarly to the white side, when the integration signal Vint is larger than the slice level Vs6, the black-side acceptance / rejection determination signal Vdb is set to “1”, and when it is smaller, the black-side acceptance / rejection determination signal Vdb is set to “0”.
<Binary signal generator 25>

The binarized signal generation unit 25 of this embodiment includes a white side edge candidate area signal Vwe, a black side edge candidate area signal Vbe, a white side edge candidate signal Vwe2, a black side edge candidate signal Vbe2, and a white side acceptance / rejection determination. Six signals of the signal Vdw and the black side acceptance / rejection determination signal Vdb are input.
As shown in FIG. 16, the binarized signal generation unit 25 includes two AND circuits 251 and 252, a rising detection circuit 253, a falling detection circuit 252, an inverting circuit 255, and a flip-flop circuit 256. Yes.

According to the binarized signal generation unit 25, the rising edge detection circuit 253 detects a rising signal of the white side edge candidate signal Vwe2, and the rising edge detection signal, the white side edge candidate area signal Vwe, and the white side acceptance / rejection determination signal Vdw. The output pulse is input to the set terminal of the flip-flop circuit 256. The black edge candidate signal Vbe2 is detected by the falling detection circuit, and the AND of the detection signal, the black edge candidate area signal Vbe, and the black side acceptance / rejection determination signal Vdb through the inverting circuit 255 is obtained. The output pulse is input to the reset terminal of the flip-flop circuit 256.
FIG. 18 shows the relationship between each signal input to the binarized signal generator 25 and each waveform of the output binarized signal.

  The binarized signal generator 25 is formed of a flip-flop circuit 256 as in the first embodiment. Here, as shown in FIG. 18, when the white side acceptance / rejection determination signal Vdw is “1” and the white side edge candidate area signal Vwe is also “1”, the rising signal of the white side edge candidate signal Vew2 is validated. Thus, the flip-flop circuit 256 is set by the FF set signal, and the binarized signal as the output is inverted to “1”. Conversely, when the black side acceptance / rejection determination signal Vdb is “0” and the black side edge candidate area signal Vbe is “1”, the falling signal of the black side edge candidate signal Veb2 is validated, and the flip-flop is turned on by the FF reset signal. The circuit 256 is reset, and the binarized signal as its output is inverted to “0”.

As shown in FIG. 19A, even if the noise signal is larger than the differentiation circuit slice level (generated by the thrust level generation circuits 212 and 222) in the waveform of the differential signal, Like the white side and black side shown in FIG. 14B, the noise signal is generated by the action of the integration circuit 26 by the slice level generation circuits 272 and 282 of FIG. Generated by the generation circuits 272 and 282 and does not affect the binarization of the differential signal.
<Effect of the second embodiment>

Even in a circuit in which it is difficult to set a slice level for removing noise depending on the status of the bar code signal, in this embodiment, the integration circuit analyzes the analog signal again, and the integrated signal is further analyzed. An accurate binarized signal that does not include noise can be output by the acceptance / rejection determination signal obtained by comparing with the two slice levels Vs5 and Vs6.
[Third embodiment]

  Next explained is a third embodiment of the optical information reading apparatus according to the invention. FIG. 20 is a diagram showing the configuration of the rear stage section 20, and the front stage section 10 is the same as that of the first embodiment shown in FIG. Also, in FIG. 20, the same reference numerals are given to the portions corresponding to those in FIG. 1, and only the differences from the first embodiment will be described with respect to their configurations and functions.

In the third embodiment, as in the second embodiment, the signal detected from the reading target can be binarized with higher accuracy without being substantially affected by noise. For this purpose, a slice level control signal generation unit 29 is provided to control slice level generation in the slice level generation circuits 212 and 222 in the white and black edge candidate area signal generation units 21 and 22. .
The slice level control signal generation unit 29 includes a differential signal level measurement circuit 291 and a slice level control circuit 292.

  As shown in FIG. 17, the differential signal level measurement circuit 291 includes a detection circuit constituted by a resistor R41, a diode D5, and a capacitor C41, and an A / D converter 290. An analog level signal obtained by detecting the differential signal Vdef is converted into an A / D signal. The signal is converted into a digital level signal by the D converter 290 and sent to the slice level control circuit 292 shown in FIG.

The slice level control circuit 292 is programmed by the CPU to perform the following control. The process is shown in the flowchart of FIG.
(1) A differential signal level measurement value digital level signal is input from the differential signal level measurement circuit 291 for each scan,
(2) Each time a predetermined (predetermined) number of times are sampled during one scan in the A / D converter 290, the newly input signal is compared with the previously input signal. The three signals up to are always stored (saved).

(3) When the specified number of times of sampling is completed, the average value Vave of the third highest value (the top three) is taken,
(4) The specified value (threshold value) Vsre and the average value Vave are compared,
When the specified value (threshold value) Vsre> average value Vave, a control signal for increasing the slice level is output, and when the specified value (threshold value) Vsre ≦ average value Vave, a control signal for decreasing the slice level is output.
Here, the level of the slice level depends on a preset value for the D / A converter constituting the slice level control circuit 292.
(5) The sampling is initialized and the process proceeds to the next scan.
The slice level control circuit 292 is composed of a D / A conversion circuit or the like, converts the input digital level signal into an analog control signal, and controls the white and black side slice level generation circuits 212 and 222. Thus, the slice level generated by each may be changed.
<Effect of the third embodiment>

According to this embodiment, even if the differential signal level changes due to the density of the bar code or the distance between the bar code and the reading device, the white side and black side edges are always based on the signal obtained by sampling the differential signal level. Since the slice level of the candidate area signal generation units 21 and 22 can be controlled, the influence of noise on the barcode binarized signal can be significantly reduced.
[Fourth embodiment]

Next, FIG. 22 shows a fourth embodiment of the optical information reader according to the present invention.
FIG. 22 also shows only the rear stage part of the fourth embodiment, and the same reference numerals are given to the parts corresponding to those in FIGS. 1, 14, and 20, and the description thereof is omitted.
In this embodiment, in order to further reduce the influence of the noise signal, the integration circuit 26 and the white and black acceptance / rejection determination signal generation units 27 and 28 provided in the second embodiment described above are provided in the third embodiment. The slice level control signal generation unit 29 in the example is provided in combination.
In this case, the slice level control signals generated by the slice level control signal generation unit 29 also control the slice level generation circuits 272 and 282 of the white and black acceptance determination signal generation units 27 and 28 to generate them. The slice level to be changed can also be changed.
[Fifth embodiment]

Next explained is a fifth embodiment of the optical information reading apparatus according to the invention.
There are various situations where an optical information reader such as a barcode scanner is used. In many cases, the amount of light varies depending on the place of use, such as a relatively dark place such as a warehouse, the outdoors directly exposed to sunlight, or a cash register of a retail store whose brightness varies depending on time and position.
This means that the magnitude of the differential signal Vdef output from the differentiating circuit 14 in each of the above-described character commands important for digital processing changes depending on the amount of light received by the photodiode 11. If the amplitude of this signal is intense, a signal with a small amplitude may not be amplified to a sufficient amplitude level, and a large signal may be saturated. Therefore, an AGC circuit is mounted to adjust the amount of light. The present invention can sufficiently cope with such a type of optical information reader.

The fifth embodiment is an embodiment of an optical information reader equipped with such an AGC circuit. FIG. 23 is a block diagram showing the overall configuration, in which parts corresponding to those in FIG. 1 are given the same reference numerals, and only different parts will be described.
In the pre-stage unit 10, an AGC circuit 30 is inserted between the low-pass filter 13 and the differentiation circuit 14. The AGC circuit 30 includes a gain control amplifier 31 and an amplifier gain control circuit 32 that generates a control signal thereof. The gain control amplifier 31 includes a JFET that is a kind of field effect transistor, and the amplifier gain control circuit 32 includes a peak value detector 321, a reference level setting circuit 322, and a comparator 323. The rear stage portion 20 of this apparatus is the same as that of the first embodiment shown in FIG.

Next, how the AGC circuit 30 of this embodiment operates will be described.
The differential signal Vdef output from the differentiation circuit 14 is input to the peak value detector 321 of the amplifier gain control circuit 32, and the peak value Vp is detected. The comparator 323 outputs a control signal Sc corresponding to the difference from the reference level Vs set in the reference level setting circuit 322, which becomes a control signal for the gain control amplifier 31.
The control signal Sc is positive when Vp> Vs, 0 when Vp = Vs, and negative when Vp <Vs. The gain control amplifier 31 varies the gain of amplification so as to be inversely proportional to the control signal Sc.

That is, when the amplitude of the differential signal Vdef decreases, the peak value Vp becomes smaller than the reference level Vs, so the control signal Sc becomes negative and the gain of the gain control amplifier 31 is increased. Conversely, when the amplitude of the differential signal Vdef increases, the peak value Vp becomes greater than the reference level Vs, so the control signal Sc becomes positive and the gain of the gain control amplifier 31 is reduced. Thereby, the average amplitude of the differential signal Vdef can be made substantially constant.
Thus, the gain correction with respect to the light amount is sufficiently performed in the front stage 10 of the apparatus. Since the rear stage unit 20 is the same as that in the first embodiment, the influence of noise is suppressed and the differential signal Vdef is accurately binarized.
[Sixth embodiment]

Next, FIG. 24 shows a sixth embodiment of the optical information reader according to the present invention.
In FIG. 24, parts corresponding to those in FIGS. 1, 14, 20, and 23 are given the same reference numerals, and only the parts different from those will be described.
This embodiment is provided in the integration circuit 26 provided in the second embodiment shown in FIG. 14, the white and black acceptance determination signal generators 27 and 28, and the third embodiment shown in FIG. The fourth embodiment shown in FIG. 20 provided with the slice level control signal generator 29 is further combined with the AGC circuit 30 of the fifth embodiment shown in FIG.

  Therefore, in this embodiment, an output signal from the differential signal level measurement circuit 291 of the slice level control signal generation unit 29 is input to the amplifier gain control circuit 32 of the AGC circuit 30, and a signal obtained by comparing it with the reference level Vs is obtained. The control signal Sc to the gain control amplifier 31 is used. In this case, since the differential signal level measurement circuit 291 outputs the average value, the amplifier gain control circuit 32 does not need to take a peak value or an average value.

Note that only one of the integration circuit 26 of the second embodiment, the white and black acceptance determination signal generation units 27 and 28, and the slice level control signal generation unit 29 of the third embodiment is AGC. It may be provided in combination with the circuit 30.
Also in these embodiments, the gain is corrected in accordance with the amount of light at the front stage portion 10 of the apparatus, and the rear stage portion 20 of the apparatus is controlled so as not to be affected by the noise signal. Thus, accurate binarization of the differential signal is performed.

The invention's effect

  As described above, the optical information reading apparatus according to the present invention removes the influence of noise, improves the reproducibility of the bar-to-space ratio, and the reading object has a low signal level and a low PCS barcode or high-definition barcode. Even so, since the detection signal can be binarized accurately, the information can be read with high accuracy.

  1 is a block diagram showing a circuit configuration of a first embodiment of an optical information reading device according to the present invention; FIG.   It is a circuit diagram which shows the specific example of the differentiation circuit 14 in FIG.   It is a wave form diagram which shows the example of the output signal from the low-pass filter 13 of FIG.   It is a wave form diagram which shows the example of the differential signal output from the differentiating circuit 14 of FIG.   It is a wave form diagram which shows the example of the differential signal in FIG. 1, and a white side and black side edge candidate area signal.   It is a wave form diagram which shows the relationship between the differential signal in FIG. 1, and a white side peak hold signal.   It is a wave form diagram which shows the relationship between the differential signal in FIG. 1, and a black side peak hold signal.   It is a wave form diagram which shows the relationship between the differential signal in FIG. 1, a white side slice level, and a white side edge candidate signal.   It is a wave form diagram which shows the relationship between the differential signal in FIG. 1, a black side slice level, and a black side edge candidate signal.   It is a wave form diagram which shows the relationship of each signal for demonstrating operation | movement of the binarization signal production | generation part 25 shown in FIG. 1 and FIG.   FIG. 2 is a circuit diagram illustrating a configuration example of white-side and black-side peak hold circuits 232 and 242 in FIG. 1.   FIG. 2 is a circuit diagram illustrating a configuration example of slice level generation circuits 233 and 243 in FIG. 1.   It is a block diagram which shows the structural example of the binarization signal production | generation part 25 in FIG.   It is a block diagram which shows the structure of the back | latter stage part of 2nd Example of the optical information reader by this invention.   FIG. 15 is a circuit diagram illustrating a configuration example of an integration circuit 26 in FIG. 14.   It is a block diagram which shows the structural example of the binarization signal production | generation part 25 in FIG.   FIG. 21 is a circuit diagram illustrating a configuration example of a differential signal level measurement circuit 291 in FIG. 20.   It is a wave form diagram which shows the relationship of each signal for demonstrating operation | movement of the 2nd Example shown in FIG.   FIG. 15 is a waveform diagram showing the relationship between the differentiation circuit output waveform and its slice level and the integration circuit output waveform and its slice level in the case of the second embodiment shown in FIG. 14.   It is a block diagram which shows the structure of the back | latter stage part of the 3rd Example of the optical information reader by this invention.   It is a flowchart which shows the operation | movement process by the slice level control signal generation part 29 shown in FIG.   It is a block diagram which shows the structure of the back | latter stage part of 4th Example of the optical information reader by this invention.   It is a block diagram which shows the whole structure of the 5th Example of the optical information reader by this invention.   It is a block diagram which shows the whole structure of the 6th Example of the optical information reader by this invention.   It is a circuit diagram which shows the example of the signal processing circuit of the conventional tracking system.   FIG. 26 is a waveform diagram showing an operation of the signal processing circuit shown in FIG. 25.   It is a circuit diagram which shows the example of the signal processing circuit of the conventional differentiation system.

Explanation of sign

10: front stage 11: photodiode 12: I / V amplifier 13: low-pass filter 14: differentiation circuit 20: rear stage 21: white side edge candidate area signal generation unit 22: black side edge candidate area signal generation unit 23: white side Edge candidate signal detection unit 24: black side edge candidate signal detection unit 25: binarized signal generation unit 26: integration circuit 27: white side acceptance determination signal generation unit 28: black side acceptance determination signal generation unit 29: slice level control signal Generation unit 30: AGC circuit

Claims (6)

A light receiving unit (11) that irradiates a reading target composed of portions having different light reflectivities, receives the reflected light, and performs photoelectric conversion, and a signal that converts a current signal photoelectrically converted by the light receiving unit into a voltage signal A converter (12), an electrical filter (13) that passes and outputs a signal in a required frequency band of the voltage signal, a differentiator (14) that differentiates an output signal of the electrical filter, and a derivative thereof In an optical information reading apparatus including a binarization processing unit (20) that performs signal processing based on a signal (Vdef) and outputs a binarized signal,
The binarization processing unit (20)
The differential signal (Vdef) is compared with positive and negative slice levels (Vws, Vbs) for removing a noise signal having a predetermined amplitude or more, and a positive transition edge at which the voltage signal shifts from a negative level to a positive level. An edge candidate area signal generation unit (21) for generating positive transition and negative transition edge candidate area signals (Vwe, Vbe) indicating a candidate and a range of negative transition edge candidates that transition from a positive level to a negative level. 22)
Each slice level (Vwps, Vbps) obtained by dividing a signal obtained by peak-holding each edge candidate area signal (Vwe, Vbe) is compared with the differential signal (Vdef), and the positive transition edge and Edge candidate signal detection units (23, 24) for detecting edge candidate signals (Vwe2, Vbe2) that are candidates for negative transition edges;
The rising edge of the positive transition edge candidate signal (Vwe2) within the valid period of the positive transition edge candidate area signal (Vwe) and the negative transition within the valid period of the negative transition edge candidate area signal (Vbe) It is constituted by a binarized signal generating unit (25) for generating a binarized signal by determining the falling edge of the edge candidate signal (Vbe2) as an edge of the negative level and the positive level of the voltage signal. An optical information reader. The optical information reader according to claim 1,
An integration circuit (26) for integrating the differential signal (Vdef) and outputting an integral signal for each valid period of the edge candidate area signals (Vwe, Vbe) for the positive transition and the negative transition;
The integration signal and positive / negative slice levels (Vs5, Vb6) for removing the noise signal are respectively compared to generate a positive / negative transition acceptance / rejection determination signal (Vdw, Vdb). (27, 28)
The binarized signal generator (25) determines the rising edge of the positive transition edge candidate signal (Vwe2) and the falling edge of the negative transition edge candidate signal (Vbe2) as the negative level and positive level edges of the voltage signal. An optical information reading apparatus characterized in that, when making a determination, the determination state of the positive / negative transfer acceptance / rejection determination signals (Vdw, Vdb) is also added as a condition. The optical information reader according to claim 1 or 2,
The differential signal (Vdef) is detected and its level is measured, and the positive and negative slice levels (Vws, Vbs) used in the edge candidate area signal generation unit (21, 22) are changed according to the level. An optical information reader comprising a slice level control signal generation unit (29) for generating a slice level control signal for the purpose. The optical information reader according to claim 3,
The slice level control signal generator (29)
Means (291) for detecting the differential signal (Vdef) and A / D converting the signal into a digital value;
For each predetermined number of samplings during the A / D conversion, n values are stored from the top, an average value Vave of the n values is taken, and compared with a specified value Vsre,
A control signal for increasing the slice level when the specified value Vsre> the average value Vave, and a control signal for generating the control signal for decreasing the slice level when the specified value Vsre ≦ the average value Vave (292). An optical information reader. An optical information reading device according to any one of claims 1 to 4,
A gain control amplifier (31) that is inserted on the input side of the differentiation section (14) and amplifies the voltage signal, and controls the gain of the gain control amplifier (31) according to the amplitude of the differentiation signal (Vdef). An optical information reader comprising an amplifier gain controller (32) for generating a control signal to be transmitted. The optical information reader according to claim 3,
The level of the differential signal (Vdef) measured by the gain control amplifier (31) that is inserted on the input side of the differentiation unit (14) and amplifies the voltage signal, and the slice level control signal generation unit (29) And an amplifier gain control section (32) for generating a control signal for controlling the gain of the gain control amplifier (31) in accordance with the optical information reading apparatus.

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