JP4254758B2 - Stream encryption device, stream encryption method, stream decryption device, and stream decryption method - Google Patents

Description

  The present invention relates to a technique for encrypting or decrypting a stream including content such as audio / video.

  With the recent spread of data communication networks, so-called home networks that allow home appliances, computers, and other peripheral devices to be connected to each other in the home and communicated between the devices are becoming popular. The home network makes it possible to share the data processing function of each device by communicating between the network connection devices. It provides convenience and comfort to users, such as sending and receiving content between network-connected devices, and is expected to become increasingly popular in the future.

  In such home networks, DTCP (Digital Transmission Content Protection), which is a de facto standard, is known as a technology for protecting the copyright of content. In DTCP, an encryption and an encryption key are exchanged between a content transmission device and a reception device to share an encryption key, and encrypted data is transferred between these devices.

As disclosed in Non-Patent Document 1 below, in DTCP / IP for deploying DTCP on an IP network, a CBC (Advanced Encryption Standard) with a key length of 128 bits is used to improve encryption strength. Cipher Block Chaining) is performed. Hereinafter, AES encryption using this CBC processing is referred to as AES-CBC encryption.
Patent Document 1 below discloses a digital content protection method using this AES-CBC encryption as an encryption mode.

  In AES-CBC encryption, 128-bit encrypted data is held in a register, the encrypted data is fed back, and the next encryption target data is subjected to an EXOR (exclusive OR) operation. AES encryption is performed on Therefore, in AES-CBC encryption, since the input / output of the encryption process is not associated with 1: 1, a specific tendency is not observed in the output and the encryption strength is increased, but in order to perform a certain encryption, The previous encryption result must be waited, and processing takes time compared to normal AES encryption.

Digital Transmission Content Protection Specification Volume 1 (Information version) Revision 1.4 February 28, 2005 (p47 etc.) JP 2004-318154 A

By the way, in the IP network transmission, there is a case where the transmission side temporarily encrypts data sent to the transmission path for reproduction in real time. In such a case, it is required to perform the encryption process and the decryption process in real time, unlike the case where the encryption key is separately transferred after the entire content (encrypted data) is sent to the receiving side. Performing CBC encryption is an obstacle to this real-time processing.
In recent years, in particular, in order to improve the image quality of images, 1080i (interlaced display of 1080 effective scanning lines) is changed to 1080p (progressive display of 1080 effective scanning lines), or the refresh rate is changed from 60 Hz to 120 Hz. High frame rates, such as changing to 240 Hz, are gradually advancing, and the ability to encrypt and decrypt content such as audio and video in real time is not catching up.

  The present invention has been made in view of the above points, and an object thereof is to provide a stream encryption device, a stream encryption method, and a stream decryption method for encrypting a stream at high speed. The present invention provides a stream decoding apparatus and a stream decoding method.

In order to overcome the above problems, the first aspect of the present invention provides:
A plurality of first data storage units each having the same storage capacity and sequentially storing data streams;
Connected to each of the plurality of first data storage units, and encrypts the data stored in the corresponding first data storage unit in order for each reference data amount for encryption to generate encrypted data A plurality of encryption units,
A plurality of second data storage units each having the same storage capacity, connected in association with each of the plurality of encryption units, and storing encrypted data generated by the corresponding encryption units;
The desired reference data is added on the condition that the plurality of second data storage units are connected in association with each other, and the encrypted data corresponding to the storage capacity is stored in the corresponding second data storage unit. A plurality of data adding sections to be output;
A first stream generation unit configured to stream each output data of the plurality of data addition units in an output order and generate a data stream;
Is a stream encryption device.

  In the present invention, the “reference data amount for encryption” means a data unit when performing encryption processing, and for example, in AES, the data amount is 128 bytes, 256 bytes or the like.

In order to overcome the above-described problem, a second aspect of the present invention provides a stream decoding method for decoding a data stream streamed in units of standard blocks in which reference data is added to a predetermined amount of encrypted data. Device.
A plurality of third data storage units for sequentially storing the reference blocks;
A plurality of data removal units that are connected in association with each of the plurality of third data storage units, remove the reference data from the reference blocks stored in the corresponding third data storage units, and extract the encrypted data When,
A plurality of pieces of decryption data that are connected in association with each of the plurality of data removal units and that sequentially decrypt the encrypted data extracted by the corresponding data removal units for each reference data amount for decryption. A decryption unit of
A plurality of fourth data storage units each having the predetermined amount of storage capacity, connected in association with each of the plurality of decoding units, and storing the decoded data generated by the corresponding decoding unit;
A second stream generation unit that generates a data stream by streaming the decoded data for the storage capacity in each fourth data storage unit in the order in which the data is stored;
Is a stream decoding apparatus.

In the present invention, the “reference block” is a concept of a data unit serving as a reference for processing a data stream as content, such as a packet unit.
The “reference data” means additional data for managing the data of the reference block such as header data.

In order to overcome the above problems, the third aspect of the present invention provides:
The data streams are sequentially stored in a plurality of first data storage units each having the same storage capacity,
Each of the plurality of encryption units connected in association with each of the plurality of first data storage units stores the data stored in the corresponding first data storage unit for each reference data amount for encryption. In order to generate encrypted data,
Each of the plurality of second data storage units each having the same storage capacity and connected in association with each of the plurality of encryption units stores the encrypted data generated by the corresponding encryption unit. And
Each of the plurality of data adding units connected in association with each of the plurality of second data storage units is provided on the condition that encrypted data corresponding to the storage capacity is stored in the corresponding second data storage unit. Add the desired reference data and output it,
In the stream encryption method, the first stream generation unit streams each output data of the plurality of data addition units in the output order, and generates a data stream.

In order to overcome the above problems, the fourth aspect of the present invention provides:
A stream decryption method for decrypting a data stream streamed in units of standard blocks in which reference data is added to a predetermined amount of encrypted data,
Each of the plurality of third data storage units sequentially stores the reference block,
Each of a plurality of data removal units connected in association with each of the plurality of third data storage units removes the reference data from the reference block stored in the corresponding third data storage unit, and Extract data,
Each of the plurality of decryption units connected in association with each of the plurality of data removal units sequentially decrypts the encrypted data extracted by the corresponding data removal unit for each reference data amount for decryption. To generate decrypted data,
Each of the plurality of fourth data storage units each having the predetermined amount of storage capacity and connected in association with each of the plurality of decoding units receives the decoded data generated by the corresponding decoding unit. Accumulate,
This is a stream decoding method in which the second stream generation unit generates a data stream by streaming the decoded data corresponding to the storage capacity in each fourth data storage unit in the order of storage.

  According to the present invention, a stream as content can be encrypted and decrypted at high speed.

  Hereinafter, a content transmission device 2 including an encryptor that is an embodiment of the content encryption device of the present invention and a content reception device 3 including a decryptor that is an embodiment of the content decryption device of the present invention. The transmission system 1 will be described.

  The content transmission system 1 is constructed as a home network in a home using a transmission path such as an Ethernet cable. The content transmission device 2 acquires content including audio and video from outside by wireless communication, performs encryption according to the DTCP / IP standard and packetization according to the transmission method for the content, and transmits the content to the transmission path. Send it out. The content receiving device 3 is configured integrally with, for example, a television receiver, decrypts encrypted data received from the transmission path, and reproduces the content on a display device such as an LCD (Liquid Crystal Display).

  Hereinafter, the configuration of the content transmission device 2 and the content reception device 3 will be described with reference to FIG. FIG. 1 is a block diagram illustrating configurations of the content transmission device 2 and the content reception device 3.

As shown in FIG. 1, the content transmitting apparatus 2 according to the embodiment includes a receiving antenna 21, a digital tuner 22, a channel decoder 23, an encryptor 24, and an IP transmitter 25.
The encryptor 24 corresponds to the stream encryption device of the present invention.

The digital tuner 22 down-converts the frequency of OFDM (Orthogonal Frequency Division Multiplexing) used for the terrestrial digital broadcast wave received by the receiving antenna 21 by frequency conversion, and the terrestrial digital broadcast signal S22 of an arbitrary channel (broadcast station). To extract.
The channel decoder 23 generates a demodulated signal by demodulating the terrestrial digital broadcast signal S22, for example, by QPSK, and generates an MPEG-TS (stream) S23 as content from the demodulated signal.

The encryptor 24 performs encryption conforming to the DTCP / IP standard for the stream S23 as the content.
As shown in the document “DTCP Volume 1 Supplement E Mapping DTCP to IP (Information version) Revision 1.1 February 28, 2005 (p13 etc.)”, the DTCP / IP standard has an ordinary key length of 128 bits in order to increase the encryption strength. It is specified that CBC (Cipher Block Chaining) processing (AES-CBC encryption is performed) for AES (Advanced Encryption Standard) encryption.
Since this AES-CBC encryption takes a long time to process compared to the normal 128-bit AES encryption, the encryptor 24 parallelizes a plurality of AES-CBC encryption processing blocks to increase the processing speed. We are trying to make it.

FIG. 2 shows a block configuration of the encryptor 24.
The encryptor 24 includes an input FIFO (First In First Out) 241, a FIFO group 242 (FIFO 242_1 to FIFO 242_4), an AES-CBC encryption unit group 243 (AES-CBC encryption unit 243_1 to AES-CBC encryption unit 243_4), A FIFO group 244 (FIFO 244_1 to FIFO 244_4), a header addition circuit group 245 (header addition circuit 245_1 to header addition circuit 245_4), and an output FIFO 246 are included.

The FIFO group 242 is an embodiment of a plurality of first data storage units of the present invention.
The AES-CBC encryption unit group 243 is an embodiment of a plurality of encryption units of the present invention.
The FIFO group 244 is an embodiment of a plurality of second data storage units of the present invention.
The header addition circuit group 245 is an embodiment of a plurality of data addition units of the present invention.
The output FIFO 246 is an embodiment of the first stream generation unit of the present invention.

As shown in the figure, in the encryptor 24, four systems of encryption processing blocks are prepared between the input FIFO 241 and the output FIFO 246. That is, the first encryption processing block including the FIFO 242_1, the AES-CBC encryption unit 243_1, the FIFO 244_1, and the header addition circuit 245_1, the second encryption including the FIFO 242_2, the AES-CBC encryption unit 243_2, the FIFO 244_2, and the header addition circuit 245_2. Processing block, FIFO 242_3, AES-CBC encryption unit 243_3, FIFO 244_3, third encryption processing block consisting of header addition circuit 245_3, FIFO 242_4, AES-CBC encryption unit 243_4, FIFO 244_4, header addition circuit 245_4 Encryption processing block is provided.
In addition, although the encryption device 24 in this embodiment is configured by four systems of encryption processing blocks, the present invention is not limited to this, and the number of encryption processing blocks can be freely set according to a request for high speed.

The input FIFO 241 temporarily stores MPEG-TS data sent from the channel decoder 23 and supplies data in order from the FIFO 242_1 to the FIFO 242_4.
Each FIFO in the FIFO group 242 has a storage capacity of 1 KB (1024 bytes). This storage capacity is set according to the data unit to which the DTCP / IP header is added.
Each FIFO in the FIFO group 242 notifies the input FIFO 241 by activating the control signal STS1x indicating the storage state when the storage capacity is filled with data supplied from the input FIFO 241.
That is, as shown in FIG. 2, when the storage capacity becomes full, the FIFO 242_1 notifies the input FIFO 241 by activating the control signal STS11 indicating the storage state. When the storage capacity is full, the FIFO 242_2 notifies the input FIFO 241 by activating the control signal STS12 indicating the storage state. When the storage capacity is full, the FIFO 242_3 notifies the input FIFO 241 by activating the control signal STS13 indicating the storage state. When the storage capacity is full, the FIFO 242_4 notifies the input FIFO 241 by activating the control signal STS14 indicating the storage state.

When the control signal STS1x (x: 1 to 4) becomes active, the input FIFO 241 activates the corresponding select signal SEL1x, selects one of the FIFOs in the FIFO group 242, and outputs data.
Therefore, the data accumulated in the input FIFO 241 is first accumulated in the FIFO 242_1, and when the FIFO 242_1 is full for 1 KB, then it is accumulated in the FIFO 242_2. 1 KB of data is sequentially stored in each FIFO.

Each encryption unit of the AES-CBC encryption unit group 243 sequentially performs AES-CBC encryption processing when 1 KB of data is accumulated in the corresponding FIFO 242_x.
FIG. 3 shows the configuration of each encryption unit 243_x (x: 1 to 4) of the AES-CBC encryption unit group 243.
As shown in FIG. 3, the AES-CBC encryption unit 243_x includes an AES encryption circuit 2431, a register 2432 for feeding back encrypted data, and a gate circuit 2433.
That is, the AES-CBC encryption unit 243_x holds 128-bit encrypted data S243 in the register 2432, feeds back the encrypted data to the input side, and the gate circuit 2433 receives the next encryption target data S242 and An EXOR operation is performed, and AES encryption based on a predetermined encryption key is performed on the 128-bit operation result.

The encrypted data respectively obtained by the AES-CBC encryption units 243_1 to 243_4 is accumulated in each FIFO of the corresponding FIFO group 244.
Each FIFO in the FIFO group 244 has a storage capacity of 1 KB (1024 bytes). This storage capacity is set according to the data unit to which the DTCP / IP header is added.

  Each header addition circuit of the header addition circuit group 245 adds a DTCP / IP header to the encrypted data of 1 KB when the storage capacity of each FIFO of the FIFO group 244 is filled with the encrypted data. The DTCP / IP header indicates protection attributes such as a random number Nc (64 bits) for generating an encryption key and E-EMI (Extended Encryption Mode Indicator: “Copy-never”, “Copy-one-generation”). Data), data indicating the content length, and the like.

Each header addition circuit of the header addition circuit group 245 generates a DTCP / IP packet by adding a DTCP / IP header to 1 KB encrypted data. Then, when the output preparation of the DTCP / IP packet is completed, the output FIFO 246 is notified by activating the control signal STS2x indicating that the output preparation is completed.
That is, as shown in FIG. 2, when the DTCP / IP header is added to the 1 KB encrypted data, the header addition circuit 245_1 notifies the output FIFO 246 by activating the control signal STS21. When the DTCP / IP header is added to the 1 KB encrypted data, the header addition circuit 245_2 notifies the output FIFO 246 by activating the control signal STS22. When the DTCP / IP header is added to the 1 KB encrypted data, the header addition circuit 245_3 notifies the output FIFO 246 by activating the control signal STS23. When the DTCP / IP header is added to the 1 KB encrypted data, the header addition circuit 245_4 notifies the output FIFO 246 by activating the control signal STS24.

  When the control signal STS2x (x: 1 to 4) becomes active, the output FIFO 246 selects one of the header addition circuits in the header addition circuit group 245 to capture data by activating the corresponding select signal SEL2x. .

Here, on the input side of the encryptor 24, data of 1 KB is sequentially stored in each FIFO in the order of FIFO 242-1, FIFO 242, FIFO 242_3, and FIFO 242_4, and encryption processing and DTCP / IP header addition are performed in this order. On the output side, the control signal STS21, control signal STS22, control signal STS23, and control signal STS24 become active in this order. Therefore, encrypted DTCP / IP packets are accumulated in the output FIFO 246 in the order in which they are accumulated in the FIFO 242_1, the FIFO 242_2, the FIFO 242_3, and the FIFO 242_4. Therefore, the data order of the input stream S23 of the encryptor 24 is maintained in the output FIFO 246.
The output FIFO 246 outputs the accumulated DTCP / IP packet as a stream S24.

  Although the storage capacity of each FIFO described above is 1 KB, it is generally necessary to set the storage capacity so that the data of the content length indicated by the DTCP / IP header can be accommodated. IEEE 802.3 stipulates that the payload of the MAC header must be 1.5 KB or less, so that the storage capacity of each FIFO is preferably about 1 to 1.4 KB.

  Next, the operation of the encryptor 24 will be described with reference to FIG. FIG. 4 is a timing chart showing the operation of each part of the encryptor 24, where (a) shows the operation state of the FIFO group 242, (b) shows the processing state of the AES-CBC encryption unit 243_1, and (c) shows the AES- The processing state of the CBC encryption unit 243_2, (d) is the processing state of the AES-CBC encryption unit 243_3, (e) is the processing state of the AES-CBC encryption unit 243_4, and (f) is the AES-CBC encryption unit 243_1. (G) shows the processing state of the AES-CBC encryption unit 243_2, (h) shows the processing state of the AES-CBC encryption unit 243_3, and (i) shows the processing state of the AES-CBC encryption unit 243_4. .

  In FIG. 4, a case where a 3 Gbps stream is processed by the encryptor 24 will be described as an example. In such a case, four systems of encryption processing blocks having a processing capacity of 1 Gbps are configured in parallel. That is, the configuration is as shown in FIG.

  As shown in FIG. 4A, the data accumulated in the input FIFO 241 is first accumulated in the FIFO 242_1 in the period 1, and when the FIFO 242_1 is full by 1 KB, then in the period 2, the data is accumulated in the FIFO 242_2. To go. Further, in the period 3, the data is accumulated in the FIFO 242_3, and when the FIFO 242_3 becomes full for 1 KB, next, in the period 4, the data is accumulated in the FIFO 242_4. Similarly, in the period 5 to 8, 1 KB data is sequentially stored in the FIFOs 242_1 to 242_4.

  In FIG. 4, it is assumed that an encryption processing block having a processing capacity of 1 Gbps requires three periods to process 1 KB of data (or one period is defined as such). For example, the 1 KB data stored in the FIFO 242_1 in the period 1 is encrypted by the AES-CBC encryption unit 243_1 in the three periods of the periods 1 to 3, and the FIFO 242_2 in the period 2 as shown in FIG. As shown in FIG. 4C, the 1 KB data stored in the A is encrypted by the AES-CBC encryption unit 243_2 in the three periods 2 to 4. Thereafter, as shown in FIGS. 4D to 4I, the 1 KB data stored in each FIFO of the FIFO group 242 is sequentially encrypted over three periods.

  Therefore, for example, 3 KB data stored in the FIFO group 242 in the periods 1 to 3 are encrypted in the three periods 3 to 5, that is, on average, 1 KB data is encrypted in one period. Since each encryption processing block requires three periods to process 1 KB of data, it can be seen that the encryption device 24 in the present embodiment achieves three times higher speed.

In the example shown in FIG. 4, three times speedup is realized by four systems of encryption processing blocks, but theoretically three times speedup is realized by three systems of encryption processing blocks. It is possible. For example, in period 4 of FIG. 4, 1 KB of data is accumulated in the FIFO 242_1, and unlike in FIG. 4F, the processing of the AES-CBC encryption unit 243_1 is started from period 4.
However, in the example shown in FIG. 4, from the viewpoint of estimating the margin in consideration of the variation in the processing capability of each encryption processing block, for example, the AES-CBC encryption unit 243_1 is configured not to perform processing in period 4. ing.

Returning to the description of FIG.
The IP transmitter 25 is mainly composed of a microcontroller, and the microcontroller controls communication with the content receiving device 3. For example, the IP transmitter 25 generates data in units of packets according to a protocol such as RTP / UDP or HTTP / TCP for the stream supplied from the encryptor 24.

5A and 5B are diagrams showing a packet configuration generated by the IP transmitter 25. FIG. 5A shows the case of an RTP / UDP packet, and FIG. 5B shows the case of an HTTP / TCP packet.
As shown in FIG. 5, in the case of an RTP / UDP packet, the IP transmitter 25 adds a RTP header, a UDP header, an IP header, and a MAC header to the DTCP / IP packet of the stream S24 to generate a stream S25. And send it to the transmission line. In the case of an HTTP / TCP packet, an HTTP header, a TCP header, an IP header, and a MAC header are added, and a stream S25 is generated and sent to the transmission path.

  Next, the configuration of the content receiving device 3 will be described.

As shown in FIG. 1, the content receiving device 3 according to the embodiment includes an IP receiver 31, a decoder 32, an MPEG decoder 33, a scan converter 34, an LCD driver 35, and an LCD 36.
The decoder 32 corresponds to the stream decoding device of the present invention.

  The IP receiver 31 is mainly composed of a microcontroller, and the microcontroller controls communication with the content transmission device 2. For example, the IP receiver 31 extracts a DTCP / IP packet from the stream supplied from the content transmission apparatus 2 and supplies the stream S31 to the decoder 32.

  The decoder 32 performs decoding based on the DTCP / IP standard for the stream S31 as the content.

FIG. 6 shows a block configuration of the decoder 32.
The decoder 32 includes an input FIFO 321, a FIFO group 322 (FIFO 322_1 to FIFO 322_4), a header removal circuit group 323 (header removal circuit 323_1 to header removal circuit 323_4), and an AES-CBC decoding unit group 324 (AES-CBC decoding unit 324_1). To AES-CBC decoding unit 324_4), FIFO group 325 (FIFO 325_1 to FIFO 325_4), and output FIFO 326.
The configuration of the decryptor 32 is similar to the configuration of the encryptor 24 shown in FIG. 2 as a whole.

The FIFO group 322 is an embodiment of a plurality of third data storage units of the present invention.
The header removal circuit group 323 is an embodiment of a plurality of data removal units of the present invention.
The AES-CBC decoding unit group 324 is an embodiment of a plurality of decoding units of the present invention.
The FIFO group 325 is an embodiment of a plurality of fourth data storage units of the present invention.
The output FIFO 326 is an embodiment of the second stream generation unit of the present invention.

As shown in the figure, in the decoder 32, four systems of decoding processing blocks are prepared between the input FIFO 321 and the output FIFO 326. That is, the first decoding processing block including the FIFO 322_1, the header removing circuit 323_1, the AES-CBC decoding unit 324_1, and the FIFO 325_1, the FIFO 322_2, the header removing circuit 323_2, the second decoding including the AES-CBC decoding unit 324_2 and the FIFO 325_2. The third decoding processing block, FIFO 322_4, header removal circuit 323_4, AES-CBC decoding unit 324_4, and FIFO 325_4, the third decoding processing block, FIFO 322_3, header removal circuit 323_3, AES-CBC decoding unit 324_3, FIFO 325_3 The decoding processing block is provided.
In addition, although the decoder 32 in the present embodiment is configured by four systems of decoding processing blocks, the present invention is not limited to this, and the number of decoding processing blocks can be freely set according to a request for high speed.

The input FIFO 321 temporarily accumulates the stream S31 supplied from the IP receiver 31, and supplies data sequentially from the FIFO 322_1 to the FIFO 322_4.
Each FIFO in the FIFO group 322 has a storage capacity of 1 KB (1024 bytes) +14 bytes. Of this storage capacity, 1 KB is set according to the data unit before the DTCP / IP header is added. Further, 14 bytes is the data amount of the DTCP / IP header added on the content transmission apparatus 2 side. That is, data in units of DTCP / IP packets sent from the content transmission device 2 is accumulated in each FIFO of the FIFO group 322.
Needless to say, the header size of 14 bytes is appropriately adjusted according to the header format added on the content transmitting apparatus 2 side.

In each FIFO of the FIFO group 322, when the storage capacity is filled with data supplied from the input FIFO 321, the input FIFO 321 is notified by activating the control signal STS3x (x: 1 to 4) indicating the storage state. .
That is, as shown in FIG. 6, when the storage capacity becomes full, the FIFO 322_1 notifies the input FIFO 321 by activating the control signal STS31 indicating the storage state. When the storage capacity becomes full, the FIFO 322_2 notifies the input FIFO 321 by activating the control signal STS32 indicating the storage state. When the storage capacity is full, the FIFO 322_3 notifies the input FIFO 321 by activating the control signal STS33 indicating the storage state. When the storage capacity is full, the FIFO 322_4 notifies the input FIFO 321 by activating the control signal STS34 indicating the storage state.

When the control signal STS3x becomes active, the input FIFO 321 activates the corresponding select signal SEL3x, selects one of the FIFOs 322, and outputs data.
Therefore, the data accumulated in the input FIFO 321 is first accumulated in the FIFO 322_1, and when the FIFO 322_1 becomes full, then the FIFO 322_2 is accumulated, and when the FIFO 322_2 becomes full, the FIFO 322_3 In this way, data in units of DTCP / IP packets (1 KB + 14 bytes) is sequentially stored in each FIFO.

  Each header removal circuit in the header removal circuit group 323 removes the 14-byte DTCP / IP header from the data stored in the corresponding FIFO in the previous stage, and supplies 1 KB encrypted data to the corresponding AES-CBC decoder. .

Each decryption unit of the AES-CBC decryption unit group 324 sequentially performs AES-CBC decryption processing when 1 KB of encrypted data is supplied from the corresponding header removal circuit 323_x.
FIG. 7 shows the configuration of each decoding unit 324 — x (x: 1 to 4) in the AES-CBC decoding unit group 324.
As illustrated in FIG. 7, the AES-CBC decoding unit 324 — x includes an AES decoding circuit 3241, a register 3242 for feeding forward decoded data, and a gate circuit 3243.
In the AES-CBC decryption unit 324_x, 128-bit encrypted data S323 is held in the register 3242, the encrypted data is fed forward to the output side, and the next decrypted data and EXOR in the gate circuit 3243 Decoded data S324 is generated by performing an operation.

Decoded data respectively obtained by the AES-CBC decoding units 324_1 to 324_4 is accumulated in each FIFO of the corresponding FIFO group 325.
Each FIFO in the FIFO group 325 has a storage capacity of 1 KB (1024 bytes). This storage capacity is appropriately set according to the data unit to which the DTCP / IP header is added.

Each FIFO of the FIFO group 325 outputs an output by activating a control signal STS4x (x: 1 to 4) indicating the accumulation state when the accumulation capacity is filled with data supplied from the corresponding AES-CBC decoder. The FIFO 326 is notified.
That is, as shown in FIG. 6, when the storage capacity becomes full, the FIFO 325_1 notifies the output FIFO 326 by activating the control signal STS41 indicating the storage state. When the storage capacity is full, the FIFO 325_2 notifies the output FIFO 326 by activating the control signal STS42 indicating the storage state. When the storage capacity is full, the FIFO 325_3 notifies the output FIFO 326 by activating the control signal STS43 indicating the storage state. When the storage capacity is full, the FIFO 325_4 notifies the output FIFO 326 by activating the control signal STS44 indicating the storage state.

  When the control signal STS4x becomes active, the output FIFO 326 activates the corresponding select signal SEL4x, selects any FIFO in the FIFO group 325, and takes in data.

  Here, on the input side of the decoder 32, data in units of DTCP / IP packets (1 KB + 14 bytes) is sequentially stored in each FIFO in the order of FIFO 322_1, FIFO 322_2, FIFO 322_3, and FIFO 322_4, and header removal and decoding are performed in this order. Therefore, on the output side, the control signal STS41, the control signal STS42, the control signal STS43, and the control signal STS44 become active in this order. Therefore, the output FIFO 326 stores the decoded data in the order in which they are stored in the FIFO 325_1, the FIFO 325_2, the FIFO 325_3, and the FIFO 325_4. Therefore, the data order of the input stream S31 of the decoder 32 is maintained in the output FIFO 326.

  As described above, since the AES-CBC decryption is performed in parallel in the decryptor 32 like the encryptor 24, the decryption process is performed at a high speed according to the number of decryption processing blocks.

The output FIFO 326 outputs the accumulated decoded data (MPEG-TS) as a stream S32.
The MPEG decoder 33 decodes a stream S32 compression-encoded by MPEG and converts it into a video signal S33 made up of RGB signals (or Y, Cb, Cr color difference signals).
The scan converter 34 performs processing for converting the horizontal synchronization frequency in accordance with the specifications of the LCD 36, and then outputs the video signal S 34 to the LCD driver 35.

As described above in detail, according to the content transmission system 1 described in the present embodiment, the content transmission device 2 encrypts and transmits a stream (content) in parallel in units of predetermined packets, and transmits the content reception device 3. The encrypted data received in units of packets is decrypted in parallel and reproduced.
Accordingly, it is possible to speed up encryption / decryption processing that takes time, such as AES-CBC encryption / decryption, and it is possible to cope with high image quality in the home network. Become.

In addition, when the AES encryption process is simply performed instead of the AES-CBC encryption process, since it is not necessary to feed back the previously processed encrypted data, a plurality of AES encryption circuits (for example, the AES encryption circuit of FIG. It is envisaged that high speed can be achieved by configuring the parallel circuit 2431) in parallel, but the data input order to each AES encryption circuit and the data output order of each AES encryption circuit are kept the same. It is difficult to keep the data structure of the stream.
On the other hand, the content transmission apparatus 2 according to the present embodiment is configured to store data in units of packets in the FIFO before performing the AES-CBC encryption process. It is easy to continuously perform the feedback processing on the collected data amount, and the input / output order before and after the AES-CBC encryption processing can be maintained in units of packets with a simple configuration. The same applies to the content receiving device 3 according to the present embodiment.

The embodiment of the present invention has been described in detail above, but the specific configuration and system are not limited to the present embodiment, and design modifications and other systems can be made without departing from the scope of the present invention. This includes adaptations.
For example, FIGS. 8 and 9 show a system having another configuration of the content transmission system 1 described above. FIG. 8 shows a content transmission system 1a configured such that encryption is performed after the content is converted into an uncompressed signal by the MPEG decoder 26 of the content transmitting apparatus 2. Therefore, in the content transmission system 1a, there is no MPEG decoder on the content receiving device 3 side.
FIG. 9 shows a content transmission system 1b in which switching units 27 and 37 for selecting whether or not to perform MPEG decoding are added to the content transmission device 2 and the content reception device 3. Of course, the switching parts 27 and 37 are switched in contact with each other.
Thus, the encryption / decryption processing is not limited to MPEG-TS.

It is a block diagram which shows the structure of the content transmitter which concerns on embodiment, and the content receiver which concerns on embodiment. It is a figure which shows the block configuration of an encryption part. It is a figure which shows the structure of each encryption part of an AES-CBC encryption part group. It is a timing chart which shows operation | movement of each part of an encryption part. It is a figure which shows the packet structure produced | generated in an IP transmitter. It is a figure which shows the block configuration of a decoding part. It is a figure which shows the structure of each decoding part of an AES-CBC decoding part group. It is a figure which shows another structure of a content transmission system. It is a figure which shows another structure of a content transmission system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Content transmission system 2 ... Content transmission apparatus
21 ... Receiving antenna, 22 ... Digital tuner, 23 ... Channel decoder,
24 ... Encryptor, 25 ... IP transmitter 3 ... Content receiver
31 ... IP receiver, 32 ... decoder, 33 ... MPEG decoder,
34 ... Scan converter, 35 ... LCD driver, 36 ... LCD

Claims (4)

A plurality of first data storage units each having the same storage capacity and sequentially storing data streams;
Connected to each of the plurality of first data storage units, and encrypts the data stored in the corresponding first data storage unit in order for each reference data amount for encryption to generate encrypted data A plurality of encryption units,
A plurality of second data storage units each having the same storage capacity, connected in association with each of the plurality of encryption units, and storing encrypted data generated by the corresponding encryption units;
The desired reference data is added on the condition that the plurality of second data storage units are connected in association with each other, and the encrypted data corresponding to the storage capacity is stored in the corresponding second data storage unit. A plurality of data adding sections to be output;
A first stream generation unit configured to stream each output data of the plurality of data addition units in an output order and generate a data stream;
A stream encryption device. A stream decryption device for decrypting a data stream streamed in units of a reference block in which reference data is added to a predetermined amount of encrypted data,
A plurality of third data storage units for sequentially storing the reference blocks;
A plurality of data removal units that are connected in association with each of the plurality of third data storage units, remove the reference data from the reference blocks stored in the corresponding third data storage units, and extract the encrypted data When,
A plurality of pieces of decryption data that are connected in association with each of the plurality of data removal units and that sequentially decrypt the encrypted data extracted by the corresponding data removal units for each reference data amount for decryption. A decryption unit of
A plurality of fourth data storage units each having the predetermined amount of storage capacity, connected in association with each of the plurality of decoding units, and storing the decoded data generated by the corresponding decoding unit;
A second stream generation unit that generates a data stream by streaming the decoded data for the storage capacity in each fourth data storage unit in the order in which the data is stored;
A stream decoding apparatus comprising: The data streams are sequentially stored in a plurality of first data storage units each having the same storage capacity,
Each of the plurality of encryption units connected in association with each of the plurality of first data storage units stores the data stored in the corresponding first data storage unit for each reference data amount for encryption. In order to generate encrypted data,
Each of the plurality of second data storage units each having the same storage capacity and connected in association with each of the plurality of encryption units stores the encrypted data generated by the corresponding encryption unit. And
Each of the plurality of data adding units connected in association with each of the plurality of second data storage units is provided on the condition that encrypted data corresponding to the storage capacity is stored in the corresponding second data storage unit. Add the desired reference data and output it,
A stream encryption method in which a first stream generation unit streams each output data of the plurality of data addition units in the order of output and generates a data stream. A stream decryption method for decrypting a data stream streamed in units of standard blocks in which reference data is added to a predetermined amount of encrypted data,
Each of the plurality of third data storage units sequentially stores the reference block,
Each of a plurality of data removal units connected in association with each of the plurality of third data storage units removes the reference data from the reference block stored in the corresponding third data storage unit, and Extract data,
Each of the plurality of decryption units connected in association with each of the plurality of data removal units sequentially decrypts the encrypted data extracted by the corresponding data removal unit for each reference data amount for decryption. To generate decrypted data,
Each of the plurality of fourth data storage units each having the predetermined amount of storage capacity and connected in association with each of the plurality of decoding units receives the decoded data generated by the corresponding decoding unit. Accumulate,
A stream decoding method in which a second stream generation unit generates a data stream by streaming the decoded data corresponding to the storage capacity in each fourth data storage unit in the order in which the data is stored.

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