JP4254561B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a non-volatile semiconductor memory device using a non-volatile semiconductor memory cell having a two-layer gate structure of a floating gate and a control gate and capable of electrically writing, reading, and erasing information. The present invention relates to a semiconductor memory device having a feature in an electron emission circuit.

A nonvolatile semiconductor memory capable of electrically writing, erasing and reading information is known as an EEPROM (Electrically Erasable Programmable Read Only Memory), and a typical example is a flash memory.
FIG. 6 is a schematic cross-sectional view showing one structural example of a memory cell of a flash memory. As shown in the figure, the memory cell 100 is formed on the surface of the silicon substrate 101 in order over the p-type silicon substrate 101, the source region 102 and the drain region 103 formed in the surface layer portion, and the two regions. The gate insulating film (tunnel oxide film) 104, the floating gate 105, the insulating film 106, and the control gate 107 are constituted by a MOS transistor having a two-layer gate structure. The source region 102, the drain region 103, and the control gate 107 are connected to the source terminal S, the drain terminal D, and the gate terminal G, respectively.

  In the memory cell (MOS transistor) 100 having such a structure, the threshold voltage with reference to the control gate 107 changes depending on whether electrons are accumulated in the floating gate 105 or not. Information is stored using this. If a state in which electrons are accumulated in the floating gate 105 is a binary “1” storage state, a state in which no electrons are stored is a “0” storage state.

For example, electrons are injected into the floating gate 105 by setting the source terminal S to the reference potential (0 V) and applying a positive high voltage (for example, 12 V) to the gate terminal G and a positive voltage (for example, 6 V) to the drain terminal D. Apply. Then, hot electrons generated near the drain region 103 are injected into the floating gate 105 over the energy barrier.
On the other hand, the electrons accumulated in the floating gate 105 are released by extracting electrons through the gate insulating film 104 by a tunnel effect. In this case, there are roughly two ways of applying a voltage to the transistor 100. In the first method, as shown in FIG. 6, a high voltage + Vpp (for example, 12 V) is applied to the source terminal S with the gate terminal G as a reference potential (0 V). The drain terminal D is opened, and the silicon substrate 101 and the gate terminal G are set to a reference potential (0 V). When a voltage is applied in this way, a strong electric field is generated between the floating gate 105 and the source region 102, and electrons accumulated in the floating gate 105 pass through the gate insulating film 104 by the tunnel effect and enter the source region 102. Extracted.

  In the second method, as shown in FIG. 7, a negative high voltage −Vpp (for example, −10 V) is applied to the gate terminal G, and a positive voltage Vcc (for example, 5 V) is applied to the source terminal S. It is. (When performing partial erasure, the source terminal S of the memory cell that is not erased is set to the reference voltage (0 V)). The drain terminal D is open, and the silicon substrate 101 is set to a reference potential (0 V). When the voltage is applied in this way, a strong electric field is generated between the floating gate 105 and the source region 102 in the memory cell in which the positive voltage Vcc is applied to the source terminal S, as in the first method. Electrons accumulated in the floating gate 105 pass through the gate insulating film 104 and are extracted to the source region 102 by a tunnel effect.

  By the way, in the case of the first method for erasing the electrons accumulated in the floating gate 105, a strong electric field is also generated between the source region 102 and the silicon substrate 101. For this reason, a junction leakage current flows between the two junctions, causing a problem in boosting the high voltage + Vpp. Further, avalanche hot holes and avalanche electrons are generated by a strong electric field and trapped in the gate insulating film (tunnel oxide film) 104, thereby deteriorating the film quality and causing a problem of reliability reduction such as a reduction in rewriting life.

In the case of the second method as well, although not as much as in the first method, a strong electric field is generated between the source region 102 and the silicon substrate 101 in order to apply the positive voltage Vcc to the source region 102. It causes the same problem as the method.
Japanese Patent Laid-Open No. 06-168597 Japanese Patent Laid-Open No. 08-31186

According to a first aspect of the present invention for solving the above problem, the first conductivity type well is formed in the second conductivity type well opposite to the first conductivity type formed on the surface layer portion of the first conductivity type silicon substrate. In a non-volatile semiconductor memory device using as a memory cell a MOS transistor in which a source region and a drain region are formed, and a two-layer gate of a floating gate and a control gate is provided on the surface with an insulating layer interposed therebetween, a negative voltage is applied to the control gate. The well is set to a reference potential, and the drain and the source are set to the reference potential or open to release the electrons accumulated in the floating gate .

  According to a first aspect of the present invention for solving the above problem, the first conductivity type well is formed in the second conductivity type well opposite to the first conductivity type formed on the surface layer portion of the first conductivity type silicon substrate. In a non-volatile semiconductor memory device using as a memory cell a MOS transistor in which a source region and a drain region are formed, and a two-layer gate of a floating gate and a control gate is provided on the surface with an insulating layer interposed therebetween, a negative voltage is applied to the control gate. Is applied to the well, and the well is set to a reference potential, and the drain and the source are set to the reference potential or open to release the electrons accumulated in the floating gate.

  According to such a configuration, since the source region and the drain region are maintained at the reference potential (0 V) or are in an electrically open state, the junction surface between the source region, the drain region, and the well is strong. No electric field is generated. Therefore, no junction leakage current flows through the junction between the two, and no problem is caused in boosting the negative high voltage. In addition, since no strong electric field is generated, avalanche hot holes and avalanche electrons are not generated, and problems such as deterioration of film quality due to trapping of them in the gate insulating film and a decrease in reliability due to a decrease in rewriting life due to them are not generated. There is an effect.

Further, the memory cell rows, and arranged in matrix of columns, the control gates of each memory cell is connected to a common word line row by row, to a common source line in the source region column unit, each The drain region is connected to a common bit line in column units, the well is formed in common in column units, a negative voltage is applied to the i row word lines, the word lines other than i rows are opened, and j The drain line, the source line, and the well in the column are set to the reference potential, and the negative voltage that is the same as the negative voltage applied to the i-row word line is applied to the drain line, the source line, and the well other than the j column. Electrons accumulated in the floating gates of the memory cells arranged in the j column are emitted .

According to such a configuration, when the electrons accumulated in the floating gates of the memory cells arranged in the selected i rows and j columns are discharged, the wells of all the memory cells arranged in a matrix are obtained. The potentials of the source region and the drain region are the same, and no electric field is generated between them .

The invention according to claim 2, in the nonvolatile semiconductor memory device according to claim 1, in the i row word line by applying a negative voltage, the word lines other than the i-th row is set to open or reference potential, The drain line, the source line, and the well are all set to a reference potential to discharge electrons accumulated in floating gates of all memory cells arranged in i rows.

  According to such a configuration, when the electrons accumulated in the floating gates of the memory cells arranged in the selected i-row are discharged, the wells, the sources of all the memory cells arranged in a matrix are released. The potentials of the region and the drain region are the same, and no electric field is generated between them. Therefore, the same effect as that of the invention described in claim 1 can be obtained.

The invention according to claim 3, in the nonvolatile semiconductor memory device according to claim 1, wherein the all of the word lines and applying a negative voltage, the drain line and the source line and the well and all the reference potential Thus, electrons accumulated in the floating gates of all the memory cells arranged in a matrix are emitted.

  According to such a configuration, when the electrons accumulated in the floating gates of all the memory cells arranged in a matrix are released all at once, the potentials of the wells, the source regions, and the drain regions of all the memory cells. Are the same and no electric field is generated between them. Therefore, the same effect as that of the invention described in claim 1 can be obtained.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing one structural example of a memory cell used in a nonvolatile semiconductor memory device according to the present invention. At the same time, a voltage application method in the case of discharging electrons accumulated in the floating gate is also shown.
As shown in FIG. 1, the memory cell 1 of this embodiment includes a first conductivity type (n-type in the figure) silicon substrate 2 and a second conductivity type opposite to the first conductivity type formed on the surface layer portion ( The figure shows a p-type well 3, a first conductivity type (n ⁺ type in the figure) source region 4 and a first conductivity type (n ⁺ type in the figure) drain region 5 formed on the surface, and the source region. 4 and the drain region 5, the gate insulating film 6 formed on the well 3, the floating gate 7 formed on the gate insulating film 6, the insulating film 8 formed on the floating gate 7, and the insulating film 8 is composed of a MOS transistor having a two-layer gate structure including a control gate 9 formed on the substrate 8.

The source region 4, the drain region 5, the control gate 9 and the well 3 are connected to the source terminal S, the drain terminal D, the gate terminal G and the well terminal W, respectively.
The floating gate 7 is formed of polysilicon and is surrounded by a perfect insulator so that electrons injected into the floating gate 7 are not discharged. Accordingly, the state in which electrons are accumulated in the floating gate 7 is associated with, for example, the data “1” storage state, and the state in which no electrons are accumulated is associated with the data “0” storage state to store binary data. be able to.

  In the memory cell 1 of the present embodiment, when the electrons accumulated in the floating gate 7 are emitted, as shown in FIG. 1, a negative voltage −Vpp (for example, −12V) is applied to the control gate 9 via the gate terminal G. On the other hand, the well 3 is connected to the reference potential (0V) side terminal of the negative voltage generation circuit 10 through the well terminal W to be kept at the reference potential (0V). The source terminal S is set to a reference potential (0 V) or open. The drain terminal D is also set to the reference potential (0 V) or open.

  When a voltage is applied to each terminal in this way, a strong electric field is generated in the thin gate insulating film 6 sandwiched between the floating gate 7 and the well 3, and the electrons accumulated in the floating gate 7 are gate-insulated by the tunnel effect. It is extracted into the well 3 through the membrane 6. That is, the electrons accumulated in the floating gate 7 are released. The extracted electrons flow out to the reference potential (0 V) side terminal of the negative voltage generation circuit 10 through the well terminal W.

  In this case, since the source region 4 and the drain region 5 are maintained at the reference potential (0 V) or are electrically open, an electric field is applied to the junction between the source region 4 and the drain region 5 and the well 3. Does not occur. Therefore, as described in the “Background Art” section, the junction leakage current does not flow through the junction between the two, and no problem is caused in boosting the negative high voltage −Vpp. In addition, since a strong electric field is not generated, avalanche hot holes and avalanche electrons are not generated, and thus there is a problem of deterioration in reliability such as deterioration of film quality due to trapping of them in the gate insulating film 6 and reduction of rewrite life. There is an effect that does not occur.

When electrons are injected into the floating gate 7, the positive voltage + Vpp (for example, 12V) generated by the positive voltage generation circuit 11 is used as the gate terminal G, the well terminal W and the source terminal S as shown in FIG. The drain terminal D is opened to the reference potential (0 V). In this way, electrons are injected from the well 3 to the floating gate 7 by the tunnel effect.
In the above description, the first conductivity type is n-type and the second conductivity type is p-type. However, the same operation is performed when the first conductivity type is p-type and the second conductivity type is n-type.

  FIG. 3 conceptually shows a configuration of a nonvolatile semiconductor memory device in which the memory cells 1 shown in FIG. 1 are arranged in a matrix of rows and columns. The nonvolatile semiconductor memory device 12 includes a memory array 13 in which the memory cells 1 are arranged in a matrix of 16 rows × 4 columns, for example, and a peripheral circuit 14 that supplies a voltage to the memory array 13. The peripheral circuit 14 conceptually shows only a portion necessary for explaining how to apply a voltage in the case where electrons accumulated in the floating gate of each memory cell, which is the point of the present invention, are emitted. It is.

  The control gates of the memory cells arranged in the memory array 13 are common to the word lines WL0 to WL15 in rows, the source terminals are common to the source lines SL0 to SL3 in columns, and the drain terminals are common in columns. Are connected to the bit lines BL0 to BL3. In the memory array 13 of this embodiment, the wells of the memory cells are formed in common in units of columns, and the wells in each column are electrically separated from the wells in the adjacent columns.

  The common well in units of columns is connected to the analog switches S0W to S3W via the respective well potential lead lines WELL0 to WELL3. The word lines WL0 to WL15 are connected to analog switches S0G to S3G, the source lines SL0 to SL3 are connected to analog switches S0S to S3S, and the bit lines BL0 to BL3 are connected to analog switches S0D to S3D, respectively.

Each analog switch is switched according to the mode of erasing data, writing data, and reading data stored in the memory cell, and each analog switch has a voltage required to operate in those modes via each analog switch. Applied to the memory cell.
The switching state of the analog switch and the state of the applied voltage shown in FIG. 3 show a state in which electrons accumulated in the floating gates of the memory cells A arranged in the 2nd row and the 2nd column are emitted as an example. In this case, a negative voltage −Vpp (for example, −12 V) is applied to the word line WL1 in the second row via the analog switch S1G, and the other word lines are electrically opened. The well potential lead line WELL1 in the second column is set to the reference potential (0 V) via the analog switch S1W, and a negative voltage −Vpp is applied to the other well potential lead lines. The source line SL1 in the second column is set to the reference potential (0 V) via the analog switch S1S, and the negative voltage −Vpp is applied to the other source lines. The bit line BL1 in the second column is set to the reference potential (0 V) via the analog switch S1D, and the negative voltage −Vpp is applied to the other bit lines.

When the voltage is applied in this manner, in the selected memory cell A in the second row and the second column, the control gate voltage is the negative voltage −Vpp, and the source region, the drain region, and the well are all at the reference potential (0 V). A strong electric field is generated between the floating gate and the well, and the electrons accumulated in the floating gate are released to the well.
In addition, in the memory cells arranged in the second column excluding the memory cell A, for example, the memory cell B, the control gate is in an open state, the source region, the drain region, and the well are all at the reference potential (0 V). Since no strong electric field is generated during this period, electrons accumulated in the floating gate are not emitted to the well.

In addition, the memory cells arranged in the second row excluding the memory cell A, for example, the memory cell C, have all the voltages of the control gate, the source region, the drain region, and the well become negative voltage −Vpp. A strong electric field is not generated between them, and the electrons accumulated in the floating gate are not emitted to the well.
In addition, in the memory cell that does not belong to the second row or the second column, for example, the memory cell D, the control gate is in an open state, and the source region, drain region, and well voltages are all negative voltage −Vpp. Since no electric field is generated between them, the electrons accumulated in the floating gate are not emitted to the well.

As described above, when the voltage application as shown in FIG. 3 is applied to the memory array 13, only the selected memory cell A in the second row and the second column stores the electrons accumulated in the floating gate. Extracted into a well. That is, electrons are emitted in bit units.
In this case, the potentials of the respective wells, source regions, and drain regions are the same for all the memory cells, and no strong electric field is generated therebetween. Therefore, as in the case of FIG. 1, no junction leakage current flows through the junction between the well and the source region and the well and the drain region, so that no problem arises in boosting the negative voltage −Vpp. In addition, since avalanche hot holes and avalanche electrons are not generated, the problem of deterioration in reliability such as deterioration of the film quality of the gate insulating film and reduction of the rewrite life does not occur.

FIG. 4 shows another embodiment of voltage application when the electrons stored in the floating gates of the memory cells constituting the memory array 13 are emitted. In the configuration of FIG. 3, electrons accumulated in the floating gate are released in bit units, but in the present embodiment, electrons accumulated in the memory cells are emitted in row units (word units).
The switching state of the analog switch and the state of the applied voltage shown in FIG. 4 show a state in which electrons accumulated in the floating gates of all the memory cells arranged in the second row are emitted as an example. As shown in the figure, in this case, a negative voltage -Vpp (for example, -12 V) is applied to the word line WL1 in the second row via the analog switch S1G, and the other word lines are in an electrically open state or a reference. The potential is set to 0V. Further, all the well potential lead lines WELL0 to WELL3, all the source lines SL0 to SL3, and all the bit lines BL0 to BL3 are set to the reference potential (0 V) via the analog switches connected to the respective lines.

When the voltage is applied in this way, in all the memory cells arranged in the selected second row, the voltage of the control gate is negative voltage −Vpp, and the source region, drain region, and well are all at the reference potential (0 V). Therefore, a strong electric field is generated between the floating gate and the well, and the electrons accumulated in the floating gate are released to the well.
On the other hand, in the memory cells arranged in rows other than the second row, the control gate is in an open state or the reference potential (0V), the source region, the drain region, and the well are all at the reference potential (0V). Since no electric field is generated between the well and the well, electrons accumulated in the floating gate are not emitted to the well. Accordingly, only the electrons accumulated in the floating gates of the memory cells arranged in the selected second row are extracted to the well. That is, electrons are emitted in units of words.

  In this case, the potentials of the respective wells, source regions, and drain regions are the same for all the memory cells, and no strong electric field is generated therebetween. Therefore, as in the case of FIG. 1, no junction leakage current flows through the junction between the well and the source region and the well and the drain region, so that no problem arises in boosting the negative voltage −Vpp. In addition, since avalanche hot holes and avalanche electrons are not generated, the problem of deterioration in reliability such as deterioration of the film quality of the gate insulating film and reduction of the rewrite life does not occur.

FIG. 5 shows still another embodiment of voltage application in the case where electrons stored in the floating gates of the memory cells constituting the memory array 13 are emitted. In this embodiment, electrons accumulated in the floating gates of all the memory cells in the memory array 13 are simultaneously emitted simultaneously.
As shown in FIG. 5, in this embodiment, a negative voltage −Vpp (for example, −12 V) is applied to all the word lines WL0 to WL3 via the analog switches S0G to S3G. All of the well potential lead lines WELL0 to WELL3, all of the source lines SL0 to SL3, and all of the bit lines BL0 to BL3 are set to the reference potential (0 V) via the analog switches connected to the respective lines.

  When the voltage is applied in this way, the voltage of the control gate is negative voltage −Vpp and the source region, the drain region, and the well are all at the reference potential (0 V) for all the memory cells. A strong electric field is generated, and the electrons accumulated in the floating gate are released to the well. That is, the electrons accumulated in the floating gates of all the memory cells in the memory array 13 can be emitted all at once.

  Also in this case, the potentials of the wells, the source region, and the drain region are the same for all the memory cells, and no strong electric field is generated between them. Therefore, as in the case of FIG. 1, no junction leakage current flows through the junction between the well and the source region and the well and the drain region, so that no problem arises in boosting the negative voltage −Vpp. In addition, since avalanche hot holes and avalanche electrons are not generated, the problem of deterioration in reliability such as deterioration of the film quality of the gate insulating film and reduction of the rewrite life does not occur.

FIG. 3 is a schematic cross-sectional view of a memory cell according to the present invention and a method of applying a voltage when electrons accumulated in a floating gate are emitted. It is the figure which showed how to apply the voltage when injecting electrons into the floating gate. It is the figure which showed the method of the voltage application in the case of discharging the electron accumulate | stored in the floating gate of the memory cell in a memory array per bit. It is the figure which showed the method of the voltage application in the case of discharging | emitting the electron accumulate | stored in the floating gate of the memory cell in a memory array per word. It is the figure which showed the method of voltage application in the case of discharging | emitting the electron accumulate | stored in the floating gate of all the memory cells in a memory array simultaneously. FIG. 2 is a view corresponding to FIG. It is another figure equivalent to FIG. 1 which concerns on a prior art.

Explanation of symbols

In the drawings, 1 is a memory cell (MOS type transistor), 2 is a silicon substrate, 3 is a well, 4 is a source region, 5 is a drain region, 6 is a gate insulating film, 7 is a floating gate, 8 is an insulating film, 9 is Control gate, 12 is a nonvolatile semiconductor memory device, 13 is a memory array, BL0 to BL3 are bit lines, D is a drain terminal, G is a gate terminal, S is a source terminal, SL0 to SL3 are source lines, W is a well terminal, WL0 to WL3 are word lines, WELL0 to WELL3 are well potential lead lines, 0V is a reference potential, and -Vpp is a negative voltage.

Claims (3)

A source region and a drain region of the first conductivity type are formed in a well of a second conductivity type opposite to the first conductivity type formed on the surface layer portion of the silicon substrate of the first conductivity type, and an insulating layer is sandwiched on the surface thereof. In a nonvolatile semiconductor memory device using a MOS transistor having a floating gate and a two-layer gate of a control gate as a memory cell, a negative voltage is applied to the control gate, the well is set as a reference potential, and the drain and source are Electrons accumulated in the floating gate are discharged as a reference potential or open , and the memory cells are arranged in a matrix of rows and columns, and the control gates of the memory cells are shared in units of rows. Each source region is connected to a common source line in column units, each drain region is connected to a common bit line in column units, and the wells are formed in common in column units. A negative voltage is applied to the i-th word line, word lines other than the i-th line are opened, j-line drain lines, source lines, and wells are set to reference potentials, and the j-column drain lines, source lines, By applying a negative voltage identical to the negative voltage applied to the i-row word line to the well, electrons accumulated in the floating gates of the memory cells arranged in the i-row and j-column are discharged. A nonvolatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a negative voltage is applied to the i-row word line, word lines other than the i-row are opened or set to a reference potential, and the drain line, the source line, and the well are all reference. A non-volatile semiconductor memory device characterized in that electrons stored in the floating gates of all memory cells arranged in i rows are discharged by using a potential. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a negative voltage is applied to all of the word lines, and all of the drain lines, source lines, and wells are set to a reference potential, thereby arranging all of them in a matrix. A non-volatile semiconductor memory device that discharges electrons accumulated in a floating gate of the memory cell .

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