JP4252577B2 - Microcomputer and data receiving method - Google Patents

Description

  The present invention relates to the realization of a protocol stack with a small program capacity. Specifically, the present invention relates to a microcomputer having a TCP / IP protocol stack and a data receiving method. And effective technology.

TCP / IP (Transmission Control Protocol / Internet Protocol) has been developed as a core technology of the network and is now the de facto standard for communication. The details of the protocol are variously defined by a large number of RFCs (Request of Comments) compiled by IETF (Internet Engineering Task Force), an organization for solving problems of the Internet. Conventionally, data communication using the TCP / IP protocol is realized by a software protocol stack processed by a CPU (Central Processing Unit) and a hardware network interface that performs packet communication processing of a MAC (Media Access Control) layer. .
Regarding the implementation of the protocol stack, Japanese Patent Laid-Open No. 2003-143221 provides a hardware protocol stack that can be executed independently of OS control. An attempt is made to guarantee real-time communication processing by preventing protocol processing executed by software under OS control from being blocked by other priority processing.
In Patent Document 2 (Japanese Patent Laid-Open No. 2003-263323), since the capacity of a program increases when a protocol stack is mounted together with an OS, a self-rewriting program including a simple communication program and a self-rewriting program can be used to reduce this. Enables upgrades to download functions and handling of advanced functions.

The present inventor examined the support of the TCP / IP protocol in network home appliances and the like. In particular, a TCP / IP protocol stack operable on a built-in ROM / RAM such as a 16-bit microcomputer for embedded control was examined. According to this, there is no idea of extremely saving resources in the already defined protocols. Implementing the TCP / IP protocol according to such protocol details requires a large storage capacity ROM to store the protocol stack and a large storage capacity work RAM to execute the protocol stack. The technique described in the above patent document is different from the technique studied by the present inventors.
An object of the present invention is to enable network connection using a TCP / IP protocol for a small-scale system such as a network home appliance.
Another object of the present invention is to provide a data processing method that can contribute to the realization of a compact TCP / IP protocol stack.
The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
[1] A microcomputer according to the present invention is formed in one semiconductor chip including a central processing unit, a RAM and a ROM, and the ROM is called and executed by an operating system, an application program, and the application program. A TCP / IP processing program is stored, and the TCP / IP processing program includes a connection request, event wait, data transmission, and connection disconnection processing program. The central processing unit reads a part of packet data into the RAM in response to a task switch command, for example, a data reception interrupt during execution of a processing program waiting for an event, and wakes up from an event waiting state when the packet data is required. Then, the application program is executed to fetch the corresponding packet data into the RAM.
Since a part of the received packet data in the MAC layer may be taken into the on-chip RAM of the microcomputer and analyzed, the work RAM which does not need processing for taking all the packet data into the work RAM and expanding it is required. The size of can be small. Further, the process of fetching the packet data into the on-chip RAM according to the result of the analysis is directly performed by the application program and does not use the protocol stack. As a result, the protocol stack can be made compact.
[2] A microcomputer according to another aspect of the present invention includes a central processing unit, a RAM and a ROM, and is formed on one semiconductor chip. The ROM is called from an operating system, an application program, and the application program. The processing program for TCP / IP to be executed is stored, and the RAM is used as a work area when the CPU executes the program. The processing program for TCP / IP includes service start, connection request, event wait, data It has a processing program for transmission and connection disconnection.
By giving a wake-up factor from the event waiting state to the event waiting processing program, it becomes possible to return to the application program and directly take in necessary packet data.
As a specific form of the present invention, the event to be waited for in the event may be connection establishment, connection disconnection, data reception, and event wait timeout. The type of event to be waited for in the event-waiting processing program is preferably specified by the application program. At this time, in response to a predetermined interrupt, the event-waiting processing program fetches a predetermined part of packet data from the outside into the RAM, and checks whether the corresponding packet is a necessary packet by checking the fetched data. And waits for an event when it is determined necessary. Then, in response to the end of the data reception event waiting state, the application program may capture the data of the corresponding reception packet into the RAM.
In the microcomputer having the above configuration, the storage capacity of the on-chip RAM can be reduced to about 2 to 4 kilobytes.
[3] In the data receiving method according to the present invention, a predetermined portion of the packet data stored in the buffer memory of the communication device constituting the TCP / IP MAC layer is read out and stored in the on-chip RAM of the microcomputer. When the packet data is determined to be necessary in one process, the second process for determining whether or not the corresponding packet is necessary by inspecting the data stored in the on-chip RAM, and the determination process. And a third process of storing a necessary part of the corresponding packet data from the buffer memory in the on-chip RAM. If it is determined in the determination process that the packet data is unnecessary, the corresponding packet data is discarded. Discarding means not storing in the on-chip RAM.
Since a part of the received packet data may be taken into the on-chip RAM of the microcomputer in the first process and analyzed in the second process, a process of taking all the packet data into the work RAM and expanding it is required. Therefore, the required work RAM size can be reduced.
By defining the first process and the second process with the protocol stack and the third process with the application program, the process of fetching the packet data into the on-chip RAM according to the analysis result of the third process is directly performed by the application program. Since the protocol stack is not used, the protocol stack can be made compact.
In a specific form of the present invention, the data of the predetermined portion is data of the 13th byte to the 42th byte from the beginning of the packet format in Internet Protocol version 4. If analyzed up to this point, ARP (Address Resolution Protocol), ICMP (Internet Control Message Protocol), TCP, UDP (User Datagram Protocol) can be dealt with.

FIG. 1 is a block diagram of a microcomputer according to the present invention.
FIG. 2 is a CPU address map.
FIG. 3 is an explanatory diagram showing the types of seven types of API programs held by the TCP / IP protocol stack.
FIG. 4 is an explanatory diagram showing a list of events recognized by the event waiting API program.
FIG. 5 is a flowchart of packet data reception processing by TCP / IP.
FIG. 6 is an explanation showing a packet format of the TCP / IP protocol in a broad sense.
FIG. 7 is an explanatory view schematically showing how 42 bytes of packet data are extracted from the buffer memory.
FIG. 8 is a flowchart showing details of the protocol analysis process (S4) of FIG.
FIG. 9 is a flowchart of TCP / IP passive connection processing.
FIG. 10 is a flowchart of active connection processing by TCP / IP.
FIG. 11 is a flowchart of data transmission processing by TCP / IP.
FIG. 12 is a flowchart of forced disconnection for TCP / IP connection.
FIG. 13 is a flowchart of normal disconnection for TCP / IP connection.

FIG. 1 shows a block diagram of a microcomputer according to the present invention. The microcomputer 1 shown in the figure is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon and formed into one chip or pellet by a complementary MOS integrated circuit manufacturing technique or the like. Packaged as needed.
The microcomputer 1 is not particularly limited, but includes a CPU (Central Processing Unit) 2, a clock oscillator 3, an interrupt controller 4, a DMAC (Direct Memory Access Controller) 5, a rewritable nonvolatile memory such as a flash memory, or ROM (Read Only Memory) 6 composed of mask ROM, RAM 7 composed of SRAM (Static Random Access Memory), Refresh Controller 8, WDT for monitoring system operation abnormality by the number of clock cycles (Watch Dog Timer) 9, TCU (Timer Counter Unit) 10, SCI (Serial Communication Interface) 11, USB (Universal Serial Bus) 12, AD (Analog / Digital) It has a converter 13, bus controller 14, and input-output ports 15, which are connected to the internal bus represented by reference numeral 16.
Although not shown, the CPU 2 has an instruction control unit and an execution unit. The instruction control unit accesses a program stored in the ROM 6 or the like, fetches an instruction, decodes the fetched instruction, and generates control information. The execution unit executes an instruction by performing an operation, an operand access, or the like according to the control information.
Although not particularly limited, the Ethernet device 20 constituting the network interface card (NIC) is connected to the input / output port 15. The Ethernet device 20 is connected to the Ethernet cable 21 and implements a hardware network interface that performs packet communication processing of the MAC layer. Although not particularly limited, the Ethernet device 20 includes an Ethernet controller 22, a buffer memory 23, a transceiver / receiver 24 coupled to the Ethernet cable 21, and the like.
The microcomputer 1 is a TCP / IP processing program (simply TCP / IP) as a protocol stack of software processed by the hardware Ethernet device 20 and CPU 2 for performing packet communication processing in order to perform data communication by the TCP / IP protocol. Protocol stack). The TCP / IP protocol stack is called from an application program and executed. Application programs include browser software and mail software. The TCP / IP protocol stack and application programs are stored in the ROM 6 together with an operating system (OS) and the like.
FIG. 2 illustrates an address map of the CPU 2. In the address space of the ROM 6, a vector, an OS, a TCP / IP protocol stack, and an application program are arranged from the top. The application program includes programs other than data communication, and may be understood as a so-called user program that is incorporated according to the needs of the user of the microcomputer 1. An OS work area (OS work), a stack area, a TCP / IP protocol stack work area (TCP / IP work), and an application program work area (user work) are allocated to the address space of the RAM 7.
FIG. 3 shows seven types of API programs held by the TCP / IP protocol stack. The service start API program is a processing program for performing initial settings for TCP / IP communication. Examples of the initial setting items include initialization of the Ethernet device 20 and initialization of the TCP / IP work. The passive connection setting API program is a processing program for setting the IP address and port number of the own port in order to wait for connection. The active connection request API program is a processing program for setting a partner port for requesting connection. The event waiting API program is a processing program that waits for a response to a setting or request. The data transmission API program is a processing program that transmits data. The connection closing API program is a processing program that blocks its own connection and leaves the other party to block the connection. The forced disconnection API program is a processing program that forcibly cuts off both the own connection and the other party's connection. The event waiting API program is a processing program for waiting for the occurrence of a predetermined event.
FIG. 4 shows a list of events recognized by the event waiting API program. The events to be recognized include the establishment of a passive / active connection to be confirmed after execution of the passive connection setting API program or the active connection API program, the close completion to be confirmed after execution of the connection close API program, and the forced disconnection API program. Forced close to be confirmed after execution, data reception that data has been received, data transmission to be confirmed after execution of the API program for data transmission, event waiting timeout (wait timeout) by the event waiting API program . Which event is to be waited is instructed from the application program by a flag or the like.
FIG. 5 illustrates a flowchart of packet data reception processing by TCP / IP. The packet data reception process is based on the assumption that the service start API program is executed and the communication settings are initialized, and then the passive connection setting or active connection setting API program is executed and the connection is established. It is said. Under this assumption, the data reception event flag is set from the application program, and the event waiting API program is called and executed. The contents of the execution are the processing shown in FIG. 5. First, it waits for a packet data reception interrupt from the Ethernet device 20 (S1).
The Ethernet device 20 sequentially receives the received packet data in the buffer memory 23, and outputs a packet data reception interrupt to the microcomputer 1 in response to the data reception. TCP / IP packet data, for example, has the format shown in FIG. 6 in the Internet protocol version 4, and includes ARP (address resolution protocol) and ICMP (Internet) included in the broad TCP / IP protocol. -In the packet formats of all protocols such as control message protocol (TCP), TCP, and UDP (user datagram protocol), the first 14 bytes are used as MAC layer control information, followed by a header and necessary data. Is accompanied. ICMP is a protocol for transferring IP error messages and control messages, and is used to check each other's status between computers connected via TCP / IP. TCP is a network transport layer protocol. UDP is a transport layer communication protocol that does not guarantee reliability. In the packet format of FIG. 6, the last two bytes of the 14-byte MAC layer control information indicate the packet type, and by referring to the data of at least 42 bytes therefrom, the protocol type of the packet data, the destination IP address And port number. In short, it can be seen whether the packet data is packet data required by the microcomputer in terms of function as a communication channel. In the processing flow of FIG. 5, when there is a packet data reception interrupt, 42 bytes of the packet data are read from the buffer memory 23 into the RAM 7 (S2). It is determined from the read data whether the packet is addressed to its own IP address (S3). If not, the packet data is discarded. To discard means that the packet data is not read from the buffer memory 23 into the RAM 7. If it is determined in step S3 that the data is addressed to its own IP address, the packet data is read from the buffer memory 23 into the RAM 7 and protocol analysis is performed (S4). According to this, since a part of the received packet data in the MAC layer has only to be taken into the on-chip RAM 7 of the microcomputer 1 and analyzed, it is necessary to perform a process of taking all the packet data into the work area of the RAM 7 and expanding it. The required size of the on-chip RAM 7 can be reduced. Incidentally, the capacity of the RAM 7 is about 2K to 4K bytes.
FIG. 7 schematically shows how 42 bytes of packet data are extracted from the buffer memory 23. The buffer memory 23 operates as a ring buffer. Packet data in the ring buffer is managed in units of pages. The Ethernet controller 23 has an MMU function for the RAM 7, and the CPU 2 uses this to read 42 bytes of data from the 13th byte to the work area (TCP / IP work) of the RAM 7 for the packet data in the page.
FIG. 8 illustrates details of the protocol analysis process (S4) of FIG. Based on the 42-byte packet data read into the RAM 7, the CPU 2 determines whether the protocol of the packet data corresponds to ARP, ICMP, TCP, UDP, or the like. In the case of ARP, an ARP reply is transmitted, and in the case of ICMP, an ICMP reply is returned. For TCP, the port number and the IP address are confirmed, and the packet data is discarded if it is not addressed to its own address. If it is addressed to its own address, if it is a control packet, a TCP reply is returned, and if it is a data packet, it wakes up from an event waiting state. Here, to wake up from the event waiting state means to end the execution of the event waiting API program, and the control of the CPU 2 shifts to the application program, and the data portion (transfer data) of the corresponding packet data is transferred according to the application program. The data is transferred from the buffer memory 23 to the RAM 7. The application program performs necessary data processing on the packet data transferred to the RAM 7. According to this, the process of fetching the packet data into the on-chip RAM 7 according to the result of the analysis is directly performed by the application program, and the protocol stack is not used. As a result, the protocol stack can be made compact. For example, the capacity of the ROM 6 is 32 Kbytes.
In the case of TCP, the occurrence of an event is recognized by protocol analysis for 42-byte packet data. In FIG. 8, the recognition of such an event is defined as connection establishment (SLEV_CONNECT), connection request success, data transmission completion (SLEV_TEND), connection disconnection (SLEV_RST), and disconnection request success (SLEV_CLS). Incidentally, the data reception event (SLEV_RX) is recognized by the Rx interrupt. When an event is recognized, it wakes up from the corresponding event waiting state, and the processing of the CPU 2 is shifted to an application program or another API program in accordance with the event.
Although FIG. 8 does not particularly show the processing when UDP is recognized, it can be considered almost the same as in the case of TCP. However, it is more simplified than TCP. For other protocols not supported by the system, the packet data is discarded.
FIG. 9 illustrates a flowchart of passive connection processing by TCP / IP. When execution of the passive connection API program is specified by the application program, the passive connection setting API program is called from the protocol stack, the IP address and port number of the own port are set, and then the event waiting API program is executed. And wait for the connection establishment event to occur. When the event occurs, the user wakes up from the event waiting state and establishes a connection.
FIG. 10 illustrates a flowchart of active connection processing by TCP / IP. When execution of the active connection API program is specified by the application program, the API program of the active connection request is called from the protocol stack, the IP address and port number of the partner port are set, and then the event waiting API program is executed. And wait for the connection establishment event to occur. When the event occurs, the user wakes up from the event waiting state and establishes a connection.
FIG. 11 illustrates a flowchart of data transmission processing by TCP / IP. The event waiting API program is executed to wait for the occurrence of a data reception event. When a data reception event occurs, it wakes up from the event waiting state, and the processing described in FIG. 5 is performed according to the application program, and the received page number and data length on the Ethernet device necessary for transmission are acquired from the buffer memory 23 to the RAM 7. To do. Next, the process proceeds to execution of the data transmission API program, and the data on the RAM 7 is transferred to the buffer memory 23 and transmitted to the Ethernet device.
FIG. 12 illustrates a flowchart of forced disconnection for a TCP / IP connection. The CPU 2 only needs to execute a forced disconnection API program.
FIG. 13 illustrates a flowchart of normal disconnection for TCP / IP connection. The CPU 2 executes the connection closing API program and then executes the event waiting API program to wait for the event of the closing completion from the connection partner. Communication by the port number is terminated due to the occurrence of a close completion event.
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention.
For example, the storage capacities of RAM and ROM are not limited to the above description and can be changed as appropriate. The microcomputer is a general term for a system-on-chip semiconductor integrated circuit having a CPU. The CPU is not limited to a 16-bit CPU, and may be a 32-bit CPU. In terms of usage, a CPU with a particularly high function is not necessary. Further, the type and processing contents of the protocol stack processing program can be changed as appropriate. Furthermore, task switching when part of the packet data is transferred from the buffer memory to the on-chip RAM is not limited to data reception interrupts, and may be performed in response to other task switch commands.

  The present invention can be widely applied to a TCP / IP interface or the like in a small-scale system represented by a network home appliance or a portable terminal and having relatively low data processing performance.

Claims (12)

A microcomputer including a central processing unit, a RAM and a non-volatile memory and formed on one semiconductor chip,
The nonvolatile memory stores an operating system, an application program, and a TCP / IP processing program that is called and executed from the application program,
The TCP / IP processing program includes a connection request, event waiting, data transmission, and connection disconnection processing program,
The central processing unit reads a part of the packet data including the destination IP address of the packet data in response to a task switch instruction during the execution of the event waiting processing program to the RAM, and requires the packet data microcomputer, wherein the capturing ends the execution of the event waiting processing program, the data unit contained in the said packet data execute the application program to the RAM when. 2. The microcomputer according to claim 1 , wherein the task switch command is a data reception interrupt. A microcomputer including a central processing unit, a RAM and a non-volatile memory and formed on one semiconductor chip,
The nonvolatile memory stores an operating system, an application program, and a TCP / IP processing program that is called and executed from the application program,
The RAM is used as a work area when the CPU executes a program,
The TCP / IP for processing program, service start, the connection request, an event waiting, have a data transmission, and disconnection processing program,
The event waiting processing program responds to a reception interrupt signal of packet data from a communication device connected to the outside, and receives a part of data including transmission destination IP address information included in the packet data from the communication device. Fetching into RAM, determining from the fetched data whether the packet data is to be received by the microcomputer;
When the application program determines that the data to be received by the microcomputer by executing the event waiting process program, the application program fetches the data portion included in the packet data into the RAM and performs predetermined data processing. A microcomputer characterized by. 4. The microcomputer according to claim 3, wherein the events to be waited for in the event are connection establishment, connection disconnection, data reception, and event wait timeout. 5. The microcomputer according to claim 4, wherein an event type to be waited for in the event wait processing program is specified by the application program. 6. The microcomputer according to claim 5 , wherein said event waiting processing program further determines whether or not the data is to be received, and terminates the event waiting state when it is determined that the data is to be received. . 7. The microcomputer according to claim 6 , wherein the application program fetches the data part included in the packet data into the RAM in response to completion of the data reception event waiting state. 8. The microcomputer according to claim 7, wherein the storage capacity of the RAM is 2 to 4 kilobytes. A first process of reading data of a predetermined portion of packet data including the protocol type, transmission destination IP address or port number of the packet data stored in the buffer memory of the communication device and storing it in the on-chip RAM of the microcomputer;
A second process for determining whether or not a corresponding packet is necessary by inspecting data of the predetermined portion stored in the on-chip RAM;
If it said packet data in the second process is determined to be necessary, the data receiving method, which comprises a third process of storing in the on-chip RAM data portion of the packet data from the buffer memory. Wherein the first process and the second process is specified in the protocol stack, the third treatment data receiving method according to claim 9, characterized in that it is defined by the application program. 10. The data receiving method according to claim 9 , wherein when the packet data is determined to be unnecessary in the second process, the packet data is discarded. Data of a predetermined portion of packet data including the protocol type, destination IP address or port number is data from the 13th byte to the 42th byte from the beginning of the packet format in Internet Protocol Version 4 The data receiving method according to claim 10 or 11 .

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