JP4241694B2 - Optical receiver - Google Patents

Description

  The present invention relates to an optical receiver that receives an optical signal in optical communication.

FIG. 10 is a circuit diagram showing an example of the configuration of the reception signal monitoring circuit 107 used in the conventional optical receiver 100. Prefixed optical receiver 100 for amplifying a photodiode 101 which converts the signal light P _in the current signal I, the transimpedance amplifier 102 which converts the current signal I from the photodiode 101 into a voltage signal, the voltage signal An amplifier (buffer) 103 and a saturation amplification unit 106, capacitive elements 104 a and 104 b that AC-couple the preamplifier 103 and the saturation amplification unit 106, and a resistance element 105 that defines an input impedance of the saturation amplification unit 106 are provided. The reception signal monitoring circuit 107 takes in the reception signal from the subsequent stage of the capacitive elements 104a and 104b and the resistance element 105 (in FIG. 10, the subsequent stage of some amplifiers included in the saturation amplification unit 106).

  In the example of FIG. 10, the received signal monitoring circuit 107 includes peak detection units 107a and 107c, a threshold voltage generation unit 107b, and a comparator 107d. The peak detection unit 107a detects the peak level of the received signal and generates a voltage signal indicating the temporal change of the peak level. On the other hand, the threshold voltage generation unit 107b generates a threshold voltage for determining signal interruption. The peak detector 107c has the same configuration as the peak detector 107a, and detects the peak level of the threshold voltage. The comparator 107d compares the magnitude of the voltage signal from each of the peak detection units 107a and 107c, and if the voltage signal from the peak detection unit 107a is smaller than the voltage signal from the peak detection unit 107c, a reception alarm indicating an input interruption Output a signal.

  In addition to the above, received signal monitoring circuits for monitoring input interruption include those described in Patent Documents 1 and 2, for example. The optical receiver described in Patent Document 1 detects an input interruption by monitoring a photocurrent flowing through a light receiving element by a current mirror circuit and comparing the magnitude of a voltage signal converted from the monitor current with a threshold value. is doing. Further, in this optical receiver, the reception signal is branched before the capacitive element for AC coupling (capacitance elements 104a and 104b in the example of FIG. 10), and the signal level is detected.

  In addition, the optical input break detection circuit described in Patent Document 2 detects a decrease in the electrical signal level of the received signal and outputs an input break alarm signal; and a data detector reproduced from the received signal. A zero-continuous detection unit that detects that a predetermined number of zeros continue.

JP 2003-152460 A JP-A-7-95156

  In the conventional reception signal monitoring circuit 107 shown in FIG. 10, the reception signal is taken in from the subsequent stage of the AC coupling capacitors 104a and 104b and the resistance element 105, and the peak level of the reception signal is detected. In this case, since the high-pass filter is formed by the capacitive elements 104a and 104b and the resistance element 105, a delay (first-order delay) occurs in the received signal waveform. In addition, the optical receiver 100, for example, a circuit for making the gain of the transimpedance amplifier 102 variable, or a low-pass filter 109 used for converting the single-phase output signal of the transimpedance amplifier into a differential signal. In the case where a feedback circuit such as a low-pass filter 108 (see FIG. 10) for removing the offset in the saturation amplifier 106 is provided, a delay or a secondary response is generated by these circuits, and the optical signal is restored when the optical signal is interrupted. Time response is complicated.

Figure 11 (a) ~ (d) are, in the case where the signal light _{P in} is interrupted at time _{t A,} is a graph showing an example of the various parts of the signal waveform in the optical receiver 100. FIG. 11A shows an example of the waveform of the reception signal S ₁ output from the preamplifier 103. Further, FIG. 11 (b) shows an example of the received signal _{S 2} of the waveform after passing through the high pass filter due to the capacitive elements 104a and 104b and the resistance element 105. Further, FIG. 11 (c) shows an example of a waveform of the voltage signal S ₃ after the peak level has been detected by the peak detecting unit 107a. FIG. 11D shows an example of the waveform of the output signal (reception alarm signal LOS) from the comparator 107d.

As described above, prior to receiving signal S ₁ output from the preamplifier 103, delay caused by the low-pass filter 109 for converting the single-phase output signal of the transimpedance amplifier 102 into a differential signal. Accordingly, as shown in FIG. 11 (a), the waveform after time t _A of the received signals S ₁ from the positive phase signal is low potential side, from the anti-phase signal is high potential side, slowly each differential midpoint the primary response wave converging to the potential V _0. The reception signal S ₂ after passing through the high pass filter further adds a delay by the high-pass filter. Therefore, as shown in FIG. 11B, the waveform after time t _A of the received signal S ₂ is a secondary response waveform with an overshoot (undershoot) when converging to the differential midpoint potential V ₀ . Become. This overshoot waveform also appears in the voltage signal S ₃ (peak level) shown in FIG. If the overshoot waveform exceeds the threshold voltage _{V th} (time _t B _~t C shown in FIG. 11 (c)), despite the input interruption of the signal light _{P in} is continued, FIG 11 (d ), The reception alarm signal LOS is temporarily canceled.

  In Patent Document 1, in order to avoid a delay due to a high-pass filter or the like, the reception signal level in the previous stage of the capacitive element is detected. However, since the output of the current-voltage conversion circuit is branched, waveform distortion occurs when a high-frequency signal is received. Further, in the optical input break detection circuit described in Patent Document 2, when the circuit is connected to the subsequent stage of the capacitive element for AC coupling, the problem of the secondary response waveform described above occurs.

  The present invention has been made in view of the above problems, and in an optical receiver having a configuration for detecting a received signal in a subsequent stage of an AC coupling capacitive element, a reception alarm based on a second-order or higher-order delay response of the received signal An object of the present invention is to provide an optical receiver capable of preventing erroneous signal cancellation.

  In order to solve the above problems, an optical receiver according to the present invention includes a photodiode that generates a photocurrent corresponding to signal light, a current-voltage conversion circuit that converts the photocurrent into an electrical reception signal, and a current-voltage conversion circuit. A capacitive element for AC coupling connected to the subsequent stage, and a received signal monitoring circuit connected to the subsequent stage of the capacitive element for detecting input signal interruption, wherein the received signal monitoring circuit has a peak level of the received signal. A peak level alarm generating unit that generates a peak level alarm signal when it is smaller than the first threshold voltage, and a bottom level alarm that generates a bottom level alarm signal when the bottom level of the received signal is larger than the second threshold voltage Based on the generation unit, the peak level alarm signal, and the bottom level alarm signal, a reception alarm is generated that generates a reception alarm signal indicating that the reception signal is disconnected. And having a beam generation unit.

  In the optical receiver described above, the received signal is maintained at a normal voltage level, and the data level is included in the received signal so that the peak level of the received signal is greater than the first threshold voltage. A threshold voltage of 1 is set. Further, the second threshold voltage is set so that the bottom level of the received signal is smaller than the second threshold voltage in a state where the received signal maintains a normal voltage level and the data component is included in the received signal. Is done. When the input is interrupted, a reception alarm signal is generated when the peak level decreases and falls below the first threshold, or when the bottom level rises and exceeds the second threshold.

  When the input of the signal light is interrupted, the data component (high frequency component) of the signal light disappears, so that the peak level and the bottom level of the received signal transition with the same time waveform. Therefore, when the peak level becomes lower than the first threshold voltage after the input is cut off and then becomes higher than the first threshold voltage, the bottom level is similarly overshot and becomes higher than the second threshold voltage. Can be. On the contrary, when the bottom level becomes larger than the second threshold voltage when the input is interrupted and undershoots and becomes smaller than the second threshold voltage, the peak level similarly undershoots and becomes lower than the first threshold voltage. Can be smaller. As described above, even when the peak level alarm signal (bottom level alarm signal) is canceled by the peak level overshoot (or bottom level undershoot), the bottom level alarm signal (peak level alarm signal) is generated during that period. Thus, the reception alarm signal can be continuously output. Therefore, according to the optical receiver described above, it is possible to prevent erroneous release of the reception alarm signal due to a second-order or higher-order delay response of the reception signal.

  In addition, the optical receiver receives the peak level alarm signal and the bottom signal at any time from when the reception signal is interrupted and the peak level alarm signal or the bottom level alarm signal is generated until the reception signal is recovered. The first and second threshold voltages may be set so that at least one of the level alarm signals is always generated. Thereby, erroneous cancellation of the reception alarm signal can be prevented more reliably.

  The optical receiver further includes a conversion circuit that converts the received signal into a differential signal, and the peak level alarm generation unit and the bottom level alarm generation unit are configured to generate a peak level alarm based on a single-phase signal among the differential signals. A signal and a bottom level alarm signal may be generated. As described above, by converting the received signal into a differential signal, the signal amplitude of the photocurrent can be equivalently doubled, so that the transition time between the high level and the low level can be shortened. , Faster signal processing becomes possible. Also, if a single-phase differential signal is used when generating the peak level alarm signal and the bottom level alarm signal, the peak level and the bottom level preferably transition with substantially the same time waveform when the input is interrupted. Even when the peak level alarm signal (bottom level alarm signal) is canceled by level overshoot (or bottom level undershoot), the interval can be preferably complemented by the bottom level alarm signal (peak level alarm signal).

  In the optical receiver, the reception signal monitoring circuit includes a first digital filter unit that removes a peak level alarm signal having a time width of a predetermined time or less, and a first digital filter unit that removes a bottom level alarm signal having a time width of a predetermined time or less. The digital filter unit may further include a second digital filter unit and a clock generation unit that provides a clock signal for counting a predetermined time to the first and second digital filter units. For example, when the peak level of the received signal is smoothed by the peak level alarm generator, the response at the time of input interruption is delayed if the capacity of the smoothing capacitor is increased, so the capacity of the smoothing capacitor can be substantially smoothed. It is preferable to set a small value in such a range. In this case, chattering occurs in the peak level alarm signal depending on the magnitude of the first threshold voltage. Similarly, in the bottom level alarm generation unit, chattering occurs in the bottom level alarm signal depending on the magnitude of the second threshold voltage. On the other hand, according to the above-described optical receiver, chattering of the peak level alarm signal and the bottom level alarm signal can be eliminated by the first and second digital filter units, so that the capacity of the smoothing capacitor can be set smaller. It is possible to output the reception alarm signal when the input is interrupted more quickly.

  In the optical receiver, the reception signal monitoring circuit receives the first latch unit that holds the peak level alarm signal that has passed through the first digital filter unit, and the bottom level alarm signal that has passed through the second digital filter unit. A second latch unit that holds the latch, and a latch release signal generation unit that generates a latch release signal for releasing the holding state of the peak level alarm signal and the bottom level alarm signal in the first and second latch units. The latch release signal generation unit does not output the peak level alarm signal from the first digital filter unit, does not output the bottom level alarm signal from the second digital filter unit, and receives the reception alarm signal from the reception alarm generation unit. The latch release signal may be generated when the output state of the signal continues for a predetermined time. . For example, in the case where the first and second digital filter units are constituted by counter circuits, etc., a signal waveform in which the output signals from the first and second digital filter units repeat a high level and a low level at a predetermined cycle. It becomes. In such a case, the peak level alarm signal and the bottom level alarm signal that have passed through the first and second digital filter units are preferably held (latched) by the first and second latch units. In this case, since the reception signal monitoring circuit includes the above-described latch release signal generation unit, when the signal light returns from the input cut-off state (that is, shifts to the normal input state), the peak level alarm signal and the bottom level alarm are generated. The signal can be canceled appropriately.

  According to the present invention, in an optical receiver having a configuration for detecting a received signal in a subsequent stage of an AC coupling capacitive element, optical reception capable of preventing erroneous cancellation of a received alarm signal due to a second-order or higher-order delay response of the received signal Can be provided.

  Hereinafter, preferred embodiments of an optical receiver according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a diagram showing a configuration of an optical receiver which is a preferred embodiment of the present invention. Optical receiver 1 shown in the figure, the output signal corresponding to the signal light input P _in DATA _+, DATA _- a is the optical communication module for outputting to the outside, for photoelectrically converting an optical signal P _in The light detection unit 2, a saturation amplification unit 3 that amplifies the photoelectrically converted electrical signal, and a reception signal monitoring circuit 4 that monitors input interruption of the reception signal are provided.

The light detection unit 2 has a small package configuration such as ROSA (Receiver Optical Sub Assembly). Light detector 2, PIN Photodiode produce a photocurrent I _in which corresponding to the signal light P _in, a photodiode 21 such as an avalanche photodiode, is connected to the anode of the photodiode 21, the light current I _in a voltage signal A transimpedance amplifier (current-voltage conversion circuit) 22 that converts the received signal _Sout to the output side of the transimpedance amplifier 22, and amplifies the received signal _Sout from the transimpedance amplifier 22, A conversion circuit that converts an average signal S _outave obtained by smoothing the reception signal S _out with the low-pass filter 24 into reception signals Sp ₁ ( _normal phase) and Sn ₁ (reverse phase) that are differential signals. A buffer (preamplifier) 23. The cathode of the photodiode 21 is connected to the power supply potential line 18, and a reverse bias voltage is applied to the photodiode 21.

The signal light P _in the optical transmission medium has been transmitted, such as an optical fiber is photoelectrically converted in the light receiving surface of the photodiode 21, the photoelectric current I _in. The photocurrent I _in is converted into a reception signal S _out which is a voltage signal by the transimpedance amplifier 22, and the average signal S _outave obtained by smoothing the reception signal S _out by the low-pass filter 24 by the buffer 23 is used. Then, a differential signal of the differential signal is generated, and the difference signal is amplified to two reception signals Sp ₁ and Sn ₁ having opposite signs and output to the saturation amplification unit 3 in the subsequent stage. Thus, by extracting the received signals Sp ₁ and Sn ₁ by differential processing, the signal amplitude _{in the} photocurrent I _in can be handled equivalently twice, so that the signal between the high level and the low level can be handled. As a result of shortening the transition time, higher-speed signal processing is enabled.

The saturation amplification unit 3 includes amplifiers 32 to 35 that amplify the received signal, a CML (Current Mode Logic) circuit 36, and a resistance element 31 that defines the input impedance of the saturation amplification unit 3. Specifically, the two input ends of the amplifier 32 of the saturation amplifying unit 3 are connected to the two output ends of the buffer 23 via the capacitive elements 13a and 13b, respectively. The capacitive elements 13a and 13b are connected to the subsequent stage of the transimpedance amplifier 22 (in the present embodiment, the subsequent stage of the buffer 23), and the photodetection unit 2 and the saturation amplification unit 3 are AC-coupled to each other. Further, the two input ends of the amplifier 32 are connected via a resistance element 31. The reception signals Sp ₁ and Sn ₁ are influenced by the capacitive elements 13 a and 13 b and the resistance element 31 and are input to the amplifier 32 as reception signals Sp ₂ and Sn ₂ . The amplifier 33 is connected to the subsequent stage of the amplifier 32, the amplifier 34 is connected to the subsequent stage of the amplifier 33, the amplifier 35 is connected to the subsequent stage of the amplifier 34, and the CML circuit 36 is connected to the subsequent stage of the amplifier 35. ing. Amplifiers 32 to 35 and CML circuit 36 amplifies and shaping the received signal _Sp 2, Sn _2, the output signal corresponding to the signal light _{P in} DATA _+, DATA _- generates a.

The saturation amplifier 3 further includes a feedback circuit 38 for removing offset components generated by the amplifiers 32 to 35. The feedback circuit 38 includes a low pass filter 37. The input terminal of the low-pass filter 37 is connected to the output terminal of the amplifier 34, and the output terminal of the low-pass filter 37 is connected to the input terminal of the amplifier 33. Low pass filter 37, by the reception signal Sp ₂ and Sn ₂ output from the amplifier 34 is averaged and subtraction the averaged signal to the reception signal Sp ₂ and Sn ₂ are input to the amplifier 34, the received signal Sp ₂ and the offset component included in Sn ₂ are removed (corrected).

  The reception signal monitoring circuit 4 includes a single-phase amplification unit 5, a peak level alarm generation unit 6a, a bottom level alarm generation unit 6b, digital filter units 7a and 7b, a peak level alarm holding unit 8a, a bottom level alarm holding unit 8b, a reception alarm. A generation unit 9, a control unit 11, and a threshold generation unit 12 are included. These circuit portions may be configured as separate circuits, or may be configured in one integrated chip.

The single-phase amplifier 5 is a circuit part for amplifying the received signals Sp ₂ and Sn ₂ that are differential signals and outputting a single-phase signal. The input terminal of the single phase amplification unit 5 of this embodiment is connected between the amplifier 33 and the amplifier 34 of the saturation amplification unit 3, and the single phase amplification unit 5 amplifies the received signals Sp ₂ and Sn ₂ after amplification. and it provides a received signal Sp ₃ pieces phase side to the peak level alarm generator 6a and the bottom level alarm generating unit 6b.

The threshold value generator 12 is a circuit part for generating threshold voltage signals V _th1 and V _th2 to be provided to the peak level alarm generator 6a and the bottom level alarm generator 6b, respectively.

Peak level alarm generating unit 6a is a circuit part for generating a peak level alarm signal LOSP ₁ when the peak level (first threshold voltage) less than the peak level of the threshold voltage signal V _th1 of the reception signal Sp ₃ . Less status than the peak level of the peak level of the received signal Sp ₃ is a threshold voltage signal V _th1 is for example occur when the signal light P _in is interrupted. Further, the digital filter unit 7a (first digital filter unit) removes the peak level alarm signal LOSP ₁ whose time width is equal to or less than a predetermined time in order to prevent erroneous detection of the peak level alarm. The peak level alarm holding unit 8a is a circuit part for holding the peak level alarm signal LOSP ₂ that has passed through the digital filter unit 7a, and constitutes a first latch unit in the present embodiment. The peak level alarm holding unit 8 a provides the held peak level alarm signal LOSP ₃ to the reception alarm generating unit 9.

Bottom level alarm generator 6b is a circuit part for generating a bottom level alarm signal LOSB ₁ is larger than the bottom level is the bottom level of the threshold voltage signal V _th2 of the received signal Sp ₃ (second threshold voltage) . Greater availability than the bottom level of the received signal Sp bottom level is the threshold voltage signal V _th1 of _3, for example, when it is no longer contain data component in the signal light P _in the (that is, when the signal light P _in becomes stationary light) Arise. The digital filter section 7b (second digital filter), in order to prevent erroneous detection of the bottom level alarm, time width to remove bottom level alarm signal LOSB ₁ of less than or equal to a predetermined time. Further, the bottom level alarm holding section 8b is a circuit portion for holding the bottom level alarm signal LOSB ₂ which has passed through the digital filter unit 7b, constituting the second latch part in the present embodiment. The bottom level alarm holding unit 8b provides the held bottom level alarm signal LOSB ₃ to the reception alarm generating unit 9.

The reception alarm generation unit 9 calculates a logical sum (OR) of the peak level alarm signal LOSP ₃ and the bottom level alarm signal LOSB ₃ and generates a reception alarm signal LOS indicating the input interruption of the reception signals Sp ₂ and Sn _2. It is a circuit part. The reception alarm signal LOS generated by the reception alarm generation unit 9 is provided to a signal processing circuit (not shown) provided outside the reception signal monitoring circuit 4.

When the received signals Sp ₂ and Sn ₂ are recovered from the input interruption, the latch release signal generation unit 10 holds the peak level alarm signal LOSP ₃ in the peak level alarm holding unit 8a and the bottom level alarm holding unit 8b. a circuit portion for generating a latch release signal S _CLR for releasing the holding state of the level alarm signal LOSB _3. The latch release signal generation unit 10 detects the return of the reception signals Sp ₂ and Sn ₂ as follows. That is, the latch release signal generation unit 10 does not output the peak level alarm signal LOSP ₂ from the digital filter unit 7 a, does not output the bottom level alarm signal LOSB ₂ from the digital filter unit 7 b, and receives from the reception alarm generation unit 9. When the state in which the alarm signal LOS is output continues for a predetermined time, it is determined that the reception signals Sp ₂ and Sn ₂ have recovered from the input interruption, and the latch release signal _SCLR is generated.

The control unit 11 provides the threshold value generation unit 12 with a threshold control signal S _C1 for controlling the magnitudes of the threshold voltage signals V _th1 and V _th2 of the threshold value generation unit 12. The control unit 11 changes the threshold value control signal S _C1 by the logic value of the received alarm signals LOS from receiving the alarm generation unit 9, and adds a hysteresis characteristic to the LOS determined. The control unit 11 also provides the latch release signal generation unit 10 with a timing control signal _SC2 for controlling the latch release timing in the latch release signal generation unit 10. The control unit 11 also includes a clock generation unit 14 that provides the digital filter units 7a and 7b with a clock signal CL for counting a predetermined time in the digital filter units 7a and 7b. The clock generating section 14, a clock signal CL, the received signal _Sp 2, Sn ₂ signal clock (i.e., signal clock of the signal light _{P in)} generated independently of independently of the. The clock generator 14 generates a clock signal CL having a clock frequency of, for example, [1 MHz]. The clock generation unit 14 provides the clock signal CL to the digital filter units 7a and 7b, the peak level alarm holding unit 8a, the bottom level alarm holding unit 8b, the reception alarm generation unit 9, and the latch release signal generation unit 10.

Here, the configuration of the reception signal monitoring circuit 4 will be described in more detail. FIG. 2 is a circuit diagram showing an internal configuration of the reception signal monitoring circuit 4. Referring to FIG. 2, the single phase amplification unit 5 is configured by a differential amplifier 51. Two input terminals (positive phase and reverse phase) of the differential amplifier 51 are connected to two output terminals of the amplifier 33 of the saturation amplifying unit 3, respectively, and a differential output signal (received signal Sp ₂₎ from the amplifier 33 is connected. , Sn ₂ ). Of the two output terminals of the differential amplifier 51, only the output terminal on the positive phase side is connected to the peak level alarm generator 6a and the bottom level alarm generator 6b. With this configuration, the single-phase amplification unit 5 amplifies the reception signals Sp ₂ and Sn ₂ that are differential signals, and then converts the single-phase (positive phase side) reception signal Sp ₃ into the peak level alarm generation unit 6a and the bottom level. This can be provided to the alarm generation unit 6b.

The peak level alarm generation unit 6 a includes peak detection units 61 and 62 and a comparator (comparator) 63. Peak detector 62 is a circuit portion for detecting the peak level of the amplitude of the received signal Sp ₃ (peak hold circuit). Peak detector 62 has, for example, a capacitor for smoothing, to produce a peak level signal S _pk illustrating transition of a peak level of the received signal Sp _3. The peak detection unit 61 has a circuit configuration similar to that of the peak detection unit 62, and generates a threshold voltage _Vpk indicating the peak level of the threshold voltage signal _Vth1 .

The comparator 63 compares the peak level signal S _pk from the peak detector 62 with the threshold voltage V _pk from the peak detector 61. The comparator 63, when the peak level signal _{S pk} is less than the threshold voltage _{V pk,} logical 1 is output to the digital filter 7a as the peak level alarm signal LOSP _1. Further, when the peak level signal S _pk becomes larger than the threshold voltage V _pk , the comparator 63 cancels the alarm by setting the peak level alarm signal LOSP ₁ to the logical value 0. Note that a hysteresis characteristic may be added to the comparator 63 in order to prevent chattering of the peak level alarm signal LOSP ₁ due to noise.

The digital filter unit 7 a includes an N-ary counter 71. The peak level alarm signal LOSP ₁ is input to the input terminal of the N-ary counter 71 from the comparator 63 of the peak level alarm generator 6a. A clock signal CL is input to the clock input terminal of the N-ary counter 71 from the clock generation unit 14 included in the control unit 11. The N-ary counter 71 refers to the logical value of the peak level alarm signal LOSP ₁ while counting a predetermined time such as N periods based on the clock signal CL from the clock generator 14, and the logical value continues for N periods. a logic one output as peak level alarm signal LOSP ₂ when was 1 to. Further, when the logical value of the peak level alarm signal LOSP ₁ becomes _{1 in} the middle of counting, the N-ary counter 71 is reset, and when the logical value of the peak level alarm signal LOSP ₁ becomes 0 again, the reset is released and N cycles Counting starts.

The peak level alarm holding unit 8a includes an OR operation circuit 81 and a D flip-flop circuit 82. One input terminal of the OR circuit 81 is connected to the N-ary counter 71, and the other input terminal is connected to the Q terminal of the D flip-flop circuit 82. The output terminal of the logical sum operation circuit 81 is connected to the D terminal of the D flip-flop circuit 82. The clock signal CL is input from the clock generator 14 to the clock terminal of the D flip-flop circuit 82. With these configurations, when the peak level alarm signal LOSP ₂ is output as the logical value 1 from the N-ary counter 71, the peak level alarm holding unit 8a outputs the Q terminal regardless of the subsequent change in the peak level alarm signal LOSP _2. Is latched to a logical value of 1. Then, the peak level alarm holding unit 8 a outputs the output from the Q terminal of the D flip-flop circuit 82 to the reception alarm generating unit 9 as the peak level alarm signal LOSP ₃ .

The bottom level alarm generation unit 6 b includes bottom detection units 64 and 65 and a comparator (comparator) 66. Bottom detector 65 is a circuit portion for detecting a bottom level of the amplitude of the received signal Sp ₃ (bottom hold circuit). Bottom detector 65 has, for example, a capacitor for smoothing, to produce a bottom level signal S _bt showing the bottom level transitions of the received signal Sp _3. Bottom detector 64 has a circuit structure similar to that of the bottom detector 65, generates a threshold voltage V _bt showing the bottom level of the threshold voltage V _th2.

Comparator 66 compares the magnitude of bottom level signal S _bt from bottom detection unit 65 and threshold voltage V _bt from bottom detection unit 64. The comparator 66, when the bottom level signal _{S bt} is larger than the threshold voltage _{V bt,} logical 1 is output to the digital filtering unit 7b as a bottom-level alarm signal LOSB _1. Further, when the bottom level signal S _bt becomes smaller than the threshold voltage V _bt , the comparator 66 releases the alarm by setting the bottom level alarm signal LOSB ₁ to the logical value 0. Note that hysteresis characteristics may be added to the comparator 66 in order to prevent chattering of the bottom level alarm signal LOSB ₁ due to noise.

The digital filter unit 7 b includes an N-ary counter 72. The bottom level alarm signal LOSB ₁ is input to the input terminal of the N-ary counter 72 from the comparator 66 of the bottom level alarm generator 6b. A clock signal CL is input to the clock input terminal of the N-ary counter 72 from the clock generator 14 included in the controller 11. The N-ary counter 72 refers to the logic value of the bottom level alarm signal LOSB ₁ while counting a predetermined time such as N periods based on the clock signal CL from the clock generator 14, and the logic value continues for N periods. and it outputs the logical value 1 as a bottom-level alarm signal LOSB ₂ when was 1 to. Further, when the logic value of the bottom level alarm signal LOSB ₁ becomes _{1 in} the middle of counting, the N-ary counter 72 is reset, and when the logic value of the bottom level alarm signal LOSB ₁ becomes 0 again, the reset is released and N cycles Counting starts.

The bottom level alarm holding unit 8b includes an OR operation circuit 83 and a D flip-flop circuit 84. One input terminal of the OR circuit 83 is connected to the N-ary counter 72, and the other input terminal is connected to the Q terminal of the D flip-flop circuit 84. The output terminal of the logical sum operation circuit 83 is connected to the D terminal of the D flip-flop circuit 84. The clock signal CL is input from the clock generator 14 to the clock terminal of the D flip-flop circuit 84. With these configurations, when the bottom level alarm signal LOSB ₂ is output as the logical value 1 from the N-ary counter 72 in the bottom level alarm holding unit 8b, the Q terminal is used regardless of the subsequent change in the bottom level alarm signal LOSB _2. Is latched to a logical value of 1. The bottom level alarm holding section 8b outputs the output from the Q terminal of the D flip-flop circuit 84 as the bottom level alarm signal LOSB ₃ to the reception alarm generator 9.

As described above, the reception alarm generation unit 9 calculates the logical sum (OR) of the peak level alarm signal LOSP ₃ and the bottom level alarm signal LOSB ₃ , and uses the calculation result as the reception alarm signal LOS. Output to the outside. In the present embodiment, the reception alarm generation unit 9 includes an OR operation circuit 91 and a D flip-flop circuit 92. One input terminal of the OR circuit 91 is connected to the Q terminal of the D flip-flop circuit 82, and the other input terminal of the OR circuit 91 is connected to the Q terminal of the D flip-flop circuit 84. Then, the logical sum operation circuit 91 calculates a logical sum (OR) of the peak level alarm signal LOSP ₃ and the bottom level alarm signal LOSB ₃ to generate a reception alarm signal LOS. The D terminal of the D flip-flop circuit 92 is connected to the output terminal of the OR circuit 91, and the clock signal CL is input from the clock generator 14 to the clock terminal of the D flip-flop circuit 92. The D flip-flop circuit 92 outputs the reception alarm signal LOS latched in synchronization with the clock signal CL to the outside of the reception signal monitoring circuit 4 from the Q terminal.

The latch release signal generation unit 10 refers to the peak level alarm signal LOSP ₂ , the bottom level alarm signal LOSB ₂ , and the reception alarm signal LOS based on the clock signal CL from the clock generation unit 14, and The logical value 1 is not output as the peak level alarm signal LOSP ₂ and the bottom level alarm signal LOSB ₂ from each, and the peak level alarm signal LOSP ₃ or the bottom level alarm signal is output from the peak level alarm holding unit 8a or the bottom level alarm holding unit 8b. When the state in which LOSB ₃ is output (that is, the state in which the reception alarm signal LOS is output) continues for M cycles (M> 2 × N + 2) or more, the latch release signal _SCLR is generated.

Specifically, the latch release signal generation unit 10 includes an OR operation circuit 15, an M-ary counter 16, and a negation circuit 17. The logical sum operation circuit 15 includes a peak level alarm signal LOSP ₂ from the N-ary counter 71, a bottom level alarm signal LOSB ₂ from the N-ary counter 72, and a signal (ie, a signal from the negative terminal of Q of the D flip-flop circuit 92). A logical sum (OR) with the negative value of the reception alarm signal LOS) is calculated, and the calculation result is provided to the M-ary counter 16. The M-ary counter 16 operates in synchronization with the clock signal CL from the clock generator 14 and counts up when the logical value of the operation result from the logical sum operation circuit 15 is zero. When the count reaches M, a logic 1 is output as the latch release signal _SCLR . The logic of the latch release signal _SCLR is negated by the negation circuit 17. The negated latch release signal _SCLR is provided to the clear terminal of the D flip-flop circuit 82 of the peak level alarm holding unit 8a and the clear terminal of the D flip-flop circuit 84 of the bottom level alarm holding unit 8b.

The operation at the time of input disconnection and input return in the optical receiver 1 having the above configuration will be described. 3 (a) to 3 (e) respectively show the signal light P _in (FIG. 3 (a)), the gain control signal V _AGC (FIG. 3 (b)) of the transimpedance amplifier 22, the reception signal S _out and the reception average. signal _{S outave} (FIG. 3 (c)), the received signal Sp ₁ and Sn ₁ (FIG. 3 (d)), as well as a graph showing an example of a waveform of the received signal Sp ₂ and Sn ₂ (to FIG. 3 (e)) . Incidentally, FIG. 3 (a) ~ (e), the signal light _{P in} rises at time _{t 1,} shows the case of interrupted at time _{t 2.}

When the signal light _{P in} is interrupted at time _{t 2} (FIG. 3 (a)), the gain control signal _{V AGC} in transimpedance amplifier 22, as shown in rapidly without lowering FIG 3 (b) gently descend. This is because the gain control circuit in the transimpedance amplifier 22 is realized by a feedback loop, and when the optical signal is cut off, the feedback loop becomes an open loop state, and the gain control signal _VAGC changes slowly. The reception signal _Sout output from the transimpedance amplifier 22 is branched into two, one is directly applied to the buffer 23, and the other is passed through the low-pass filter 24, thereby receiving one-phase reception with a first-order delay. A reception average signal S _outave that is an average voltage of the signal S _out is created, and the reception signal S _out and the reception average signal S _outave have waveforms as shown in FIG.

Subsequently, in the buffer 23, the reception signal S _out is converted into reception signals Sp ₁ and Sn ₁ which are differential signals using the reception average signal S _outave . At this time, the low-pass filter 24, as shown in FIG. 3 (d), the received signal Sp ₁ of the positive phase side become waveform discharged from the low potential side slowly to differential midpoint potential V _0, reverse phase side The received signal Sn ₂ has a waveform that is slowly discharged from the high potential side to the differential midpoint potential V ₀ . Thereafter, the reception signals Sp ₁ and Sn ₁ overshoot when they converge to the differential midpoint potential V _{0 due} to the time constant τ of the high-pass filter (HPF) formed by the capacitive elements 13 a and 13 b and the resistive element 31. In addition, the received signals Sp ₂ and Sn ₂ include second-order or higher-order response waveforms with undershoot (FIG. 3 (e)).

The high-pass filter (HPF) described above is formed by the output impedance R _out of the buffer 23, the capacitance C _ac of the capacitive elements 13a and 13b, and the input impedance R _in defined by the resistive element 31 of the saturation amplifying unit 3. The In this case, the time constant τ is expressed by the following equation (1).

Normally, R _in and R _out are designed to be 50 [Ω] per phase for impedance matching between the photodetecting unit 2 and the saturation amplification unit 3 such as ROSA, but in the case of a low-speed signal (155 Mbps, etc.) Since the influence of reflection is small, it may be terminated with a high resistance of 1 [kΩ] in order to set the low-frequency cutoff frequency low. For example, when receiving a SONET / SDH signal, it is necessary to receive 72 bits of the same code continuation without deterioration of the error rate, and the low-frequency cutoff frequency f _CL is determined as in the following equation (2).

In Equation (2), BR is the transmission bit rate [bit / s], CID (Consecutive Identical Digits) is the number of consecutive bits of the same sign [bit], and AP (Amplitude Penalty) is the amplitude penalty (1% amplitude penalty). If there is, it is 0.01). As an example, when BR = 155.52 [Mbit / s] (in the case of OC-3 / STM-1), CID = 72, AP = 0.01, f _CL is set to 3.455 [kHz] or less. It is necessary to Here, when R _out = 50 [Ω] and R = 1 [kΩ], C _ac for realizing f _CL ≦ 3.455 [kHz] is 43.8 [nF] or more. At this time, the time constant τ is about 46 [μsec].

The received signals Sp ₂ and Sn ₂ that have passed through the capacitive elements 13 a and 13 b for AC coupling are amplified by the amplifiers 32 to 35 and the CML circuit 36 of the saturation amplifying unit 3. At this time, the offset voltage generated in the amplifiers 32 to 35 is removed by the feedback circuit 38 including the low-pass filter 37. Received signal _Sp 2, Sn _2, the output signal DATA corresponding to the signal light _{P in} each _+, DATA _- is outputted as the external circuit of the optical receiver 1 (e.g. CDR (Clock and Data Recovery) circuit). The reception signals Sp ₂ and Sn ₂ are branched to the reception signal monitoring circuit 4 between the amplifier 33 and the amplifier 34.

Figure 4 each of (a) ~ (h), when the signal light _{P in} is cut off at time _{t 2, the} signal light _{P in} (FIG. 4 (a)), the received signal Sp ₂ and Sn ₂ (FIG. 4 ( b)), a peak level signal S _pk (FIG. 4 (c)), a peak level alarm signal LOSP ₁ (FIG. 4 (d)), a clock signal CL (FIG. 4 (e)), a peak level alarm signal LOSP ₂ (FIG. 4 (f)), a peak level alarm signal LOST ₃ (FIG. 4 (g)), and a graph showing an example of a waveform of a reception alarm signal LOS (FIG. 4 (h)).

As described above, when the signal light _{P in} is interrupted at time _{t 2} (FIG. 4 (a)), the waveform of the reception signal _Sp 2, Sn ₂ is a secondary or higher order response waveform with overshoot A waveform including this is obtained (FIG. 4B). Thereafter, the reception signals Sp ₂ and Sn ₂ are amplified by the single-phase amplification unit 5, and only the signal on the positive phase side is output as the reception signal Sp ₃ . Received signal Sp ₃ is taken into peak level alarm generating unit 6a, is peak detected by the peak detector 62 is output as a peak level signal _{S pk} (Fig 4 (c)). At this time, the peak level signal S _pk has a second-order or higher order response waveform with overshoot similarly to the reception signal Sp _2. Depending on the magnitude of the threshold voltage V _pk , the peak level signal S _pk at the time of overshoot is There is a case where the threshold voltage _Vpk is exceeded. In FIG. 4 (c), the following interruption of the signal light _{P in} (time _{t 2),} during the time _{t 3} at time _{t 4} the peak level signal _{S pk} exceeds the threshold voltage _{V pk.} Thus, the peak level alarm signal LOSP ₁ indicating the magnitude comparison result between the peak level signal _{S pk} and the threshold voltage _{V pk,} as shown in FIG. 4 (d), during interruption of the signal light _{P in} (time _{t 2)} logic The waveform transitions to value 1, temporarily returns to logic value 0 at time t ₃ , and then transitions to logic value 1 again at time t ₄ .

The peak level alarm signal LOSP ₁ is taken into the N-ary counter 71 of the digital filter unit 7a. While the peak level alarm signal LOSP ₁ is a logical value 1, the N-ary counter 71 counts for a predetermined time (N cycles) based on the clock signal CL (FIG. 4 (e)) from the clock generator 14, and the N cycles After counting (time t ₅ ), the logic value of the output signal (peak level alarm signal LOSP ₂ ) is changed to 1 (FIG. 5 (f)). For example, when the frequency of the clock signal CL is 1 [MHz] and the count number N is 4, when N cycles are converted into time, 4 [μsec] is obtained. That is, in this example, when the peak level signal S _pk is lower than the threshold voltage V _pk for 4 [μsec], the logical value of the peak level alarm signal LOSP ₂ transitions to 1.

Further, when the peak level alarm signal LOSP ₁ returns from the logical value 1 to 0, the N-ary counter 71 resets the N-cycle count and makes the logical value of the peak level alarm signal LOSP ₂ transition to 0. In the example of FIG. 5 (f), the so logical value of the peak level alarm signal LOSP ₁ is transitioned to 0 once at time _{t 3,} the logical value of the peak level alarm signal LOSP ₂ also temporarily at time _{t 3} 0 It will transition to. Then, after the logical value of the peak level alarm signal LOSP ₁ changes to ₁ again (time t ₄ ) and after N cycles (time t ₆ ), the logical value of the peak level alarm signal LOSP ₂ also changes to 1 again. Yes.

In general, an output from a counter circuit such as an N-ary counter 71 (peak level alarm signal LOSP ₂ ) is a logic value 1 and a logic value 0 every N cycles while the peak level alarm signal LOSP ₁ is a logic value 1. repeat. Therefore, it is desirable to latch (hold) the logical value of the peak level alarm signal LOSP ₂ by the peak level alarm holding unit 8a. In the example of FIG. 4G, the output from the peak level alarm holding unit 8a (peak level alarm signal LOSP ₃ ) one cycle after the logical value of the peak level alarm signal LOSP ₂ changes to 1 (time t ₇ ). Is held at a logical value of 1. Then, the peak level alarm signal LOSP ₃ is input to the reception alarm generating unit 9, the logic value 1 is output at time _{t 8} after one cycle as received alarm signal LOS (FIG. 4 (h)).

Further, each, in a case where the signal light _{P in} is cut off at time _{t 2, the} signal light _{P in} (FIG. 5 (a)), the received signal Sp ₂ and Sn ₂ (diagram of FIG. 5 (a) ~ (h) 5 (b)), bottom level signal S _bt (FIG. 5 (c)), bottom level alarm signal LOSB ₁ (FIG. 5 (d)), clock signal CL (FIG. 5 (e)), bottom level alarm signal LOSB ₂ (FIG. 5 (f)), the bottom level alarm signal LOSB ₃ (FIG. 5 (g)), and is a graph showing an example of a waveform of the received alarm signals LOS (FIG. 5 (h)).

When the signal light _{P in} is interrupted at time _{t 2} (FIG. 5 (a)), the waveform of the reception signal _Sp 2, Sn ₂ is a waveform comprising two or higher order response waveform with overshoot and undershoot (FIG. 5B). Thereafter, the reception signals Sp ₂ and Sn ₂ are amplified by the single-phase amplification unit 5, and only the signal on the positive phase side is output as the reception signal Sp ₃ . Received signal Sp ₃ is taken into bottom level alarm generating unit 6b, is bottom detection by bottom detector 65 is output as the bottom level signal _{S bt} (FIG. 5 (c)). At this time, the bottom level signal S _bt has a second-order or higher order response waveform with overshoot, similarly to the reception signal Sp _2, and the bottom level signal S _bt may be _reduced during overshoot depending on the magnitude of the threshold voltage V _bt. The threshold voltage _Vbt can be exceeded. In FIG. 5 (c), the following interruption of the signal light _{P in} (time _{t 2),} a bottom level signal _{S bt} between times _{t 10} from the time _{t 9} exceeds the threshold voltage _{V bt.} Therefore, the bottom level alarm signal LOSB ₁ indicating the magnitude comparison result between the bottom level signal S _bt and the threshold voltage V _bt transitions to the logical value 1 at time t ₉ as shown in FIG. _{At 10} , the waveform returns to the logical value 0 again.

Here, the transition timing (time t ₉ and time t ₁₀ ) of the bottom level alarm signal LOSB ₁ shown in FIG. 5D depends on the magnitude of the threshold voltage V _bt . That is, as the threshold voltage V _bt is smaller, the transition timing (time t ₉ ) of the bottom level alarm signal LOSB _{1 to} the logical value 1 is earlier, and the transition timing to the logical value 0 (time t ₁₀ ) is later. . Therefore, as the threshold voltage _{V bt} is small, the time logic value of the bottom level alarm signal LOSB ₁ is 1 becomes longer. Moreover, the transition timing of the peak level alarm signal LOSP ₁ that shown in FIG. 4 (d) also depends on the magnitude of the threshold voltage _{V pk.} That is, referring to FIG. 4D, as the threshold voltage V _pk increases, the transition timing (time t ₃ ) of the peak level alarm signal LOSP _{1 to} the logical value 0 is delayed, and the transition to the logical value 0 occurs. The timing (time t ₄ ) is advanced. Accordingly, as the threshold voltage V _pk increases, the time during which the logical value of the peak level alarm signal LOSP ₁ is 0 is shortened. In FIG. 5D, the time change of the peak level alarm signal LOSP ₁ shown in FIG. 4D is indicated by a dotted line.

In the optical receiver 1 of the present embodiment, the threshold voltages _Vpk and _Vbt are preferably set as follows. That is, after the reception signals Sp ₂ and Sn ₂ are cut off from input (more precisely, after the logical value of the peak level alarm signal LOSP ₁ or the bottom level alarm signal LOSB ₁ transits to 1 after the input is cut off), the received signal The threshold voltage V so that at least _one of the peak level alarm signal LOSP ₁ and the bottom level alarm signal LOSB ₁ is always generated at any time before Sp ₂ and Sn ₂ return. It is preferable to set _pk and _Vbt .

Specifically, in FIG. 5D, the transition timing (time t) of the bottom level alarm signal LOSB _{1 to} the logical value 1 rather than the transition timing (time t ₃ ) of the peak level alarm signal LOSP _{1 to} the logical value 0. ₉ ) and the transition timing of the bottom level alarm signal LOSB _{1 to} the logic value 0 (time t ₁₀ ) so that the peak level alarm signal LOSP ₁ transitions to the logic value 1 (time t ₄ ). The threshold voltages V _pk and V _bt are preferably set so as to be slower. Thus, by setting the threshold voltages V _pk and V _bt so that the front and rear portions of the bottom level alarm signal LOSB ₁ overlap with a part of the peak level alarm signal LOSP ₁ , any time after the input is cut off is set. Also, at least _one of the peak level alarm signal LOSP ₁ and the bottom level alarm signal LOSB ₁ is always generated.

Note that such set values of the threshold voltages V _pk and V _bt may be determined in advance, or the output from the OR operation circuit 91 (the latched reception alarm signal LOS) is fed back to the threshold generator 12. May be determined.

The bottom level alarm signal LOSB ₁ generated in this way is taken into the N-ary counter 72 of the digital filter unit 7a. While the bottom level alarm signal LOSB ₁ is a logical value 1, the N-ary counter 72 counts for a predetermined time (N cycle) based on the clock signal CL (FIG. 5 (e)) from the clock generator 14, and the N cycle After counting (time t ₁₁ ), the logic value of the output signal (bottom level alarm signal LOSB ₂ ) is changed to 1 (FIG. 5 (f)). For example, when the frequency of the clock signal CL is 1 [MHz] and the count number N is 4, when N cycles are converted into time, 4 [μsec] is obtained. That is, in this example, when the state in which the bottom level signal S _bt is smaller than the threshold voltage V _bt continues for 4 [μsec], the logic value of the bottom level alarm signal LOSB ₂ transitions to 1.

Further, when the bottom level alarm signal LOSB ₁ returns from the logical value 1 to 0, the N-ary counter 72 resets the N-cycle count and makes the logical value of the bottom level alarm signal LOSB ₂ transition to 0. In the example of FIG. 5 (f), the so logical value of the bottom level alarm signal LOSB ₁ is transitioning at time _{t 10} to 0, the logical value of the bottom level alarm signal LOSB _2, the time _{t 10} after the transition to 1 do not do.

As described above, the output from the counter circuit such as the N-ary counter 72 (bottom level alarm signal LOSB ₂ ) is the logical value 1 and the logical value 0 every N cycles while the bottom level alarm signal LOSB ₁ is the logical value 1. Are repeated (see FIG. 5F). Therefore, it is desirable to latch (hold) the logical value of the bottom level alarm signal LOSB ₂ by the bottom level alarm holding unit 8b. In the example of FIG. 5G, the output from the bottom level alarm holding unit 8b (bottom level alarm signal LOSB ₃ ) one cycle after the logical value of the bottom level alarm signal LOSB ₂ transitions to 1 (time t ₁₂ ). Is held at a logical value of 1. Then, the bottom level alarm signal LOSB ₃ is input to the reception alarm generating unit 9, the logic value 1 is output at time _{t 13} after the one period as a reception alarm signal LOS (FIG. 5 (h)).

The reception alarm generation unit 9 outputs a logical sum (OR) of the peak level alarm signal LOSP ₃ and the bottom level alarm signal LOSB ₃ as the reception alarm signal LOS. Therefore, in practice, the reception alarm signal LOS is the earlier of the time t ₈ when the peak level alarm signal LOSP ₃ transitions to the logical value 1 and the time t _{13 when} the bottom level alarm signal LOSB ₃ transitions to the logical value 1. At time, it will transition to a logical value of 1.

Next, an operation when the signal light P _in is restored from the input disconnection state. 6 (a) ~ Each (h), when the signal light _{P in} is restored at time _{t 14,} the signal light _{P in} (FIG. 6 (a)), the received signal Sp ₂ and Sn ₂ (FIG. 6 ( b)), a peak level alarm signal LOSP ₁ (FIG. 6 (c)), a clock signal CL (FIG. 6 (d)), a peak level alarm signal LOSP ₂ (FIG. 6 (e)), and a latch release signal S _CLR (FIG. 6 (f)), a peak level alarm signal LOSS ₃ (FIG. 6 (g)), and a graph showing an example of a waveform of a reception alarm signal LOS (FIG. 6 (h)).

When the signal light _{P in} is restored at time _{t 14} (FIG. 6 (a)), the received signal Sp ₂ and Sn ₂ is the time _{t 14} rise to the derivative form (FIG. 6 (b)), the peak level signal _{S pk} threshold Since the voltage V _pk is exceeded, the peak level alarm signal LOSP ₁ transitions to the logical value 0 at time t ₁₄ (FIG. 6C). Then, the N-ary counter 71 of the digital filter section 7a that has been counting for a predetermined time (N cycles) based on the clock signal CL (FIG. 4E) sets the peak level alarm signal LOSP _{1 to} the logical value 0. a state always being reset by the transition, the output value from the N-ary counter 71 (logical value of the peak level alarm signal LOSP ₂₎ is secured to the time t ₁₄ after 0. Although not shown, the bottom level alarm signal LOSB ₁ also always has a logical value 0 after the rising times t _{14 of} the reception signals Sp ₂ and Sn ₂ . Thus, N-ary counter 72 in the digital filter unit 7b also always a reset state, the output value from the N-ary counter 72 (logical value of the bottom level alarm signal LOSB ₂₎ is secured to the time t ₁₄ after 0.

Thus, while the logical value of the peak level alarm signal LOSP ₂ and the bottom level alarm signal LOSB ₂ by the return of the signal light P _in is fixed to 0, the respective peak level alarm holder 8a and the bottom level alarm holding portion 8b Since the peak level alarm signal LOSP ₃ and the bottom level alarm signal LOSB ₃ output from are still latched to the logic value 1, this latch needs to be released. Latch release is performed by a latch release signal _SCLR from the latch release signal generation unit 10.

When the following two conditions are satisfied, the latch release signal generation unit 10 outputs the latch release signal _SCLR to the peak level alarm holding unit 8a and the bottom level alarm holding unit 8b. That is, the two conditions are (1) when both the peak level alarm signal LOSP ₂ and the bottom level alarm signal LOSB ₂ have a logical value of 0, and when the received alarm signal LOS has a logical value of 1, and (2) This is when the state 1) lasts longer than N cycles (preferably (2 × N + 2) cycles or more). Here, in the condition (2), “preferably not less than (2 × N + 2) period” means that during the counting operation of the N-ary counter 71 (or 72), as shown in FIG. This is because a logical value 1 and a logical value 0 are alternately output every N cycles as LOSP ₂ (or bottom level alarm signal LOSB ₂ ). That is, in order to avoid erroneous determination, it is necessary to assume the worst case (when there is a change from 0 consecutive bits to 1 consecutive bits at the same time as the transition from the logical value 0 to 1), (2 × It is necessary to consider a case in which the peak level alarm signal LOSP ₂ and the bottom level alarm signal LOSB ₂ become the logical value 0 during the (N + 1) period. That is, it is preferable to provide the the return decision of the signal light _{P in (2 × N + 1} ) or more cycles of latency. Further, since the peak level alarm signal LOSP ₁ (bottom level alarm signal LOSB ₁ ) from the peak level alarm generator 6 a (bottom level alarm generator 6 b) is asynchronous with the clock signal CL from the clock generator 14, There is a possibility that the transition of the alarm signal LOSP ₁ (bottom level alarm signal LOSB ₁ ) is delayed by one cycle at the maximum. Therefore, it is preferable to provide the signal light P _in addition at least one cycle of latency to return determination of. From the above, it is preferable to release the latches of the peak level alarm holding unit 8a and the bottom level alarm holding unit 8b when the state (1) continues longer than (2 × N + 2) cycles.

Specifically, first, the logical sum operation circuit 15 calculates the logical sum of the logical values of the peak level alarm signal LOSSP ₂ and the bottom level alarm signal LOSB ₂ and the negative value of the reception alarm signal LOS. An operation result indicating the condition (1) is generated. When the logical value of the calculation result is 0, the condition (1) is satisfied. Then, while the logical value of the operation result is 0, the M-ary counter 16 performs counting, and when the count reaches M (M ≧ 2 × N + 2, M = 16 in the example of FIG. 6) (FIG. 6). latch release signal _{S CLR} at time _{t 15)} of (f) is output. If the condition (1) is not satisfied during counting, the M-ary counter 16 is reset and the latch release signal _SCLR is not output. The logic of the latch release signal _SCLR is inverted by the negation circuit 17 (FIG. 6 (f)), and is output to the peak level alarm holding unit 8a and the bottom level alarm holding unit 8b. As a result, the peak level alarm holding unit 8a and the bottom level alarm holding unit 8b have the peak level alarm signal LOSP ₃ and the bottom level alarm signal LOSB ₃ having a logical value of 0 (FIG. 6 (g)). The logical value of the reception alarm signal LOS transitions to 0 at (time t _{16 in} FIG. 6 (h)). Thus, the reception alarm signal LOS is canceled.

The time from the signal light P _in is restored to unlatch signal S _CLR is output (latch release timing) is dependent on the relationship between the return timings of the count state and the signal light P _in the M-ary counter 16 Therefore, the longest cycle is (M + 2) and the shortest cycle is (M + 2-N). In this embodiment, a timing control signal S _C2 for controlling the latch release timing in the latch release signal generation unit 10 is provided from the control unit 11 to the latch release signal generation unit 10. The M-ary counter 16 is configured to be able to change the count number in accordance with the timing control signal _SC2 . For example, the count number M can be set to either 16 or 32.

Received signal monitoring circuit 4 of this embodiment, there is no data component from the signal light P _in, can output the received alarm signals LOS even when it becomes a steady light. Figure 7 (a) ~ each (e), in a case that became from the signal light _{P in} a steady light eliminates the data component at time _{t 2, the} signal light _{P in} (FIG. 7 (a)), the received signal Sp ₂ And Sn ₂ (FIG. 7B), bottom level signal S _bt (FIG. 7C), peak level signal S _pk (FIG. 7D), and peak level alarm signal LOSP ₁ and bottom level alarm signal LOSB ₁ is a graph showing an example of the waveform of FIG. 7 (e).

Figure 7 when it becomes from the signal light P _in at time t ₂ as shown in (a) the steady light eliminates data components, as shown in FIG. 7 (b), the received signal Sp ₂ are differential from the high potential side It converges to the middle point potential V _0, the received signal Sn ₂ converges from the low potential side to the differential midpoint potential V _0. At this time, the received signals Sp ₂ and Sn ₂ have a waveform including a second-order or higher order response waveform with overshoot and undershoot. Thereafter, the reception signals Sp ₂ and Sn ₂ are amplified by the single-phase amplification unit 5, and only the signal on the positive phase side is output as the reception signal Sp ₃ . Received signal Sp ₃ is taken into bottom level alarm generating unit 6b, is bottom detection by bottom detector 65 is output as the bottom level signal _{S bt} (FIG. 7 (c)). At this time, the bottom level signal S _bt has a second-order or higher order response waveform with an undershoot similarly to the reception signal Sp _2. Depending on the magnitude of the threshold voltage V _bt , the bottom level signal S _bt A case may occur where the threshold voltage _Vbt is below. In FIG. 7 (c), the following interruption of the signal light _{P in} (time _{t 2),} a bottom level signal _{S bt} between times _{t 18} from the time _{t 17} is below the threshold voltage _{V bt.} Thus, the bottom level alarm signal LOSB ₁ indicating the magnitude comparison result between the bottom level signal _{S bt} and the threshold voltage _{V bt,} as shown in FIG. 7 (e), during interruption of the signal light _{P in} (time _{t 2)} logic transition to the value 1, after once returned to a logic zero at time t _17, again a waveform to transition to logic 1 at time t _18.

The reception signal Sp ₃ is taken into peak level alarm generating unit 6a, is peak detected by the peak detector 62 is output as a peak level signal _{S pk} (FIG 7 (d)). At this time, the peak level signal S _pk has a second-order or higher order response waveform with an undershoot similarly to the reception signal Sp _2, and the peak level signal S _pk at the time of undershoot depends on the magnitude of the threshold voltage V _{pk. Below the} threshold voltage _Vpk . In FIG. 7 (d), the following cut-off of the signal light _{P in} (time _{t 2),} the peak level signal _{S pk} Between time _{t 19} at time _{t 20} is below the threshold voltage _{V pk.} Therefore, the peak level alarm signal LOSP ₁ indicating the magnitude comparison result between the peak level signal S _pk and the threshold voltage V _pk transitions to the logical value 1 at time t ₁₉ as shown in FIG. _{At 20} , the waveform returns to the logical value 0 again.

As described above, the threshold voltages V _pk and V _bt are set to the peak level alarm signal LOSP ₁ or the bottom level alarm signal LOSB ₁ after the reception signals Sp ₂ and Sn ₂ are disconnected. At least _one of the peak level alarm signal LOSP ₁ and the bottom level alarm signal LOSB ₁ at any time from when the logic value of the first to the received signals Sp ₂ and Sn ₂ recovers. It is preferable to set so that the following signal is always generated. In the example of FIG. 7E, the transition timing (time t ₁₉ ) of the peak level alarm signal LOSP _{1 to} the logical value 1 is higher than the transition timing (time t ₁₇ ) of the bottom level alarm signal LOSB _{1 to} the logical value 0. And the transition timing (time t ₂₀ ) of the peak level alarm signal LOSP _{1 to} the logical value 0 is greater than the transition timing (time t ₁₈ ) of the bottom level alarm signal LOSB _{1 to} the logical value 1. The threshold voltages _Vpk and _Vbt may be set so as to be delayed.

Incidentally, in the case of a fixed light eliminates the data component from the signal light _{P in,} for peak level alarm signal LOSP ₁ and the bottom level alarm signal LOSB ₁ subsequent signal processing operation, the operation described above (FIG. 4 (e) ~ (H) and FIG. 5 (e) to (h)). Also, the signal processing operation in the case where the data component in the signal light P _in is restored, is similar to the operation described above (FIG. 6 (b) ~ (h) ).

Next, operations of the peak level alarm generation unit 6a and the bottom level alarm generation unit 6b will be described in more detail. Figure 8 is a graph showing an example of a waveform of the signal light _{P in} peak level signal when the interruption _{S pk} (to FIG. 8 (a)) and the bottom level signal _{S bt} (Figure 8 (b)). FIG. 9 is waveform in the case of a fixed light eliminates the data component from the signal light _{P in,} the peak level signal _{S pk} (to FIG. 9 (a)) and the bottom level signal _{S bt} (to FIG. 9 (b)) It is a graph which shows an example.

Peak detector 62 of the peak level alarm generating unit 6a, and the bottom detector 65 of the bottom level alarm generating unit 6b, for example, smoothing the peak level and bottom level of the received signal Sp ₃ using a capacitor for smoothing Thus, the peak level signal S _pk and the bottom level signal S _bt are generated. The reception signal Sp ₃ is maintaining a normal voltage level, in a state contained data component in the reception signal Sp ₃ is such that the peak level signal S _pk of the reception signal Sp ₃ is greater than the threshold voltage V _pk , Threshold voltage V _pk (threshold voltage signal V _th1 ) is set. Similarly, the received signal Sp ₃ is maintaining a normal voltage level, in a state contained data component in the reception signal Sp ₃ is, as the bottom level of the received signal Sp ₃ is smaller than the threshold voltage V _bt, threshold The voltage V _bt (threshold voltage signal V _th2 ) is set. Then, the comparator 63 of the peak level alarm generation unit 6a outputs a logical value 1 as the peak level alarm signal LOSP ₁ when the peak level signal S _pk falls below the threshold voltage V _pk (see FIG. 8A). To do. Further, the comparator 66 of the bottom level alarm generating unit 6b, when the bottom level signal _{S bt} exceeds the threshold voltage _{V bt} (see FIG. 9 (b)), outputs a logical value 1 as a bottom-level alarm signal LOSB ₁ To do.

Here, when a smoothing capacitor having a large capacitance is used for the peak detectors 62 and 65, the waveform can be made smoother, but the response to the input interruption is delayed. On the other hand, when a smoothing capacitor having a small capacitance is used, the response to an input interruption can be made faster, but a signal waveform remains a little as shown in FIGS. Therefore, for example, when the threshold voltage V _pk is set high as the threshold voltage V _pk2 in FIG. 8A, chattering occurs in the output signal (peak level alarm signal LOSP ₁ ) from the comparator 63. However, since the received signal monitoring circuit 4 of the present embodiment includes the digital filter unit 7a, chattering of the peak level alarm signal LOSP ₁ can be suitably removed. Similarly, the chattering generated in the bottom level alarm signal LOSB ₁ can be suitably removed by the digital filter unit 7b.

The effect which the optical receiver 1 by this embodiment demonstrated above has is demonstrated. In the optical receiver 1 of this embodiment, when the signal light P _in becomes input interruption, the data component of the signal light P _in (high frequency component) is eliminated, the peak level of the received signal Sp 2 _(or Sn ₂₎ And the bottom level transitions with the same time waveform. Therefore, the reception signal Sp ₂ The amplified by generated received signal Sp ₃ peak level (peak level signal _{S pk)} is made temporarily lower than the threshold voltage _{V pk,} when the input interruption of the signal light _{P in,} then When the threshold voltage V _pk becomes larger than the threshold voltage V _pk (FIG. 4C), the bottom level (bottom level signal S _bt ) can also be over-shot and become larger than the threshold voltage V _bt (FIG. 4). 5 (c)). Conversely, when the signal light P _in the bottom level when the input interruption of (bottom level signal S _bt) becomes temporarily larger than the threshold voltage V _bt, becomes smaller than the threshold voltage V _bt and then undershoots (Figure 7 (c)), the peak level (peak level signal S _pk ) can similarly undershoot and become smaller than the threshold voltage V _pk (FIG. 7 (d)). As described above, even when the peak level alarm signal LOSP ₁ (bottom level alarm signal LOSB ₁ ) is canceled due to the overshoot of the peak level signal S _pk (or the undershoot of the bottom level signal S _bt ), the bottom during the cancellation By generating the level alarm signal LOSB ₁ (peak level alarm signal LOSP ₁ ), the reception alarm signal LOS can be continuously output without being released. Therefore, according to the optical receiver 1 of the present embodiment, it is possible to prevent erroneous release of the reception alarm signal LOS due to a second-order or higher-order delay response of the reception signal Sp ₂ (or Sn ₂ ).

In the optical receiver 1 according to the present embodiment, the reception signal monitoring circuit 4 is connected to the subsequent stage of the AC coupling capacitors 13a and 13b connected to the subsequent stage of the transimpedance amplifier 22. Therefore, unlike the optical receiver described in Patent Document 1, it is possible to reduce waveform distortion when receiving a high-frequency signal. In the present embodiment, the received signals Sp ₂ and Sn ₂ are also branched for detection of input interruption, but the branch circuit is lumped constant by branching inside the IC constituting the saturation amplifying unit 3. Can be handled. As a result, the influence on the high-frequency signal can be reduced as compared with the method of branching from the previous stage of AC coupling as in Patent Document 1.

Also, as in the present embodiment, the received signal _Sp 2, Sn ₂ peak is a input interruption level alarm signal LOSP ₁ or bottom level alarm signal LOSB ₁ reception signal _Sp 2 from being generated, Sn ₂ is restored The threshold voltages V _pk and V _bt are set so that at least _one of the peak level alarm signal LOSP ₁ and the bottom level alarm signal LOSB ₁ is always generated at any time in between. Preferably it is. As a result, as shown in FIGS. 5D and 7E, the peak level alarm signal LOSP ₁ and the bottom level alarm signal LOSB ₁ can complement each other with certainty. Can be more reliably prevented.

Further, as in the present embodiment, the peak level alarm generation unit 6a and the bottom level alarm generation unit 6b are based on a single-phase signal (reception signal Sp ₂ ) among the differential signals (reception signals Sp ₂ and Sn ₂ ). Preferably, the peak level alarm signal LOSP ₁ and the bottom level alarm signal LOSB ₁ are generated. Thus, as shown in FIG. 4 (c) and FIG. 5 (c), the well FIGS. 7 (c) and 7 FIG. 7 (d), the on input interruption of the signal light _{P in} a peak level signal _{S pk} And the bottom level signal _Sbt transitions with substantially the same time waveform. Therefore, even when the peak level alarm signal LOSP ₁ is (bottom level alarm signal LOSB ₁₎ is released by the overshoot of the peak level signal _{S pk} (or undershoot of the bottom level signal _{S bt),} bottom level alarm signal LOSB therebetween ₁ (peak level alarm signal LOSP ₁ ) can be preferably complemented.

Further, as in the present embodiment, the received signal monitoring circuit 4 provides the digital filter units 7a and 7b and the clock generation for providing the digital filter units 7a and 7b with a clock signal CL for counting a predetermined time (N period). It is preferable to have the part 14. Accordingly, since it removes the chattering of the peak level alarm signal LOSP ₁ and the bottom level alarm signal LOSB _1, can be set smaller the capacitance of the capacitor for smoothing the digital filter 7a and 7b, the input of the signal light P _in The reception alarm signal LOS can be output earlier when the interruption occurs.

  The optical receiver according to the present invention is not limited to the above-described embodiment, and various modifications are possible. For example, in the above-described embodiment, the peak level alarm signal and the bottom level alarm signal are generated using the reception signal on the positive phase side in the single-phase amplification unit, but these alarm signals are generated using the reception signal on the reverse phase side. May be generated. The present invention can also be applied to the case where the reception signal captured by the reception signal monitoring circuit is not a differential signal but a single end signal. That is, the peak level alarm signal generation unit and the bottom level alarm generation unit may generate the peak level alarm signal and the bottom level alarm signal by detecting the peak level and the bottom level of the single-ended signal.

FIG. 1 is a diagram showing a configuration of an optical receiver which is a preferred embodiment of the present invention. FIG. 2 is a circuit diagram showing an internal configuration of the received signal monitoring circuit. 3, the rising signal light at time _{t 1,} in the case of blocked at time _{t 2,} (a) the signal light _P in, (b) gain control signal _V AGC transimpedance amplifier, (c) the received signal _{S out And} (d) received signals Sp ₁ and Sn ₁ , and (e) received signals Sp ₂ and Sn ₂ are graphs showing examples of waveforms. FIG. 4 shows (a) signal light P _in , (b) received signals Sp ₂ and Sn ₂ , (c) peak level signal S _pk , and (d) peak level alarm when the signal light is interrupted at time t ₂ . signal LOSP _1, is a graph showing an example of (e) the clock signal CL, (f) the peak level alarm signal LOSP _2, (g) the peak level alarm signal LOSP _3, and (h) receiving alarm signals LOS waveform. FIG. 5 shows (a) signal light P _in , (b) received signals Sp ₂ and Sn ₂ , (c) bottom level signal S _bt , and (d) bottom level alarm when the signal light is interrupted at time t ₂ . signal LOSB _1, is a graph showing an example of (e) the clock signal CL, (f) the bottom level alarm signal LOSB _2, (g) bottom level alarm signal LOSB _3, and (h) receiving alarm signals LOS waveform. FIG. 6 shows (a) signal light P _in , (b) received signals Sp ₂ and Sn ₂ , (c) peak level alarm signal LOSP ₁ , (d) clock signal when the signal light returns at time t ₁₄ . CL, is a graph showing an example of (e) a peak level alarm signal LOSP _2, (f) a latch release signal _S CLR, (g) the peak level alarm signal LOSP _3, and (h) receiving alarm signals LOS waveform. FIG. 7 shows (a) signal light P _in , (b) received signals Sp ₂ and Sn ₂ , and (c) bottom level signal S _bt when the data component disappears from the signal light at time t ₂ to become stationary light. is a graph showing an example of (d) the peak level signal _{S pk,} and (e) a peak level alarm signal LOSP ₁ and the bottom level alarm signal LOSB ₁ waveform. FIG. 8 is a graph showing examples of waveforms of (a) peak level signal S _pk and (b) bottom level signal S _bt when the signal light is blocked. FIG. 9 is a graph showing an example of the waveforms of (a) peak level signal S _pk and (b) bottom level signal S _bt when there is no data component from the signal light and the light becomes steady light. FIG. 10 is a circuit diagram showing an example of the configuration of a received signal monitoring circuit used in a conventional optical receiver. 11, when the signal light is cut off at time t _A, is a graph showing an example of the various parts of the signal waveform in the conventional optical receiver. (A) An example of the waveform of the received signal output from the preamplifier is shown. (B) An example of a waveform of a received signal after passing through a high-pass filter including a capacitive element and a resistive element is shown. (C) shows an example of the waveform of the voltage signal after the peak level is detected by the peak detector. (D) An example of the waveform of the output signal (reception alarm signal) from the comparator is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Optical receiver, 2 ... Optical detection part, 3 ... Saturation amplification part, 4 ... Received signal monitoring circuit, 14 ... Clock generation part, 21 ... Photodiode, 22 ... Transimpedance amplifier, 23 ... Buffer, 32-35 ... Amplifier, 36 ... CML circuit, 38 ... Feedback circuit, 51 ... Differential amplifier, 61,62 ... Peak detector, 64,65 ... Bottom detector, 82,84,92 ... D flip-flop circuit, CL ... Clock signal, I _{in ...} photocurrent, LOS ... received alarm _{signal, LOSP 1, LOSP 2, LOSP} 3 ... peak level alarm _{signal, LOSB 1, LOSB 2, LOSB} 3 ... bottom level alarm signal, P _{in ...} signal light, S _{pk ...} peak level signal, S _{bt ...} bottom level signal, S _{C1 ...} threshold control signal, S _{C2 ...} timing control signal, _{S CLR ...} rack Release _{signal, S out, Sp 1, Sn} 1, Sp 2, Sn 2, Sp 3 ... reception _{signal, S outave ...} received average signal.

Claims (5)

A photodiode that generates a photocurrent corresponding to signal light;
A current-voltage conversion circuit for converting the photocurrent into an electrical reception signal;
A capacitive element for AC coupling connected to a subsequent stage of the current-voltage conversion circuit;
A reception signal monitoring circuit that is connected to a subsequent stage of the capacitive element and detects an input interruption of the reception signal;
The received signal monitoring circuit is
A peak level alarm generator for generating a peak level alarm signal when the peak level of the received signal is lower than a first threshold voltage;
A bottom level alarm generator for generating a bottom level alarm signal when the bottom level of the received signal is greater than a second threshold voltage;
An optical receiver, comprising: a reception alarm generation unit that generates a reception alarm signal indicating an input interruption of the reception signal based on the peak level alarm signal and the bottom level alarm signal.   The peak level alarm signal and the bottom level at any time after the reception signal is interrupted and the peak level alarm signal or the bottom level alarm signal is generated until the reception signal is restored. 2. The optical receiver according to claim 1, wherein the first and second threshold voltages are set so that at least one of the alarm signals is always generated. A conversion circuit for converting the received signal into a differential signal;
The peak level alarm generation unit and the bottom level alarm generation unit generate the peak level alarm signal and the bottom level alarm signal based on a single-phase signal among the differential signals. The optical receiver according to 1 or 2. The received signal monitoring circuit is
A first digital filter section for removing the peak level alarm signal having a time width of a predetermined time or less;
A second digital filter section for removing the bottom level alarm signal having a time width of a predetermined time or less;
The clock generation unit for providing a clock signal for counting the predetermined time to the first and second digital filter units, further comprising: Optical receiver. The received signal monitoring circuit is
A first latch unit that holds the peak level alarm signal that has passed through the first digital filter unit;
A second latch unit for holding the bottom level alarm signal that has passed through the second digital filter unit;
A latch release signal generating unit for generating a latch release signal for releasing the holding state of the peak level alarm signal and the bottom level alarm signal in the first and second latch units;
The latch release signal generation unit does not output the peak level alarm signal from the first digital filter unit, does not output the bottom level alarm signal from the second digital filter unit, and the reception alarm generation unit 5. The optical receiver according to claim 4, wherein the latch release signal is generated when a state in which the reception alarm signal is output from is continued beyond the predetermined time.

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