JP4234689B2 - Data processing method and data processing apparatus - Google Patents

Description

  The present invention relates to a data processing method and a data processing device, and more particularly to a data processing method and a data processing device compliant with IEEE1394 which is a serial interface standard.

  In recent years, with the development of multimedia, an increase in the amount of data transfer between a personal computer and peripheral devices and an increase in transfer speed are required. In particular, IEEE1394, which is one of serial interfaces, has attracted attention as an interface for connecting peripheral devices such as digital video cameras, digital VTRs, color page printers, and the like that handle large amounts of audio and image data to personal computers.

  In recent years, the IEEE1394 protocol, which exhibits real-time properties, has attracted attention for transferring large amounts of data such as moving images that require continuity. The IEEE1394 protocol has a first transfer mode in which data can be transferred every certain period (125 μs), that is, a so-called isochronous transfer mode. In other words, if the transfer time of image (moving image) data transferred to a computer becomes irregular, it becomes discontinuous when the image (moving image) is reproduced, and the reality is applied. Therefore, if image (moving image) data is always transferred at a constant time in the isochronous transfer mode (Isoc transfer mode) in the IEEE1394 protocol, a realistic image (moving image) can be reproduced.

  FIG. 11 shows a block circuit showing a configuration of a conventional IEEE1394 protocol controller (IPC) 80 built in a personal computer. The IPC 80 is provided between an IEEE1394 bus cable that connects peripheral devices and a microprocessor unit (MPU). The IPC 80 includes a protocol control circuit unit 81, a data storage memory 82 including a FIFO, an IEEE1394 interface 83, and an MPU interface 84.

  The IEEE1394 interface 83 is connected to a peripheral device such as a digital video camera via an IEEE1394 bus cable. The IEEE1394 interface 83 inputs image data transferred from the digital video camera as isochronous data. As shown in FIG. 12, isochronous data is always transferred in the form of a packet (Isoc packet) every 125 μs period (Isoc cycle).

  The IEEE1394 interface 83 outputs an Isoc packet of the isochronous data (Isoc data) to the protocol control circuit unit 81. The protocol control circuit unit 81 checks whether the packet is addressed to itself from the header of the input Isoc packet, and then converts the Isoc packet from serial to parallel and stores it in the storage memory 82. The Isoc packet stored in the storage memory 82 is output to the MPU via the MPU interface 84. Then, the MPU processes the Isoc data based on the header information of the Isoc packet.

  The IEEE1394 protocol has a second transfer mode, that is, a so-called Asyncronous transfer mode in addition to an isochronous transfer mode. The asynchronous transfer mode (Asyn transfer mode) is a mode in which data is transferred by using a surplus time during which no packet (Isoc packet) is transferred in the Isoc cycle. In other words, asynchronous data packets (Asyn packets) are transferred in the remaining time of the first Isoc packet in one Isoc cycle as shown in FIG. When the asynchronous data (Asyn data) of the Asyn packet is input via the IEEE1394 interface 83, the protocol control circuit unit 81 checks whether the packet is addressed to itself from the header of the Asyn packet. The Asyn packet is converted from serial to parallel and stored in the storage memory 82. The Asyn packet stored in the storage memory 82 is output to the MPU via the MPU interface 84. Then, the MPU processes Asyn data based on the header information of the Asyn packet.

  Accordingly, as shown in FIG. 12, when the IPC 80 transfers the Isoc packet 86 and Asyn packet 87 during the first Isoc cycle and the Isoc packet 88 is transferred during the next Isoc cycle, the IPC 80 receives the Isoc packet 86, Asyn packet 87, The controller control processing data 89 and the Isoc packet 88 are output to the MPU in this order. The controller control processing data 89 is data generated in the IPC 80 or by the MPU, and is command data for data processing performed between the MPU and the ISP 80.

  As described above, although the Isoc packets 86 and 88 can be input for each Isoc cycle in the Isoc transfer mode, the Isoc packet 88 of the next cycle completes the output of the Asyn packet 87 and the data 89 of the controller control process. Cannot output until. That is, the IPC 80 cannot transfer the next Isoc packet during the Asyn packet transfer or the controller control operation. Therefore, even in the IEEE protocol, there is a problem that reproduction of images (moving images) lacking in continuity and real time is impaired.

  Further, the conventional IPC 80 stores the packets 86, 87, 88 with the headers 86a, 87a, 88a attached in front of the transfer data 86b, 87b, 88b in the data storage memory 82 and outputs them to the MPU as they are. Was. That is, the analysis of the headers 86a, 87a, 88a attached to the packets 86, 87, 88 is left to the upper MPU. By the way, a large amount of data such as image data cannot be transferred by one Isoc packet 86 in one Isoc cycle. Therefore, the data is divided into a plurality of blocks and transferred over several cycles. At this time, headers 86a and 88a are attached to the Isoc packets 86 and 88 transferred separately for each cycle. The image data 86b and 88b transferred after being divided into the packets 86 and 88 are used as continuous data when actually used, and a header attached to each packet is unnecessary.

  Therefore, the MPU has to sequentially recognize and remove the headers 86a and 88a of the input Isoc packets 86 and 88 to create continuous data. As a result, the load on the MPU increases only by that amount, so that there is a problem in that the data processing speed is lowered and the reproduction of images with lack of continuity and real time is impaired.

  Also in the case of transmission, the MPU has to perform a process of adding a header suitable for the packet to be transmitted to the data, and the load is large as in the case of reception.

  The present invention has been made to solve the above-described problems, and can guarantee further continuity and real-time performance of data, and is a device that requires continuity and real-time performance of a large amount of data such as image data. An object is to provide a suitable data processing method and data processing apparatus.

  The invention of claim 1 receives the first transfer data transferred in the first transfer mode at a certain period between the external device and stores it in the first transfer data storage memory, The second transfer data transferred in the second transfer mode in which the data transfer is performed at a time when the data transfer in the first transfer mode is not performed is received and stored in the second transfer data storage memory. Then, the first transfer data stored in the first transfer data storage memory is read from the first interface, and the second transfer data stored in the second transfer data storage memory is read from the second interface. Read out.

  The invention of claim 2 receives the first transfer data transferred in the first transfer mode at regular intervals with the external device, stores the first transfer data in the first transfer data storage memory, The second transfer data transferred in the second transfer mode in which the data transfer is performed at a time when the data transfer in the first transfer mode is not performed is received and stored in the second transfer data storage memory. The first transfer data stored in the first transfer data storage memory is transferred to the internal device via the first interface, and the second transfer data stored in the second transfer data storage memory is stored. Is transferred to the internal device via the second interface.

According to a third aspect of the present invention, there is provided a first transfer data storage memory for transferring first transfer data transferred to and from an external device in a first transfer mode at a certain period through a first interface. The second transfer data transmitted in the second transfer mode in which the data transfer is performed at a time when the data transfer is not performed in the first transfer mode is stored via the second interface. Thus, the data is transmitted after being stored in the second transfer data storage memory.
According to a fourth aspect of the present invention, there is provided the data processing method according to the second aspect, wherein the first transfer data read from the first transfer data storage memory is transferred to the internal device via the first interface. The first transfer data for transmission from the internal device is stored in the first transfer data storage memory via the first interface, and the first transfer data for transmission is stored in the first transfer data storage memory. Transfer to the external device in the first transfer mode;
The second transfer data for reception read from the second transfer data storage memory is transferred to the internal device via the second interface, and the second transfer data for transmission from the internal device. Is stored in the second transfer data storage memory via the second interface, and the second transfer data for transmission is transferred to the external device in the second transfer mode.

A fifth aspect of the present invention is the data processing method according to any one of the first to fourth aspects, wherein the first transfer data storage memory and the second transfer data storage memory are a plurality of memories. Was included.

According to a sixth aspect of the present invention, in the data processing method according to any one of the first to fifth aspects, the first transfer data storage memory includes a reception memory and a transmission memory. did.

A seventh aspect of the present invention is the data processing method according to any one of the first to sixth aspects, wherein the second transfer data storage memory includes a reception memory and a transmission memory. did.

The invention according to claim 8 is the data processing method according to any one of claims 1 to 7 , wherein the first interface includes a reception interface and a transmission interface.

According to a ninth aspect of the present invention, in the data processing method according to any one of the first to eighth aspects, the second interface includes a reception interface and a transmission interface.

According to a tenth aspect of the present invention, in the data processing method according to any one of the first to ninth aspects, the control data stored in the third memory is used.
The invention according to claim 1 1, in the data processing method according to any one of claims 1-10, wherein the second interface, and also serves as an interface to the processor.

The invention of claim 1 2, in the data processing method according to any one of claims 1 to 1 1, wherein the first transfer data were to be supplied to the first DMA.
The invention of claim 1 3, in the data processing method according to any one of claims 1 to 1 2, wherein the second transfer data were then supplied to the second DMA.

The invention of claim 1 4, in the data processing method according to any one of claims 1 to 1 3, wherein the first transfer mode is isochronous transfer mode, the second transfer mode, This is the asynchronous transfer mode.

The invention of claim 1 5, storing the first transfer data for receiving and storing first transfer data to be transferred every predetermined period which is an external device in the first transfer mode A second memory for receiving and storing second transfer data transferred in a second transfer mode in which data transfer is performed at a time when data transfer is not performed in the first transfer mode; A transfer data storage memory; a first interface for transferring the first transfer data read from the first transfer data storage memory; and the second transfer data storage memory read from the second transfer data storage memory. And a second interface for transferring two pieces of transfer data.

The invention according to claim 16 is the first transfer data storage for receiving and storing the first transfer data transferred in the first transfer mode at regular intervals with the external device. A second memory for receiving and storing second transfer data transferred in a second transfer mode in which data transfer is performed at a time when data transfer is not performed in the first transfer mode; A transfer data storage memory, a first interface for transferring the first transfer data read from the first transfer data storage memory to an internal device, and a read from the second transfer data storage memory And a second interface for transferring the second transfer data to the internal device.

The invention of claim 1 7, a first interface for receiving a first transfer data to be transferred every predetermined period which is an external device in the first transfer mode, from the first interface The first transfer data storage memory for storing the first transfer data and the second transfer mode in which data transfer is performed at a time when data transfer is not performed in the first transfer mode. A second interface for receiving the second transfer data, and a second transfer data storage memory for storing the second transfer data from the second interface.

The invention of claim 1 8, in the data processing apparatus according to any one of claims 15-17, a plurality of the first transfer data storing memory the second storage memory for transferring data Includes memory.

According to a nineteenth aspect of the present invention, in the data processing device according to any one of the fifteenth to eighteenth aspects, the first transfer data storage memory includes a reception memory and a transmission memory.

According to a twentieth aspect of the present invention, in the data processing device according to any one of the fifteenth to nineteenth aspects, the second transfer data storage memory includes a reception memory and a transmission memory.

According to a twenty-first aspect of the present invention, in the data processing device according to any one of the fifteenth to twentieth aspects, the first interface includes a reception interface and a transmission interface.

According to a twenty-second aspect of the present invention, in the data processing device according to any one of the fifteenth to twenty- first aspects, the second interface includes a reception interface and a transmission interface.

The invention according to claim 23 is the data processing device according to any one of claims 15 to 22 , further comprising a third memory for storing control data.
According to a twenty-fourth aspect of the present invention, in the data processing device according to any one of the fifteenth to twenty- third aspects, the second interface also serves as an interface to the processor.

A twenty-fifth aspect of the invention is the data processing device according to any one of the fifteenth to twenty- fourth aspects, further comprising a first DMA to which the first transfer data is supplied.
The invention of claim 26 is the data processing device according to any one of claims 15 to 25 , further comprising a second DMA to which the second transfer data is supplied.

The invention according to claim 27 is the data processing device according to any one of claims 15 to 26 , wherein the first transfer mode is an isochronous transfer mode, and the second transfer mode is an asynchronous mode. It is an eggplant transfer mode.

The invention according to claim 28 is a data processing device provided between the internal device and the external device, and stores the first transfer data transferred in the first transfer mode every certain period. The first transfer data for reception read from the first transfer data storage memory is transferred to the internal device, and the first transfer data for transmission from the internal device is used for the first transfer data. A first interface to be stored in a storage memory and second transfer data to be transferred in a second transfer mode in which data transfer is performed when data transfer in the first transfer mode is not performed are stored. The second transfer data for reception read from the second transfer data storage memory is transferred to the internal device, and the second transfer data for transmission from the internal device is transferred to the second transfer data. And a second interface for storage in use storage memory.

The invention according to claim 29 is the data processing device according to claim 28 , wherein the first transfer data storage memory stores first reception transfer data for storing the first transfer data for reception. A storage memory; and a first transmission transfer data storage memory for storing the first transmission data for transmission.

The invention of claim 30 is the data processing device according to claim 28 or claim 29 , wherein the second transfer data storage memory stores a second transfer data for receiving. A transfer data storage memory for reception, and a second transfer data storage memory for transmission for storing the second transfer data for transmission.

The invention according to claim 31 is the data processing device according to any one of claims 28 to 30 , wherein the first interface includes a first reception interface and a first transmission interface. .

The invention of claim 32 is the data processing device according to any one of claims 28 to 31 , wherein the second interface includes a second reception interface and a second transmission interface. .

The invention of claim 33 is the data processing device according to any one of claims 28 to 32 , further comprising a third memory for storing control data.
The invention of claim 34 is the data processing apparatus according to any one of claims 28 to 33 , wherein the second interface also serves as an interface to the processor.

The invention of claim 35 is the data processing apparatus according to any one of claims 28 to 34 , further comprising a first DMA to which the first transfer data is supplied.
The invention of claim 36, the data process unit according to any one of claims 28-35, comprising a second DMA of the second transfer data is supplied.

The invention of claim 37 is the data processing apparatus according to any one of claims 28 to 36 , wherein the first transfer mode is an isochronous transfer mode, and the second transfer mode is an asynchronous mode. It is an eggplant transfer mode.

(Function)
According to the first aspect of the present invention, the first transfer data and the second transfer data are stored in the first transfer data storage memory and the second transfer data storage memory, respectively. Read from the interface.

  In the invention of claim 2, the first transfer data is received and stored in the first transfer data storage memory, the second transfer data is received and stored in the second transfer data storage memory, The first transfer data stored in one transfer data storage memory is transferred to the internal device via the first interface, and the second transfer data stored in the second transfer data storage memory is the second transfer data. Is transferred to the internal device via the interface.

According to a third aspect of the present invention, the first transfer data is transmitted after being stored in the first transfer data storage memory via the first interface, and the data transfer in the first transfer mode is not performed. The second transfer data for which data transfer is performed is transmitted after being stored in the second transfer data storage memory via the second interface.
In the invention of claim 4, in addition to the operation of the data processing method of claim 2, the first transfer data for reception read from the first transfer data storage memory is sent via the first interface. The first transfer data for transmission from the internal device is stored in the first transfer data storage memory via the first interface, and the first transfer data for transmission is stored in the first transfer data. The second transfer data for reception, which is transferred to the external device in the first transfer mode and read from the second transfer data storage memory, is transferred to the internal device via the second interface, from the internal device. The second transfer data for transmission is stored in the second transfer data storage memory via the second interface, and the second transfer data for transmission is transferred to the external device in the second transfer mode. Be done

In the invention of claim 5 , in addition to the operation of the data processing method according to claims 1 to 4 , the first transfer data storage memory and the second transfer data storage memory include a plurality of memories.
According to the sixth aspect of the invention, in addition to the operation of the data processing method according to the first to fifth aspects, the first transfer data storage memory includes a reception memory and a transmission memory.

According to the seventh aspect of the invention, in addition to the operation of the data processing method according to the first to sixth aspects, the second transfer data storage memory includes a reception memory and a transmission memory.
According to an eighth aspect of the invention, in addition to the operation of the data processing method according to the first to seventh aspects, the first interface includes a reception interface and a transmission interface.

According to the ninth aspect of the present invention, in addition to the operation of the data processing method according to the first to eighth aspects, the second interface includes a reception interface and a transmission interface.
In the invention of claim 10 , in addition to the operation of the data processing methods of claims 1 to 9 , control data stored in the third memory is used.

In the invention of claim 1 1, in addition to the operation of the data processing method according to claim 1-10, the second interface, also serves as an interface to the processor.
In the invention of claim 1 2, in addition to the operation of the data processing method according to claim 1 to 1 1, the first transfer data is supplied to the first DMA.

In the invention of claim 1 3, in addition to the operation of the data processing method according to claim 1 to 1 2, the second transfer data is supplied to the second DMA.
In the invention of claim 1 4, in addition to the operation of the data processing method according to claim 1 to 1 3, the first transfer mode is isochronous transfer mode, a second transfer mode in Aye Synchronous Transfer Mode is there.

In the invention of claim 15 , the received first transfer data is stored in the first transfer data storage memory, the received second transfer data data is stored in the second transfer data storage memory, The first transfer data for reception stored in the first transfer data storage memory is transferred via the first interface, and the second transfer data stored in the second transfer data storage memory is , Transferred via the second interface.

In the invention of claim 16 , the first transfer data is received and stored by the first transfer data storage memory, the second transfer data is received and stored by the second transfer data storage memory, The first transfer data read from the first transfer data storage memory by the first interface is transferred to the internal device, and the second transfer data read from the second transfer data storage memory by the second interface is transferred. Transfer data is transferred to the internal device.

In the invention of claim 17 , the first transfer data is received by the first interface, the first transfer data is stored in the first transfer data storage memory, and the second transfer data is stored by the second interface. Is received, and the second transfer data is stored in the second transfer data storage memory.

In the eighteenth aspect of the invention, in addition to the operation of the data processing device according to the fifteenth to seventeenth aspects, the first transfer data storage memory and the second transfer data storage memory include a plurality of memories.

According to the nineteenth aspect of the present invention, in addition to the operation of the data processing device according to the fifteenth to eighteenth aspects, the first transfer data storage memory includes a reception memory and a transmission memory.
According to the twentieth aspect of the invention, in addition to the operation of the data processing device according to the fifteenth to nineteenth aspects, the second transfer data storage memory includes a reception memory and a transmission memory.

In accordance with the twenty-first aspect of the present invention, in addition to the operation of the data processing device according to any of the fifteenth to twentieth aspects, the first interface includes a reception interface and a transmission interface.

In the invention of claim 22 , in addition to the operation of the data processing device of claims 15 to 21 , the second interface includes a reception interface and a transmission interface.

In the invention of claim 23 , in addition to the operation of the data processing device of claims 15 to 22 , a third memory for storing control data is provided.
In the twenty-fourth aspect of the invention, in addition to the operation of the data processing device according to the fifteenth to twenty- third aspects, the second interface also serves as an interface to the processor.

According to a twenty-fifth aspect of the invention, in addition to the operation of the data processing device according to the fifteenth to twenty- fourth aspects, a first DMA to which the first transfer data is supplied is provided.
According to a twenty-sixth aspect of the invention, in addition to the operation of the data processing device according to the fifteenth to twenty- fifth aspects, a second DMA to which second transfer data is supplied is provided.

According to the twenty-seventh aspect of the invention, in addition to the operation of the data processing device according to the fifteenth to twenty- sixth aspects, the first transfer mode is an isochronous transfer mode, and the second transfer mode is an asynchronous transfer mode.

In the invention of claim 28 , the first transfer data for reception read from the first transfer data storage memory by the first interface is transferred to the internal device, and the first data for transmission from the internal device is also transmitted. One transfer data is stored in the first transfer data storage memory, and the second transfer data for reception read from the second transfer data storage memory is transferred to the internal device by the second interface. At the same time, the second transfer data for transmission from the internal device is stored in the second transfer data storage memory.

In the present invention of claim 29, in addition to the functions of the data processing apparatus according to claim 28, in the first storage memory for transferring data, the first receiver for storing first transfer data for reception A transfer data storage memory for transmission and a first transfer data storage memory for transmission for storing first transfer data for transmission.

In the invention of claim 30 , in addition to the operation of the data processing device according to claims 28 to 29 , the second transfer data storage memory stores the second transfer data for receiving the second transfer data for reception. A transfer data storage memory for reception and a second transfer data storage memory for transmission for storing second transfer data for transmission.

In the invention of claim 31 , in addition to the operation of the data processing device of claims 28 to 30 , the first interface includes a first reception interface and a first transmission interface. .

In the invention of claim 32 , in addition to the operation of the data processing device of claims 28 to 31 , the second interface includes a second reception interface and a second transmission interface. .

According to a thirty-third aspect of the invention, in addition to the operation of the data processing device according to the twenty-eighth to thirty- second aspects, a third memory for storing control data is provided.
In the invention of claim 34 , in addition to the operation of the data processing device of claims 28 to 33 , the second interface also serves as an interface to the processor.

According to a thirty-fifth aspect of the present invention, in addition to the operation of the data processing device according to the twenty-eighth to thirty- fourth aspects, a first DMA to which the first transfer data is supplied is provided.
In the present invention of claim 36, in addition to the functions of the data processing apparatus according to claim 28-35, the second transfer data is provided with a second DMA supplied.

In the thirty-seventh aspect of the invention, in addition to the operation of the data processing device according to the twenty-eighth to thirty- sixth aspects, the first transfer mode is an isochronous transfer mode, and the second transfer mode is an asynchronous transfer mode.

According to the first to thirty-seventh aspects of the present invention, the first transfer data and the second transfer data are stored in separate storage memories and transferred through separate interfaces. It is possible to guarantee the reproduction of a secured and realistic video or the like.

(First embodiment)
FIG. 1 shows a system configuration conforming to IEEE1394, which is one of serial interfaces. In FIG. 1, a personal computer (hereinafter referred to as a personal computer) 1, a digital VTR 2 as an external device, a color page printer 3 as an external device, and a digital video camera 4 as an external device are connected via an IEEE1394 bus 5. Are connected to each other. The host computer 1, digital VTR 2, color page printer 3, and digital video camera 4 are connected to each other via an IEEE 1394 bus cable (hereinafter referred to as an IEEE 1394 bus) 5, and an IEEE 1394 protocol controller for enabling data transfer conforming to IEEE 1394. Are provided.

  FIG. 2 shows a block circuit for explaining the configuration of a system compliant with IEEE1394 provided in the personal computer 1. The personal computer 1 includes an IEEE1394 protocol controller (hereinafter referred to as IPC) 11, a microprocessor unit (hereinafter referred to as MPU) 12 as an internal device, and two first and second DMAs (Direct Memory Access) as internal devices. Controllers 13 and 14 are provided. The IPC 11, MPU 12, first DMA controller (hereinafter referred to as first DMAC) 13, and second DMA controller (hereinafter referred to as second DMAC) 14 are each formed by a one-chip semiconductor integrated circuit device (LSI).

  The IPC 11 exchanges data with the MPU 12, the first DMAC 13, and the second DMAC 14. The IPC 11 is connected to an IEEE1394 protocol controller (IPC) provided in the digital VTR 2, the color page printer 3, and the digital video camera 4 via the IEEE1394 bus 5.

  FIG. 3 shows a block circuit for explaining the circuit configuration of the IPC 11. The IPC 11 includes first to fourth storages including a physical layer processing circuit 20, a link layer processing circuit 21, first and second transmission packet processing circuits 22a and 22b, first and second reception packet processing circuits 23a and 23b, and a FIFO. Memory (first to fourth FIFO) 24a to 24d, control internal register 25, first and second 1394 interfaces (hereinafter referred to as first and second 1394 I / Fs) 26a and 26b, isochronous data transmission Interface (hereinafter referred to as Isoc transmission I / F) 27a, isochronous data reception interface (hereinafter referred to as Isoc reception I / F) 28a, asynchronous data transmission interface (hereinafter referred to as Asyn transmission I / F) 27b, asynchronous data reception interface (hereinafter referred to as "Asyn reception I / F") 28b, An MPU interface (hereinafter referred to as MPUI / F) 29 is provided.

The first 1394 I / F 26a is connected to the digital VTR2 via the IEEE1394 bus 5, and is a packet in the isochronous transfer (Isoc transfer) mode between the physical layer processing circuit 20 and the IPC of the digital VTR2 (hereinafter referred to as “Isoc transfer”). , An Isoc packet) 31 and a packet (hereinafter referred to as an Asyn packet) 32 in the asynchronous transfer (Asyn transfer) mode. The second 1394 I / F 26 b is connected to the color page printer 3 via the IEEE1394 bus 5, and isoc packet 31 in the Isoc transfer mode between the physical layer processing circuit 20 and the IPC of the color page printer 3. The Asyn packet 32 is exchanged in the Asyn transfer mode.
The Isoc packet 31 includes a header 31a and isochronous data (hereinafter referred to as Isoc data) 31b. The Asyn packet 32 includes a header 32a and asynchronous data (hereinafter referred to as Asyn data) 32b.

  The Isoc transmission I / F 27a is connected to the first DMAC 13, and transfers transfer data (Isoc packet 31) for transmission in the Isoc transfer mode from the first DMAC 13 to the first FIFO 24a. The Isoc reception I / F 28a is connected to the first DMAC 13, and transfers the transfer data (Isoc packet 31) received in the Isoc transfer mode stored in the second FIFO 24b to the first DMAC 13.

  The Asyn transmission I / F 27b is connected to the second DMAC 14, and transfers transfer data (Asyn packet 32) for transmission in the Asyn transfer mode from the second DMAC 14 to the third FIFO 24c. The Asyn reception I / F 28b is connected to the second DMAC 14, and transfers the transfer data (Asyn packet 32) received in the Asyn transfer mode stored in the fourth FIFO 24d to the second DMAC 14. The MPUI / F 29 is connected to the MPU 12 and exchanges various command data and the like between the MPU 12 and the control internal register 25.

  The physical layer processing circuit 20 inputs the Isoc packet 31 and Asyn packet 32 received by the first and second 1394 I / Fs 26 a and 26 b and outputs them to the link layer processing circuit 21. In addition, the physical layer processing circuit 20 receives the transmission Isoc packet 31 and the transmission Asyn packet 32 from the link layer processing circuit 21. Then, the physical layer processing circuit 20 sends the Isoc packet 31 and the Asyn packet 32 via the first or second 1394 I / F 26a, 26b to the transmission destination digital VTR 2, color page printer 3, or digital video. Send to camera 4.

  The link layer processing circuit 21 inputs the Isoc packet 31 and the Asyn packet 32 received from the physical layer processing circuit 20. The link layer processing circuit 21 determines whether the packet is addressed to itself (personal computer 1) based on the contents of the headers 31a, 32a attached to the heads of the packets 31, 32. Is supplied to the first or second received packet processing circuits 23a and 23b. If the packet is not addressed to itself, the link layer processing circuit 21 passes the packets 31 and 32 through the physical layer processing circuit 20 and the first or second 1394 I / F 26a, 26b to the digital destination. The data is transmitted to the VTR 2, the color page printer 3, or the digital video camera 4.

  The link layer processing circuit 21 determines whether the received packet addressed to itself is an Isoc packet 31 or an Asyn packet 32 from the contents of the header added to the packets 31 and 32. When the received packet is an Isoc packet 31, the link layer processing circuit 21 supplies the Isoc packet 31 to the first reception packet processing circuit 23a. If the received packet is an Asyn packet 32, the link layer processing circuit 21 supplies the Asyn packet 32 to the second received packet processing circuit 23b.

  Further, the link layer processing circuit 21 is supplied with the transmission Isoc packet 31 from the first transmission packet processing circuit 22a and is supplied with the transmission Asyn packet 32 from the second transmission packet processing circuit 22b.

  The first received packet processing circuit 23 a is supplied with the Isoc packet 31 received from the link layer processing circuit 21. The first received packet processing circuit 23 a performs error correction check processing on the received Isoc packet 31. That is, in the present embodiment, error correction processing is separately performed on the header 31a and the Isoc data 31b of the Isoc packet 31. The first received packet processing circuit 23a supplies the second FIFO 24b with the Isoc packet 31 subjected to error correction processing.

  The second FIFO 24b receives the reliable Isoc packet 31 subjected to the error correction process, and outputs it to the next-stage Isoc reception I / F 28a in the input order. The Isoc reception I / F 28a passes the Isoc packet 31 including the header 31a and the Isoc data 31b to the first DMAC 13 as described above.

  The Asyn packet 32 received from the link layer processing circuit 21 is supplied to the second received packet processing circuit 23b. The second received packet processing circuit 23 b performs error correction check processing on the received Asyn packet 32. In the same manner as described above, the header 32a and the Asyn data 32b of the Asyn packet 32 are separately processed for error correction. The second received packet processing circuit 23b supplies the Asyn packet 32 subjected to error correction processing to the fourth FIFO 24d.

  The fourth FIFO 24d receives the reliable Asyn packet 32 that has been subjected to the error correction process, and outputs it to the Asyn reception I / F 28b in the next stage in the order of input. The Asyn reception I / F 28b passes the Asyn packet 32 including the header 32a and the Asyn data 32b to the second DMAC 14 as described above.

  The first FIFO 24a inputs the Isoc packet 31 for transmission from the first DMAC 13 via the Isoc transmission I / F 27a for transmission in the Isoc transfer mode, and supplies the packet to the first transmission packet processing circuit 22a in the order of input. . The first transmission packet processing circuit 22a generates an error correction code for the Isoc packets 31 that are sequentially input. That is, in the present embodiment, processing for generating and adding error correction codes separately for the header 31a and the Isoc data 31b of the Isoc packet 31 is performed. The first transmission packet processing circuit 22a supplies the link layer processing circuit 21 with the Isoc packet 31 to which the generated error correction code is added to the header 31a and the Isoc data 31b.

  The third FIFO 24c inputs the transmission Asyn packet 32 for transmission in the Asyn transfer mode from the second DMAC 14 via the Asyn transmission I / F 27b, and supplies it to the second transmission packet processing circuit 22b in the input order. . The second transmission packet processing circuit 22b generates an error correction code for the Asyn packet 32 that is sequentially input. Then, in the same manner as described above, a process for generating and adding an error correction code separately for the header 32a and the Asyn data 32b of the Asyn packet 32 is performed. The second transmission packet processing circuit 22b supplies the link layer processing circuit 21 with the Asyn packet 32 in which the generated error correction code is added to the header 32a and the Asyn data 32b.

  The control internal register 25 is provided between the MPUI / F 29 and the link layer processing circuit 21. The control internal register 25 temporarily stores control data 33 such as various commands executed between the MPU 12 and the IPC 11. Then, the control data 33 from the MPU 12 input via the MPUI / F 29 is read by the link layer processing circuit 21 and causes the IPC 11 to execute a control operation for the transfer control process. The control data from the link layer processing circuit 21 is read by the MPU 12 and causes the MPU 12 to execute a control operation for transfer control processing.

Next, the operation of the IPC 11 configured as described above will be described.
For convenience of explanation, a case will be described in which transmission and reception packets 31 and 32 are generated in the time series shown in FIG. Now, in the first Isoc cycle, the first Isoc packet for reception 31 that is generated is supplied to the link layer processing circuit 21 via the first 1394 I / F 26 a and the physical layer processing circuit 20. The Isoc packet 31 for reception is determined as the Isoc packet 31 in the Isoc transfer mode from the header 31a of the packet by the link layer processing circuit 21, and is supplied to the first reception packet processing circuit 23a. The Isoc packet 31 supplied to the first received packet processing circuit 23a is supplied to the second FIFO 24b after error correction check processing is performed. The Isoc packet 31 stored in the second FIFO 24b is supplied to the first DMAC 13 via the Isoc reception I / F 28a.

  In a first Isoc cycle, a transmission Isoc packet 31 generated after the reception Isoc packet 31 is supplied from the first DMAC 13 to the first transmission packet processing circuit 22a via the Isoc transmission I / F 27a and the first FIFO 24a. The The Isoc packet 31 for transmission supplied to the first transmission packet processing circuit 22 a is supplied to the link layer processing circuit 21 with the generated error correction code added to the header 31 a and Isoc data 31 b of the packet 31. The The Isoc packet 31 for transmission supplied to the link layer processing circuit 21 is supplied with a header that specifies transmission in the Isoc transfer mode and is supplied to the physical layer processing circuit 20. The transmission Isoc packet 31 supplied to the physical layer processing circuit 20 is transmitted to the transmission destination, for example, the color page printer 3 via the second 1394 I / F 26b.

  In the first Isoc cycle, the reception Asyn packet 32 generated after the transmission Isoc packet 31 is supplied to the link layer processing circuit 21 via the first 1394 I / F 26a and the physical layer processing circuit 20. The The Asyn packet 32 for reception is determined as the Asyn packet 32 in the Asyn transfer mode from the header 32a of the packet by the link layer processing circuit 21, and is supplied to the second received packet processing circuit 23b. The Asyn packet 32 supplied to the second received packet processing circuit 23b is supplied to the fourth FIFO 24d after error correction check processing is performed. The Asyn packet 32 stored in the fourth FIFO 24d is supplied to the second DMAC 14 via the Asyn reception I / F 2b.

  When the first Isoc cycle is completed and the next Isoc cycle is reached, an Isoc packet 31 for reception is first supplied to the link layer processing circuit 21 via the first 1394 I / F 26a and the physical layer processing circuit 20. . This Isoc packet 31 for reception is determined as the Isoc packet 31 in the Isoc transfer mode by the link layer processing circuit 21 and supplied to the first received packet processing circuit 23a, similarly to the Isoc packet 31 of the previous Isoc cycle. The The Isoc packet 31 is supplied to the second FIFO 24b after error correction check processing is performed by the first received packet processing circuit 23a. The Isoc packet 31 stored in the second FIFO 24b is supplied to the first DMAC 13 via the Isoc reception I / F 28a.

  In this Isoc cycle, the transmission Isoc packet 31 generated after the reception Isoc packet 31 is transmitted from the first DMAC 13 via the Isoc transmission I / F 27a and the first FIFO 24a in the same manner as in the previous Isoc cycle. 1 is supplied to the transmission packet processing circuit 22a. The transmission Isoc packet 31 is supplied with an error correction code by the first transmission packet processing circuit 22 a and supplied to the link layer processing circuit 21. In addition, a header that specifies transmission of the Isoc packet 31 for transmission in the Isoc transfer mode is added by the first transmission packet processing circuit 22a, and is supplied to the physical layer processing circuit 20 via the link layer processing circuit 21. The The transmission Isoc packet 31 supplied to the physical layer processing circuit 20 is transmitted to the transmission destination, for example, the color page printer 3 via the second 1394 I / F 26b.

  In this Isoc cycle, the transmission Asyn packet 32 generated after the transmission Isoc packet 31 is supplied from the second DMAC 14 to the second transmission packet processing circuit 22b via the Asyn transmission I / F 27b and the third FIFO 24c. . The Asyn packet 32 for transmission is added with an error correction code by the second transmission packet processing circuit 22b and supplied to the link layer processing circuit 21. The Asyn packet 32 for transmission is supplied to the physical layer processing circuit 20 via the link layer processing circuit 21 with a header for specifying transmission in the Asyn transfer mode by the second transmission packet processing circuit 22b. The transmission Asyn packet 32 supplied to the physical layer processing circuit 20 is transmitted to the transmission destination, for example, the color page printer 3 via the second 1394 I / F 26b.

Next, features of the IPC 11 configured as described above will be described below.
(1) In this embodiment, storage memory (first and second FIFOs 24a and 24b) for storing transfer data (Isoc packet 31) in Isoc transfer mode and storage for storing transfer data (Asyn packet 32) in Asyn transfer mode The memories (third and fourth FIFOs 24c and 24d) were provided separately. Also, interfaces (Isoc transmission and reception interfaces 27a and 28a) for inputting / outputting transfer data (Isoc packet 31) in the Isoc transfer mode and interfaces (Asyn transmission and transmission) for transferring transfer data (Asyn packet 32) in the Asyn transfer mode. Receiving interfaces 27b and 28b) are provided separately.

  Then, the Isoc packet 31 transferred in the Isoc transfer mode and the Asyn packet 32 transferred in the Asyn transfer mode are stored in separate storage memories, and input / output to / from different interfaces. Therefore, for example, each reception Isoc packet 31 transferred in each Isoc cycle has a reception Asyn packet 32 transferred in the Asyn transfer mode at a surplus time in each Isoc cycle. Without being interrupted by the transfer operation of the Asyn packet 32, it can be transferred continuously from the Isoc reception I / F 28a to the first DMAC 13. As a result, the Isoc packet 31 for transferring image data such as a moving image that requires continuity is further ensured in continuous transfer and real-time transfer as compared with the conventional case, thereby ensuring the reproduction of a realistic moving image.

  (2) In the present embodiment, the Isoc packet 31 for transmission is separately stored in the first FIFO 24a, the Isoc packet 31 for reception is separately stored in the second FIFO 24b, and the Isoc packet 31 for transmission is stored in the first DMAC 13. An Isoc transmission I / F 27a for transferring and an Isoc receiving I / F 28a for transferring the receiving Isoc packet 31 are provided.

  Then, the transmission Isoc packet 31 and the reception Isoc packet 32 transferred in the Isoc transfer mode are separately transferred to the first DMAC 13. Therefore, the reception Isoc packet 31 transferred in each Isoc cycle is transmitted from the Isoc reception I / F 28a to the first DMAC 13 even if the transmission of the transmission Isoc packet 31 and the reception Isoc packet 31 is mixed. Can be transferred to. As a result, the Isoc packet 31 that transfers image data such as a moving image that requires continuity can ensure more continuous transfer and real-time transfer, and guarantee the reproduction of a realistic moving image.

  (3) Furthermore, in the present embodiment, as shown in FIG. 4, control data 33 such as a command for controller control processing performed with the MPU 12 is transmitted / received via the MPUI / F 29. Therefore, the Isoc packet 31 can be transferred without restriction even if the control data 33 such as a command for controller control processing is exchanged.

  (4) Furthermore, in the present embodiment, the Asyn packet 32 for transmission is separately stored in the third FIFO 24c and the Asyn packet 32 for reception is separately stored in the fourth FIFO 24d, and the Asyn packet 32 for transmission is stored in the second DMAC 14. Asyn transmission I / F 27b for transferring and Asyn reception I / F 28b for transferring Asyn packet 32 for reception.

  Then, the Asyn packet 32 for transmission and the Asyn packet 32 for reception are separately transferred to the second DMAC 14. Accordingly, even if the transmission of the Asyn packet 32 for transmission and the transfer of the Asyn packet 32 for reception coexist, the transfer of the respective Asyn packets 32 can be transferred continuously.

(Second Embodiment)
In the present embodiment, the IPC 11 shown in the first embodiment is modified. Therefore, only the IPC 11 will be described. FIG. 5 shows a block circuit for explaining the circuit configuration of the IPC 11 of the present embodiment. In addition, the code | symbol same about the same structure as 1st Embodiment is used, and the detail is abbreviate | omitted.

  The IPC 11 includes a physical layer processing circuit 20, first and second 1394 I / Fs 26a and 26b, a link layer processing circuit 36, an Isoc packet processing circuit 37a, an Asyn packet processing circuit 37b, an Isoc transfer FIFO 38a, and an Asyn transfer FIFO 38b. A first DMA interface (first DMA I / F) 39a, a second DMA interface (second DMA I / F) 39b, a control internal register 25, and an MPUI / F 29.

  The first DMA I / F 39a is connected to the first DMAC 13. Then, the first DMA I / F 39 a transfers the transmission and reception Isoc packets 31 to and from the first DMAC 13. In other words, in the present embodiment, as described in the first embodiment, the dedicated Isoc transmission I / F 27a for the Isoc packet 31 for transmission and the dedicated IocF 31 for the reception Isoc packet 31 are used. The I soc reception I / F 28a is not provided separately, and one first DMA I / F 39a transfers the transmission and reception Isoc packets 31 to and from the first DMAC 13. Therefore, the first DMAC 13 of the first embodiment includes interfaces corresponding to the Isoc transmission I / F 27a and the Isoc reception I / F 28a. In the first DMAC 13 of the present embodiment, the first DMA I / F 39a includes Only one corresponding interface is provided.

  The Isoc transfer FIFO 38a stores transmission and reception Isoc packets 31. When the Isoc transfer FIFO 38a receives the Isoc packet 31 for transmission from the first DMA I / F 39a, the Isoc transfer FIFO 38a supplies the packet data to the Isoc transfer packet processing circuit 38a in the input order. When the Isoc transfer FIFO 38a receives the Isoc packet 31 for reception from the Isoc packet processing circuit 37a, it supplies the data of the packet to the first DMA I / F 39a in the input order. That is, in the present embodiment, as described in the first embodiment, the dedicated first FIFO 24a for storing the transmission Isoc packet 31 and the dedicated FIFO for storing the reception Isoc packet 31 are used. The second FIFO 24b is not separately provided, and one Isoc transfer FIFO 38a stores the Isoc packet 31 for transmission and reception. Therefore, when the Isoc transfer FIFO 38a stores and transfers one of the data of the reception and transmission Isoc packets 31, it cannot store the other data.

  The Isoc packet processing circuit 37a is supplied with Isoc packets 31 for transmission and reception. The Isoc packet processing circuit 37 a performs error correction code generation for the transmission Isoc packet 31 and error correction check for the reception Isoc packet 31. When the Isoc packet processing circuit 37a receives the Isoc packet 31 for transmission from the FIFO 38a for Isoc transfer, the Isoc packet processing circuit 37a generates an error correction code for the packet 31. That is, the Isoc packet processing circuit 37a generates and adds error correction codes separately for the header 31a and the Isoc data 31b of the Isoc packet 31, and outputs the error correction codes to the link layer processing circuit 36. When the Isoc packet processing circuit 37a receives the Isoc packet 31 for reception from the link layer processing circuit 36, the Isoc packet processing circuit 37a performs error correction check processing on the packet 31. In other words, the Isoc packet 37a is subjected to error correction processing separately for the header 31a and the Isoc data 31b of the Isoc packet 31, and then output to the Isoc transfer FIFO 38a.

  The second DMA I / F 39b is connected to the second DMAC 14. Then, the second DMA I / F 39b transfers the Asyn packet 32 for transmission and reception to and from the second DMAC 14. In other words, in this embodiment, as described in the first embodiment, the dedicated Asyn transmission I / F 27b for the Asyn packet 32 for transmission and the dedicated for the Asyn packet 32 for reception. Each Asyn reception I / F 28b is not provided separately, and one second DMA I / F 39b transfers the Asyn packet 32 for transmission and reception to and from the second DMAC 14. Therefore, the second DMAC 14 of the first embodiment has interfaces corresponding to the Asyn transmission I / F 27b and the Asyn reception I / F 28b, respectively. However, in the second DMAC 14 of the present embodiment, the second DMA I / F 39b Only one corresponding interface is provided.

  The Asyn transfer FIFO 38b stores Asyn packets 32 for transmission and reception. When the Asyn transfer FIFO 38b receives the Asyn packet 32 for transmission from the second DMA I / F 39b, the Asyn transfer FIFO 38b supplies the data of the packet to the Asyn transfer packet processing circuit 38b in the input order. When the Asyn transfer FIFO 38b receives the Asyn packet 32 for reception from the Asyn packet processing circuit 37b, the Asyn transfer FIFO 38b supplies the data of the packet to the second DMA I / F 39b in the input order. In other words, in this embodiment, as described in the first embodiment, the dedicated third FIFO 24c for storing the transmission Asyn packet 32 and the dedicated third FIFO 24c for storing the reception Asyn packet 32 are used. The fourth FIFO 24d is not provided separately, and one Asyn transfer FIFO 38b stores the Isoc packet 32 for transmission and reception. Therefore, the Asyn transfer FIFO 38b cannot store the other data when storing and transferring one of the data of the reception and transmission Isoc packets 32.

  The Asyn packet processing circuit 37b is supplied with Asyn packets 32 for transmission and reception. The Asyn packet processing circuit 37b performs error correction code generation for the Asyn packet 32 for transmission and error correction check for the Asyn packet 32 for reception. When the Asyn packet 32 for transmission is input from the Asyn transfer FIFO 38b, the Asyn packet processing circuit 37b generates an error correction code for the packet 32. That is, the Asyn packet processing circuit 37b generates and adds error correction codes separately for the header 32a and Asyn data 32b of the Asyn packet 32, and outputs them to the link layer processing circuit 36. Also, when the Asyn packet processing circuit 37b receives the Asyn packet 32 for reception from the link layer processing circuit 36, the Asyn packet processing circuit 37b performs error correction check processing on the packet 32. In other words, the Asyn packet 37b performs error correction processing separately on the header 32a and Asyn data 32b of the Asyn packet 32, and then outputs them to the Asyn transfer FIFO 38b.

Next, the operation of the IPC 11 configured as described above will be described.
For convenience of explanation, a case will be described in which the receiving Isoc packet 31 and the receiving Asyn packet 32 are generated in the time series shown in FIG. Now, in the first Isoc cycle, the first reception Isoc packet 31 is supplied to the link layer processing circuit 36 via the first 1394 I / F 26 a and the physical layer processing circuit 20. The Isoc packet 31 is determined by the link layer processing circuit 36 as an Isoc packet 31 in the Isoc transfer mode from the header of the packet, and is supplied to the Isoc packet processing circuit 37a. The Isoc packet 31 is supplied to the Isoc transfer FIFO 38a after being subjected to a check process for error correction by the Isoc packet processing circuit 37a. The Isoc packet 31 supplied to the Isoc transfer FIFO 38a is supplied to the first DMAC 13 via the first DMA I / F 39a.

  Subsequently, in this first Isoc cycle, the Asyn packet 32 generated after the Isoc packet 31 is supplied to the link layer processing circuit 36 via the first 1394 I / F 26 a and the physical layer processing circuit 20. The Asyn packet 32 is determined by the link layer processing circuit 36 as an Asyn packet 32 in the Asyn transfer mode from the header of the packet, and is supplied to the Asyn packet processing circuit 37b. The Asyn packet 32 is supplied to the Asyn transfer FIFO 38b after being checked by the Asyn packet processing circuit 37b for error correction. The Asyn packet 32 supplied to the Asyn transfer FIFO 38b is supplied to the second DMAC 14 via the second DMA I / F 39b.

  When the first Isoc cycle is completed and the next Isoc cycle is reached, the first generated Isoc packet 31 is similarly received via the first 1394 I / F 26a and the physical layer processing circuit 20 through the link layer processing circuit. 36. The Isoc packet 31 is determined as the Isoc packet 31 in the Isoc transfer mode by the link layer processing circuit 36 and supplied to the Isoc packet processing circuit 37a. The Isoc packet 31 is supplied to the Isoc transfer FIFO 38a after being subjected to a check process for error correction by the Isoc packet processing circuit 37a. The Isoc packet 31 supplied to the Isoc transfer FIFO 38a is supplied to the first DMAC 13 via the first DMA I / F 39a.

Next, features of the IPC 11 configured in the second embodiment as described above will be described below.
(1) In the present embodiment, an Isoc transfer FIFO 38a for storing transfer data (Isoc packet 31) in Isoc transfer mode and an Asyn transfer FIFO 38b for storing transfer data (Asyn packet 32) in Asyn transfer mode are provided separately. It was. Also, a first DMA I / F 39a for inputting / outputting transfer data (Isoc packet 31) in the Isoc transfer mode and a second DMA I / F 39b for inputting / outputting transfer data (Asyn packet 32) in the Asyn transfer mode are provided separately.

  Then, the Isoc packet 31 transferred in the Isoc transfer mode and the Asyn packet 32 transferred in the Asyn transfer mode are stored in separate storage memories (FIFOs 38a and 38b), and are stored in separate interfaces (DMA I / Fs 39a and 39b). I / O was made. Therefore, for example, each reception Isoc packet 31 transferred in each Isoc cycle has a reception Asyn packet 32 transferred in the Asyn transfer mode at a surplus time in each Isoc cycle. Without being interrupted by the transfer operation of the Asyn packet 32, it can be transferred continuously from the Isoc reception I / F 28a to the first DMAC 13. As a result, the Isoc packet 31 for transferring image data such as a moving image that requires continuity is further ensured in continuous transfer and real-time transfer as compared with the conventional case, thereby ensuring the reproduction of a realistic moving image.

  (2) In the present embodiment, as shown in FIG. 6, exchange of control data 33 such as commands for controller control processing performed with the MPU 12 is performed via the MPUI / F 29. Therefore, the Isoc packet 31 can be transferred without restriction even if the control data 33 such as a command for controller control processing is exchanged.

(Third embodiment)
This embodiment is a modification of the IPC 11 shown in the second embodiment. Therefore, only the IPC 11 will be described. FIG. 7 shows a block circuit for explaining the circuit configuration of the IPC 11 of the present embodiment. In addition, the code | symbol is made the same about the same structure as 2nd Embodiment, and the detail is abbreviate | omitted.

  The IPC 11 includes a physical layer processing circuit 20, first and second 1394 I / Fs 26a and 26b, a link layer processing circuit 36, an Isoc packet processing circuit 37a, an Asyn packet processing circuit 37b, an Isoc transfer FIFO 38a, and an Asyn transfer FIFO 38b. The first DMA interface (first DMA I / F) 39a, the control internal register 25, and the MPU / DMA interface (MPU / DMA I / F) 40 are provided. That is, in this embodiment, the second DMA I / F 39b and the MPUI / F 29 of the second embodiment are combined with one MPU / DMA I / F 40. Therefore, for convenience of explanation, only the MPU / DMA I / F 40 will be described.

  The MPU / DMA I / F 40 is connected to the second DMAC 14 and the MPU 12. The MPU / DMA I / F 40 transfers Asyn packets 32 for transmission and reception to / from the second DMAC 14. The MPU / DMA I / F 40 transfers the control data 33 between the MPU 12 and the control internal register 25. The MPU / DMA I / F 40 transfers the Asyn packet 32 for transmission from the second DMAC 14 to the Asyn transfer FIFO 38b, and transfers it to the second DMAC 14 when it receives the Asyn packet 32 for reception from the Asyn transfer FIFO 38b. Also, the MPU / DMA I / F 40 transfers the control data 33 from the MPU 12 to the control internal register 25 and transfers the reception control data 33 from the control internal register 25 to the MPU 12.

Next, the operation of the IPC 11 configured as described above will be described.
For convenience of explanation, a case will be described in which the reception Isoc packet 31 and the reception Asyn packet 32 are generated in the time series shown in FIG. Now, in the first Isoc cycle, the first reception Isoc packet 31 is supplied to the link layer processing circuit 36 via the first 1394 I / F 26 a and the physical layer processing circuit 20. The Isoc packet 31 is supplied to the first DMAC 13 via the link layer processing circuit 36, the Isoc packet processing circuit 37a, the Isoc transfer FIFO 38a, and the first DMA I / F 39a, as in the second embodiment.

  Subsequently, in this first Isoc cycle, the Asyn packet 32 generated after the Isoc packet 31 is similar to the second embodiment in that the first 1394 I / F 26a, the physical layer processing circuit 20, and The data is supplied to the Asyn packet processing circuit 37b via the link layer processing circuit 36. The Asyn packet 32 is supplied to the MPU / DMA I / F 40 after being checked by the Asyn packet processing circuit 37b for error correction. The Asyn packet 32 is determined as an Asyn packet 32 by the MPU / DMA I / F 40 and supplied to the second DMAC 14.

  When the first Isoc cycle is completed and the next Isoc cycle is reached, the first Isoc packet for reception 31 that is generated is the first 1394 I / F 26a, physical layer processing circuit, as in the second embodiment. 20, is supplied to the first DMAC 13 via the link layer processing circuit 36, the Isoc packet processing circuit 37a, the Isoc transfer FIFO 38a, and the first DMA I / F 39a.

Next, the features of the IPC 11 configured in the third embodiment as described above will be described below.
(1) In the present embodiment, an Isoc transfer FIFO 38a for storing transfer data (Isoc packet 31) in Isoc transfer mode and an Asyn transfer FIFO 38b for storing transfer data (Asyn packet 32) in Asyn transfer mode are provided separately. It was. In addition, a first DMA I / F 39a for inputting / outputting transfer data (Isoc packet 31) in the Isoc transfer mode and an MPU / DMA I / F 40 for inputting / outputting transfer data (Asyn packet 32) in the Asyn transfer mode are separately provided.

  Therefore, as in the second embodiment, for example, each reception Isoc packet 31 transferred in each Isoc cycle is received in the Asyn transfer mode at a surplus time in each Isoc cycle. Even if the Asyn packet 32 exists, it can be continuously transferred from the Isoc reception I / F 28a to the first DMAC 13 without being interrupted by the transfer operation of the Asyn packet 32. As a result, the Isoc packet 31 for transferring image data such as a moving image that requires continuity is further ensured in continuous transfer and real-time transfer as compared with the conventional case, thereby ensuring the reproduction of a realistic moving image.

  (2) In the present embodiment, as shown in FIG. 8, exchange of control data 33 such as commands for controller control processing performed with the MPU 12 is performed via the MPU / DMA I / F 40. Therefore, the Isoc packet 31 can be transferred without restriction even if the control data 33 such as a command for controller control processing is exchanged.

(Fourth embodiment)
In this embodiment, in the IPC 11 shown in the second embodiment, the link layer processing circuit 36 and the first DMA I / F 39a are changed and the link layer processing circuit 36 and the second DMA I / F 39b are changed. is there. Therefore, the changed part will be described for convenience of explanation. FIG. 9 shows a block circuit for explaining a main circuit configuration of the IPC 11 of the present embodiment. In addition, the code | symbol is made the same about the same structure as 2nd Embodiment, and the detail is abbreviate | omitted.

  In FIG. 9, the processing circuit for the Isoc packet includes an error correction generation circuit (hereinafter referred to as a CRC generation circuit) 41a, an error correction check circuit (hereinafter referred to as a CRC check circuit) 41b, an Isoc packet generation unit 42a, and an Isoc packet analysis unit 42b. , And an instruction analysis unit 43. Further, the FIFO for Isoc transfer is composed of an FIFO 44a dedicated to the Isoc header and an FIFO 44b dedicated to the Isoc data.

  The CRC check circuit 41b is supplied with the Isoc packet 31 for reception from the link layer processing circuit 36. The CRC check circuit 41b performs error correction processing of the reception Isoc packet 31 for each of the header 31a and the Isoc data 31b, removes the correction code, and sends the data of the reception Isoc packet 31 to the Isoc packet analysis unit 42b. Supply. The analysis unit 42b separates the header 31a and the Isoc data 31b constituting the Isoc packet 31. The number of bytes in the header of the packet is fixed (8 bytes, of which 4 bytes are header information and the remaining 4 bytes are error correction codes), and the number of bytes of Isoc data can be found by looking at the data length in the header. Then, the separation process is performed by counting the number of bytes.

  The separated header 31a is supplied to the Isoc header dedicated FIFO 44a. The separated Isoc data 31b is supplied to the Isoc data dedicated FIFO 44b. Accordingly, the Isoc header dedicated FIFO 44a stores only the header 31a, and the Isoc data dedicated FIFO 44b stores only the Isoc data 31b.

  The Isoc header dedicated FIFO 44a transfers the stored separated header 31a to the first DMAC 13 in order via the first DMA I / F 39a in the order of input. The Isoc data dedicated FIFO 44b transfers the stored separated Isoc data 31b to the first DMAC 13 in order via the first DMA I / F 39a in the order of input. Accordingly, the first DMAC 13 inputs only the Isoc header 31a from the FIFO 44a dedicated FIFO 44a via the first DMA I / F 39a, and passes the first DMA I / F 39a based on the transaction type, data length, address, etc. in the header 31a. Isoc data 31b of the FIFO 44b dedicated to Isoc data can be input.

  The Isoc header dedicated FIFO 44a stores only the header 31a necessary for the Isoc packet 31 transferred from the first DMAC 13 via the first DMA I / F 39a, and the header 31a is input in the order of input to the Isoc packet generation unit 42a. Forward. On the other hand, the FIFO 44b dedicated to the Isoc data stores only the Isoc data 31b to be transferred by the Isoc packet 31 transferred from the first DMAC 13 via the first DMA I / F 39a, and stores the Isoc data 31b to the Isoc packet generator 42a. Transfer in the order entered. The first DMAC 13 issues an instruction and outputs the instruction to the instruction analysis unit 43 via the first DMA I / F 39a. The instruction analysis unit 43 analyzes the instruction and outputs data necessary for generating the Isoc packet 31 to the Isoc packet generation unit 42a.

  The Isoc packet generator 42a generates an Isoc packet 31 for transmission from the header 31a from the Isoc header dedicated FIFO 44a and the Isoc data 31b from the Isoc data dedicated FIFO 44b based on the instruction data from the instruction analyzing unit 43. The Isoc packet generation unit 42a supplies the generated Isoc packet 31 for transmission to the CRC generation circuit 41a. The CRC generation circuit 41a generates an error correction code for the header 31a and the Isoc data 31b of the Isoc packet 31 from the Isoc packet generation unit 42a, and adds the generated error correction code to the header 31a and the Isoc data 31b, respectively. The Isoc packet 31 to which the error correction code is added is supplied to the link layer processing circuit 36.

  On the other hand, the Asyn packet processing circuit includes an error correction generation circuit (hereinafter referred to as a CRC generation circuit) 45a, an error correction check circuit (hereinafter referred to as a CRC check circuit) 45b, an Asyn packet generation unit 46a, an Asyn packet analysis unit 46b, and , And an instruction analysis unit 47. The Asyn transfer FIFO is composed of an Asyn header dedicated FIFO 48a and an Asyn data dedicated FIFO 48b.

  The CRC check circuit 45 b is supplied with the Asyn packet 32 for reception from the link layer processing circuit 36. The CRC check circuit 45b performs error correction processing on the receiving Asyn packet 32 for each of the header 32a and Asyn data 32b, removes the correction code, and sends the data of the receiving Asyn packet 32 to the Asyn packet analysis unit 46b. Supply. The analysis unit 46b separates the header 32a and the Asyn data 32b constituting the Asyn packet 32. The number of bytes in the header of the packet is fixed (8 bytes, of which 4 bytes are header information and the remaining 4 bytes are error correction codes), and the number of bytes of Asyn data can be found by looking at the transaction code in the header. Then, the separation process is performed by counting the number of bytes.

  The separated header 32a is supplied to the Asyn header dedicated FIFO 48a. The separated Asyn data 32b is supplied to the Asyn data dedicated FIFO 48b. Therefore, the Asyn header dedicated FIFO 48a stores only the header 32a, and the Asyn data dedicated FIFO 48b stores only the Asyn data 32b.

  The Asyn header dedicated FIFO 48a transfers the stored separated header 32a to the second DMAC 14 in order via the second DMA I / F 39b in the order of input. The Asyn data dedicated FIFO 48b transfers the stored separated Asyn data 32b to the second DMAC 14 in order via the second DMA I / F 39b in the order of input. Therefore, the second DMAC 14 inputs only the Asyn header 32a from the Asyn header dedicated FIFO 48a through the second DMA I / F 39b, and passes through the second DMA I / F 39b based on the transaction type, data length, address, etc. in the header 32a. Asyn data 32b of the FIFO 48b dedicated to Asyn data can be input.

  The Asyn header dedicated FIFO 48a stores only the header 32a necessary for the Asyn packet 32 transferred from the second DMAC 14 via the second DMA I / F 39b, and in the order in which the header 32a is input to the Asyn packet generator 46a. Forward. On the other hand, the Asyn data dedicated FIFO 48b stores only Asyn data 32b transferred by the Asyn packet 32 transferred from the second DMAC 14 via the second DMA I / F 39b, and stores the Asyn data 32b to the Asyn packet generator 46a. Transfer in the order entered. The second DMAC 14 issues an instruction and outputs the instruction to the instruction analysis unit 47 via the second DMA I / F 39b. The instruction analysis unit 47 analyzes this instruction and outputs data necessary for generating the Asyn packet 32 to the Asyn packet generation unit 46a.

  The Asyn packet generator 46 a generates an Asyn packet 32 for transmission from the header 32 a from the Asyn header dedicated FIFO 48 a and the Asyn data 32 b from the Asyn data dedicated FIFO 48 b based on the instruction data from the instruction analyzer 47. The Asyn packet generation unit 46a supplies the generated transmission Asyn packet 32 to the CRC generation circuit 45a. The CRC generation circuit 45a generates an error correction code for the header 32a and the Asyn data 32b of the Asyn packet 32 from the Asyn packet generation unit 46a, and adds the generated error correction code to the header 32a and the Asyn data 32b, respectively. The Asyn packet 32 to which the error correction code is added is supplied to the link layer processing circuit 36.

Next, the operation of the IPC 11 configured as described above will be described.
Now, when the image data becomes a plurality of reception Isoc packets 31 and is generated for each Isoc cycle, the Isoc packets 31a are sequentially supplied from the link layer processing circuit 36 to the CRC check circuit 41b. Each Isoc packet 31 is subjected to error correction processing for each header 31a and Isoc data 31b in the CRC check circuit 41b, and then the correction code is removed and supplied to the Isoc packet analysis unit 42b. Each Isoc packet 31 is separated into a header 31a and an Isoc data 31b constituting the Isoc packet 31 by the analysis unit 42b, the header 31a is supplied with the FIFO 44a dedicated to the Isoc header, and the Isoc data 31b is supplied to the FIFO 44b dedicated to the Isoc data .

  The header 31a of each Isoc packet 31 stored in the Isoc header dedicated FIFO 44a is sequentially read out by the first DMAC 13 via the first DMA I / F 39a. The first DMAC 13 sequentially reads the Isoc data 31b of each Isoc packet 31 of the Isoc data dedicated FIFO 44b via the first DMA I / F 39a based on the transaction type, data length, address and the like in the header 31a. Then, the first DMAC 13 performs data processing using the Isoc data 31b of each packet 31 continuously read from the Isoc data dedicated FIFO 44b as one image data.

  Next, when the image data is output from the first DMAC 13 as a plurality of Isoc data 31 for transmission, each of the Isoc data 31 for transmission is stored via the first DMA I / F 39a via the FIFO 44b dedicated to Isoc data. Is done. On the other hand, the first DMAC 13 stores the header 31a necessary for converting the Isoc data 31a transferred from the first DMAC 13 into the Isoc packet 31 to the Isoc header dedicated FIFO 44a via the first DMA I / F 39a. Further, the first DMAC 13 outputs an instruction to the instruction analysis unit 43 via the first DMA I / F 39a. The instruction analysis unit 43 outputs data necessary for generating the Isoc packet 31 based on the instruction to the Isoc packet generation unit 42a.

  The Isoc packet generation unit 42a generates an Isoc packet 31 for transmission from the header 31a from the Isoc header dedicated FIFO 44a and the Isoc data 31b from the Isoc data dedicated FIFO 44b based on the instruction data. The Isoc packet 31 for transmission generated by the Isoc packet generation unit 42a is supplied to the CRC generation circuit 41a. The Isoc packet 31 for transmission is supplied to the link layer processing circuit 36 after the CRC generation circuit 41a adds an error correction code to the header 31a and the Isoc data 31b.

  The reception Asyn packet 32 is also operated by the CRC check circuit 45b, the Asyn packet analysis unit 46b, the Asyn header dedicated FIFO 48a, and the Asyn data dedicated FIFO 48b in the same manner as the reception Isoc packet 31 described above. The Asyn data 32b of the packet 32 is supplied to the second DMAC 14.

  The Asyn data 32b output from the second DMAC 14 is operated by the CRC generation circuit 45a, the Asyn packet generation unit 46a, the Asyn header dedicated FIFO 48a, and the Asyn data dedicated FIFO 48b in the same manner as the reception Isoc data 31b. Asyn packet 32 is generated.

Next, features of the IPC 11 configured in the fourth embodiment as described above will be described below.
(1) In the present embodiment, the reception Isoc packet 31 is separated into the header 31a and the Isoc data 31b, and the header 31a is stored in the Isoc header dedicated FIFO 44a and the Isoc data 31b is stored in the Isoc data dedicated FIFO 44b. . Then, the first DMAC 13 reads the transaction type, data length, address and the like in the header 31a of each Isoc packet 31 of the FIFO 44a dedicated FIFO 44a. The first DMAC 13 sequentially reads the Isoc data 31b of each Isoc packet 31 of the Isoc data dedicated FIFO 44b via the first DMA I / F 39a based on the transaction type, data length, address, and the like.

  Accordingly, since the first DMAC 13 continuously reads the Isoc data 31b of each packet 31 from the Isoc data dedicated FIFO 44b, the header 31a is removed as in the conventional case when processing the Isoc data 31b as one image data. Then, the process of combining is performed. Therefore, since there is no processing for removing the header 31a as in the prior art, the load of the first DMAC 13 is reduced by that much and the time of the combining processing operation is shortened. As a result, the Isoc packet 31 for transferring image data such as a moving image that requires continuity can ensure continuous transfer and real-time transfer, and guarantee the reproduction of a realistic moving image.

Similarly, in the second DMAC 14, since the Asyn data 32b of each packet 32 is continuously read from the Asyn data dedicated FIFO 48b, the load is reduced accordingly.
(2) In the present embodiment, the Isoc data 31b for transmission is stored in the FIFO 44b dedicated to Isoc data, and the header 31a for the Isoc packet 31 is stored in the FIFO 44a dedicated to Isoc header. The first DMAC 13 outputs an instruction for making the Isoc data 31 a for transmission into the Isoc packet 31 to the instruction analysis unit 43. The instruction analysis unit 43 outputs data necessary for generating the Isoc packet 31 to the Isoc packet generation unit 42a. The Isoc packet generation unit 42a generates a transmission Isoc packet 31 from the header 31a of the Isoc header dedicated FIFO 44a and the Isoc data 31b of the Isoc data dedicated FIFO 44b based on the instruction data. The CRC generation circuit 41 a adds an error correction code to the transmission Isoc packet 31 generated by the Isoc packet generation unit 42 a and supplies the error correction code to the link layer processing circuit 36. Accordingly, since the first DMAC 13 generates the packet 31 of the Isoc data 31b in the IPC 11, the load is reduced accordingly.

Similarly, since the second DMAC 14 generates the packet 32 of the Asyn data 32b in the IPC 11, the load is reduced accordingly.
(Fifth embodiment)
FIG. 10 shows a block circuit showing a circuit configuration of the IPC 11 according to the fifth embodiment. The IPC 11 includes an IEEE1394 interface (IEEE1394 I / F) 51, a physical layer processing circuit 52, a link layer processing circuit 53, an error correction code generation circuit (CRC generation circuit) 54a, an error correction check circuit (CRC check circuit) 54b, The packet generation unit 55a, the packet analysis unit 55b, the instruction analysis unit 56, a header dedicated FIFO 57a, a data dedicated FIFO 57b, and an MPU interface (MPUI / F) 59 are configured.

  The IEEE 1394 I / F 51 is connected to the digital VTR 2 and the color page printer 3 via the IEEE 1394 bus 5 and is connected to the IP V of the digital VTR 2 and to the IPC of the color page printer 3. Asyn packet 32 is exchanged. The physical layer processing circuit 52 inputs the Isoc packet 31 and the Asyn packet 32 received by the IEEE1394 I / F 51 and supplies them to the link layer processing circuit 53. The link layer processing circuit 53 determines whether the packet is addressed to itself (personal computer 1) based on the contents of the headers 31a, 32a attached to the heads of the packets 31, 32. Is supplied to the CRC check circuit 54b. If the packet is not addressed to itself, the link layer processing circuit 53 sends the packets 31 and 32 via the physical layer processing circuit 52 and the IEEE1394 I / F 51 to the destination digital VTR 2, color page printer 3, or Transmit to the digital video camera 4.

  Further, the physical layer processing circuit 52 inputs the transmission Isoc packet 31 and the transmission Asyn packet 32 from the link layer processing circuit 53. The physical layer processing circuit 52 sends the Isoc packet 31 and Asyn packet 32 via the first or second 1394 I / F 26a, 26b to the destination digital VTR 2, color page printer 3, or digital video camera 4. Send to.

  The link layer processing circuit 53 inputs the Isoc packet 31 and the Asyn packet 32 received from the physical layer processing circuit 52. The link layer processing circuit 53 supplies the received Isoc packet 31 and Asyn packet 32 to the CRC check circuit 54b.

  The link layer processing circuit 53 is supplied with the Isoc packet 31 and Asyn packet 32 for transmission from the CRC generation circuit 54a. The link layer processing circuit 53 supplies the Isoc packet 31 and Asyn packet 32 for transmission to the physical layer processing circuit 52.

  The CRC check circuit 54 b is supplied with the Isoc packet 31 and Asyn packet 32 for reception from the link layer processing circuit 53. The CRC check circuit 54b performs error correction processing for the reception Isoc packet 31 and Asyn packet 32 for each of the headers 31a and 32a and the data 31b and 32b, removes the correction code, and sends the packet analysis unit 55b for reception. The data of the packets 31 and 32 is supplied. The analysis unit 55b separates the headers 31a and 32a and the data 31b and 32b constituting the packets 31 and 32 as in the fourth embodiment.

  The separated headers 31a and 32a are supplied to the header dedicated FIFO 57a. The separated data 31b and 32b are supplied to the data dedicated FIFO 57b. Accordingly, the header dedicated FIFO 57a stores only the headers 31a and 32a, and the data dedicated FIFO 57b stores only the data 31b and 32b.

  The header dedicated FIFO 57a sequentially transfers the stored separated headers 31a, 32a to the MPU 12 via the MPUI / F 58 in the order of input. The data dedicated FIFO 57b sequentially transfers the stored separated data 31b and 32b to the MPU 12 via the MPUI / F 58 in the order of input. Therefore, the MPU 12 inputs only the headers 31a and 32a from the header dedicated FIFO 57a via the MPUI / F 58, and the data via the MPUI / F 58 based on the transaction type, data length, address, etc. in the headers 31a and 32a. Data 31b and 32b of the dedicated FIFO 57b can be input.

  The header dedicated FIFO 57a stores only the headers 31a and 32a necessary for the Isoc packet 31 and the Asyn packet 32 transferred from the MPU 12 via the MPUI / F 58, and inputs the headers 31a and 32a to the packet generation unit 55a. Transfer in order. On the other hand, the data dedicated FIFO 57b stores only the Isoc packet 31 and Asyn data 32b transferred by the Isoc packet 31 and Asyn packet 32 transferred from the MPU 12 via the MPUI / F 58, and generates the data 31b and 32b as a packet. The data are transferred in the order input to the unit 55a. The MPU 12 issues an instruction and outputs the instruction to the instruction analysis unit 56 via the MPUI / F 58. The instruction analysis unit 56 analyzes this instruction and outputs data necessary for generating the Isoc packet 31 and the Asyn packet 32 to the packet generation unit 55a.

  The packet generation unit 55a generates transmission packets 31 and 32 from the headers 31a and 32a from the header dedicated FIFO 57a and the data 31b and 32b from the data dedicated FIFO 57b based on the instruction data from the instruction analysis unit 56. The packet generation unit 55a supplies the generated transmission packets 31 and 32 to the CRC generation circuit 54a. The CRC generation circuit 54a generates error correction codes for the headers 31a and 31a and the data 31b and 32b of the packets 31 and 32, and adds the generated error correction codes to the headers 31a and 32a and the data 31b and 32b, respectively. The transmission packets 31 and 32 to which the error correction code is added are supplied to the link layer processing circuit 53.

Next, the operation of the IPC 11 configured as described above will be described.
Now, when image data becomes a plurality of reception Isoc packets 31 and is generated for each Isoc cycle, the Isoc packets 31 are sequentially supplied from the link layer processing circuit 53 to the CRC check circuit 54. Each Isoc packet 31 is subjected to error correction processing for each header 31a and Isoc data 31b in the CRC check circuit 54b, and then the correction code is removed and supplied to the packet analysis unit 55b. In each Isoc packet 31, the analysis unit 55b separates the Isoc packet 31 into a header 31a and an Isoc data 31b, supplies the header 31a to the header dedicated FIFO 57a, and supplies the Isoc data 31b to the data dedicated FIFO 57b.

  The header 31a of each Isoc packet 31 stored in the header dedicated FIFO 57a is sequentially read out by the MPU 12 via the MPUI / F 58. The MPU 12 sequentially reads the Isoc data 31b of each Isoc packet 31 from the data dedicated FIFO 57b via the MPUI / F 58 based on the transaction type, data length, address, etc. in the header 31a. Then, the MPU 12 performs data processing using the Isoc data 31b of each packet 31 read continuously from the data dedicated FIFO 57b as one image data.

  Next, when the image data is output from the MPU 12 as a plurality of Isoc data 31 for transmission, each Isoc data 31 for transmission is stored via the MPUI / F 58 via the data dedicated FIFO 57b. On the other hand, the MPU 12 stores the header 31 a necessary for making the Isoc data 31 a transferred from the MPU 12 into the Isoc packet 31 in the header dedicated FIFO 57 a via the MPUI / F 58. Further, the MPU 12 outputs an instruction to the instruction analysis unit 56 via the MPUI / F 58. The instruction analysis unit 56 outputs data necessary for generating the packet 31 based on the instruction to the packet generation unit 42a.

  Based on the instruction data from the instruction analysis unit 56, the packet generation unit 55a generates a transmission Isoc packet 31 from the header 31a from the header dedicated FIFO 57a and the Isoc data 31b from the data dedicated FIFO 57b. The Isoc packet 31 for transmission generated by the Isoc packet generation unit 42a is supplied to the CRC generation circuit 41a. The Isoc packet 31 for transmission is supplied to the link layer processing circuit 36 after the CRC generation circuit 54a adds an error correction code to the header 31a and the Isoc data 31b.

  Note that the reception Asyn packet 32 is similar to the above-described reception Isoc packet 31, and the CRC check circuit 54b, the packet analysis unit 55b, the header dedicated FIFO 57a, and the data dedicated FIFO 57b operate, and the Asyn packet 32 Asyn data 32b is supplied to the MPU 12.

  Also, the Asyn data 32b output from the MPU 12 is the same as the Isoc data 31b for reception, and the Asyn packet 32 is generated by the operation of the CRC generation circuit 54a, the packet generation unit 55a, the header dedicated FIFO 57a, and the data dedicated FIFO 57b. Is generated.

Next, the characteristics of the IPC 11 configured in the fifth embodiment as described above will be described below.
(1) In this embodiment, the receiving packets 31 and 32 are separated into headers 31a and 32a and data 31b and 32b, the headers 31a and 32a are assigned to the header dedicated FIFO 57a, and the data 31b and 32b are transferred to the data dedicated FIFO 57b. Stored. Then, the MPU 12 reads the transaction type, data length, address, and the like in the headers 31a and 32a of each packet 31 of the header dedicated FIFO 57a. The MPU 12 reads the data 31b of each packet 31 and 32 of the data dedicated FIFO 57b in order based on the transaction type, data length, address, and the like.

  Accordingly, for example, since the Isoc data 31b of each packet 31 is continuously read from the data-dedicated FIFO 57b, the MPU 12 removes the header 31a as before when processing the Isoc data 31b as one image data. Process to compose. Therefore, since there is no processing for removing the header 31a as in the prior art, the load on the MPU 12 is reduced by that much and the time for the synthesis processing operation is shortened. As a result, the Isoc packet 31 for transferring image data such as a moving image that requires continuity can ensure continuous transfer and real-time transfer, and guarantee the reproduction of a realistic moving image.

  Similarly, for the packet 32 in the Asyn transfer mode, the MPU 12 similarly reduces the load because the Asyn data 32b of each packet 32 has been continuously read from the data dedicated FIFO 57b.

  (2) In this embodiment, the transmission data 31b and 32b are stored in the data dedicated FIFO 57b, and the headers 31a and 32a for the packets 31 and 32 are stored in the header dedicated FIFO 57a. The MPU 12 transmits data 31b. Instructions for making 32b into packets 31 and 32 are output to the instruction analysis unit 56. The instruction analysis unit 56 outputs data necessary for generating the packet 55 to the packet generation unit 55a. The packet generator 55a generates transmission packets 31 and 32 from the headers 31a and 32a of the header dedicated FIFO 57a and the data 31b and 32b of the data dedicated FIFO 57b based on the data. The CRC generation circuit 54 a adds an error correction code to the transmission packets 31 and 32 and supplies the packet to the link layer processing circuit 36. Accordingly, since the MPU 12 generates the packet 31 of the data 31b and 32b by the IPC 11 only by transferring the data 31 and 32, the load is reduced accordingly.

The system block diagram using the IEEE1394 bus of 1st Embodiment. The block circuit diagram for demonstrating the structure in a personal computer. The block circuit diagram for demonstrating the protocol controller for IEEE1394. Explanatory drawing for demonstrating the effect | action of 1st Embodiment. The block circuit diagram for demonstrating the protocol controller for IEEE1394 in 2nd Embodiment. Explanatory drawing for demonstrating the effect | action of 2nd Embodiment. The block circuit diagram for demonstrating the protocol controller for IEEE1394 in 3rd Embodiment. Explanatory drawing for demonstrating the effect | action of 3rd Embodiment. The principal part block circuit diagram for demonstrating the protocol controller for IEEE1394 in 4th Embodiment. The block circuit diagram for demonstrating the protocol controller for IEEE1394 in 5th Embodiment. FIG. 6 is a block circuit diagram for explaining an outline of a conventional IEEE1394 protocol controller. Explanatory drawing for demonstrating the effect | action of the conventional protocol controller for IEEE1394.

Explanation of symbols

1 Personal computer
2 Digital VTR
3 Color page printer 4 Digital video camera 5 IEEE1394 bus 11 IEEE1394 protocol controller (IPC)
12 Microprocessor unit 13 First DMA controller (first DMAC)
14 Second DMA controller (second DMAC)
20 Physical layer processing circuit 21 Link layer processing circuit 22a, 22b First and second transmission packet processing circuits 23a, 23b First and second received packet processing circuits 24a-24d First to fourth storage memories (first to fourth FIFOs) )
26a, 26b First and second 1394 I / F
27a Isochronous data transmission interface (Isoc transmission I / F)
28a Isochronous data reception interface (Isoc reception I / F)
27b Asynchronous data transmission interface (Asyn transmission I / F)
28b Asynchronous data reception interface (Asyn reception I / F)
29 MPU interface (MPUI / F)
31 Isoc packet 31a Header 31b Isochronous data (Isoc data)
32 Asyn packet 32a Header 32b Asynchronous data (Asyn data)

Claims (37)

Receiving the first transfer data transferred in the first transfer mode at regular intervals with the external device, and storing the first transfer data in the first transfer data storage memory;
The second transfer data transferred in the second transfer mode in which the data transfer is performed at a time when the data transfer in the first transfer mode is not performed is received and stored in the second transfer data storage memory. And
Reading the first transfer data stored in the first transfer data storage memory from the first interface;
A data processing method, wherein the second transfer data stored in the second transfer data storage memory is read from a second interface. Receiving the first transfer data transferred in the first transfer mode at regular intervals with the external device, and storing the first transfer data in the first transfer data storage memory;
The second transfer data transferred in the second transfer mode in which the data transfer is performed at a time when the data transfer in the first transfer mode is not performed is received and stored in the second transfer data storage memory. And
Transferring the first transfer data stored in the first transfer data storage memory to the internal device via the first interface;
A data processing method comprising: transferring second transfer data stored in the second transfer data storage memory to an internal device via a second interface. The first transfer data transferred in the first transfer mode at a certain period between the external device and the first transfer data is stored in the first transfer data storage memory via the first interface and then transmitted.
The second transfer data transferred in the second transfer mode in which data transfer is performed at a time when the data transfer in the first transfer mode is not performed is transferred to the second transfer data via the second interface. A data processing method comprising: transmitting data after storing in a storage memory. 3. The data processing method according to claim 2, wherein the first transfer data for reception read from the first transfer data storage memory is transferred to the internal device via the first interface, and the internal data is transferred to the internal device. First transfer data for transmission from the apparatus is stored in the first transfer data storage memory via the first interface, and the first transfer data for transmission is set to the first transfer mode. To the external device,
The second transfer data for reception read from the second transfer data storage memory is transferred to the internal device via the second interface, and the second transfer data for transmission from the internal device. Is stored in the second transfer data storage memory via the second interface, and the second transfer data for transmission is transferred to the external device in the second transfer mode. Data processing method. 5. The data processing method according to claim 1, wherein the first transfer data storage memory and the second transfer data storage memory include a plurality of storage memories. 6. Data processing method. 6. The data processing method according to claim 1, wherein the first transfer data storage memory includes a reception memory and a transmission memory. . 7. The data processing method according to claim 1, wherein the second transfer data storage memory includes a reception memory and a transmission memory. . 8. The data processing method according to claim 1, wherein the first interface includes a reception interface and a transmission interface. 9. The data processing method according to claim 1, wherein the second interface includes a reception interface and a transmission interface. The data processing method according to any one of claims 1 to 9, wherein control data stored in a third memory is used. The data processing method according to any one of claims 1 to 10, wherein the second interface also serves as an interface to a processor. 12. The data processing method according to claim 1, wherein the first transfer data is supplied to a first DMA. The data processing method according to any one of claims 1 to 12, wherein the second transfer data is supplied to a second DMA. 14. The data processing method according to claim 1, wherein the first transfer mode is an isochronous transfer mode and the second transfer mode is an asynchronous transfer mode. A characteristic data processing method. A first transfer data storage memory for receiving and storing the first transfer data transferred in the first transfer mode at regular intervals with the external device;
  For second transfer data for receiving and storing second transfer data transferred in the second transfer mode in which data transfer is performed at a time when data transfer in the first transfer mode is not performed Storage memory;
  A first interface for transferring the first transfer data read from the first transfer data storage memory;
  A second interface for transferring the second transfer data read from the second transfer data storage memory;
A data processing apparatus comprising: A first transfer data storage memory for receiving and storing the first transfer data transferred in the first transfer mode at regular intervals with the external device;
  For second transfer data for receiving and storing second transfer data transferred in the second transfer mode in which data transfer is performed at a time when data transfer in the first transfer mode is not performed Storage memory;
  A first interface for transferring the first transfer data read from the first transfer data storage memory to an internal device;
  A second interface for transferring the second transfer data read from the second transfer data storage memory to an internal device;
A data processing apparatus comprising: A first interface for receiving first transfer data transferred in a first transfer mode at regular intervals with an external device;
  A first transfer data storage memory for storing the first transfer data from the first interface;
  A second interface for receiving second transfer data transferred in a second transfer mode in which data transfer is performed at a time when data transfer is not performed in the first transfer mode;
  A second transfer data storage memory for storing the second transfer data from the second interface;
A data processing apparatus comprising: 18. The data processing apparatus according to claim 15, wherein the first transfer data storage memory and the second transfer data storage memory include a plurality of storage memories. Data processing device. 19. The data processing device according to claim 15, wherein the first transfer data storage memory includes a reception memory and a transmission memory. . 20. The data processing device according to claim 15, wherein the second transfer data storage memory includes a reception memory and a transmission memory. . 21. The data processing device according to claim 15, wherein the first interface includes a reception interface and a transmission interface. The data processing apparatus according to any one of claims 15 to 21, wherein the second interface includes a reception interface and a transmission interface. 23. The data processing device according to claim 15, further comprising a third memory for storing control data. 24. The data processing apparatus according to claim 15, wherein the second interface also serves as an interface to a processor. 25. The data processing apparatus according to claim 15, further comprising a first DMA to which the first transfer data is supplied. 26. The data processing device according to claim 15, further comprising a second DMA to which the second transfer data is supplied. 27. The data processing apparatus according to claim 15, wherein the first transfer mode is an isochronous transfer mode, and the second transfer mode is an asynchronous transfer mode. Characteristic data processing device. A data processing device provided between an internal device and an external device,
  The first transfer data for reception read out from the first transfer data storage memory in which the first transfer data transferred in the first transfer mode at a certain period is stored is transferred to the internal device. And a first interface for storing the first transfer data for transmission from the internal device in the first transfer data storage memory;
  Reading from the second transfer data storage memory storing the second transfer data transferred in the second transfer mode in which the data transfer is performed at a time when the data transfer in the first transfer mode is not performed A second interface for transferring the second transfer data for reception to the internal device and storing the second transfer data for transmission from the internal device in the second transfer data storage memory When
A data processing apparatus comprising: 29. The data processing device according to claim 28, wherein the first transfer data storage memory includes a first reception transfer data storage memory for storing the reception first transfer data, and the transmission data. And a first transmission transfer data storage memory for storing the first transfer data. 30. The data processing device according to claim 28, wherein the second transfer data storage memory is a second reception transfer data storage memory for storing the second transfer data for reception. And a second transmission transfer data storage memory for storing the second transmission data for transmission. 31. The data processing device according to claim 28, wherein the first interface includes a first reception interface and a first transmission interface. apparatus. 32. The data processing device according to claim 28, wherein the second interface includes a second reception interface and a second transmission interface. apparatus. 33. A data processing apparatus according to claim 28, further comprising a third memory for storing control data. 34. The data processing apparatus according to claim 28, wherein the second interface also serves as an interface to a processor. 35. The data processing apparatus according to any one of claims 28 to 34, further comprising a first DMA to which the first transfer data is supplied. 36. The data processing apparatus according to any one of claims 28 to 35, further comprising a second DMA to which the second transfer data is supplied. 37. The data processing device according to claim 28, wherein the first transfer mode is an isochronous transfer mode, and the second transfer mode is an asynchronous transfer mode. Characteristic data processing device.

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