JP4229744B2 - Image processing apparatus, image processing method, and color image forming apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to an image processing apparatus and an image processing method.,In particular, the present invention relates to an image processing apparatus and an image processing method, in which image data is encoded, temporarily stored in a memory, and then decoded.,And a color image forming apparatus.
[0002]
[Prior art]
FIG. 50 is a schematic configuration diagram of a conventional Tandham type copying machine. In the copying machine shown in the figure, the RGB data of the document read by the scanner 602 is subjected to smoothing filter processing such as image processing such as shading correction and MTFγ correction by the smoothing filter processing device 602. Thereafter, the encoding device 604 performs encoding using a multi-value image compression algorithm (JPEG or the like) and stores the encoded data in the memory 605. Then, at the time of printout, the data is delayed for each plate, the code data is read from the memory 605 by the decoding devices 606C-K, and is decoded into RGB data by the above-described compression algorithm. The image processing devices 607C to 607K perform color conversion processing to convert the data into CMYK data, and then perform gradation processing to convert the data into binary, quaternary, or 8-value. The image processing apparatuses 607C to 607K transfer only the data corresponding to the C, M, Y, and K plates after gradation processing to the 8-line memories 608C to 608K and temporarily store them, and the C to K printer controller 609C. -K transfer C, M, Y, and K data stored in the 8-line memories 608C-K to the C-K printer engines 610C-K. As described above, the conventional Tandham type copying machine has a decoding device and an image processing device dedicated to each plate.
[0003]
As a compression method of image data, there is a method of converting image data into frequency components by orthogonal transformation such as DCT (Discrete Cosine Transform) and quantizing the conversion coefficient. In particular, as a method for encoding a multi-value image using DCT, a JPEG method standardized by ITU-T and ISO is known.
[0004]
The above-described tandem type copier has a decoding processing device dedicated to each version, and variable-length code data such as JPEG is sequentially decoded with a delay for each version. However, in such a configuration, since the variable length code cannot be read in the middle, a decoding processor for each version is required, and thus a large number of gates is required.
[0005]
In the case of the JPEG system, since the block of image data to be encoded is 8 × 8 pixels, as shown in FIG. 50, an 8-line line memory for storing image data after decoding is required. . As a result, when the line memory is built in the ASIC or the like, a large area is required, and when the line memory is provided outside the ASIC, there is a problem that the cost is increased.
[0006]
For example, as a method of reducing the 8-line memory of FIG. 50, a method of compressing in units of blocks that are long in the horizontal direction is conceivable. In such a method, vertical processing is performed to remove only high-frequency components in the horizontal direction by quantization processing. Only the edge of the direction appears clearly, and the image quality deteriorates.
[0007]
By the way, in the JPEG system, it is possible to insert RSTm (restart marker) which is a marker code to be inserted at every interval (restart interval) specified by DRI (restart interval definition marker). Immediately after the marker code, the predicted value of the DC coefficient in the DCT method is reset. Normally, this restart marker is mainly used for the purpose of recovery from a decoding error due to a transmission error. As an image processing apparatus using a restart marker, for example, Patent Document 1 and Patent Document 2 are known.
[0008]
[Patent Document 1]
JP 2000-083214 A
[Patent Document 2]
JP 2002-262099 A
[0009]
[Problems to be solved by the invention]
  The present invention has been made in view of the above, and an image processing apparatus capable of reducing the capacity of a line memory for storing decoded image data to make the hardware configuration small and inexpensive. Image processing method,Another object of the present invention is to provide a color image forming apparatus.
[0010]
[Means for Solving the Problems]
  In order to solve the above-mentioned problem, an invention according to claim 1 is an image processing apparatus, wherein the input image data is divided into blocks each composed of a plurality of pixels, and the block unit divided by the dividing unit is used. An encoding unit that performs an encoding process on the image data, a storage unit that stores the code data that the encoding unit has performed the encoding process, and a decoding process that is performed on the code data stored by the storage unit in units of blocks And decoding means for decoding the image data and sending the decoded image data in units of a predetermined pixel line.The decoding means determines the end of the block line by reading the restart marker inserted for each block line of the code data stored in the storage means, and is the same if it is determined not to be the end of the block line The code data of the block line is read again from the storage means and subjected to decoding processing.It is characterized by that.
[0014]
  Claims2The invention according to claim1The invention is characterized in that the encoding means performs a JPEG compression process on the image data, and the decoding means performs a JPEG expansion process.
[0016]
  Claims3The invention according to claim1In the present invention, the decoding means includes a judging means for judging whether or not a restart marker is added to the code data, and when the judgment result of the judging means is negative, The code data is read out from the storage means and subjected to decoding processing until the judgment means judges that the restart marker is added.
[0019]
  Claims4The invention according to claim 1 to claim 13In the invention according to any one of the above, the predetermined pixel line unit is one pixel line unit or two pixel line units.
[0022]
  Claims5The invention according to claim 1 to claim 14The image processing apparatus according to any one of the above is applied to a color image forming apparatus.
[0023]
  Claims6According to another aspect of the present invention, there is provided an image processing method, a division step of dividing input image data into blocks each including a plurality of pixels, and a code for performing an encoding process on the image data in units of blocks divided in the division step. An encoding step, a storage step for storing code data encoded in the encoding step in a memory, and a decoding process for the code data stored in the memory in the storage step in units of blocks. A decoding step of decoding the image data and sending the decoded image data in units of predetermined pixel lines.The decoding step determines the end of the block line by reading the restart marker inserted for each block line of the code data stored in the memory, and if it is not the end of the block line, the same block The code data of the line is read again from the storage means and subjected to decoding processing.It is characterized by that.
[0027]
  Claims7The invention according to claim6According to the invention, in the decoding step, the image data is subjected to JPEG compression processing, and in the decoding step, JPEG expansion processing is performed.
[0029]
  Claims8The invention according to claim6In the invention according to the invention, the decoding step includes a determination step of determining whether or not a restart marker is added to the code data, and when the determination result in the determination step is negative, Reading the code data of the block from the memory and performing the decoding process on the code data are repeated until it is determined in the determination step that the restart marker is added.
[0032]
  Claims9The invention according to claim6~ Claim8In the invention according to any one of the above, the predetermined pixel line unit is one pixel line unit or two pixel line units.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, with reference to the drawings, an image processing apparatus and an image processing method according to the present invention will be described.,A preferred embodiment of the color image forming apparatus will be described in detail in the order of (Embodiment 1), (Embodiment 2), and (Embodiment 3).
[0035]
(Embodiment 1)
The image processing apparatus according to the first embodiment will be described with reference to FIGS. In the first embodiment, a case where the image processing apparatus is applied to a 4-drum type digital color copying machine will be described as an example.
[0036]
[Mechanical configuration of image processing device]
FIG. 1 is a cross-sectional view illustrating a schematic mechanical configuration of the image processing apparatus according to the first embodiment. The image processing apparatus shown in FIG. 1 has a structure in which a scanner unit 1 is arranged at the top, a large-capacity paper feeding device 2 with casters at the bottom, and a printer unit 3 at the center. The scanner unit 1 includes a lamp 5 that scans and illuminates a document on the document table 4, first, second, and third mirrors 6, 7 and 8, an imaging lens 9, a dichroic prism 10, and a red light receiver (CCD). 11R, a green light receiver 11G, a blue light receiver 11B, and the like.
[0037]
In such a configuration, the reflected light from the original when irradiated by the lamp 5 is reflected by the first, second, and third mirrors 6, 7, and 8 and enters the imaging lens 9. The image light is imaged on the dichroic prism 10 by the imaging lens 9, and is split into, for example, light of three types of wavelengths of red (R), green (G), and blue (B). It is incident on the photoreceiver 11G and the blue photoreceiver 11B.
[0038]
Each CCD (light receiver) 11R, 11G, 11B converts the incident light into a digital signal and outputs the digital signal, and the output is subjected to necessary processing in an image processing unit (not shown) to record recording color information of each color, For example, it is converted into a recording formation signal of each color of black (Bk), yellow (Y), magenta (M), and cyan (C). Signals Y, M, C, and Bk for each color from the image processing unit are input to the printer unit 3 and sent to the laser beam emitting devices 12Y, 12M, 12C, and 12Bk corresponding to the respective colors.
[0039]
In the example of FIG. 1, four sets of recording devices (image forming stations) 13Y, 13M, 13C, and 13Bk are arranged in the printer unit 3 side by side. The recording device 13 (13Y, 13M, 13C, 13Bk) includes a photosensitive drum 14 (14Y, 14M, 14C, 14Bk) in addition to the laser beam emitting device 12 (12Y, 12M, 12C, 12Bk).
[0040]
The photosensitive drum 14 includes a charging charger 15 (15Y, 15M, 15C, 15Bk), a developing device 16 (16Y, 16M, 16C, 16Bk), a transfer charger 17 (17Y, 17M, 17C, 17Bk), a cleaning device, A static eliminator and the like are provided in the same manner as a known copying apparatus.
[0041]
Further, a transfer belt 21 is stretched below the four photosensitive drums 14Y, 14M, 14C, and 14Bk arranged horizontally, and each of the transfer chargers 17Y, 17M, 17C, and 17Bk has a loop shape. Arranged inside the transfer belt 21.
[0042]
A two-stage sheet feeding unit 19 is provided on the right side of the printer unit 3, and a fixing roller 22 is provided in the vicinity of the downstream portion of the transfer belt 21. Further, a paper discharge roller 23 is provided on the downstream side. In the printer unit 3 having such a configuration, the photosensitive drum 14 uniformly charged by the charging charger 15 forms a latent image of each color light image by exposure by the laser light emitting device 12 as writing means. This latent image is developed by the developing device 16 to form a visible image.
[0043]
The transfer paper fed from the paper feed unit 19, for example, one of the two paper feed cassettes, is fed by the registration roller 20 by the paper feed roller 18, and sent to the transfer belt 21 at the same timing. The transfer paper conveyed by the transfer belt 21 is sequentially fed to the photosensitive drums 14Bk, 14C, 14M, and 14Y on which the visible images are formed, and the visible images are transferred under the action of the transfer chargers 17Bk, 17C, 17M, and 17Y. Is done. The transferred transfer paper is fixed by the fixing roller 22 and discharged by the paper discharge roller 23. Note that the transfer paper can be accurately conveyed at the speed of the transfer belt 21 by being electrostatically attracted to the transfer belt 21.
[0044]
[Hardware configuration of image processing apparatus]
FIG. 2 is a block diagram showing a hardware configuration of the image processing apparatus of FIG. As shown in FIG. 2, the image processing apparatus includes a CPU 101, a CPU_I / F 102, a memory controller 103, a main memory 104, a local I / F 105, a ROM 106, a panel controller 107, a panel 108, and a scanner 109. The smoothing filter processing device 110, the encoding device 111, the decoding devices 112C-K, the C-K plate image processing devices 113C-K, the one-line memories 114C-K, and the C-K plate engine controller 115C. To K and C to K version printer engines 116C to 116K.
[0045]
In the above configuration, since one line memory is used as the line memory, the encoding device 111, the smoothing filter processing device 110, the decoding devices 112C to 112K, the C to K plate image processing device 113, and one line are used. The memories 114C to K, the C to K version engine controllers 115C to K, and the like can be integrated into one chip by an LSI such as an ASIC.
[0046]
The CPU 101 controls the entire image processing apparatus according to programs stored in the ROM 106 and the main memory 104. The CPU_I / F 102 is connected between the CPU 101 and the memory controller 103 and processes an I / F between the CPU 101 and the memory controller 103. The memory controller 103 controls reading / writing of the main memory 104, and controls data transfer between the CPU 101, the local I / F 105, the decoding devices 112 </ b> C to 112 </ b> K, the encoding device 111, and the main memory 104.
[0047]
The main memory 104 stores image data read by the scanner 109, a program to be executed by the CPU 101, various data, and the like. FIG. 3 is a diagram illustrating an example of the format of the main memory 104. As shown in FIG. 3, the main memory 104 includes a code page memory area 104a for storing a plurality of pages of encoded data for one page, a program area 104b for storing various programs of the CPU 101, and the like. FIG. 4 is a diagram showing an example of the format of one page of code data stored in the code page memory area 104a of FIG. In the code page memory area 104a, as shown in FIG. 4, code data is stored in units of blocks with 8 × 8 pixels of image data as one block, and a restart marker (RSTm) is provided at the end of each block line. Added.
[0048]
The local I / F 105 processes I / Fs such as the ROM 106, the panel controller 107, the CPU 101, and the main memory 104. The ROM 106 stores programs executed by the CPU 101 and font information such as characters. The panel controller 107 controls the panel 108. The panel 108 notifies the CPU 101 of an operation from the user.
[0049]
The scanner 109 optically reads a color document to be copied and transfers multi-value RGB data for one page to the smoothing filter processing device 110. The smoothing filter processing device 110 performs smoothing filter processing on the RGB data input from the scanner 109 and transfers it to the encoding device 111. The encoding device 111 encodes the smoothed filter-processed image data input from the smoothing filter-processing device 110, transfers the encoded code data to the main memory 104 via the memory controller 103, and the code page. Store in the memory area 104a.
[0050]
The decoding devices 112 </ b> C to 112 </ b> K read and decode the code data stored in the code page memory area 104 a of the main memory 104 via the memory controller 103, and the decoded RGB data is a C to K version image processing device. Transfer to 113C-K, respectively.
[0051]
The C to K image processing apparatuses 113C to 113K perform color conversion processing and gradation processing on the C, M, Y, and K data respectively decoded by the C, M, Y, and K version decoding apparatuses 112C to K. The C, M, Y, and K data after the gradation processing are sequentially transferred and stored in the one-line memories 114C to 114K in a predetermined pixel unit (for example, 8 pixels) of one pixel line.
[0052]
The one-line memories 114C to 114K store C, M, Y, and K data for one line subjected to gradation processing, respectively. The C to K version engine controllers 115C to 115K sequentially read C, M, Y, and K data for one line stored in the one line memories 114C to K, respectively, and transfer them to the C to K version printer engines 116C to 116K. To do. The C to K version printer engines 116C to K print out the C, M, Y, and K data transferred from the C to K version engine controllers 115C to 115K.
[0053]
FIG. 5 is a flowchart for explaining the overall processing of the image processing apparatus of FIG. 2, and FIG. 6 is a diagram for explaining a transfer path of image data of the image processing apparatus of FIG. With reference to FIGS. 5 and 6, the overall processing of the image processing apparatus of FIG. 2 will be described.
[0054]
5 and 6, the color document is optically read by the scanner 109, and multi-value RGB data for one page is output to the smoothing filter processing apparatus 110 (step S101, (1)). The smoothing filter processing apparatus 110 performs smoothing filter processing on the multivalued RGB data input from the scanner 109 and outputs the processed data to the encoding apparatus 111 (step S102, (2)). The encoding device 111 JPEG-encodes the multivalued RGB data input from the smoothing filter processing device 110 and stores the code data for one page in the code page memory area 104 a of the main memory 104 via the memory controller 103. (Step S103, (3)).
[0055]
The decoding devices 112C to 112K independently decode the code data stored in the code page memory area 104a of the main memory 104 with delay for each plate in synchronization with the C to K version printer engines 116C to K, respectively. It is to become. First, the decoding devices 112C to 112K read the code data stored in the code page memory area 104a of the main memory 104 via the memory controller 103 (4), and decode the read code data to obtain a multi-value. Are transferred to the C to K image processing apparatuses 113C to 113K (step S104, (5)). The C to K plane image processing apparatuses 113C to 113K perform color correction processing on the multivalued RGB data input from the decoding apparatuses 112C to K to convert them into CMYK data (step S105), and further, multivalued data. The C, M, Y, and K data are binarized by performing gradation processing on the CMYK data, and then transferred to and stored in the one-line memories 114C to 114K (step S106, (6)).
[0056]
The C to K version engine controllers 115C to K read C, M, Y, and K data from the one-line memories 114C to K in synchronization with the C version to K version printer engines 116C to K, respectively (7). The data are transferred to the C to K version printer engines 116C to 116K (step S107, (8)). Then, the C to K plate printer engines 116C to 116K form images of C, M, Y, and K data, respectively (step S108).
[0057]
[Encoding device]
FIG. 7 is a block diagram showing a detailed configuration of the encoding device 111 of FIG. As shown in FIG. 7, the encoding device 111 includes an 8-line memory 121, an encoding processing device 122, a memory address generation device 123, a memory I / F 124, a line memory write controller 125, and a controller 126. ing.
[0058]
The controller 126 controls the entire encoding device 111. The 8-line memory 121 temporarily stores the RGB data sequentially input from the smoothing filter processing apparatus 110 for 8 lines. The line memory write controller 125 generates an address for writing the RGB data filtered by the smoothing filter processing device 110 to the 8-line memory 121. The encoding processing device 122 reads out RGB data from the 8-line memory 121 in units of 8 × 8 pixels (blocks), encodes the data, and generates code data. The memory address generation device 123 generates an address of the main memory 104 that transfers the code data generated by the encoding processing device 122 via the memory I / F 124. The memory I / F 124 performs I / F with the memory controller 103.
[0059]
8 is a diagram for explaining the overall processing flow of the encoding device 111 in FIG. 7. FIG. 8A shows the entire processing flow of the encoding device 111 in FIG. 7, and FIG. These are diagrams showing the reading direction of an 8 × 8 pixel block from the 8-line memory 121. FIG.
[0060]
With reference to FIG. 8, the overall processing of the encoding device 111 in FIG. 7 will be described. In FIG. 8A, the encoding device 111 sequentially stores the RGB data smoothed by the smoothing filter processing device 110 in the 8-line memory 121 (step S201), and the 8-line memory 121 stores 8 lines of RGB data. It is determined whether or not the image data has been stored (step S202). If 8 lines have not been stored ("N" in step S2), the RGB data storage is continued while the 8 lines have been stored. (“Y” in step S202), the RGB data is read from the 8-line memory 121 in the reading direction shown in FIG. 8B, and a block of 8 × 8 pixels is read, JPEG-encoded in units of blocks, and the encoded data is main. It is stored in the code page memory area 104a of the memory 104 (step S203).
[0061]
Then, it is determined whether or not the processing for one block line has been completed (step S204). If the processing for one block line has not been completed ("N" in step S204), the process returns to step S203, and the eight lines The next block is read from the memory 121, encoded, stored in the main memory 104, and the same process is repeatedly executed until the process for one block line is completed (steps S203 and S204).
[0062]
On the other hand, when the processing for one block line is completed (“Y” in step S204), as shown in FIG. 4 above, the one block line of the code data stored in the code page memory area 104a of the main memory 104 is displayed. A restart marker is added to the end (step S205). Then, it is determined whether or not the image of one page has been completed (step S206). If the image of one page has not been completed, the process returns to step S201, and the same processing is performed for the next block line. The same process is repeated until the process ends (steps S201 to S206).
[0063]
FIG. 9 is a block diagram showing a detailed configuration of the encoding processing device 122 of FIG. As shown in FIG. 9, the encoding processing device 122 includes an 8 × 8 buffer 131, an 8-line memory address generation device 132, an RGB → YUV conversion device 133, a Y2D DCT processing device 134, and a U2D DCT process. Device 135, V2-dimensional DCT processing device 135, Y quantization processing device 137, U quantization processing device 138, V quantization processing device 139, Y entropy encoding device 140, and U entropy encoding device 141 A V entropy encoding device 142, a restart marker generating device 143, and a code format generating device 144.
[0064]
The 8 × 8 buffer 131 stores RGB data of an 8 × 8 pixel block read from the 8-line memory 121. The 8-line memory address generation device 132 generates a read address of the 8-line memory 121, and transfers a block line end signal to the restart marker generation device 143 when the end of the block line is reached.
[0065]
The RGB → YUV converter 133 reads out RGB data of 8 × 8 pixels from the 8 × 8 buffer 131 and converts it into YUV data, converts the Y component to the Y2D DCT processor 134, and the U component to the U2D DCT process. The V component is transferred to the device 135 to the V2-dimensional DCT processing device 136. FIG. 10 is a diagram illustrating an example of a format of code data of one block. In the example shown in the figure, 8 × 8 pixels are encoded for each of Y, U, and V.
[0066]
The Y two-dimensional DCT processing device 134 performs two-dimensional DCT (discrete cosine transform) on the Y component and transfers the result to the Y quantization processing device 137. The U two-dimensional DCT processor 135 performs a two-dimensional DCT (discrete cosine transform) on the U component and transfers the result to the U quantization processor 138. The V2-dimensional DCT processing device 139 performs two-dimensional DCT (discrete cosine transform) on the V component and transfers the result to the V quantization processing device 139.
[0067]
The Y quantization processing device 131 quantizes the Y component after DCT processing input from the Y two-dimensional DCT processing device 134 and transfers it to the Y entropy encoding device 140. The U quantization processing device 132 quantizes the U component after DCT processing input from the U two-dimensional DCT processing device 135 and transfers the quantized U component to the U entropy coding device 141. The V quantization processing device 139 quantizes the Y component after DCT processing input from the V2-dimensional DCT processing device 136 and transfers the quantized Y component to the V entropy encoding device 142.
[0068]
The Y entropy encoding device 140 entropy-encodes the quantized Y data input from the Y quantization processing device 131 and transfers the encoded Y data to the code format generation device 144. The U entropy encoding device 141 entropy-encodes the quantized U component input from the U quantization processing device 138 and transfers it to the code format generation device 144. The V entropy encoding device 142 entropy-encodes the quantized V component input from the V quantization processing device 139 and transfers the encoded V component to the code format generation device 144.
[0069]
When the one-block line end signal is input from the 8-line memory address generation device 132, the restart marker generation device 143 generates a restart marker and transfers it to the code format generation device 144. The code format generation device 144 receives code data and code lengths input from the Y, U, and V entropy encoding devices 140, 141, and 142, and a restart marker generation device 143 in the case of the end of the block line. A restart marker is received, and these codes are sequentially put into one code and collected, and output as code data for each block.
[0070]
FIG. 11 is a block diagram showing a detailed configuration of the 8-line memory address generation device 132 of FIG. The 8-line memory address generation device 132 includes a register 151, an adder 152, a comparator 153, and a multiplier 154, as shown in FIG.
[0071]
The register 151 stores the number of processing blocks of the image data input from the adder 152 and is initialized every time the image data in the 8-line memory 121 is read (initialized when one block line is completed). . The adder 152 performs “+1” processing on the number of processing blocks stored in the register 151. The comparator 153 determines whether or not the number of processing blocks stored in the register 152 is equal to the number of horizontal blocks. If the number of processing blocks is equal to the number of horizontal blocks, the comparator 153 outputs a one block line end signal as a restart marker generation device. Forward to 143. The multiplier 154 multiplies the number of processing blocks stored in the register 151 by the number of one block word in the 8-line memory 121 and calculates the start address of 8 × 8 pixels to be read next to the 8-line memory 121.
[0072]
FIG. 12 is a block diagram showing a detailed configuration of the Y, U, V entropy encoding devices 140, 141, 142 of FIG. The Y, U, and V entropy encoding devices 140, 141, and 142 have the same configuration. FIG. 13 is an explanatory diagram for explaining the AC coding procedure, FIG. 14 is an explanatory diagram for explaining the DC coding, and FIG. 15 is an explanatory diagram for explaining the DC / AC value cut-out process. ing.
[0073]
The Y, U, V entropy encoding devices 140, 141, 142 include an 8 × 8 DCT coefficient storage device 161, a DC / AC value cutout device 162, a DC value encoding device 163, and an AC value encoding device 164. As shown in FIG. 13, 8 × 8 DCT coefficients are zigzag AC encoded, and DC components are DC encoded as shown in FIG. 14.
[0074]
The 8 × 8 DCT coefficient storage device 161 is a buffer for storing 8 × 8 DCT coefficients, and stores 8 × 8 post-quantization DCT coefficients input from the Y quantization processing device 131. As shown in FIG. 15, the DC / AC cutout device 162 cuts out a DC value and an AC value from 64 DCT coefficients of 8 × 8. The DC value encoding device 163 has a Huffman table as shown in FIG. 16, accesses the Huffman table according to the DC value, calculates the DC code and the code length at each DC value, and the DC code and the DC code. The length is transferred to the code format generator 144. The AC value encoding device 164 includes a Huffman table as shown in FIG. 17, accesses the Huffman table according to the AC value, calculates the AC code and the code length at each AC value, and determines the AC code and the AC code. The code length is transferred to the code format generator 144.
[0075]
The code format generation device 144 combines each code into one code from the DC, AC code and DC, and AC code length input from the DC encoding device 163 and the AC value encoding device 164, and outputs it as one code data. .
[0076]
[Decryption device]
FIG. 18 is a diagram showing a detailed configuration of the decoding apparatuses 112C to 112K in FIG. Decoding devices 112C-K have the same configuration. As shown in FIG. 18, the decoding devices 112C to 112K include a memory I / F 201, a BUF 202, a decoding processing device 203, an 8 × 8 pixel buffer 204, a horizontal pixel selection device 205, and an 8 × 1 pixel. And a buffer 206.
[0077]
The memory I / F 201 reads code data at an address designated by the decoding processing device 203 from the code page memory area 104 a of the main memory 104 in units of 8 × 8 pixels (blocks) and transfers the code data to the buffer 202. The buffer 202 temporarily stores the code data and then transfers it to the decoding processing device 203. The decoding processing device 203 reads the code data from the code page memory area 104 a of the main memory 104, decodes it, and transfers it to the 8 × 8 pixel buffer 204. The 8 × 8 pixel buffer 204 temporarily stores the decoded 8 × 8 pixel RGB data. The horizontal pixel selection device 205 extracts the 8 × 1 pixel RGB data of the line currently processed from the 8 × 8 pixel buffer 204 and transfers it to the 8 × 1 pixel buffer 206. The 8 × 1 pixel buffer 206 temporarily stores the RGB data of 8 × 1 pixels selected by the horizontal pixel selection device 205 and transfers the RGB data to the C to K plane image processing devices 113C to 113K, respectively.
[0078]
FIG. 19 is a diagram showing an overall processing flow of the decoding apparatuses 112C to 112K in FIG. With reference to FIG. 19, the entire process of the decoding apparatuses 112C to 112K in FIG. 18 will be described.
[0079]
In FIG. 19, first, the pixel line counter I is initialized to I = 0 (step S301), and the head address of the currently accessed code is held (step S302). Subsequently, the block of code data at the head address of the currently accessed code is read from the code page memory area 104a of the main memory 104 and decoded in units of 8 × 8 pixels (block) (step S303). Then, the RGB data of 8 pixels in the horizontal direction of the I line of the decoded block is transferred to the C to K plane image processing apparatuses 113C to 113K (step S304). Then, it is determined whether or not a restart marker is added (step S305). If no restart marker is detected ("N" in step S305), the process returns to step S303, and the code data of the next block is obtained. The same processing is repeated until the restart marker is detected (until the end of one block line) is read out from the main memory 104 and decoded (steps S303 to S305).
[0080]
If a restart marker is detected (“Y” in step S305), the pixel line counter I is incremented by “1” to set I = I + 1 (step S306). Then, in order to determine whether or not the pixel line has completed one block line, it is determined whether or not I <8 (step S307).
[0081]
If I <8 (“Y” in step S307), after returning to the head address of the held code (step S308), the process returns to step S303, and the block of code data at the head address of the held code is read again. The decoding process is repeatedly executed until I ≧ 8 (steps S303 to S308).
[0082]
If I ≧ 8 (“N” in step S307), it is determined whether or not one page has been completed (step S309). If not, the head address of the next block line is held and the same This process is repeated until one page is completed (steps S301 to S309).
[0083]
In this manner, the decoding devices 112C to 112K read the restart marker inserted for each block line by the encoding device 111, determine the end of the block line, and if it is not the end, Returning to the address and reading the code data of the same block line again, the decoded image data can be transferred in units of 1 pixel × 8 pixels.
[0084]
20 and 21 are explanatory diagrams for explaining a case where the decoding device 111 performs transfer processing in units of one pixel line. FIG. 20 illustrates processing for the first pixel line, and FIG. 21 illustrates two pixels. An explanatory view for explaining processing of the line is shown.
[0085]
As shown in FIG. 20, the decoding apparatus 111 first reads the 8 × 8 pixel block from the main memory 104, decodes the code data, and starts the decoded 8 × 8 pixel. Only the horizontal 8 pixels (1) of the first pixel line are transferred to the image processing apparatus 113, and then the image processing apparatus 113 transfers to the 1-line memory 114. Next, the decoding device 111 reads out and decodes the code data of the next block from the main memory 104, and performs image processing only on the decoded horizontal 8 pixels ([2]) of the first pixel line from the 8 × 8 pixels. The data is transferred to the device 113, and this process is sequentially executed until one block line is completed.
[0086]
In the processing of the second pixel line, as shown in FIG. 21, the decoding apparatus 111 reads out an 8 × 8 pixel block from the main memory 104 again, decodes the code data, and starts from the decoded 8 × 8 pixels. Only the horizontal 8 pixels of the second pixel line are transferred to the image processing device 113, and then the image processing device 113 transfers to the 1-line memory 114. Subsequently, the decoding device 111 reads the code data of the next block from the main memory 104 and decodes it, and only the horizontal 8 pixels ((2)) of the second pixel line from the 8 × 8 pixels of the decoded block are decoded. The data is transferred to the image processing apparatus 113, and this process is sequentially executed until one block line is completed.
[0087]
Processing similar to the above is continued until eight pixel lines (one block line) are completed, whereby one line of image data is stored in the one line memory 114. When the 8 pixel lines are completed, the next block line block is read and the same processing is executed until one page is completed.
[0088]
FIG. 22 is a block diagram showing a detailed configuration of the decryption processing apparatus 203 of FIG. As shown in FIG. 22, the decoding processing device 203 includes an entropy encoding device 211, a Y inverse quantization processing device 212, a U inverse quantization processing device 213, a V inverse quantization processing device 214, and a Y2D. An IDCT processing device 215, a U2D IDCT processing device 216, a V2D IDCT processing device 217, a YUV → RGB conversion device 218, and a code memory address generation device 219 are provided.
[0089]
The entropy decoding device 211 sequentially reads out code data of 8 × 8 pixels stored in the buffer 202, performs entropy decoding processing of Y, U, and V components, and 8 × 8 of each component after quantization. The DCT coefficients are transferred to the Y, U, and V quantization processors 212 to 214, respectively.
[0090]
The Y inverse quantization processing device 212 performs inverse quantization on the quantized 8 × 8 DCT coefficient of the Y component input from the entropy decoding device 211, and converts the 8 × 8 pixel DCT coefficient of the Y component. Calculate and transfer to the Y2D IDCT processor 215. The U inverse quantization processing device 213 performs inverse quantization on the quantized U component 8 × 8 DCT coefficient input from the entropy decoding device 211 to obtain a U component 8 × 8 pixel DCT coefficient. Calculate and transfer to U2D IDCT processor 216. The V inverse quantization processing device 214 performs inverse quantization on the 8 × 8 DCT coefficient of the U component after quantization input from the entropy decoding device 211 to obtain the DCT coefficient of 8 × 8 pixels of the V component. Is calculated and transferred to the V2D IDCT processor 217.
[0091]
The Y2D IDCT processing device 215 performs IDCT (Inverse Discrete Cosine Transform) on the Y component 8 × 8 pixel DCT coefficient input from the Y inverse quantization processing device 215 to obtain the Y component 8 × 8 pixel. Data is calculated and transferred to the YUV → RGB converter 218. The U two-dimensional IDCT processing device 216 performs IDCT (Inverse Discrete Cosine Transform) on the 8 × 8 pixel DCT coefficient of the U component input from the U inverse quantization processing device 213, and 8 × 8 pixel of the U component Data is calculated and transferred to the YUV → RGB converter 218. The V2D IDCT processing device 217 performs IDCT (Inverse Discrete Cosine Transform) on the 8 × 8 pixel DCT coefficient of the V component input from the V inverse quantization processing device 214 to obtain 8 × 8 pixel of the V component. Data is calculated and transferred to the YUV → RGB converter 218.
[0092]
The YUV → RGB conversion device 218 converts the 8 × 8 pixel Y, U, and V data input from the Y, U, and VIDCT processing devices 215, 216, and 217 into RGB data and transfers them to the 8 × 8 pixel buffer 204. To do.
[0093]
The code memory address generation device 219 generates a code memory address for reading the code data stored in the code page memory area 104a of the main memory 104, and receives the block line end signal from the entropy decoding device 211. To return to the first address of the stored block line.
[0094]
FIG. 23 is a block diagram showing a detailed configuration of the entropy decoding device 211 of FIG. As shown in FIG. 23, the entropy decoding device 211 includes a read code register 221, a shifter 222, a restart code determination device 223, a DC value encoding device 224, an AC value encoding device 225, and a MUX 226. The shift value generation device 227 and the 8 × 8 data generation device 228 are provided.
[0095]
The read code register 221 temporarily stores code data read from the code page memory area 104 a of the main memory 104. The shifter 222 performs a shift process to cut out DC and AC codes from the code data in the read code register 221. The restart code determination device 223 determines the restart marker inserted in the code data, generates a block line end signal, and transfers the restart marker code length to the shift value generation device 227 via the MUX 226.
[0096]
The DC value decoding device 224 reads and decodes the DC code at the head of the shifter 222, transfers the DC data to the 8 × 8 data generation device 228, and transmits the DC code length to the shift value generation device via the MUX 226. Forward to H.227. The AC value decoding device 225 decodes the AC value from the portion exceeding the BIT for the DC code from the shifter 222, transfers the AC data to the 8 × 8 data generation device 228, and transmits the AC code length via the MUX 226. Transfer to the shift value generator 227. The MUX 226 shifts the DC code length, the AC code length, and the restart code length (consumed code length) input from the DC value decoding device 224, the AC value coding device 225, and the restart code determination device 223, as a shift value generation device. Forward to H.226. At this time, the MUX 226 first controls the sign of the DC value, but controls the AC value because the sign of the AC value continues thereafter.
[0097]
The shift value generation device 227 controls the shift amount of the shifter 222 based on the DC code length, AC code length, and restart code length input from the MUX 226. In this case, when the shift value exceeds the capacity of the code register 221, a NEXTGATEFLG (code word request signal) requesting the next code is sent to the code memory address generation device 219. The 8 × 8 data generation device 228 transfers the decoded 8 × 8 DCT coefficients after quantization to the Y, U, and V inverse quantization processing devices 212 to 214.
[0098]
FIG. 24 is a block diagram showing a configuration of the shift value generation circuit 227 of FIG. The shift value generation circuit 227 includes a MUX 231, a register 232, a register 233, a MUX 234, an adder 235, a comparator 236, a subtracter 237, and a register 238.
[0099]
The MUX 231 selects the start of the next code in the word stored in the registers 232 and 233 or the start value of the next code straddling the next word. The register 232 stores the leading value of the code in the word of the block line. Further, the register 232 is toggled, and alternately switches based on the block line end signal input from the restart code determination device 223 and stores the end value of the block line. At this time, the end value of the previous block line (the current start value of the block line) stored in the other register 233 is used to return to the start value of the block line. The register 233 accumulates the DC value, the AC code length from the AC value decoding devices 224, 225, and the DC code length, and stores the head value of the code to be processed in the code word.
[0100]
The MUX 234 switches the value of the adder 235 and the value of the register 232 based on the block line termination signal input from the restart code determination device 223. The adder 235 performs an accumulative calculation of the DC value, the AC code length from the AC value decoding devices 224 and 225, and the DC code length. The comparator 236 determines whether the value in the word obtained by accumulating the DC value, the DC code length input from the AC value decoding device 224, 225, or the like and the AC code length crosses the next word. However, when straddling, NEXTDATAFLAG is generated to request the sign of the next word. The subtracter 237 obtains the leading value of the code in the next word when straddling the next word. The register 238 stores NEXTDATAFLAG obtained by the comparator 236.
[0101]
FIG. 25 is a block diagram showing a detailed configuration of the code memory address generation device 219 of FIG. As shown in FIG. 25, the code memory address generation device 219 includes a register 241, an adder 242, a MUX 243, a register 424, and an OR circuit 245.
[0102]
The register 241 stores a code address to be processed by the main memory 104. The adder 242 counts up the address of the code processed by the main memory 104. The MUX 243 switches the value from the adder 242 and the previous block line end (current block line start point) value based on the block line end signal input from the restart code determination device 223. The register 424 stores the end value of the previous block line (the start point of the current block line) based on the block line end signal or the code word request signal input from the restart code determination device 223. The OR circuit 245 outputs the OR output of the block line termination signal and the code word request signal input from the restart code determination device 223 to the register 241.
[0103]
FIG. 26 is a block diagram showing a configuration of the C plane image processing apparatus 113C of FIG. The C plane image processing apparatus 113C includes a buffer 251, a color correction processing apparatus 252, a gradation processing apparatus 253, a PIXEL TO PLANE conversion apparatus 254, a buffer 255, a one-line memory address generation apparatus 256, a controller 257, and the like. It has.
[0104]
The buffer 251 temporarily stores the decoded RGB data input from the decoding device 111C. The color correction processing device 252 performs color correction of the RGB data (multi-value data) stored in the buffer 251 and converts it into C data (multi-value data). The gradation processing device 253 converts the data, such as binary, quaternary, and 16-value data after gradation processing, which are input from the color correction processing device 253. The PIXEL TO PLANE conversion device 254 converts only binary data, binary data, 16-value data, etc., subjected to gradation processing by the gradation processing device 253 from PXEL to PLANE and transfers them to the buffer 255. To do. The buffer 255 temporarily stores the converted C data input from the PIXEL TO PLANE conversion device 254. The 1-line memory address generator 256 generates an address of the 1-line memory 114C, and the C data stored in the buffer 255 is transferred to the designated address. The controller 257 controls the C plane image processing apparatus 113C.
[0105]
The M to K plate image processing apparatuses 113M to 113K differ only in the colors to be output, and the basic configuration is the same as that of the C plate image processing apparatus 113C.
[0106]
FIG. 27 is a diagram showing a processing flow of the C plane image processing apparatus 13C of FIG. With reference to FIG. 27, the process of the C plane image processing apparatus 13C of FIG. 26 will be described. 27, RGB data transferred from the decoding device 112C is stored in the buffer 251 (step S401), and the color correction processing device 252 performs color correction processing to convert the RGB data into C data (step S402). . Then, the gradation processing device 253 converts the multivalued C data into binary C data (step S403). Then, the C data after gradation processing is collected to a fixed length only for the designated plane and transferred to the one-line memory 114C (step S404). It is determined whether or not all the images have been processed (step S405), and the same processing is repeated until all the images are completed (steps S401 to S405).
[0107]
As described above, according to the first embodiment, by adding a restart marker to the end of one block line of a block processed with image data, the end of one block line of code data can be easily searched. Since the code data of the same block line is repeatedly read at the time of decoding and the decoded image data of each block is output in units of one pixel line, the line memory for storing the decoded image data is reduced. It is possible to reduce the size and cost of the hardware configuration by increasing the capacity. Thereby, it is possible to reduce the memory amount and gate scale of the image processing LSI.
[0108]
In the first embodiment described above, the 1-line memories 114C-K are arranged between the C-K plate image processing apparatuses 113C-K and the C-K plate engine controllers 115C-K. ... 114K may be arranged between the decoding devices 112C-K and the C-K plate image processing devices 113C-K. Further, it may be configured without providing a one-line memory. FIG. 28 is a diagram illustrating a configuration of an image processing apparatus without a one-line memory.
[0109]
In the first embodiment described above, the image data is transferred from the decoding devices 112C to 112K to the C to K image processing devices 113C to 113K in units of 8 pixels of one pixel line. The RGB data may be transferred from the decoding devices 112C to 112C to the C to K plate image processing devices 113C to 113K using pixel lines or four pixel lines. In this case, a two-line memory or a four-line memory is required, but the line memory can be made smaller than when processing is performed in one block (in this case, an eight-line memory is required). Also, in this case, the number of readings can be reduced to 1/2 for a 2 pixel line and 1/4 for a 4 pixel line, compared to processing with a 1 pixel line.
[0110]
FIG. 29 is a diagram illustrating a configuration of an image processing apparatus having a two-line memory. In this case, as described above, data is transferred in units of two pixel lines. With reference to FIG. 30 and FIG. 31, the case of processing with two pixel lines will be described.
[0111]
In the process of the first line, as shown in FIG. 30, first, the decoding devices 112C to 112K read 8 × 8 pixel blocks from the main memory 104, decode the code data, and decode the decoded 8 × 8 pixels. Only the 8 horizontal pixels ((1)) of the 1st pixel line and the 2nd pixel line (2 pixel line) are transferred to the C-K plate image processing devices 113C-K, and then transferred to the 1-line memories 114C-K To do. Then, the code data of the next block is read from the main memory 104, the code data is decoded, and only the horizontal 8 pixels ((2)) of the 1 pixel line and the 2 pixel line from the decoded 8 × 8 pixels are converted to C˜ The image data is transferred to the K plate image processing apparatuses 113C to 113K, and this process is sequentially executed until one block line is completed.
[0112]
In the process of the third line, as shown in FIG. 31, the decoding devices 112C to 112K read the same 8 × 8 pixel block from the main memory 104, decode the code data, and start from the decoded 8 × 8 pixel. Only the horizontal 8 pixels of the 3rd pixel line and the 4th pixel line (2 pixel lines) are transferred to the C to K image processing devices 113C to K, and then transferred to the 1 line memories 114C to K. Next, the code data of the next block is read from the memory, the code data is decoded, and only the horizontal 8 pixels ((2)) of 3 pixel lines and 4 pixel lines from the decoded 8 × 8 pixels are C to K. The image data is transferred to the plate image processing apparatuses 113C to 113K, and this process is sequentially executed until one block line is completed.
[0113]
Then, the same processing as described above is continued until the end of the 8 pixel line. When the 8 pixel line ends, the block of the next block line is read and the same processing is performed until the end of one page. Execute.
[0114]
(Embodiment 2)
An image processing apparatus according to the second embodiment will be described with reference to FIGS. In the image processing apparatus according to the first embodiment, the encoding apparatus adds a restart marker to the end of one block line of the code data, and the decoding apparatus detects the restart marker and detects the end of one block line. However, in the image processing apparatus according to the second embodiment, the encoding apparatus does not add a restart marker, and the decoding apparatus uniquely detects the end of one block line of code data. Is. Since the image processing apparatus according to the second embodiment has substantially the same configuration as the image processing apparatus according to the first embodiment, only different points will be described here. The overall hardware configuration of the image processing apparatus according to the second embodiment is the same as that shown in FIG.
[0115]
[Encoding device]
The overall hardware configuration of the encoding apparatus according to the second embodiment is the same as that shown in FIG. FIG. 32 is a diagram showing an overall processing flow of the encoding apparatus 111 (FIG. 7) according to the second embodiment. FIG. 6A shows the overall processing flow of the encoding apparatus 111 according to the second embodiment, and FIG. 6B shows the reading direction of the 8 × 8 pixel block from the 8-line memory. With reference to FIG. 32, the entire process of the encoding apparatus 111 of Embodiment 2 is demonstrated.
[0116]
32A, the encoding device 111 sequentially stores the RGB data subjected to the smoothing filter processing by the smoothing filter processing device 110 in the 8-line memory 121 (step S501), and the 8-line memory 121 stores 8 lines of RGB data. If it is determined whether or not 8 lines have been stored (step S502), if 8 lines have not been stored ("N" in step S502), storage of RGB data is continued while 8 lines have been stored. (“Y” in step S502), RGB data is read from the 8-line memory 121 as 8 × 8 pixels as one block in the direction shown in FIG. 32B, and the read 8 × 8 pixels are JPEG encoded. The encoded data is stored in the code page memory area 104a of the main memory 104 (step S503).
[0117]
Then, it is determined whether or not the processing of one block line has been completed (step S504). If the processing of one block line has not been completed ("N" in step S504), the process returns to step S503, and eight lines The next block is read from the memory 121, encoded, and the same process is repeated until the process for one block line is completed (steps S503 and S504).
[0118]
On the other hand, when the processing for one block line is completed (“Y” in step S504), it is determined whether or not the image for one page has been completed (step S505). In step S501, the same processing is performed for the next block line, and the same processing is repeatedly executed until one page is completed (steps S501 to S506).
[0119]
FIG. 33 is a block diagram showing a detailed configuration of the encoding processing device 122 of FIG. The encoding processing device 122 shown in FIG. 33 does not add a restart marker, and therefore has a configuration in which the restart marker processing device is deleted from the encoding processing device in FIG. 9 and has an 8-line memory address. The generation device 132 is configured not to send a 1 block line end signal. 33, parts having the same functions as those in FIG. 9 are denoted by the same reference numerals.
[0120]
As shown in FIG. 33, the encoding processing device 122 includes an 8 × 8 buffer 131, an 8-line memory address generation device 132, an RGB → YUV conversion device 133, a Y2D DCT processing device 134, and a U2D DCT process. Device 135, V2-dimensional DCT processing device 135, Y quantization processing device 137, U quantization processing device 138, V quantization processing device 139, Y entropy encoding device 140, and U entropy encoding device 141 And a V entropy encoding device 142 and a code format generation device 144.
[0121]
The 8 × 8 buffer 131 stores 8 × 8 pixel block RGB data read from the 8-line memory 121. The 8-line memory address generation device 132 generates a read address for the 8-line memory 121.
[0122]
The RGB → YUV converter 133 reads out RGB data of 8 × 8 pixels from the 8 × 8 buffer 131 and converts it into YUV data, converts the Y data to the Y2D DCT processor 134, and the U component to the U2D DCT process. The V data is transferred to the device 135 to the V2-dimensional DCT processing device 136.
[0123]
The Y two-dimensional DCT processing device 134 performs two-dimensional DCT (discrete cosine transform) on the Y component and transfers the result to the Y quantization processing device 137. The U two-dimensional DCT processor 135 performs a two-dimensional DCT (discrete cosine transform) on the U component and transfers the result to the U quantization processor 138. The V2-dimensional DCT processing device 139 performs two-dimensional DCT (discrete cosine transform) on the V component and transfers the result to the V quantization processing device 139.
[0124]
The Y quantization processor 131 quantizes the Y data after DCT processing input from the Y two-dimensional DCT processor 134 and transfers the quantized Y data to the Y entropy encoder 140. The U quantization processing device 132 quantizes the U data after DCT processing input from the U two-dimensional DCT processing device 135 and transfers the quantized U data to the U entropy coding device 141. The V quantization processing device 139 quantizes the Y data after DCT processing input from the V2-dimensional DCT processing device 136 and transfers the quantized data to the V entropy encoding device 142.
[0125]
The Y entropy encoding device 140 entropy-encodes the quantized Y data input from the Y quantization processing device 131 and transfers the encoded Y data to the code format generation device 144. The U entropy encoding device 141 performs entropy encoding on the quantized U data input from the U quantization processing device 138 and transfers it to the code format generation device 144. The V entropy encoding device 142 performs entropy encoding on the quantized V data input from the V quantization processing device 139 and transfers the encoded V data to the code format generation device 144.
[0126]
The code format generator 144 receives the code data and the code length from the Y, U, and V entropy encoders 140, 141, and 142, sequentially puts these codes into one code, and outputs the code data as a batch. .
[0127]
The configuration of the 8-line memory address generation device in FIG. 33 is a configuration in which the comparison device is deleted in FIG.
[0128]
[Decryption device]
The entire hardware configuration of the decoding apparatus according to the second embodiment is the same as that shown in FIG. FIG. 34 is a diagram showing an overall processing flow of the decoding apparatus according to the second embodiment. With reference to FIG. 34, the overall processing of the decoding apparatus according to the second embodiment will be described.
[0129]
In FIG. 34, first, the pixel line counter I is initialized to I = 0, and the horizontal block number counter XNCT is initialized to XNCT = 0 (step S601). Then, the head address of the currently accessed code is held (step S602). Subsequently, the block of code data at the head address of the currently accessed code is read from the main memory 104 and decoded in units of 8 × 8 pixels (step S603). Then, the decoded 8 × 1 pixel RGB data of the I-line is transferred to the C to K image processing apparatuses 113C to 113K (step S604). The horizontal block number counter XNCT is incremented by “1” to set XNCT = XNCT + 1 (step S605), and it is determined whether XNCT> the number of blocks in the horizontal direction (step S606). XNCT> horizontal direction If it is not the number of blocks (“N” in step S606), the process returns to step S603, and the code data of the next block is read from the main memory 104 and decoded, until XNCT> the number of blocks in the horizontal direction (1 The same process is repeatedly executed (until the block line ends) (steps S603 to S606).
[0130]
If XNCT> the number of blocks in the horizontal direction (“Y” in step S606), the pixel line counter I is incremented by “1” to be I = I + 1 (step S607). Then, in order to determine whether or not the pixel line has completed one block line, it is determined whether or not I <8 (step S608).
[0131]
If I <8 (“Y” in step S608), after returning to the head address of the retained code (step S609), the process returns to step S603 to reread the block of code data at the head address of the retained code. The decoding process is repeatedly executed until I ≧ 8 (steps S603 to S609).
[0132]
If I ≧ 8 (“N” in step S608), it is determined whether or not one page has been completed (step S610). If not, the head address of the next block line is held, and the same This process is repeated until one page is completed (steps S601 to S609).
[0133]
In this way, the decoding apparatus counts the number of horizontally processed blocks in accordance with the set number of horizontal blocks, determines the end of the block line, returns to the head address of the block line, and returns to the same block line. Is read again, the decoded image data can be output in units of 1 pixel × 8 pixels.
[0134]
FIG. 35 is a block diagram showing a detailed configuration of the decryption processing apparatus 203 of FIG. The decoding processing device 203 shown in FIG. 35 has a configuration in which a block line end determination device 301 is added to detect the end of the block line in the decoding processing device 203 of FIG. In FIG. 35, parts having the same functions as those in FIG.
[0135]
As shown in FIG. 35, the decoding processing device 203 includes an entropy coding device 211, a Y inverse quantization processing device 212, a U inverse quantization processing device 213, a V inverse quantization processing device 214, and a Y2D. An IDCT processing device 215, a U2D IDCT processing device 216, a V2D IDCT processing device 217, a YUV → RGB conversion device 218, a code memory address generation device 219, and a block line end determination device 301 are provided.
[0136]
The entropy decoding device 211 sequentially reads the code data stored in the buffer 202, performs entropy decoding processing of the Y, U, and V components, and converts the 8 × 8 DCT coefficients of each component after quantization to Y, Transfer to U, V quantization processing devices 212-214.
[0137]
The Y inverse quantization processing device 212 performs inverse quantization on the quantized 8 × 8 DCT coefficient of the Y component input from the entropy decoding device 211, and converts the 8 × 8 pixel DCT coefficient of the Y component. Calculate and transfer to the Y2D IDCT processor 215. The U inverse quantization processing device 213 performs inverse quantization on the quantized U component 8 × 8 DCT coefficient input from the entropy decoding device 211 to obtain a U component 8 × 8 pixel DCT coefficient. Calculate and transfer to U2D IDCT processor 216. The V inverse quantization processing device 214 performs inverse quantization on the 8 × 8 DCT coefficient of the U component after quantization input from the entropy decoding device 211 to obtain the DCT coefficient of 8 × 8 pixels of the V component. Is calculated and transferred to the V2D IDCT processor 217.
[0138]
The Y2D IDCT processing device 215 performs IDCT (Inverse Discrete Cosine Transform) on the Y component 8 × 8 pixel DCT coefficient input from the Y inverse quantization processing device 215 to obtain the Y component 8 × 8 pixel. Data is calculated and transferred to the YUV → RGB converter 218. The U two-dimensional IDCT processing device 216 performs IDCT (Inverse Discrete Cosine Transform) on the 8 × 8 pixel DCT coefficient of the U component input from the U inverse quantization processing device 213, and 8 × 8 pixel of the U component Data is calculated and transferred to the YUV → RGB converter 218. The V2D IDCT processing device 217 performs IDCT (Inverse Discrete Cosine Transform) on the V component 8 × 8 pixel DCT coefficient input from the inverse quantization processing device 214 to obtain V component 8 × 8 pixel data. Is calculated and transferred to the YUV → RGB conversion device 218.
[0139]
The YUV → RGB conversion device 218 converts the 8 × 8 pixel Y, U, V data input from the Y, U, V two-dimensional IDCT processing devices 215, 216, 217 into RGB data, and the 8 × 8 pixel buffer 204. Forward to.
[0140]
The code memory address generation device 219 generates a code memory address for reading the code data stored in the code page memory area 104a of the main memory 104, and receives a block line end signal from the block line end determination device 301. Then, it returns to the head address of the stored block line.
[0141]
The block line end determination device 301 counts the number of processed horizontal blocks, determines whether the specified number of horizontal blocks has been exceeded, and generates a block line end signal when the number of horizontal blocks has been exceeded. Then, the data is transferred to the code memory address generation device 219 and the entropy decoding device 211.
[0142]
FIG. 36 is a block diagram showing a detailed configuration of the entropy decoding device 211 of FIG. The entropy decoding device 211 shown in FIG. 36 has a configuration in which the restart code determination device is deleted from the entropy decoding device 211 of FIG. In FIG. 36, parts having the same functions as those in FIG.
[0143]
As shown in FIG. 36, the entropy decoding device 211 includes a read code register 221, a shifter 222, a DC value encoding device 224, an AC value encoding device 225, a MUX 226, a shift value generation device 227, An 8 × 8 data generation device 228 and a controller 302 are provided.
[0144]
The read code register 221 temporarily stores the code of the code page memory area 104 a of the main memory 104. The shifter 222 performs a shift process to cut out the DC and AC codes from the code of the read code register 221.
[0145]
The DC value decoding device 224 reads and decodes the DC code at the head of the shifter 222, transfers the DC data to the 8 × 8 data generation device 228, and transmits the DC code length to the shift value generation device via the MUX 226. Forward to H.227. The AC value decoding device 225 decodes the AC value from the portion exceeding the BIT for the DC code from the shifter 222, transfers the AC data to the 8 × 8 data generation device 28, and transmits the AC code length via the MUX 226. Transfer to the shift value generator 227.
[0146]
The MUX 226 transfers the DC code length and the AC code length input from the DC value decoding device 224 and the AC value encoding device 225 to the shift value generating device 226. At this time, the MUX 226 first controls the sign of the DC value, but controls the AC value because the sign of the AC value continues thereafter.
[0147]
The shift value generation device 227 controls the shift amount of the shifter 222 based on the DC code length and AC code length input from the MUX 226. In this case, when the shift value exceeds the capacity of the code register 221, the next code is requested. The 8 × 8 data generation device 228 transfers the decoded 8 × 8 DCT coefficients after quantization to the Y, U, and V inverse quantization processing devices 212 to 214.
[0148]
The controller 302 controls the entropy decoding device 221, generates a block code signal each time one block of code data is decoded, and transfers the block code signal to the block line end determination device 301.
[0149]
The hardware configuration of the shift value generation circuit 227 of FIG. 36 is the same as that of FIG. The shift value generation circuit 227 of the second embodiment is different from the first embodiment only in that a block line termination signal is input to the register 232 and the MUX 234 from the block line termination determination device 301 in FIG. (In Embodiment 1, it is input from the restart code determination device 223).
[0150]
FIG. 37 is a diagram showing a configuration of the code memory address generation device of FIG. The hardware configuration of the code memory address generation device 219 shown in FIG. 37 is the same as that shown in FIG. The code memory address generation device of the second embodiment is different from the first embodiment only in that a block line termination signal is input from the block line termination determination device 301 to the MUX 231 and the OR circuit 245 (see the embodiment). In the first embodiment, it is input from the restart code determination device 223).
[0151]
FIG. 38 is a diagram showing a detailed configuration of the block line end determination device 301 of the decoding processing device of FIG. As illustrated in FIG. 38, the block line end determination device 301 includes a register 311, an adder 312, a comparator 313, and an FF (flip-flop) 314.
[0152]
The register 311 receives a block code signal output every time one block is decoded from the entropy decoding device, receives +1 data from the adder 312 and stores it, thereby sequentially counting up and processing. Store the number of blocks. The adder 312 counts up the number of processed blocks stored in the register 311. The comparator 313 compares the number of horizontal blocks of the image with the number of processed blocks stored in the register 311, determines the end of the block line, generates a block line end signal, and generates the FF 314 and the entropy encoding device 211. And the end of the block line is notified by transferring to the code memory address generator 219. The FF 314 temporarily stores the block line termination signal input from the comparator 313 and initializes the value of the register 311.
[0153]
As described above, according to the image processing apparatus of the second embodiment, the decoding apparatus searches for the end of one block line of code data, repeatedly reads out the code data of the same block line, and decodes it. Since the image data of each block is output in units of one pixel line, the capacity of the line memory for storing the decoded image data can be reduced, and the hardware configuration can be made small and inexpensive. It becomes possible. Thereby, it is possible to reduce the memory amount and gate scale of the image processing LSI.
[0154]
In the second embodiment, as in the first embodiment, the image data may be transferred from the decoding device to the image processing device in units of 2 or 4 pixel lines × 8 pixels in the horizontal direction.
[0155]
(Embodiment 3)
An image processing apparatus according to the third embodiment will be described with reference to FIGS. In the first and second embodiments, the case where the image processing apparatus is applied to a four-drum type digital color copying machine has been described. In the third embodiment, the image processing apparatus is applied to a four-drum type color printer. The case will be described.
[0156]
[Mechanical configuration of image processing device]
FIG. 39 is a cross-sectional view illustrating a schematic mechanical configuration of the image processing apparatus according to the third embodiment. As shown in FIG. 39, this color printer forms images of four colors (Y, M, C, K) by independent image forming systems 401Y, 401M, 401C, 401K, and synthesizes the images of these four colors. 4 drum tandem engine type image forming apparatus.
[0157]
Each of the image forming systems 401Y, 401M, 401C, 401K includes a photoconductor as an image carrier, for example, a small-diameter OPC (organic photoconductor) drum 402Y, 402M, 402C, 402K. The OPC drums 402Y, 402M, 402C. , 402K, charging rollers 403Y, 403M, 403C, 403K as charging means and electrostatic latent images on the OPC drums 402Y, 402M, 402C, 402K are respectively developed with a developer from the upstream side of the image forming so as to surround 402K. Developing devices 404Y, 404M, 404C, and 404K that produce toner images of Y, M, C, and K colors, cleaning devices 405Y, 405M, 405C, and 405K, static eliminators 406Y, 406M, 406C, and 406K are disposed. .
[0158]
Beside each developing device 404Y, 404M, 404C, 404K, toner bottle units 407Y, 407M, 407C, 407K for supplying Y toner, M toner, C toner, K toner to the developing devices 404Y, 404M, 404C, 404K, respectively. Is arranged. Each image forming system 401Y, 401M, 401C, 401K is provided with an independent optical writing device 408Y, 408M, 408C, 408K, and this optical writing device 408Y, 408M, 408C, 408K is a laser diode (laser diode as a laser light source). LD) light sources 409Y, 409M, 409C, 409K, collimating lenses 410Y, 410M, 410C, 410K, fθ lenses 411Y, 411M, 411C, 411K, and other polygonal parts 412Y, 412M, 412C, 412K as deflection scanning means , Mirrors 413Y, 413M, 413C, 413K, 414Y, 414M, 414C, 14K, and the like.
[0159]
The image forming systems 401Y, 401M, 401C, and 401K are arranged vertically, and the transfer belt unit 415 is arranged on the right side so as to contact the OPC drums 402Y, 402M, 402C, and 402K. The transfer belt unit 415 is rotationally driven by a drive source (not shown) with the transfer belt 416 stretched around rollers 417 to 420. A paper feed tray 421 storing transfer paper as a transfer material is disposed below the apparatus, and a fixing device 422, a paper discharge roller 423, and a paper discharge tray 424 are disposed above the apparatus.
[0160]
At the time of image formation, in each of the image forming systems 401Y, 401M, 401C, 401K, the OPC drums 402Y, 402M, 402C, 402K are rotated by a driving source (not shown), and the OPC drums are charged by the charging rollers 403Y, 403M, 403C, 403K. 402Y, 402M, 402C, and 402K are uniformly charged, and the optical writing devices 408Y, 408M, 408C, and 408K perform optical writing on the OPC drums 402Y, 402M, 402C, and 402K based on the image data of each color, whereby the OPC drum An electrostatic latent image is formed on 402Y, 402M, 402C, and 402K.
[0161]
The electrostatic latent images on the OPC drums 402Y, 402M, 402C, and 402K are developed by the developing devices 404Y, 404M, 404C, and 404K, respectively, to become toner images of Y, M, C, and K colors, while the paper feed tray 421 is used. Then, the transfer paper is fed in the horizontal direction by the paper feed roller 425 and is conveyed vertically in the image forming systems 401Y, 401M, 401C, and 401K by the transport system. The transfer paper is electrostatically attracted and held on the transfer belt 416 and is conveyed by the transfer belt 416, and a transfer bias is applied by a transfer bias applying unit (not shown) so that Y on the OPC drums 402Y, 402M, 402C, and 402K, A full color image is formed by sequentially superimposing and transferring toner images of M, C, and K colors. The transfer paper on which the full-color image is formed is fixed to the full-color image by the fixing device 422 and is discharged to the paper discharge tray 24 by the paper discharge roller 423.
[0162]
[Hardware configuration of image processing apparatus]
FIG. 40 is a block diagram illustrating a hardware configuration of the image processing apparatus according to the third embodiment. In FIG. 40, parts having the same functions as those in FIG. As shown in FIG. 40, the image processing apparatus according to the third embodiment includes a CPU 101, a CPU_I / F 102, a memory controller 103, a main memory 104, a local I / F 105, a ROM 106, a panel controller 107, A panel 108, a communication controller 501, a smoothing filter processing device 110, an encoding device 111, decoding devices 112C to K, C to K version image processing devices 113C to K, 1-line memories 114C to K, C-K version engine controllers 115C-K and C-K version printer engines 116C-K are provided.
[0163]
The CPU 101 controls the entire digital color copying machine according to programs stored in the ROM 106 and the main memory 104. The CPU_I / F 102 is connected between the CPU 101 and the memory controller 103 and processes an I / F between the CPU 101 and the memory controller 103. The memory controller 103 controls reading / writing of the main memory 104, and controls data transfer between the CPU 101, the local I / F 105 decoding devices 112 </ b> C to 112 </ b> K and the encoding device 111, and the main memory 104.
[0164]
The main memory 104 stores input image data, programs to be executed by the CPU 101, various data, and the like. FIG. 41 is a diagram showing an example of the format of the main memory 104. As shown in FIG. As shown in FIG. 41, the main memory 104 has an RGB band memory area 104c for storing multi-value RGB data for one band, and a code page memory area for storing encoded data in units of bands for a plurality of pages. 104a, a program area 104b for storing various programs of the CPU 101, and the like. FIG. 42 is a diagram showing the format of the code page memory area 104a. FIG. 43 is a diagram illustrating an example of a format of a band code stored in the code page memory area 104.
[0165]
The local I / F 105 processes I / Fs such as the ROM 106, the panel controller 107, the CPU 101, and the main memory 104. The ROM 106 stores programs executed by the CPU 101 and font information such as characters. The panel controller 107 controls the panel 108. The panel 108 notifies the CPU 101 of an operation from the user.
[0166]
The communication controller is connected to a network, receives various data and commands from the network, and is connected to various controllers via the memory controller 107.
[0167]
The encoding device 111 encodes the multi-value RGB band data stored in the multi-value RGB band memory area 104c of the main memory 104, and stores the code data in the code page memory area 104a.
[0168]
The decoding devices 112 </ b> C to 112 </ b> K read and decode the code data stored in the code page memory area 104 a of the main memory 104 via the memory controller 103, and the decoded RGB data is a C to K version image processing device. Transfer to 113C-K, respectively.
[0169]
The C to K image processing apparatuses 113C to 113K perform color conversion processing and gradation processing on the C, M, Y, and K data respectively decoded by the C, M, Y, and K version decoding apparatuses 112C to K. The C, M, Y, and K data after gradation processing are sequentially transferred and stored in the one-line memories 114C to 114K in units of one line.
[0170]
The one-line memories 114C to 114K store C, M, Y, and K data for one line subjected to gradation processing, respectively. The C to K version engine controllers 115C to 115K sequentially read C, M, Y, and K data for one line stored in the one line memories 114C to K, respectively, and transfer them to the C to K version printer engines 116C to 116K. To do. The C, M, Y, and K version printer engines 115C to 115K print out the C, M, Y, and K data transferred from the C to K version engine controllers 115C to 115K.
[0171]
44 is a flowchart for explaining the overall processing of the image processing apparatus of FIG. 40, and FIG. 45 is a diagram for explaining a transfer path of image data in the image processing apparatus of FIG. With reference to FIGS. 44 and 45, the overall processing of the image processing apparatus shown in FIG. 40 will be described.
[0172]
44 and 45, the CPU 101 stores the RGB data received via the communication controller for each band in the RGB band memory area 104c of the main memory 104 via the memory controller 103 (step S701, (1)). The encoding device 111 reads the multi-value RGB band from the RGB band memory area 104C of the main memory 104 ((3)), encodes the code data, and stores the code data in the code page memory area 104a of the main memory 104. (Step S702, (3)). In this case, the code length of each band is calculated, the head address for each band is calculated, and the band data of the encoded RGB data and the head address of each band are stored in the code page memory area 104 a of the main memory 104. .
[0173]
Decoding devices 112C-K independently decode the code data stored in main memory 104 in synchronization with C-K printer engines 116C-K, respectively. First, the decoding devices 112C to 112K read the code data stored in the main memory 104 via the memory controller 103 (4), decode the read code data and decode the decoded RGB data to C respectively. To the K plate image processing apparatuses 113C to 113K (step S703, (5)). The C to K image processing apparatuses 113C to 113K perform color correction processing on the RGB data input from the decoding apparatuses 112C to 112K to convert them into CMYK data (step S704), and perform gradation on the CMYK data. After the processing, the C, M, Y, and K data are binarized, and then transferred to and stored in the 1-line memories 114C to 113K (steps S705 and (6)).
[0174]
The C to K version engine controllers 115C to K read C, M, Y, and K data from the one-line memories 114C to 113K in synchronization with the C version to K version printer engines 115C to K, respectively (7). The data are transferred to the C to K version printer engines 116C to 116K (step S706, (8)). Then, the C to K version printer engines 116C to 116K form images of C, M, Y, and K data, respectively (step S707).
[0175]
[Encoding device]
FIG. 46 is a block diagram showing a detailed configuration of the encoding device 111 in FIG. As shown in FIG. 46, the encoding device 111 includes an encoding processing device 122, a memory address generation device 123, a memory I / F 124, and a controller 126.
[0176]
The controller 126 controls the entire encoding device 111. The memory I / F 124 performs I / F with the memory controller 103. The encoding device 123 reads an image in units of 8 × 8 pixels (blocks) from the main memory 104 via the memory I / F 124 and encodes it to generate code data. The memory address generation device 123 generates an address of the main memory 104 that transfers the code data generated by the encoding processing device 122 via the memory I / F 124.
[0177]
47 is a diagram for explaining the overall processing flow of the encoding device 111 of FIG. 40. FIG. 47A shows the overall processing flow of the encoding device 111 of FIG. 40, and FIG. Indicates the reading direction of the block. With reference to FIG. 47, the overall processing of the encoding device 111 in FIG. 40 will be described.
[0178]
In FIG. 47A, the encoding device 111 sequentially reads 8 × 8 pixels as one block from the RGB band code area 104c of the main memory 104, and JPEG-encodes the encoded data as a block. The code page memory area 104a of the main memory 104 is stored (step S801).
[0179]
Then, it is determined whether or not the processing for one block line has ended (step S802). If the processing for one block line has not ended ("N" in step S802), the process returns to step S801, and the main memory The next block is read out from the RGB band code area 104c of 104 and encoded, and the same processing is repeatedly executed until the processing of one block line is completed (steps S801 and S802).
[0180]
On the other hand, when the processing for one block line is completed (“Y” in step S802), a restart marker is added to the end of one block line of the code data stored in the code page memory area 104a of the main memory 104. (Step S803). Then, it is determined whether or not the processing for one band is completed (step S804). If the processing for one band is not completed, the process returns to step S801, and the same processing is performed for the next block line. The same process is repeatedly executed until the process ends (steps S801 to S804).
[0181]
FIG. 48 is a block diagram showing a detailed configuration of the encoding processing device 122 of FIG. As shown in FIG. 11, the encoding processing device 122 includes an 8 × 8 buffer 131, a read memory address generation device 503, an RGB → YUV conversion device 133, a Y2D DCT processing device 134, and a U2D DCT processing device. 135, V2D DCT processing unit 135, Y quantization processing unit 137, U quantization processing unit 138, V quantization processing unit 139, Y entropy encoding unit 140, U entropy encoding unit 141, The V entropy encoding device 142 and the code format generating device 144 are provided.
[0182]
The 8 × 8 buffer 131 stores 8 × 8 pixel block RGB data read from the 8-line memory 121. The read address generation device 503 generates a read address of the main memory 104 and transfers a block line end signal to the restart marker generation device 143 when the end of one block line is detected.
[0183]
The RGB → YUV converter 133 reads out the RGB data of 8 × 8 pixels from the 8 × 8 buffer 131 and converts it into YUV data, converts the Y data to the Y2D DCT processor 134, and the U data to the U2D DCT process. The V data is transferred to the device 135 to the V2-dimensional DCT processing device 136.
[0184]
The Y two-dimensional DCT processor 134 performs two-dimensional DCT (discrete cosine transform) on the Y data and transfers the Y data to the Y quantization processor 137. The U two-dimensional DCT processing unit 135 performs two-dimensional DCT (discrete cosine transform) on the U data and transfers the U data to the U quantization processing unit 138. The V2-dimensional DCT processing device 139 performs two-dimensional DCT (discrete cosine transform) on the V data and transfers it to the V quantization processing device 139.
[0185]
The Y quantization processor 131 quantizes the Y data after DCT processing input from the Y two-dimensional DCT processor 134 and transfers the quantized Y data to the Y entropy encoder 140. The U quantization processing device 132 quantizes the U data after DCT processing input from the U two-dimensional DCT processing device 135 and transfers the quantized U data to the U entropy coding device 141. The V quantization processing device 139 quantizes the Y data after DCT processing input from the V2-dimensional DCT processing device 136 and transfers the quantized data to the V entropy encoding device 142.
[0186]
The Y entropy encoding device 140 entropy-encodes the quantized Y component input from the Y quantization processing device 131 and transfers the encoded Y component to the code format generation device 144. The U entropy encoding device 141 entropy-encodes the quantized U component input from the U quantization processing device 138 and transfers it to the code format generation device 144. The V entropy encoding device 142 entropy-encodes the quantized V component input from the V quantization processing device 139 and transfers the encoded V component to the code format generation device 144.
[0187]
The restart marker generation device 143 generates a restart marker and transfers it to the code format generation device 144 when a one block line end signal is input from the read memory address generation device 132. The code format generator 144 receives the code data from the Y, U, and V entropy encoders 140, 141, and 142, the code length thereof, and the restart marker from the restart marker generator 143, and sequentially outputs these codes. The data is put into one code and output as a summary code data.
[0188]
FIG. 49 is a block diagram showing a detailed configuration of the read memory address generation device 503 of FIG. The read memory address generation device 503 includes a register 511, an adder 512, a comparator 513, a register 514, an adder 515, a multiplier 516, and an adder 517.
[0189]
The adder 512 counts the number of processing blocks in the horizontal direction and stores it in the register 511. The register 511 stores the number of processing blocks in the horizontal direction and is initialized for each block line. The comparator 513 generates a block line end signal when the number of processing blocks in the horizontal direction reaches the number of horizontal blocks.
[0190]
The register 514 stores the number of processing blocks for each band. The adder 515 counts the number of processing blocks for each band. The multiplier 516 multiplies the number of words in one block for generating the address of the main memory 104 by the number of processed blocks. The adder 517 adds the head address of the band code for generating the address of the main memory 104 and the data amount accumulated by the multiplier 516 to generate and output a read memory address.
[0191]
The configuration of the decoding apparatus in FIG. 40 is the same as that in the first embodiment, and thus the description thereof is omitted.
[0192]
In the third embodiment, the encoding device adds a restart marker to the end of one block line of code data, and the decoding device detects the restart marker to detect the end of one block line. However, as in the second embodiment, the encoder may be configured to detect the end of one block line of the code data independently without adding a restart marker in the encoder.
[0193]
Similarly to the first embodiment, the image data may be transferred from the decoding device to the image processing device in units of 2 or 4 pixel lines × 8 pixels.
[0194]
The present invention is not limited to the above-described first to third embodiments, and can be appropriately modified and executed without departing from the gist of the invention.
[0195]
For example, in the present embodiment, the JPEG encoding method using DCT has been described as the encoding method, but Wavelet conversion may be used. In addition, although the block size of the image data is 8 pixels × 8 pixels, other sizes may be used.
[0196]
【The invention's effect】
  As described above, according to the image processing apparatus of the first aspect, the decoding unit can send the image data in units of the predetermined pixel line smaller than the block unit, and stores the decoded image data. Therefore, the capacity of the line memory can be reduced, and the hardware configuration can be made small and inexpensive.In addition, it is possible to repeatedly read out the block line of the image data by a simple method.
[0198]
  Claims2According to the image processing apparatus, it is possible to encode image data using the highly versatile JPEG method.
[0199]
  Claims3According to the image processing apparatus, the end of the block line of the image data can be detected by a simple method, and the block line can be read repeatedly.
[0201]
  Claims4According to the image processing apparatus, the line memory for storing the decoded image data can be a one-line memory or a two-line memory.
[0203]
  Claims5According to the color image forming apparatus, it is possible to reduce the capacity of the line memory for storing the decoded image data in the color image forming apparatus, thereby making the hardware configuration small and inexpensive.
[0204]
  Claims6According to the image processing method, the image data can be transmitted in units of a predetermined pixel line smaller than the block unit, the line memory for storing the decoded image data is reduced in capacity, and the hardware configuration is reduced. It becomes possible to make it small and inexpensive.In addition, it is possible to repeatedly read out the block line of the image data by a simple method.
[0206]
  Claims7According to this image processing method, it is possible to encode image data by the highly versatile JPEG method.
[0207]
  Claims8According to the image processing method, it is possible to detect the end of the block line of the image data by a simple method and repeatedly read out the block line.
[0209]
  Claims9According to the image processing method, the line memory for storing the decoded image data can be a 1-line memory or a 2-line memory.
[Brief description of the drawings]
1 is a cross-sectional view showing a schematic mechanical configuration of an image processing apparatus according to a first embodiment;
FIG. 2 is a block diagram of a hardware configuration of the image processing apparatus according to the first embodiment.
FIG. 3 is a diagram illustrating an example of a format of a main memory in FIG. 2;
4 is a diagram showing a format of data for one page stored in a code page memory area of the main memory in FIG. 2; FIG.
FIG. 5 is a diagram showing an overall processing flow of the image processing apparatus of FIG. 2;
6 is a diagram for explaining a transfer path of image data of the image processing apparatus of FIG. 2; FIG.
7 is a block diagram showing a detailed configuration of the encoding device in FIG. 2; FIG.
FIG. 8 is a diagram showing an overall processing flow of the encoding apparatus of FIG. 9;
9 is a block diagram showing a detailed configuration of the encoding processing apparatus in FIG. 7;
FIG. 10 is a diagram illustrating an example of a format of YUV data.
11 is a block diagram showing a detailed configuration of the 8-line memory address generation device of FIG. 9;
12 is a diagram illustrating a detailed configuration of the entropy encoding device of FIG. 9;
FIG. 13 is an explanatory diagram for explaining an AC encoding procedure;
FIG. 14 is an explanatory diagram for explaining a procedure of DC encoding.
FIG. 15 is an explanatory diagram for explaining cutout of an AC value and a DC value.
16 is a diagram illustrating a configuration of the DC value encoding device of FIG. 12;
17 is a diagram illustrating a configuration of the AC value encoding device of FIG. 12;
18 is a block diagram showing a detailed configuration of the decoding apparatus in FIG. 2. FIG.
FIG. 19 is a diagram showing a processing flow of the decryption apparatus of FIG. 18;
FIG. 20 is an explanatory diagram for describing processing in units of one pixel line of the decoding device (part 1);
FIG. 21 is an explanatory diagram for describing processing in units of one pixel line of the decoding device (part 2);
22 is a block diagram showing a detailed configuration of the decoding processing apparatus in FIG. 18;
23 is a block diagram showing a detailed configuration of the entropy decoding device in FIG.
24 is a block diagram showing a detailed configuration of the shift value generation circuit of FIG. 23. FIG.
25 is a block diagram showing a detailed configuration of the code memory address generation device of FIG. 22;
26 is a block diagram showing a detailed configuration of a C plane image processing apparatus 112C in FIG.
FIG. 27 is a diagram showing a processing flow of the C plane image processing apparatus of FIG. 26;
FIG. 28 is a diagram illustrating a hardware configuration of an image processing apparatus without a one-line memory.
FIG. 29 is a diagram illustrating a hardware configuration of an image processing apparatus having a two-line memory.
FIG. 30 is an explanatory diagram for describing processing in units of two pixel lines of the decoding device (part 1);
FIG. 31 is an explanatory diagram for describing processing in units of two pixel lines of the decoding device (part 2);
FIG. 32 is a diagram showing an overall processing flow of the encoding apparatus according to the second embodiment;
FIG. 33 is a block diagram showing a detailed configuration of the encoding processing apparatus according to the second embodiment;
FIG. 34 is a diagram showing an overall processing flow of the decoding apparatus according to the second embodiment;
FIG. 35 is a block diagram showing a detailed configuration of the decoding processing apparatus according to the second embodiment;
36 is a block diagram showing a detailed configuration of the entropy decoding device in FIG. 35. FIG.
37 is a block diagram showing a detailed configuration of the code memory address generation device in FIG. 35;
38 is a diagram showing a detailed configuration of the block line end determination device in FIG. 35;
FIG. 39 is a cross-sectional view illustrating a schematic mechanical configuration of the image processing apparatus according to the third embodiment;
FIG. 40 is a block diagram of a hardware configuration of the image processing apparatus according to the third embodiment.
41 is a diagram showing an example of a format of a main memory in FIG. 40. FIG.
42 is a diagram showing an example of a format of a code page memory area in FIG. 41. FIG.
43 is a diagram showing an example of a format of data stored in a code page memory area of FIG. 42. FIG.
44 is a flowchart for explaining overall processing of the image processing apparatus in FIG. 40; FIG.
45 is an explanatory diagram for describing a transfer path of image data of the image processing apparatus in FIG. 40; FIG.
46 is a block diagram showing a detailed configuration of the encoding apparatus in FIG. 40. FIG.
47 is a diagram showing an overall processing flow of the encoding apparatus in FIG. 46; FIG.
48 is a block diagram showing a detailed configuration of the encoding processing apparatus in FIG. 46. FIG.
49 is a block diagram showing a detailed configuration of the read memory address generation device of FIG. 48. FIG.
FIG. 50 is a diagram for explaining a conventional technique.
[Explanation of symbols]
101 CPU
102 CPU_I / F
103 Memory controller
104 memory
105 Local I / F
106 ROM
107 Panel controller
108 panels
109 scanner
110 Smoothing filter processing device
111 Encoder
112C-K decoding device
113C-K C-K image processing apparatus
114C-K 1 line memory
115C-K C-K version engine controller
116C-K C-K printer engine
121 8-line memory
122 Encoding processing device
123 Memory address generator
124 Memory I / F
125 line memory write controller
126 controller
210 Memory I / F
202 BUF
203 Decoding processing device
204 8 × 8 pixel buffer
205 Horizontal pixel selection device
206 8 × 1 pixel buffer

Claims (9)

A dividing means for dividing the input image data into blocks composed of a plurality of pixels;
Encoding means for performing encoding processing on the image data in units of blocks divided by the dividing means;
Storage means for storing code data that has been encoded by the encoding means;
Decoding the image data by decoding the code data stored in the storage means in units of blocks, and decoding means for sending the decoded image data in units of predetermined pixel lines ,
The decoding means determines the end of the block line by reading the restart marker inserted for each block line of the code data stored in the storage means, and if it is determined that it is not the end of the block line, the same block An image processing apparatus , wherein the line code data is read again from the storage means and subjected to decoding processing.   The image processing apparatus according to claim 1, wherein the encoding unit performs JPEG compression processing on the image data, and the decoding unit performs JPEG expansion processing. The decoding means includes a determination means for determining whether or not a restart marker is added to the code data. If the determination result of the determination means is negative, the code data of the next block is to perform a decoding process thereto from the storage means, the image processing apparatus according to claim 1, wherein the said determination means restart marker is added and repeating until determination. The image processing apparatus according to any one of claims 1 to 3 , wherein the predetermined pixel line unit is one pixel line unit or two pixel line units. Color image forming apparatus characterized by the application of the image processing apparatus according to any one of claims 1 to 4. A dividing step of dividing the input image data into blocks each including a plurality of pixels; an encoding step of performing encoding processing on the image data in units of blocks divided in the dividing step; and encoding processing in the encoding step Storing the code data performed in the memory, decoding the image data by performing block decoding on the code data stored in the memory in the storage step, and decoding the image data A process of sending data in units of predetermined pixel lines,
The decoding step determines the end of the block line by reading a restart marker inserted for each block line of the code data stored in the memory, and if it is determined that it is not the end of the block line, the same block line The image processing method is characterized in that the code data is read again from the storage means and subjected to decoding processing. The image processing method according to claim 6 , wherein in the decoding step, the image data is subjected to JPEG compression processing, and in the decoding step, JPEG expansion processing is performed. The decoding step includes a determination step of determining whether or not a restart marker is added to the code data. If the determination result in the determination step is negative, the code data of the next block is 7. The image processing method according to claim 6 , wherein reading from the memory and decoding processing are repeated until it is determined in the determination step that the restart marker is added. Wherein the predetermined pixel line unit, an image processing method according to any one of claims 6 to claim 8, which is a 1-pixel line unit or pixel lines.

Images