JP4226581B2 - System and method for generating a reference voltage - Google Patents

Description

  The present invention relates to electrical circuits, and more particularly to a system and method for generating a reference voltage.

AMLCD (active matrix liquid crystal) is the most advanced flat panel display technology. The AMLCD has a matrix including a plurality of pixels (pixels), and the plurality of pixels constitute an image. In a thin film transistor (TFT) panel, the TFT is a switch and capacitor for each pixel of the AMLCD, turning on (bright) / off (dark) individual pixels. In addition to the normal display mode of all gradations, the display device generally has several power saving display modes. For example, an n gradation mode (n is an integer smaller than the number of all gradation levels) for displaying an image with fewer gradations, a partial display mode in which only a part of the display device is used, and / or a display device is reproduced. An example is the standby mode in which the operation is suspended until the start.
By integrating the driving (reference voltage generation) circuit into the display panel using TFT technology, the cost can be greatly reduced. In order to provide accurate analog voltage control to the reference voltage generation circuit and to simplify the circuit structure, a resistor string that provides a reference voltage is used. Please refer to FIG. FIG. 1 is an explanatory diagram showing a reference voltage generating circuit 10 listed in US Pat. No. 6,839,043. Reference voltage generating circuit 10 includes switch circuits 41 and 42, voltage dividing resistors R1-R7, and switches SW15 and SW16. The switch circuits 41 and 42 include switches SW11 and SW12, and switches SW13 and SW14. The switches SW11 to SW14 use the output terminals A and B of the resistor string as the positive power supply Vcc, and the power supply Vss whose voltage level is lower than that of the power supply Vcc. To be coupled to. According to the row inversion driving method, the power supply devices Vcc and Vss provide opposite phases for every predetermined period. The voltage dividing resistors R1 to R7 are connected in series between the output terminals A and B of the resistor string via the switches SW15 and SW16, and the voltages V0 and V7 and V1 to V16 obtained by dividing the resistor string are digital. / Output to analog converter (DAC).
Please refer to FIG. FIG. 2 is a timing chart showing the operation of the conventional reference voltage generation circuit 10. The reference voltage generation circuit 10 in FIG. 1 connects the node A to the positive power supply device Vcc in the first drive cycle and connects the node B to the power supply device Vss, and connects the node B to the positive power supply device Vcc in the second drive cycle. In addition, the reference voltages V0 and V7 are provided by connecting the node A to the power supply device Vss. According to FIG. 2, the drive cycle alternates at regular time intervals, which are determined by the control pulses φ1, φ2. Note that the reference voltages V1-V6 for the intermediate gradation are generated by the voltage division of the voltage dividing resistors R1-R7. In the power saving mode, the switches SW15 and SW16 are turned off (open circuit) based on the control pulse φ3, thereby cutting off the current supply to the voltage dividing resistors R1 to R7. As a result, no current flows through the voltage dividing resistors R1-R7, and no power is consumed, so that overall power consumption can be saved. The voltage levels V1 and V6 in the power saving mode are indicated as zero voltage according to FIG. 2, but in actuality, when the connection between the resistor string and the power supply devices Vcc and Vss is cut off, the conventional reference voltage generation circuit 10 generates the floating voltage. May occur.
Therefore, the conventional reference voltage generation circuit 10 has the following drawbacks. First, in the power saving mode, the connection between the resistor string and the power supply devices Vcc and Vss is disconnected using the switches SW15 and SW16. Unlike MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which are fabricated on a silicon wafer and have thick silicon as the active film, TFTs (thin film transistors) have a thin film (generally a polysilicon thin film) as their active film, so their resistance The value is larger than the MOSFET. Therefore, in order to reduce the turn-on time and voltage drop of the reference voltage generation circuit 10, the switches SW15 and SW16 need to be large enough to realize a low turn-on resistance. As a result, the reference voltage generation circuit 10 occupies a large area. Next, in the power saving mode, if the connection between the resistor string and the power supply devices Vcc and Vss is disconnected, the reference voltage generation circuit 10 outputs a floating voltage to the DAC. This will affect the stability of the DAC while at the same time leading to more power consumption.
U.S. Patent No. 6,839,043

  It is an object of the present invention to provide a system and method for generating a reference voltage for solving the problems of the conventional techniques.

The present invention provides a system for generating a reference voltage. The system includes an integrated reference voltage generating circuit, and the integrated reference voltage generating circuit is coupled between a resistor circuit including a plurality of resistors connected in series, a first end of the resistor circuit, and a first power source. A first switch, a second switch coupled between the first end of the resistor circuit and the second power source, a third switch coupled to the second end of the resistor circuit, and a second end of the resistor circuit A fourth switch coupled to the first resistor, a first resistor coupled between the first end of the resistor circuit and the first switch, and a second switch coupled between the first end of the resistor circuit and the second switch. A second resistor, a third resistor coupled between the second end of the resistor circuit and the third switch, a fourth resistor coupled between the second end of the resistor circuit and the fourth switch, and a first resistor Switch, second switch, third switch, fourth switch And a control circuit for controlling the pitch.
The present invention provides a system for generating other reference voltages. The system displays an image and is coupled to an integrated reference voltage generation circuit, a multiplexer that selects output data from input data in various modes of operation, a multiplexer and an integrated reference voltage generation circuit, It includes a digital / analog converter (DAC) that processes input data of a full-tone display image, and an integrated reference voltage generation circuit and a control circuit that sends a signal to a multiplexer according to the operation mode of the system. The integrated reference voltage generating circuit includes a resistor circuit including a plurality of resistors connected in series, a first switch coupled between a first end of the resistor circuit and a first power supply, and a first end of the resistor circuit A second switch coupled between the second power source, a third switch coupled to the second end of the resistor circuit, a fourth switch coupled to the second end of the resistor circuit, and the resistor circuit A first resistor coupled between the first end of the first resistor and the first switch; a second resistor coupled between the first end of the resistor circuit and the second switch; A third resistor coupled between the three switches, a fourth resistor coupled between the second end of the resistance circuit and the fourth switch, a first switch, a second switch, and a third switch; And a control circuit for controlling the fourth switch.
The present invention further provides a method for generating a reference voltage. The method provides a resistance circuit including a plurality of resistors connected in series, and when displaying an image in a power-saving manner, the first end and the second end of the resistance circuit are coupled to the same power source, When displaying an image in a modulated manner, the method includes a step of coupling a first end of the resistor circuit to the first power source and a second end to the second power source.

The present invention can fix the voltage of the entire resistance circuit in the power saving mode, thereby stopping the DAC in a stable state. Therefore, the integrated reference voltage generating circuit according to the present invention can reduce the power consumption and maintain the stability of the DAC without occupying a large area in the power saving mode.

In order to elaborate on the features of such an apparatus and method, specific examples are given and described below with reference to the figures.
The system and method for generating a reference voltage according to the present invention can reduce power consumption and / or compensate for charge injection effects. The present invention is suitable for a display system such as a panel display.

Please refer to FIG. FIG. 3 is an explanatory diagram showing an integrated reference voltage generating circuit 30 according to the present invention. The integrated reference voltage generation circuit 30 includes a resistance circuit 32, switches SW 1 -SW 4, resistors R 1 -R 4, electric (voltage) sources Vcc and Vss, and a control circuit 34. The power supply Vcc provides a higher voltage than the power supply Vss. Resistor circuit 32 includes a plurality of voltage-dividing resistors Rd1-Rd63 connected in series, switch SW1 is coupled between node C of resistor circuit 32 and power supply Vss, and switch SW2 is connected to node C of resistor circuit 32 and power supply Vcc. The switch SW3 is coupled between the node D of the resistor circuit 32 and the power source Vss, and the switch SW4 is coupled between the node D of the resistor circuit 32 and the power source Vcc. The resistor R1 is coupled between the node C of the resistor circuit 32 and the switch SW1, the resistor R2 is coupled between the node C of the resistor circuit 32 and the switch SW2, and the resistor R3 is coupled to the node D of the resistor circuit 32 and the switch SW3. The resistor R4 is coupled between the node D of the resistor circuit 32 and the switch SW4. The integrated reference voltage generation circuit 30 provides a reference voltage by dividing the resistance circuit 32.

In the embodiment shown in FIG. 3, the integrated reference voltage generation circuit 30 provides a reference voltage V0-V63 between any two adjacent voltage dividing resistors in the resistor circuit 32, and is based on a signal from the control circuit 34. The switches SW1-SW4 are turned on / off. Switches SW1-SW4 are differently doped. For example, the switches SW1 and SW3 can be N-type transistors, and the switches SW2 and SW4 can be P-type transistors, and vice versa. When the switches SW1 and SW3 are N-type transistors and the switches SW2 and SW4 are P-type transistors, when the control signal “1” (high voltage level) is received, the switches SW1 and SW3 are turned on (closed circuit), The switches SW2 and SW4 are turned off (open circuit). On the other hand, when the control signal “0” (low voltage level) is received, the switches SW1 and SW3 are turned off and the switches SW2 and SW4 are turned on.

Please refer to FIG. FIG. 4 is a timing diagram of the integrated reference voltage generating circuit 30 according to the present invention. According to FIG. 4, φ1-φ4 represents a control pulse, which has both high and low levels. In order to briefly explain the operation of the integrated reference voltage generation circuit 30 in the normal mode and the power saving mode, only the reference voltages V0, V1, V62, and V63 are shown. In order to prevent electroplating of ionic impurities and display delay of the liquid crystal, the polarity of the liquid crystal cell is inverted at regular intervals. The integrated reference voltage generation circuit 30 connects the node C of the resistor circuit 32 to the power source Vcc and the node D to the power source Vss in the first driving cycle, and connects the node C of the resistor circuit 32 in the second driving cycle. The reference voltages V0 and V63 are generated by connecting the node D to the power supply Vcc while connecting to the power supply Vss. According to FIG. 4, both drive cycles alternate at regular intervals based on the control pulses φ1 and φ2. In the normal mode, the control circuit 34 generates a control pulse φ4 and a high level control pulse φ3 that alternate between high and low levels, and provides the control pulses φ1 and φ2 to the switches SW1-SW4 based on the control pulse φ4. In the first driving cycle, the resistance circuit 32 is coupled to the power supply Vcc and the power supply Vss via the switches SW4 and SW1, respectively. In the second driving cycle, the resistance circuit 32 is connected via the switches SW2 and SW3, respectively. Are coupled to the power supply Vcc and the power supply Vss. Further, an intermediate reference voltage V1-V62 is generated by voltage division of the voltage dividing resistors Rd1-Rd63 of the resistor circuit 32.

In the power saving mode, the control pulse φ3 is switched to a low level, and the control pulse φ4 is maintained as it is in the normal mode, thereby generating high level control pulses φ1 and φ2. Accordingly, the switches SW2 and SW4 are turned off, and the connection between the resistance circuit 32 and the power source Vcc is disconnected. At the same time, the switches SW1 and SW3 are turned on, and the resistance circuit 32 is connected to the power supply Vss. Therefore, in the power saving mode, since no current flows in the resistor circuit 32, the power consumption of the voltage dividing resistor can be reduced. However, both ends of the resistor circuit 32 remain coupled to the power source Vss in the power saving mode, even though no current flows. Compared with the conventional reference voltage generation circuit 10, the present invention can fix the voltage across the resistor circuit 32 to Vss in the power saving mode, thereby stopping the DAC in a stable state. Therefore, the integrated reference voltage generation circuit 30 can reduce power consumption and maintain the stability of the DAC even if it does not occupy a large area in the power saving mode.

Please refer to FIG. FIG. 5 is an equivalent circuit diagram of the pixel 50. The pixel 50 includes a thin film transistor (TFT) that turns the pixel on / off, a storage capacitor Cst that stores data, and a liquid crystal capacitor Clc that represents the capacitance of the liquid crystal element. Data transmitted to the pixel 50 is stored in the capacitors Cst and Clc, and the parasitic capacitor Cgd represents the parasitic capacitance of the pixel 50. The signal from the gate line turns on the TFT, and the data from the data line is stored in the capacitors Cst and Clc. The reference voltage generated by the integrated reference voltage generation circuit is transmitted to the DAC, and the DAC selects one of the reference voltages and sends it to the data line.

The charge injection effect refers to a level change caused by the stray capacitance represented by the parasitic capacitor Cgd. Please refer to FIG. FIG. 6 is an explanatory diagram showing the charge injection effect. According to FIG. 6, Vgate represents the voltage sent to the gate line. When the voltage Vp is sent to the data line, Vpixel (dashed line) represents the ideal voltage across the capacitors Cst and Clc, and Vpixel ′ represents the actual voltage across the capacitors Cst and Clc. Under the influence of the charge injection effect, Vpixel ′ and Vpixel are different, and the difference is defined as a voltage drop ΔVp. Under the influence of the voltage drop ΔVp, data stored in the capacitors Cst and Clc may be lost, and the value is expressed by the following equation.
An integrated reference voltage generator such as circuit 30 can compensate for the charge injection effect using resistors R1-R4. That is, the voltage drop ΔVp is determined based on the capacitances of the capacitors Cst, Clc, and Cgd, and further compensated by providing various voltages across the resistor circuit 32 with resistors R1 to R4. Among them, the resistance values of the resistors R1 to R4 vary depending on the value of ΔVp. In the integrated reference voltage generating circuit 30 according to the present invention, the resistors R1 and R4 have the same resistance value, and the resistors R2 and R3 have the same resistance value.

Please refer to FIG. FIG. 7 is an explanatory diagram showing an integrated reference voltage generating circuit 70 according to Embodiment 2 of the present invention. The integrated reference voltage generation circuit 70 includes a resistor circuit 32, switches SW 1 -SW 4, resistors R 1 -R 4, electric (voltage) sources Vcc and Vss, and a control circuit 34. The power supply Vcc provides a higher voltage than the power supply Vss. Resistor circuit 32 includes a plurality of voltage dividing resistors Rd1-Rd63 connected in series. It should be noted that the integrated reference voltage generation circuit 70 differs from the conventional reference voltage generation circuit 10 in that it includes at least resistors R1-R4 for compensating for the charge injection effect.

Please refer to FIG. FIG. 8 is an explanatory diagram showing a display system 80 using an integrated reference voltage generating circuit according to the present invention. The display system 80 in FIG. 8 includes multiplexers (MUX) 81 and 82, a buffer 83, a control circuit 84, a timing controller (TC) 85, a DAC 87, and a reference voltage generation circuit 89. The reference voltage generation circuit 89 is the integrated reference voltage generation circuit 30 or 70 in FIG. 3 or 7 and provides a reference voltage to the DAC 87. Based on the signal from the control circuit 84, the MUX 81 selects output data from partial display mode input data, 8-color display mode input data, and normal mode input data. In the normal mode, the reference voltage generation circuit 89 performs voltage division and provides a plurality of reference voltages to the DAC 87. At this time, the MUX 81 selects the normal mode input data processed by the DAC 87 and the buffer 83 as output data. In the power saving mode such as the partial display mode or the 8-color display mode, both ends of the resistor circuit of the reference voltage generation circuit 89 are coupled to the same power source (in the case of the integrated reference voltage generation circuit 30), or the power source Is disconnected (in the case of the integrated reference voltage generation circuit 70). At this time, the MUX 81 selects partial display mode input data or 8-color display mode input data as output data.
Therefore, the integrated reference voltage generating circuit according to the present invention occupies a smaller area than the prior art.

The above are preferred embodiments of the present invention, and do not limit the scope of the present invention. Therefore, any modifications or changes that can be made by those skilled in the art, which are made within the spirit of the present invention and have an equivalent effect on the present invention, shall belong to the scope of the claims of the present invention. To do.

The system and method for generating a reference voltage according to the present invention can reduce power consumption and / or compensate for charge injection effects. The present invention is suitable for a display system such as a panel display.

It is explanatory drawing showing the reference voltage generation circuit hung up by US Patent 6,839,043. It is a timing diagram showing operation of the conventional reference voltage generation circuit. It is explanatory drawing showing the integrated type reference voltage generation circuit by Example 1 of this invention. FIG. 6 is a timing diagram of an integrated reference voltage generation circuit according to the present invention. It is an equivalent circuit diagram of a pixel. It is explanatory drawing showing the charge injection effect. It is explanatory drawing showing the integrated type reference voltage generation circuit by Example 2 of this invention. It is explanatory drawing showing the display system using the integrated type reference voltage generation circuit by this invention.

Explanation of symbols

10, 30, 70, 89 Reference voltage generation circuit 12 Resistor string 32 Resistor circuit 34, 84 Control circuit 41, 42 Switch circuit 50 Pixel 80 Display system 81, 82 MUX
83 Buffer 85 Timing controller 87 DAC
AD Node Cgd Parasitic Capacitor Cst Storage Capacitor Clc Liquid Crystal Capacitor R1-7, Rd1-63 Voltage Dividing Resistor SW1-4, SW11-16 Switch

Claims (20)

A resistance circuit including a plurality of resistors connected in series;
A first switch coupled via a first resistor between a first end of the resistor circuit and a first power source;
A second switch coupled via a second resistor between a first end of the resistor circuit and a second power source;
A third switch coupled to the second end of the resistor circuit via a third resistor ;
A fourth switch coupled to the second end of the resistor circuit via a fourth resistor ;
An integrated reference voltage generation circuit including a control circuit for controlling the first switch, the second switch, the third switch, and the fourth switch is provided. In the power saving mode, both ends of the resistor circuit are first A system for generating a reference voltage , wherein the switch is controlled to be connected to either one of a power source and a second power source . Wherein both the first power supply and the second power supply system is a voltage source, the voltage level of the first power source system for generating a reference voltage according to claim 1, wherein a lower than the voltage level of the second power supply. 3. The system for generating a reference voltage according to claim 2, wherein the second power source in the system is a positive voltage source . The system of claim 1, wherein the third switch in the system is coupled to a first power source. The system of claim 1, wherein the fourth switch in the system is coupled to a second power source. The system of claim 2, wherein the third switch is coupled to a first power source and the fourth switch is coupled to a second power source. 2. The system for generating a reference voltage according to claim 1, wherein the first switch and the third switch are N-type transistors, and the second switch and the fourth switch are P-type transistors. The system further includes:
A fifth switch coupled between the first end and the first resistor and second resistor of said of said resistor circuit,
System for generating a reference voltage according to claim 1, characterized in that it comprises a sixth switch coupled between the third resistor and the fourth resistor and a second end wherein said resistor circuit. A system for generating a reference voltage,
A resistance circuit including a plurality of resistors connected in series;
A first switch coupled via a first resistor between a first end of the resistor circuit and a first power source;
A second switch coupled via a second resistor between a first end of the resistor circuit and a second power source;
A third switch coupled to the second end of the resistor circuit via a third resistor ;
A fourth switch coupled to the second end of the resistor circuit via a fourth resistor ;
A first switch of said, and a second switch, a third switch, and a integrated reference voltage generating circuit and a control circuit for controlling the fourth switch, in the power saving mode, the both ends of the resistor circuit The switch is controlled to be connected to either one power source or the second power source,
Furthermore, a multiplexer that selects output data from input data in various operation modes;
A digital / analog converter (DAC) coupled to a multiplexer and an integrated reference voltage generation circuit for processing input data of a full-tone display image;
System for generating a reference voltage, characterized in that it is used to display an image and a control circuit which sends a signal to the integrated reference voltage generating circuit and the multiplexer in accordance with the system operation mode. 10. The system for generating a reference voltage according to claim 9, wherein the multiplexer selects output data of the system from input data of full gradation mode, partial display mode or 8-color display mode. The system for generating a reference voltage according to claim 9, further comprising a buffer coupled between the DAC and the multiplexer. 12. The system for generating a reference voltage according to claim 11, wherein the system further comprises a timing controller coupled between a buffer, a control circuit, and an integrated reference voltage generation circuit. The system for generating a reference voltage according to claim 9, further comprising a pixel display device and a reference voltage generation circuit provided in the pixel display device. The system of claim 13, wherein the pixel display is an active matrix liquid crystal display (AMLCD). Providing a resistance circuit including a plurality of resistors connected in series;
When displaying an image in all gradations, the first end of the resistor circuit is coupled to the first power source, the second end is coupled to the second power source,
When displaying an image in a power-saving manner, the first and second ends of the resistance circuit include a step of coupling to either the first power source or the second power source. How to generate voltage. When displaying the images in the power saving mode, generating a first end and a reference voltage according to claim 15, characterized in that it comprises from second end both voltage coupling to the lower voltage source of said resistor circuit how to. When an image is to be displayed on all gradations manner, the first end of said resistor circuit to a positive voltage source, and characterized in that it comprises from coupling to the voltage source of the second end lower voltage of said resistor circuit 16. A method for generating a reference voltage according to claim 15. The step of coupling a different supply said first end and a second end, the via when displaying an image in the entire gradation method, in order to compensate for the charge injection effect, the a first end first resistance of said resistor circuit 16. The method of generating a reference voltage according to claim 15, further comprising coupling the second end of the resistor circuit to the second power source via the second resistor in the first power source. The step of coupling the first end and the second end to different power sources includes the step of connecting the first end of the resistor circuit to the positive voltage source via the first resistor when displaying an image in all gradations. 19. A method for generating a reference voltage according to claim 18, comprising coupling the end via a second resistor to a lower voltage source . 16. The method of generating a reference voltage according to claim 15, further comprising the step of providing to the DAC a voltage that occurs between two adjacent resistors.