JP4225451B2 - Overcurrent protection method, power supply device and image forming apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention implements an overcurrent protection control of a switching power supply device that switches a switching circuit inserted on the primary side of the transformer in response to a PWM pulse to generate a desired voltage on the secondary side of the transformer. The present invention relates to a power supply device and an image forming apparatus incorporating the same.
[0002]
[Prior art]
  For example, commercial AC is input, the rectified and smoothed DC voltage is switched at a high frequency (for example, around 100 KHz), applied to the primary winding of the transformer, and the voltage induced in the secondary winding of the transformer is rectified. Switching power supplies that output a DC voltage are used in many electrical devices. The output voltage of the power supply is stabilized to a constant voltage by detecting this and controlling the switching ratio, that is, the duty of the PWM pulse. As a method for performing this control, conventionally, switching ON / OFF control using an analog circuit has been performed. In general, in a switching power supply, the operation mode of the power supply circuit may be changed in accordance with fluctuations in the input voltage or load current in order to optimize control. The conventional analog method has a feature that a plurality of control circuits as hardware must be prepared for switching the operation mode, and the circuit configuration becomes extremely complicated. Recently, this has been solved by performing digital control, for example, using a digital signal processor (DSP).
[0003]
  In the PWM control power supply device disclosed in Japanese Patent Laid-Open No. 2000-14144, the current value flowing through the output circuit on the secondary side of the transformer is detected, and when the detected value exceeds a predetermined value, switching is forcibly stopped. And an AND gate inserted in a signal line for supplying a PWM pulse generated by the DSP to the switching driver, and a reset circuit for resetting the latch circuit when switching is turned off. The latch circuit is set, and the AND gate is closed with the output at the time of setting, and the reset circuit resets the latch circuit in synchronization with the subsequent change of the PWM pulse to the switch-on level. The overcurrent protection that turns off the switching on the primary side of the transformer in response to the overcurrent on the secondary side of the transformer is a pulse-by-pulse overcurrent protection that is performed during the switching on period within one cycle of the PWM pulse. . The output circuit has another set of current detection circuit and voltage detection circuit, and these detection signals are digitally converted with a control period longer than the period of the PWM pulse and read into the DSP to determine the duty of the PWM pulse. To be referenced.
[0004]
[Problems to be solved by the invention]
  However, a circuit for detecting the value of the current flowing in the output circuit for pulse-by-pulse overcurrent protection is provided on the secondary side of the transformer. Although it can be detected without delay of overcurrent protection, it is provided on the secondary side of the transformer, so that a level shift occurs in the current detection signal, and the current value flowing through the switching element on the primary side is accurately determined. There was a problem that it could not be detected. This impairs the reliability of pulse-by-pulse overcurrent protection.
[0005]
  In addition, since the switching driver on the primary side of the transformer and the overcurrent detection circuit provided on the secondary side and the DSP are connected by an AND gate, a set circuit, and a reset circuit, circuit connection is complicated.
[0006]
  The present invention detects the overcurrent on the primary side even in the digital control system, and is not affected by the level shift generated on the primary side and the secondary side of the transformer, and improves the reliability of the overcurrent protection of the power supply device. The first purpose is to simplify the connection between the overcurrent detection circuit and a digital control circuit such as a DSP, and to enable high-speed control for digital control. Switching pulse of the switching power supply (frequency 100 kHz) A second object is to perform pulse-by-pulse control capable of stopping and restarting the power supply every time. The third object is to provide a switching power supply with a plurality of output power systems with high reliability of overcurrent protection, and the fourth object is to simplify the connection between the power supply circuit and the DSP, In addition to these, a fifth object is to provide overcurrent protection for each output system. A sixth object is to make the power supply device of the image forming apparatus highly reliable in overcurrent protection.
[0007]
[Means for Solving the Problems]
  (1) Transformer (TR11), primary side circuit (DRIVE11, FET11) that supplies switching power to the primary winding of the transformer in response to PWM pulses, rectifies the voltage generated at the secondary winding of the transformer, and loads A digital signal processing device including a secondary circuit (D11, D12) for supplying power to the power supply, a digital processing pulse generator (65) for generating the PWM pulse, and a CPU (61) for supplying data defining the PWM pulse to the digital processing pulse generator (65) (48), comprising a power supply device (41),
  The on-current of the primary circuitCurrent detectionThrough the resistor (R11)To constant voltage (Vc) A resistor different from the current detection resistor (R12) And diode (D13) The other resistance is connected to the current detection resistor via the constant voltage. (12) And diode (D13) A voltage proportional to the voltage betweenApplied to the light emitting driver (Tr11) energizing the light emitting element of the photocoupler (49) including the light emitting element (LD11) and the photoelectric conversion element (PT41),TheLight reception signal of photoelectric conversion element (PT41)OverAs a current signal (PDPINT = L), it is given to the digital signal processing device (48), and the pulse generator (65) of the digital signal processing device (48) responds to the overcurrent signal (PDPINT = L). Overcurrent protection method to stop the switching-on output(FIGS. 4 to 13).
[0008]
  In addition, in order to make an understanding easy, the code | symbol of the corresponding element or the corresponding matter of the Example shown in drawing and mentioned later in parentheses is added for reference. The same applies to the following.
[0009]
  Action and effect
  According to this, the on-current of the primary circuit of the transformer (TR11) is detected, and when it is an overcurrent, the pulse generator (65) stops its switching-on output. Since the primary side current detection signal can be obtained without level shift, the reliability is high.ExcessCurrent protection can be easily realized. The primary side circuit and digital signal processing device (48) are isolated by photocoupler (49), and there is no potential interference between them, and the reliability is high.ExcessCurrent protection can be easily realized. Since the pulse generator (65) stops switching-on output in response to the overcurrent signal, the connection between the power supply circuit and the digital signal processor (48) is simplified.
[0010]
  While the on-current of the primary circuit is low, the voltage of the resistor (R11) through which it flows is low, and the voltage at the control signal input terminal of the light-emitting driver (Tr11) propagates forward in the diode (D13) in that direction. The current flows out, so that the voltage of the resistor (R11) is as low as that of the resistor (R11), and the light emitting driver (Tr11) does not pass through the light emitting element (LD11).
[0011]
  When the on-current of the primary circuit becomes excessive, the voltage of the resistor (R11) through which it flows increases, but this is applied in the reverse direction to the diode (D13), so the on-current of the primary circuit is the light emitting driver (Tr11 ) Does not flow into the control signal input terminal. That is, the diode (D13) prevents an excessive current or an overvoltage from being applied to the control signal input terminal of the light emitting driver (Tr11). However, since a high voltage of the resistor (R11) is applied to the cathode side of the diode (D13), current outflow from the control signal input terminal of the light emitting driver (Tr11) to the resistor (R11) due to application of the constant voltage (Vc) Then, the voltage at the control signal input terminal rises, and in response thereto, the light emitting driver (Tr11) energizes the light emitting element (LD11), and the light emitting element (LD11) emits light.
[0012]
  A relatively simple electric circuit around the light emitting driver (Tr11) causes a binary voltage change at the control signal input terminal of the light emitting driver (Tr11) to indicate whether the on-current of the primary side circuit is excessive, In addition, no overvoltage is applied to the light emitting driver (Tr11).
[0013]
DETAILED DESCRIPTION OF THE INVENTION
  (2)The overcurrent signal (PDPINT = L) Is the digital signal processing device (48) An interrupt signal for the pulse generator (65) Stops the switching-on output in response to the interrupt signal, and then the CPU restarts the pulse output by the pulse generator, and the digital signal processor performs pulse-by-pulse switching power supply of the primary circuit. The protection control is performed as described in (1) above.Overcurrent protection method.
[0014]
  According to this, the on-current of the primary circuit of the transformer (TR11) is detected, and when it is an overcurrent, the pulse generator (65) stops its switching-on output. Since the primary-side current detection signal can be obtained without level shift, highly reliable pulse-by-pulse overcurrent protection can be easily realized. The primary circuit and digital signal processor (48) are isolated by photocoupler (49) with respect to current conduction, so there is no potential interference between them, and pulse-by-pulse overcurrent with high reliability. Protection can be realized easily. Since the pulse generator (65) stops switching-on output in response to the overcurrent signal, the connection between the power supply circuit and the digital signal processor (48) is simplified.
[0015]
  (3) Transformer (TR11), primary side circuit (DRIVE11, FET11) that supplies switching power to the primary winding of the transformer in response to PWM pulses, rectifies the voltage generated at the secondary winding of the transformer, and loads A digital signal processing device including a secondary circuit (D11, D12) for supplying power to the power supply, a digital processing pulse generator (65) for generating the PWM pulse, and a CPU (61) for supplying data defining the PWM pulse to the digital processing pulse generator (65) (48), comprising a power supply device (41),
  The on-current of the primary circuitCurrent detectionThrough the resistor (R11)To constant voltage (Vc) A resistor different from the current detection resistor (R12) And diode (D13) The other resistance is connected to the current detection resistor via the constant voltage. (R12) And diode (D13) A voltage proportional to the voltage betweenThe digital signal processing device (48), the digital signal processing device converts the voltage into digital data, the digital data is more than a set valueOverburdenGenerates a current signal (PDPINT = L)The pulse generator stops the switching-on output in response to the overcurrent signal.(72-75 in Fig. 15), overcurrent protection method(FIGS. 14 to 18).
[0016]
  According to this, the primary-side on-current detection means (R11) converts the primary-side current of the transformer (TR11) into a voltage, and the A / D conversion means (72) of the digital signal processing device (48) The voltage is converted into digital data, and the comparison means (73) generates an overcurrent signal (PDPINT = L / PDPINT1 = L) when the value represented by the digital data exceeds the set value, and the pulse generator (65) In response, the switching-on output is stopped. Since the voltage, which is a primary-side current detection signal, can be obtained without level shift, highly reliable pulse-by-pulse overcurrent protection can be easily realized. Since the pulse generator (65) stops switching-on output in response to the overcurrent signal, the connection between the power supply circuit and the digital signal processor (48) is simplified. Since the A / D conversion means (72) and the comparison means (73) are provided in the digital signal processing device (48), the primary circuit is simplified, and the circuit between the power supply circuit and the digital signal processing device (48) is simplified. Connection is simplified.
[0017]
  While the on-state current of the primary side circuit is low, the voltage of the resistor (R11) through which it flows is low, and the voltage at the voltage dividing end of the resistance voltage divider (R12-R14) propagates forward in the diode (D13). A current flows in this direction, which is as low as the voltage of the resistor (R11). When the on-current of the primary circuit becomes excessive, the voltage of the resistor (R11) through which it flows increases, but this is applied in the reverse direction to the diode (D13), so the on-current of the primary circuit is a resistance voltage divider circuit. Does not flow into the partial pressure end of (R12-R14). That is, the diode (D13) prevents an excessive current or an overvoltage from being applied to the voltage dividing end of the resistance voltage dividing circuit (R12-R14). But,diode (D13)Since a voltage with a high resistance (R11) is applied to the cathode side of the resistor, the outflow of current from the voltage dividing end of the resistance voltage dividing circuit (R12-R14) to the resistance (R11) due to the application of the constant voltage (Vc) stops. The voltage at the voltage dividing end rises.
[0018]
  With a relatively simple electric circuit, a voltage corresponding to the on-current level of the primary side circuit appears in the resistance voltage dividing circuit (R12-R14), and an overvoltage is generated in the resistance voltage dividing circuit (R12-R14). There is no participation.
[0019]
  (4) After the CPU (61) responds to the overcurrent signal (PDPINT = L) and the pulse generator (65) stops switching on output, the pulse generator (65) generates a PWM pulse. , Above (3) Overcurrent protection method.
[0020]
  Thus, energization of the pulse-by-pulse and overload protection for stopping the energization in response to the overcurrent detection during the PWM pulse switching-on period and outputting the PWM pulse of the next cycle can be realized. In other words, pulse-by-pulse energization protection control with high energization stability and overload protection function can be realized.
[0021]
  (5) The pulse generator (65) sets the PWM pulse output port to high impedance in response to the overcurrent signal (PDPINT = L) and holds it; the CPU (61) holds the overcurrent signal (PDPINT). = L), interrupt processing is started, and after this interrupt processing stops the switching-on output, the high-impedance holding of the pulse generator is released and PWM pulses are output to the register. The overcurrent protection method according to any one of (1) to (4) above.
[0022]
  The PWM pulse has a high frequency of, for example, 100 KHz. The pulse generator (65) of the digital signal processing device (48) is, for example, an event manager of a DSP, and an overcurrent signal (PDPINT = L) is generated. After a delay of 3 to 4 clock cycles of the operation frequency of 61), the PWM pulse output port is set to high impedance (PWM pulse output cutoff) and this is held. This process is very fast. Therefore, the primary circuit is switched off substantially without delay.
[0023]
  However, in response to the overcurrent signal (PDPINT = L), the CPU (61) proceeds to interrupt processing, where data for PWM pulse output is set in the register of the pulse generator (65). After the overcurrent signal (PDPINT = L) is generated, a time of several μsec elapses until the data for PWM pulse output is set in the pulse generator (65) by the above-described soft interrupt program.
[0024]
  This causes a delay in the output of the PWM pulse (switch-on level) exceeding about one half of one cycle of the 100 KHz PWM pulse, and this period overlaps with the off period within one cycle of the PWM pulse. Even if the ON output of one pulse is cut off by the overcurrent protection of the pulse, the PWM pulse output of the PWM pulse output before and after the OFF period following the original ON period in which the ON output is cut off during one cycle of the PWM pulse elapses. Therefore, a new period of pulse energization is started by setting the data for this purpose. That is, the output of the PWM pulse is restarted from the next period in a manner that is substantially continuous with the previous period.
[0025]
  Therefore, it is not necessary to insert a gate for PWM pulse interruption, a latch for holding interruption, and a reset circuit for releasing it between the power supply circuit and the digital signal processing device (48). Connection with the signal processing device (48) is simplified.
[0026]
  (6) Transformer (TR11);
  Primary circuit (DRIVE11, FET11) that supplies switching power to the primary winding of the transformer in response to PWM pulses;
  Secondary circuit that rectifies the voltage generated in the secondary winding of the transformer and supplies power to the load (D11, D12);
  The on-current of the primary circuitDetect current detection resistor(R11);
  Constant voltage line (Vc) And a resistor different from the current detection resistor. (R12) And diode (D13) A series circuit that passes the other resistor and the diode from the constant voltage line in this order and applies the constant voltage of the constant voltage line toward the current detection resistor in an energizable manner. (R12, D13) ;
  Light emitting element (LD11) And photoelectric conversion element (PT41) A photoelectric conversion signal of the photoelectric conversion element due to light emission of the light emitting element is an overcurrent signal (PDPINT = L / PDPINT1 = L) Photocoupler generated as (49) ;
  Said another resistance (R12) And diode (D13) When the voltage between is increased, the light emitting element (LD11) LED driver that emits light when energized (Tr11) ;and,
  A digital signal processor (48) including a pulse generator (65) that generates the PWM pulse and stops the PWM pulse output in response to the overcurrent signal, and a CPU that supplies the pulse generator with data for PWM pulse output. );
WithPower supply(FIGS. 4 to 13).
[0027]
  According to this, the primary side on-current detection means (R11) converts the primary side current of the transformer (TR11) into a voltage,The electricityWhen the pressure exceeds the set value, an overcurrent signal (PDPINT = L / PDPINT1 = L) is generated, and the pulse generator (65) stops switching-on output in response. Since the voltage that is the primary side current detection signal can be obtained without level shift, pulse-by-pulse overcurrent protection with high reliability can be easily realized. Since the pulse generator (65) stops switching-on output in response to the overcurrent signal, the connection between the power supply circuit and the digital signal processor (48) is simplified.
[0028]
  Primary circuit and digital signal processor (48)photoSince the couplers (49, 50) are isolated from each other in terms of current flow, there is no potential interference between them, and pulse-by-pulse overcurrent protection with high reliability can be easily realized. The connection of the digital signal processor (48) with the overcurrent signal (PDPINT = L / PDPINT1 = L, PDPINT2 = L) lines is simplified.
[0029]
  (7)The power supply device includes the transformer (TR11 / TR21) Primary side circuit (DRIVE11, FET11 / DRIVE21, FET21) Secondary side circuit (D11, D12 / D21, D22) , Current detection resistor (R11 / R21) , Series circuit (R12, D13 / R22, D23) , Light emitting element (LD11 / LD21) And light emitting driver (Tr11 / Tr21) First and second circuits each comprising (46,47) A photocoupler (49,50) Photoelectric conversion element (PT41) Is a light-emitting element of the first and second circuits (D11 / D21) Receiving light from any of the above;The pulse generator (65) of the digital signal processing device (48) is:Give to first and second circuitGenerating first and second PWM pulses, andPhotoelectric conversion element (PT41) FromOver current signalissue(PDPINT = L)According toIn response, the first and second PWM pulse outputs are stopped, and the CPU receives data for the first and second PWM pulse outputs.The pulse generator(65)IngiveAs described in (6) abovePower supply (4 to 11).
[0030]
  According to this, the first circuit (46) and the second circuit (47) can be controlled by a set of digital signal processing devices (48), and power can be supplied simultaneously to separate loads from them. With respect to each circuit (46, 47), the operation and effect described in (6) above can be realized.
[0031]
  (8)The power supply device includes the transformer (TR11 / TR21) Primary side circuit (DRIVE11, FET11 / DRIVE21, FET21) Secondary side circuit (D11, D12 / D21, D22) , Current detection resistor (R11 / R21) , Series circuit (R12, D13 / R22, D23) ,Photo coupler (49/50) And light emitting driver (Tr11 / Tr12) First and second circuits each comprising (46,47) Comprising:The pulse generator (65) of the digital signal processing device (48) is:Give to first and second circuitGenerate first and second PWM pulsesFrom the first circuitIn response to the first overcurrent signal (PDPINT1 = L), the first PWM pulse output is stopped,From the second circuitThe CPU stops the second PWM pulse output in response to the second overcurrent signal (PDPINT2 = L), and the CPU stores data for the first and second PWM pulse outputs.To the pulse generatorgiveAs described in (6) abovePower supply(Fig. 4, Fig. 12, Fig. 13).
[0032]
  According to this, the first circuit (46) and the second circuit (47) can be controlled by a set of digital signal processing devices (48), and power can be supplied simultaneously to separate loads from them. With respect to each circuit (46, 47), the operation and effect described in (6) above can be realized individually. In the above (7), when one of the first circuit (46) and the second circuit (47) is overloaded on the primary side, the primary side energization is interrupted in both circuits, but this embodiment (8) Then, when one side becomes a primary overload, the primary side energization is cut off, but the other energization continues. The independence of the first circuit (46) and the second circuit (47) is high.
[0033]
  (9) Transformer (TR11);
  Primary circuit (DRIVE11, FET11) that supplies switching power to the primary winding of the transformer in response to PWM pulses;
  Secondary circuit that rectifies the voltage generated in the secondary winding of the transformer and supplies power to the load (D11, D12);
  The on-current of the primary circuitDetect current detection resistor(R11);
  Constant voltage line (Vc) And a resistor different from the current detection resistor. (R12) And diode (D13) A series circuit that passes the other resistor and the diode from the constant voltage line in this order and applies the constant voltage of the constant voltage line toward the current detection resistor in an energizable manner. (R12, D13) ;and,
  Said another resistance (R12) And diode (D13) A / D conversion means for converting voltage proportional to the voltage between the two to digital data (72) , The value represented by the digital dataComparing means (73) for generating an overcurrent signal (PDPINT1) when the value exceeds a set value, a pulse generator (65) for generating the PWM pulse and stopping the PWM pulse output in response to the overcurrent signal, and Digital signal processing device including a CPU for supplying data for PWM pulse output to a pulse generator (48);
WithPower supply(FIGS. 14 to 18).
[0034]
  According to this, the primary-side on-current detection means (R11) converts the primary-side current of the transformer (TR11) into a voltage, and when the comparison means exceeds the set value, the overcurrent signal (PDPINT = L / PDPINT1 = L) and the pulse generator (65) stops the switching-on output in response. Since the A / D conversion means (72, 74) and the comparison means (73, 75) are provided in the digital signal processing device (48), the primary circuit is simplified, and the power supply circuit and the digital signal processing device (48) are provided. The connection between is further simplified.
[0035]
  (10)The power supply device includes the transformer (TR11 / TR21) Primary side circuit (DRIVE11, FET11 / DRIVE21, FET21) Secondary side circuit (D11, D12 / D21, D22) , Current detection resistor (R11 / R21) , Series circuit (R12, D13 / R22, D23) And comparison means (73/75) First and second circuits each comprising (46,47) Comprising:The pulse generator (65) of the digital signal processing device (48) is:Give to first and second circuitGenerate first and second PWM pulses to generate first and secondFrom the circuitThe first and second PWM pulse outputs are stopped in response to any of the overcurrent signals, and the CPU outputs data for the first and second PWM pulse outputs.To the pulse generatorgiveAs described in (9) abovePower supply(Fig. 17).
[0036]
  According to this, the first circuit (46) and the second circuit (47) can be controlled by a set of digital signal processing devices (48), and power can be supplied simultaneously to separate loads from them. With respect to each circuit (46, 47), the operation and effect described in (9) above can be realized.
[0037]
  (11)The power supply device includes the transformer (TR11 / TR21) Primary side circuit (DRIVE11, FET11 / DRIVE21, FET21) Secondary side circuit (D11, D12 / D21, D22) , Current detection resistor (R11 / R21) , Series circuit (R12, D13 / R22, D23) And comparison means (73/75) First and second circuits each comprising (46,47) Comprising:In the digital signal processor (48), the pulse generator (65, 71)Give to first and second circuitGenerating first and second PWM pulses;From the first circuitIn response to the first overcurrent signal, the first PWM pulse output is stopped,From the second circuitThe CPU stops the second PWM pulse output in response to the second overcurrent signal, and the CPU stores data for the first and second PWM pulse outputs.To the pulse generatorgiveAs described in (9) abovePower supply(FIGS. 14-16, 18).
[0038]
  According to this, the first circuit (46) and the second circuit (47) can be controlled by a set of digital signal processing devices (48), and power can be supplied simultaneously to separate loads from them. With respect to each circuit (46, 47), the functions and effects described in (9) above can be realized individually. In the above (10), when one of the first circuit (46) and the second circuit (47) is overloaded on the primary side, both circuits cut off the primary side energization. Then, when one side becomes a primary overload, the primary side energization is cut off, but the other energization continues. The independence of the first circuit (46) and the second circuit (47) is high.
[0039]
  (12)The pulse generator (65,71) Is the first circuit (46) First overcurrent signal from (PDPINT1) In response to the first PWM pulse output (PWM11) Stop the second circuit (47) Second overcurrent signal from (PDPINT2) First and second PWM pulse outputs in response to (PWM11, PWM21) According to (8) or (11) abovePower supply(FIGS. 13 and 16).
[0040]
  (13) The first circuit (46) is a high power power supply circuit that outputs a high DC voltage (24V) for supplying power to a high load that consumes a large amount of power, and the second circuit (47) has a low power consumption. (7), (8), which is a low power power supply circuit that outputs a low DC voltage (5 V, 5 VE) for supplying power to the control circuit and the elements.(10),The power supply device according to (11) or (12).
[0041]
  According to this, all the required power can be fed simultaneously to a device or an electric circuit including a control circuit and an element having a high load and a low power consumption with a large power consumption.
[0042]
  (14) The second circuit (47) has a voltage output terminal (5V) at which the load is turned off at the time of energy saving standby, and an energy saving standby power supply terminal (5VE) at which the load is continuously turned on at the time of energy saving standby. (13) The power supply device.
[0043]
  All the required power can be supplied to a device or an electric circuit having an energy saving standby function including a control circuit and an element having a high power consumption and a high load and a low power consumption.
[0044]
  (15) After the CPU (61) responds to the overcurrent signal (PDPINT / PDPINT1, PDPINT2) and the pulse generator (65/65, 71) stops switching on output, the pulse generator The PWM pulse generation is resumed; the power supply device according to (6), (7), (8), (9), (10), (11), (12), (13) or (14).
[0045]
  As a result, energization is stopped in response to overcurrent detection in the PWM pulse switching-on period, and pulse-by-pulse energization and overload protection for outputting the PWM pulse of the next cycle are realized. That is, the pulse-by-pulse energization protection control with high energization stability and overload protection function is realized.
[0046]
  (16) The pulse generator (65/65, 71) maintains the PWM pulse output port as a high impedance in response to the overcurrent signal (PDPINT = L / PDPINT1 = L, PDPINT2 = L); The CPU (61) starts an interrupt process in response to the overcurrent signal, and by this interrupt process, after the pulse generator stops switching-on output, the high-impedance holding of the pulse generator is canceled and the Data for PWM pulse output is set in the register; the power supply device according to (15) above.
[0047]
  The PWM pulse has a high frequency of, for example, 100 KHz, and the pulse generator (65/65, 71) of the digital signal processing device (48) is, for example, a DSP event manager. ) After a delay of 3 to 4 clock cycles of the operating frequency, the PWM pulse output port is set to high impedance and an output inhibition flag (1 bit data) is set (H = 1) to set the PWM pulse cycle and pulse. Clear the register that stores the data that determines the duty. This process is very fast. Therefore, the primary circuit is switched off substantially without delay.
[0048]
  However, the CPU 61 proceeds to the interrupt process in response to the overcurrent signal, where the output prohibit flag of the pulse generator is canceled (cleared to 0), and the PWM generator outputs the PWM pulse to the register of the pulse generator. Set the data. There is a time delay of several microseconds from the occurrence of the overcurrent signal to the start of the execution of the above-described soft interrupt program, and several microseconds for the pulse generator to restart the PWM pulse output in the interrupt processing. The time elapses.
[0049]
  This causes a delay in the output of the PWM pulse (switch-on level) exceeding about one half of one cycle of the 100 KHz PWM pulse, and this period overlaps with the off period within one cycle of the PWM pulse. Even if the ON output of one pulse is interrupted by the overcurrent protection of the pulse, the output of the PWM pulse is restarted from the next one cycle in a manner that is substantially continuous with the previous one cycle.
[0050]
  Therefore, it is not necessary to insert a gate for PWM pulse interruption, a latch for holding interruption, and a reset circuit for releasing it between the power supply circuit and the digital signal processing device (48). Connection with the signal processing device (48) is simplified.
[0051]
  (17) The power supply device (41) according to any one of (6) to (16); and image forming means (42, 43) that is fed from the power supply device and forms an image represented by image data; Including image forming device (PTR).
[0052]
  The power supply device (41) exhibits the actions and effects described in the above (6) to (16), thereby improving the reliability and stability of overload protection of the image forming means (42, 43).
[0053]
  (18) The power supply device (41) according to (14); image forming means (42, 43) for forming an image represented by image data supplied from the power supply device; and the first circuit of the power supply device during energy saving standby Switch means (44) for cutting off the power supply from the (46) to the image forming means (42, 43) and the power supply from the voltage output terminal (5V) of the second circuit (47) to the image forming means (42, 43). ); An image forming apparatus (PTR).
[0054]
  Since the power supply device (41) of (14) above has an energy saving standby power feeding end (5VE), even if the switch means (44) is opened (shut off) for energy saving standby, control that requires power supply even during energy saving standby Power can be supplied to the circuit and the element from the power supply end (5VE), and the energy-saving standby design of the image forming apparatus (PTR) is easy.
[0055]
  (19) The image forming apparatus according to (17) or (18), further comprising a printer controller (20) that converts print information given from outside into image data and gives the image data to the image forming means (43). According to this, print information from a host such as a personal computer or a facsimile can be printed out.
[0056]
  (20) The image forming apparatus according to (17), (18) or (19) further including an original scanner (SCR) that reads an original image, generates image data, and supplies the image data to the image forming means (43). According to this, a document image can be copied.
[0057]
  (21The PWM output port destination that stops output according to the input port destination that has detected overcurrent can be set by software by rewriting the data in the DSP (FIG. 18). (23) or (24) above Switching power supply.
[0058]
  According to this, since the data in the DSP is rewritten to the PWM output port destination where the output is stopped according to the input port destination where the overcurrent is detected, there is no restriction on the wiring layout of the switching power supply board, and it can be freely done. There is an effect that it is possible to set the correspondence between the overcurrent signal input port or the A / D input port to which the current detection signal is applied and the PWM pulse output port.
[0059]
  Also, there is an effect of realizing flexible primary overcurrent protection control. Specifically, when the switching element for basic voltage output generates an overcurrent, not only the switching ON / OFF of the switching element but also the switching ON / OFF of the switching elements of other output voltage circuits are simultaneously stopped. Let When an overcurrent is generated in the switching element of the other output voltage circuit, there is an effect that flexible overcurrent protection control can be performed such that only switching ON / OFF of the switching element is stopped.
[0060]
  Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.
[0061]
【Example】
  -1st Example-
  FIG. 1A shows an outline of an image forming apparatus incorporating a switching power supply device according to an embodiment of the present invention. This image forming apparatus has a color printer PTR and an image scanner SCR, an automatic document feeder ADF, a sorter 11 and others, and is connected from a host PCa such as a personal computer (hereinafter referred to as a PC) to an IEEE1284-I / This is a system configuration in which print data (image information) is given through F and printed out (image output). The image forming apparatus shown in FIG. 1A is a digital color copying machine having a composite function, and can itself generate a copy of a document.
[0062]
  FIG. 1B shows an outline of the mechanism of a printer PTR that forms part of the digital color copying machine shown in FIG. The printer PTR of this embodiment is an electrophotographic laser scanning color printer, and includes a printer mechanism, a paper feeding device (bank), a double-side paper feeding device, and a post-processing device (sorter) 11. The laser scanner 3 of the printer PTR is supplied with image data divided into color components of Bk (black), Y (yellow), M (magenta), and C (shear) for each color unit. Each color unit is one image forming unit.
[0063]
  At the time of monochromatic recording, image data of one of the four colors is given to the laser scanner 3. The photosensitive member 1 is rotationally driven at a constant speed, charged by the main charger 2, and the charged position is adjusted to an appropriate potential by the quenching lamp QL. The laser scanner 3 scans and projects the laser modulated by the image data on the charging surface. Thereby, an electrostatic latent image corresponding to the image data is formed on the photoreceptor 1. The electrostatic latent image is developed by a developing device (Bk) having a developing toner of a color corresponding to an image formation designated color (for example, Bk) of the rotation positioning type developing device 4 to become a visible image, that is, a toner image. . The toner image is transferred to the transfer belt 6 by the transfer charger 5 and transferred to the transfer paper fed by the registration roller 7 by the transfer separation charger 8. The transfer paper carrying the toner image is transferred by the transport belt 9. It is sent to the fixing device 10.
[0064]
  The fixing device 10 fixes the toner image on the transfer paper to the transfer paper by heating and pressing. After the fixing, the transfer paper is discharged to the sorter 11. The surface of the photoreceptor after the transfer of the toner image is cleaned by the cleaning device 12. The surface of the transfer belt 6 that has been transferred is wiped with a cleaning blade 13. Reference numeral 14 denotes a reflection type optical sensor called a P sensor that detects the toner density on the surface of the photoreceptor, 15 denotes a reflection type optical sensor that detects a mark indicating the reference position of the transfer belt 6, and 16 denotes the temperature of the fixing roller. It is a temperature sensor to detect.
[0065]
  When two or more colors are overlaid (most typical is full-color recording), the above-described toner image formation on the photoreceptor 1 and transfer onto the transfer belt 6 are repeated for each color and transferred. The toner images of the respective colors are transferred on the belt 6 in a superimposed manner, and transferred onto the transfer paper after completing the overlapping transfer for the required colors.
[0066]
  FIG. 2 shows an outline of the electrical system of the image forming apparatus shown in FIG. The printer controller 20 is connected to a color printer PTR, an operation panel OPB that performs display for the operator and control of function setting input from the operator, a scanner SCR, an automatic document feeder ADF, and an IEEE 1284 Centro I / F 30 connected to the personal computer PCa. ing.
[0067]
  In FIG. 2, the elements of the printer PTR shown in FIG. 1 that require power supply for the progress of the image forming process are collectively shown as the engine load 42, and control of the image forming process and other controls in the printer are performed. The device is shown as an engine controller 43.
[0068]
  The printer controller 20 includes a CPU 21 as a main processor, an ASIC (Application Specific IC) 22 that performs system bus control and image processing, a ROM 23 that stores a control program for the CPU 21, and an NVRAM 24 that can retain data even when the power is turned off. , A DRAM (image memory) 25 capable of temporarily storing received data from the host PCa via the IEEE 1284 Centro I / F 30 and storing image image data formed based on the received data; and image data representing a character shape A font ROM 26 for converting character data to image data stored at the time of image formation, an operation panel I / F 27 for controlling / communication of the operation panel OPB, a scanner I / F 28, an engine controller 43, and an image data transmission. When a change is detected by detecting a change in the HLH signal given to the IEEE1284-I / F 30 from the host PCa and the IEEE1284-I / F 30 capable of communication conforming to the engine I / F29 and IEEE1284 A host ON / OFF detection circuit 31 that informs the CPU 21 via the ASI 22 is included.
[0069]
  The host ON / OFF detection circuit 31 changes the HLH signal of the host PCa (H: host power ON / L: host power OFF) from L (host power OFF) to H (host power ON) (host power ON) ) And when changing from H to L (the host power supply changes to OFF), this is notified to the CPU 21 via the ASI 22.
[0070]
  The printer controller 20 analyzes the print data which is image information from the host PCa which is an external device and a command for instructing printing, develops a bitmap into a state where the print data can be printed as output image data, and analyzes the print mode from the command. The operation is determined. The print data and command are received through the IEEE1284-I / F 30 and operated. Also, print data, document reading data, output image data processed for output, and compressed data obtained by compressing them are transferred to the host PCa via the printer controller 20 and stored or generated in the machine. can do.
[0071]
  The document scanner SCR condenses the reflected light of the lamp irradiation on the surface of the document on a light receiving element by a mirror and a lens. The light receiving element (CCD in this embodiment) is in a sensor board unit (hereinafter simply referred to as SBU) in the scanner SCR, and an image signal converted into an electrical signal in the CCD is a digital signal, After being converted into the read image data, it is output to the printer controller 20. The automatic document feeder ADF mounted on the scanner SCR feeds and discharges the document to and from the scanner SCR.
[0072]
  The printer controller 20 includes an image processing ASIC 22 that performs system bus control, image memory access control, control for image formation from the DRAM 25, and the like. The read image data of the scanner SCR is transferred to the ASIC 22, and the ASIC 22 corrects signal deterioration due to quantization of the optical system and the digital signal (signal deterioration of the scanner system: distortion of read image data due to scanner characteristics). The image data is written into the DRAM 25. Alternatively, the image data is converted into output image data by a processing system for printer output inside the ASIC 22 and given to the printer PTR via the engine I / F 28.
[0073]
  In other words, the ASIC 22 includes a job for storing the read image data in the DRAM 25 and reusing it, and a job for forming an image on the printer PTR without storing it in the memory. As an example of storing in the DRAM 25, when copying a plurality of original documents, there is a method of operating the scanner SCR only once, storing read image data in the DRAM 25, and reading the stored data a plurality of times. As an example in which the DRAM 25 is not used, when only one original is copied, the read image data may be processed as it is for printer output, so that it is not necessary to write to the DRAM 25.
[0074]
  First, when the DRAM 25 is not used, the ASIC 22 performs image quality processing for converting luminance data from the CCD into area gradation. The signal changed to the area gradation after the image quality processing is given to the printer PTR, and is given to the writing control through the image memory in the printer PTR. In the writing control, post-processing relating to dot arrangement and pulse control for reproducing dots are performed on the image forming unit 3 to form a reproduced image on the transfer paper.
[0075]
  When storing in the DRAM 25, the ASIC 22 performs access control of the DRAM 25, expansion of print data (character code / character bit conversion) of the external host PCa, and compression of image data for effective use of the memory. After data compression, the data is stored in the DRAM 25, and the stored data is read as necessary. The read data is expanded, returned to the original image data, subjected to image quality processing, and output to the printer PTR. That is, a visible image (toner image) is formed on the transfer paper.
[0076]
  In the flow of image data, the composite function of the digital copying machine is realized by the bus control of the ASIC 22. In each job, for example, a copy function and a printer output function, the ASIC 22 controls the allocation of the common bus use right to the scanner SCR, ASIC 22 and printer PTR.
[0077]
  Next, the energy saving mode of the printer PTR and the printer controller 20 will be described. In the printer PTR, there is a switching power supply device 41 that generates DC power from AC commercial power, and the generated DC power is supplied to the engine controller 43, the printer controller 20, and the engine load 42.
[0078]
  Here, if the DC power generated by the switching power supply 41 is +5 V and +24 V that can be controlled ON / OFF by the engine controller 43, and the main SW (not shown) as the main power switch is ON, the DC power is always turned on. + 5VE and + 24V are supplied to the engine controller 43 and the engine load 42, and + 5VE is supplied to the engine controller 43 and the printer controller 20. In normal operation, that is, in operation mode, all of + 5V, + 24V and + 5VE are in the ON state. In the energy saving mode, the switch 44 is turned OFF (OPEN) by the engine controller 43, and the power supply of + 5V and + 24V is stopped. Only a part of the controller 20 and the engine controller 43 is supplied with + 5VE power.
[0079]
  The power + 5VE supplied from the switching power supply 41 to the printer controller 20 is drawn to the power ON / OFF 34 in the printer controller 20. The power ON / OFF 34 includes two power ON / OFF relays (hereinafter simply referred to as power relays) and a relay driver that selectively turns them ON / OFF. A power ON / OFF controller 33 is provided for each relay driver. , ON (switch closed) / OFF (switch open) instruction signal is given. The switch contact piece of each power supply relay is connected to a power supply line to which power supply + 5VE is supplied from the power supply device 41, and power supply lines PS1 and PS2 are connected to the switch contact of each power supply relay.
[0080]
  The power supply line PS1 supplies power to the CPU 21, the ASIC 22, the program ROM 23, the host ON / OFF detection circuit 31, and the key operation detection circuit of the operation panel I / F 27. By this power supply, the host ON / OFF detection circuit 31 indicates that the logical sum of each HLH signal of the host PCa has changed from L to H (the host power supply has changed to ON), and the logical sum has changed from H to L. The CPU 21 can be notified of the change (the host power supply is changed to OFF) via the ASI 22. Similarly, the operation panel I / F 27 can notify the CPU 21 that a key operation has been performed. A signal line and an electric circuit for supplying these notification signals to the CPU 21 of the ASIC 22 are fed from the feed line PS1. Since the CPU 21 and the program ROM 23 are also supplied with power from the power supply line PS1, the CPU 21 operates according to the program in the program ROM 23 as long as the first power supply relay that connects the power supply line PS1 to + 5VE is ON.
[0081]
  When the main power switch for supplying commercial alternating current to the power supply device 41, that is, the main SW is turned on and the power supply device 41 generates power + 5VE, a power-on reset circuit (not shown) in the power ON / OFF 34 generates a reset signal. The power supply ON / OFF 34 resets (initializes) itself, thereby turning on only the first power supply relay connected to the first power supply line PS1. As a result, a power source + 5VE is added to the power source ON / OFF controller 33, CPU 21, ASIC 22, program ROM 23, and operation panel I / F 27 (in the key operation detection circuit), and each performs a power on reset operation to initialize itself. Turn into.
[0082]
  FIG. 3 shows an outline of the circuit configuration of the switching power supply device 41. A 100 V commercial AC voltage is applied to the DC conversion circuit 45 from the AC input terminals IN1 and IN2. The DC conversion circuit 45 includes an input filter that blocks high-frequency noise of the 100V commercial AC line from entering the power supply device 41 and prevents high-frequency noise generated by the power supply device 41 from leaking to the commercial AC line. The AC voltage is applied through this input filter to a rectifying / smoothing circuit including a full-wave rectifying diode bridge DB1 and a smoothing capacitor C1.
[0083]
  Further, the AC voltage is also applied to a starting circuit composed of a resistor R1 and a relay RA1. When an AC voltage is applied, the relay contact between the voltage input terminal Vcc of the digital control unit 48 constituted by the digital signal processor (DSP) of the relay RA1 and the diode D32 connected to the battery B1 is closed. As a result, the digital control unit 48 is activated to output the first PWM pulse to the driver DRIVE 11 of the first power supply circuit 46 and to output the second PWM pulse to the driver DRIVE 21 of the second power supply circuit 47. As a result, the first power supply circuit 46 and the second power supply circuit 47 enter an operating state, and generate voltages of about 24V and about 5V, respectively.
[0084]
  The DC voltage converted by the DC conversion circuit 45 is applied to the primary windings of the transformers TR11 and TR21 of the first power supply circuit 46 and the second power supply circuit 47. When the switching elements FET11 and FET21 are turned on, the primary side ground is connected from the DC conversion circuit 45 through the primary windings, the switching elements, and the current value detection circuits ISEN11 and ISEN21.GCurrent flows through
[0085]
  FIG. 4 shows the configuration of the current value detection circuits ISEN11 and ISEN21. Since the switching element FET11 of the first power supply circuit 46 is for high load output that outputs DC 24V for mainly supplying power to the power load, the two FETs are connected in parallel. The current flowing through the FET 11 flows through the current detection resistor R11, and the voltage of the resistor R11 is proportional to the primary current. A capacitor C12 connected in parallel with the resistor R11 bypasses high frequency noise.
[0086]
  A constant voltage Vc generated by a constant voltage circuit (not shown) connected to a winding (not shown) of the transformer TR11 is added to a series circuit of resistors R12, R13, R14 of the comparison circuit (D13, R12-R14). Between the resistors R12 and R13, the diode D13 is connected to the resistor R11, and the voltage of the resistor 11, that is, the current detection signal is applied to the cathode of the diode D13. A base of a transistor Tr11 that is an LED driver is connected between the resistors R13 and R14. A constant voltage Vc is applied to the series circuit of the resistor R15, the light emitting diode LD11 of the insulating coupler 49, and the resistor R16, and the collector of the transistor Tr11 is connected to the light emitting diode LD11.
[0087]
  The potential between the resistors R12 and R13 of the comparison circuit is approximately the same as the voltage of the resistor 11, that is, the current detection signal level. When the primary winding current of the transformer TR11, that is, the primary current value flowing through the FET 11, is small, the base potential of the transistor Tr11 is low. Therefore, the transistor Tr11 is substantially off and the light emitting diode LD11 does not emit light substantially. When the primary current value flowing through the FET 11 becomes an overcurrent, the potential between the resistors R12 and R13 of the comparison circuit (the voltage of the resistor 11) rises, the base potential of the transistor Tr11 rises, and the transistor Tr11 becomes conductive. The light emitting diode LD11 emits light.
[0088]
  This light illuminates the phototransistor PT41 shown in FIG. 5 in the insulating coupler 49, whereby the phototransistor PT41 turns from off to on. The collector of the phototransistor PT41 is connected to the constant voltage Vcc through the resistor R41, and the signal line connected to the collector is an overcurrent detection signal line, which is a digital control unit (hereinafter referred to as a digital signal processor (DSP)). 48) is connected to the interrupt input port Iint1, so when the primary current of the transformer TR11 of the first power supply circuit 46 exceeds the set value, the overcurrent detection signal line (DSP) The interrupt input port Iint1) is lowered from the high level H (Vcc) to the low level L (secondary ground potential). This low level L is an interrupt request level.
[0089]
  Refer to FIG. 3 again. Since the second power supply circuit 47 has a low output that applies a constant low voltage of 5 V to the control circuit and the control element, the FET 21 is a single FET. The second power supply circuit 47 has a constant voltage output terminal (5V) and an energy saving power supply terminal (5VE) that supplies 5V even during energy saving standby.
[0090]
  A resistor R21 for current detection is connected in series with the FET 21 of the second power supply circuit 47. The circuit configuration and circuit operation of the current value detection circuit ISEN21 including the resistor R21 are the same as those of the current value detection circuit ISEN11.
[0091]
  In this embodiment, the light generated by the light emitting diode LD21 of the current value detection circuit ISEN21 also illuminates the phototransistor PT41. Therefore, when the primary current of the transformer TR21 of the second power supply circuit 47 exceeds the set value, The overcurrent detection signal line (DSP interrupt input port Iint1) drops from the high level H (Vcc) to the low level L (secondary ground potential) that is the interrupt request level.
[0092]
  Refer to FIG. 3 again. The drive circuit DRIV11 of the first power supply circuit 46 is connected to a PWM output port PWM11 that outputs a first PWM pulse that is a switching ON / OFF signal of the DSP 48. DRIV11, transformer TR11 and switching element FET11 constitute a primary side switch circuit, and the output voltage of DC conversion circuit 45 is chopped by switching in response to a PWM pulse, and pulsed through the primary winding of transformer TR11.
[0093]
  On the secondary side of the transformer TR11, there is an output circuit that converts a pulse voltage induced in the secondary winding into a direct current and outputs it. The output circuit includes diodes D11 and D12, choke coil CH11, secondary side overcurrent detection circuit ISEN12 that detects secondary side overcurrent, output voltage detection circuit VSEN11, and smoothing capacitor C11.
[0094]
  The secondary side overcurrent detection circuit ISEN12 is configured to convert the current flowing through the output circuit of the first power supply circuit 46 into a voltage (secondary current detection signal) corresponding to the magnitude of the current and output it, and is output from the ISEN12. The voltage (secondary current detection signal) is applied to the A / D conversion input port If11 of the DSP 48.
[0095]
  The output voltage detection circuit VSEN11 applies a voltage proportional to the output voltage Vout11 (24V) of the first power supply circuit 46 to the A / D conversion input port Vf11 of the DSP 48.
[0096]
  Further, the output circuit on the secondary side of the transformer TR21 of the second power supply circuit 47 has the same configuration as that of the first power supply circuit 46, but further, a power supply for supplying power to the DSP 48 is provided. This comprises a diode D31 connected to the tertiary winding of the transformer TR21, a capacitor C31, a constant voltage circuit CV31, and a backflow prevention diode D33. Connected between the power supply terminals Vcc and GND of the DSP 48 is a series circuit of a battery B1, a diode D32, and a contact that is opened and closed by a relay contact piece that is closed and driven by the relay RA1 of the starting circuit.
[0097]
  FIG. 5 shows the configuration of the DSP 48. In this example, an event manager is used for the PWM pulse generator 65. There are a plurality of PWM pulse output ports, and the CPU 61 loads the data defining the PWM pulse and the pulse duty addressed to each output port into the pulse generation control register in the PWM pulse generator 65. When this load occurs, the PWM pulse generator 65 generates a PWM pulse defined by the register data and outputs it from the PWM pulse output port. In this embodiment, each PWM pulse is output from the two PWM pulse output ports PWM11 and PWM21 to the switching drivers DRIVE11 and DRIVE21. Data defining the period and duty of each PWM pulse is set in the pulse generator 65 by the CPU 61.
[0098]
  The A / D converter 68 in the DSP 48 includes a feedback signal representing the output current (If11), the output voltage (Vf11) and the circuit temperature (TEM) of the first power supply circuit 46, and the output current ( If21) and a feedback signal representing the output voltage (Vf21) is applied. The A / D converter 68 converts the feedback signal applied to the designated input channel into digital data under the control (instruction) of the CPU 61 via the interface 67, and latches it in its output register. A conversion completion signal is generated.
[0099]
  In response to this conversion completion signal, the CPU 61 reads feedback digital data (A / D conversion data), calculates the PWM pulse duty for setting the output voltage of the power supply circuit to the set voltage (24V, 5V), and Is written to the pulse generator 65, or the output current abnormality of the power supply circuit is detected or the first power supply circuit 46 is overheated.
[0100]
  A program for performing the above-described operation or processing of the CPU 61 is written in the EEPROM 62. The RAM 63 is used for temporary storage or storage of data.
[0101]
  Refer to FIG. 3 again. When the commercial AC voltage is turned on, that is, input from IN1 and IN2, the current flows to the relay RA1 of the starting circuit via the resistor R1 by the DC voltage rectified by the diode bridge DB1, and the voltage of the battery B1 is supplied to the power supply of the DSP 48. The contact RA1 for applying to the voltage input terminal Vcc is turned on. As a result, the operating voltage is supplied to the DSP 48, the DSP 48 is activated, and the CPU 61 performs the control operation shown in FIG. 6A in accordance with the program of the EEPROM 62.
[0102]
  That is, referring to FIG. 6A, when the operating voltage is applied to the CPU 61, the internal and external registers and input / output ports are set in a standby state (initialization: step 1), and the PWM pulse applied to the pulse generator 65 is obtained. In the PWM register which is an output register for storing data defining (period and duty), an initial value (PWM pulse period, first reference value defining duty for 24V output, and duty for 5V output) Is written (step 2). These data are written on the CPU operation program in the EEPROM 62. In the following, when the step number or symbol is entered in parentheses, the word “step” is omitted, and only the step number or symbol is entered.
[0103]
  Next, the CPU 61 resets the interrupt register of the pulse generator 65 and writes the data of the PWM register to the PWM pulse generation control register of the pulse generator 65 (3). The pulse generator 65 starts generating (outputting) PWM pulses based on the data that has been written. When the level of the interrupt signal line PDPINT of the pulse generator 65 becomes L, the pulse generator 65 sets its PWM pulse output port to high impedance (output circuit cutoff), thereby turning off the FET (11/21), and the pulse The generator 65 sets its internal output prohibition flag to 1 indicating prohibition, and continues high impedance as long as this 1 is present. However, when the interrupt register of the pulse generator 65 is reset, 1 of this output prohibition flag is set. It means clearing to 0, which indicates the prohibition release.
[0104]
  Next, the CPU 61 starts a program timer with a 200 μsec time limit (4) and permits a timer interrupt in response to the time over (5). The CPU 61 further permits an external interrupt in response to a change from the level H to L of the interrupt signal line PDPINT of the pulse generator 65 (6). Then, until the operating voltage to the CPU 61 runs out, that is, until the commercial AC power supply stops, an infinite loop waiting for the occurrence of an interrupt is entered (7).
[0105]
  Reference is now made to FIG. Thereafter, when the 200 μsec timer expires, the CPU 61 proceeds to the timer interrupt (TII) shown in FIG. 6B, restarts the 200 μsec timer (21), and sets the input voltage channel of the A / D converter 68. , No. Set to 0 to instruct A / D conversion to the A / D converter 68 (22), and permit an interrupt in response to the completion of A / D conversion (23). The A / D converter 68 has an input port No. The digital conversion of the analog signal of 0, that is, the feedback signal (Vf21) representing the output voltage of the second power supply circuit 47 is started, and when this is completed, an end signal (conversion data read ready) is generated. In response to this end signal, the CPU 61 proceeds to an A / D conversion end interrupt (ADI) shown in FIG.
[0106]
  In response to the interrupt (AD1) shown in FIG. 7, the CPU 61 corresponds to the input port (channel) of the A / D conversion that has just been completed (31-34). If it is 0, “5V output control” (35) 1 is “24V output control” (36), no. 2 for “5V secondary overcurrent protection” (37), 3 is “24V secondary overcurrent protection” (38), When it is 4, “overheat protection control” (38) is executed.
[0107]
  FIG. 8 shows the content of “5V output control” (35). When proceeding to this, the CPU 61 reads the data (the output voltage data of the second power supply circuit 47) converted by the A / D converter 68 into the register Vf21 (41), and is it over the set value Rf5V (overvoltage)? Is checked (42). If the output voltage data read this time is less than the set value Rf5V, an error amount with respect to 5V of the output voltage data read this time is calculated, the error amount is converted into a PWM pulse duty, and data defining this pulse duty is calculated (43), It is updated and written in the PWM register set in the CPU 61 or RAM 63, and the data in the PWM register is written in the PWM pulse generation control register of the pulse generator 65 (44). As a result, the PWM pulse output from the pulse generator 65 to the pulse output port PWM21 changes to a duty for reducing the error amount of the output voltage to zero. This is feedback control of the output voltage of the second power supply circuit 47.
[0108]
  When the output voltage of the second power supply circuit 47 is equal to or higher than the set value Rf5V (overvoltage), the CPU 61 writes data of PWM duty 0% in the PWM register (47). Thereby, all the pulse outputs of the pulse generator 65 are stopped, and the FET 11 and the FET 21 are turned off. Next, the CPU 61 prohibits all interrupts permitted to itself (48). As a result, the CPU 61 enters an operation stop state (infinite loop), the DSP 48 stops operating until the AC voltage is interrupted once and turned on again, and both the first power supply circuit 46 and the second power supply circuit 47 operate. Stop and no output.
[0109]
  When the duty of the PWM pulse (PWM 21) is updated as described above instead of the above-described overvoltage, the CPU 61 changes the No. of the A / D conversion input channel. 1 is designated and A / D conversion is instructed to the A / D converter 68 (45), and an interrupt in response to the completion of A / D conversion is permitted (46). The A / D converter 68 has an input port No. The digital conversion of the analog signal of 1, that is, the feedback signal (Vf11) representing the output voltage of the first power supply circuit 46 is started, and when this conversion is completed, an end signal (conversion data read ready) is generated. In response to this end signal, the CPU 61 proceeds to an A / D conversion end interrupt (ADI) shown in FIG. 7, and proceeds from step 32 in FIG. 7 to “24V output control” (36).
[0110]
  FIG. 9 shows the content of “24V output control” (36). This content is the same as the above-mentioned “5V output control” (35), and the PWM pulse (PWM11) given to the driver FET 11 of the first power supply circuit 46 so that the output voltage of the first power supply circuit 46 becomes the set value 24V. ) Is similarly feedback controlled (51-54). If the output voltage of the first power supply circuit 46 is an overvoltage, the DSP 48 stops driving the first power supply circuit 46 and the second power supply circuit 47 and stops the control operation (57, 58). When the output voltage of the first power supply circuit 46 is not an overvoltage and the duty of the PWM pulse (PWM 11) is updated, the CPU 61 changes the A / D conversion input channel No. 2 is designated and A / D conversion is instructed to the A / D converter 68 (55), and an interrupt in response to the completion of the A / D conversion is permitted (56). The A / D converter 68 has an input port No. Digital conversion of the analog signal 2, that is, the feedback signal (If 21) representing the output current of the second power supply circuit 47 is started, and when this conversion is completed, an end signal (conversion data read ready) is generated. In response to this end signal, the CPU 61 proceeds to an A / D conversion end interrupt (ADI) shown in FIG. 7, and then proceeds from step 33 in FIG. 7 to “5V secondary overcurrent protection” (37).
[0111]
  FIG. 10 shows the content of “5V secondary side overcurrent protection” (37). When proceeding to this, the CPU 61 reads the data converted by the A / D converter 68 (output current data of the first power supply circuit 46) into the register If21 (61), which is equal to or higher than the set value Rf5Vi (overcurrent). Is checked (62). If it is equal to or greater than the set value Rf5Vi, the DSP 48 stops driving the first power supply circuit 46 and the second power supply circuit 47 and stops the control operation (65, 66). When the current is not overcurrent, the CPU 61 determines the A / D conversion input channel No. 3 is designated to instruct A / D conversion to the A / D converter 68 (63), and an interrupt in response to the completion of the A / D conversion is permitted (64). The A / D converter 68 has an input port No. The digital conversion of the analog signal 3, that is, the feedback signal (If 11) representing the output current of the first power supply circuit 46 is started, and when this is completed, an end signal (conversion data read ready) is generated. In response to this end signal, the CPU 61 proceeds to an A / D conversion end interrupt (ADI) shown in FIG. 7, and then proceeds from step 34 of FIG. 7 to “24V secondary side overcurrent protection” (38).
[0112]
  The content of “24V secondary side overcurrent protection” (38) is the same as the content of “5V secondary side overcurrent protection” (37) described above. If the output current (If11) of the second power supply circuit 47 is normal in the “24V secondary side overcurrent protection” (38), the CPU 61 determines whether the A / D conversion input channel No. 4 is designated, A / D conversion is instructed to the A / D converter 68, and an interrupt in response to completion of the A / D conversion is permitted. The A / D converter 68 has an input port No. The digital conversion of the analog signal No. 4, that is, the temperature detection signal (THM) of the thermistor TH provided in the first power supply circuit 46 is started, and when this is finished, an end signal (conversion data read ready) is generated. In response to the end signal, the CPU 61 proceeds to an A / D conversion end interrupt (ADI) shown in FIG. 7, and proceeds from step 34 in FIG. 7 to “overheat protection control” (39).
[0113]
  FIG. 11 shows the content of “overheat protection control” (39). When proceeding to this, the CPU 61 reads the data (temperature detection data of the thermistor TH) converted by the A / D converter 68 into the register TEM (81), and checks whether it is equal to or higher than the set value RfTEM (overtemperature). (82). If it is equal to or greater than the set value RfTEM, the DSP 48 stops driving the first power supply circuit 46 and the second power supply circuit 47 and stops the control operation (85, 86). When the temperature is not overtemperature, the CPU 61 determines the A / D conversion input channel No. 0 is designated to instruct the A / D converter 68 to perform A / D conversion (83), and an interrupt in response to the completion of A / D conversion is permitted (84). The A / D converter 68 has an input port No. The digital conversion of the analog signal of 0, that is, the feedback signal (Vf21) representing the output voltage of the second power supply circuit 47 is started, and when this is completed, an end signal (conversion data read ready) is generated. In response to this end signal, the CPU 61 proceeds to an A / D conversion end interrupt (ADI) shown in FIG. 7, and then proceeds from step 31 in FIG. 7 to “5V output control” (35). The contents of the “5V output control” (35) are as described above.
[0114]
  As described above, the reading of the feedback signal (A / D conversion), the updating of the PWM pulse duty, the detection of the output overcurrent, and the detection of overheating are repeated in a predetermined order. These series, that is, FIG. 6B. 7 and steps 31 to 39 of “A / D conversion end interrupt” (AD1) shown in FIG. 7 is less than 200 μsec. Therefore, this series of processes is performed by the 200 μsec timer. Complete before over. When the 200 μsec timer expires, the CPU 61 executes again the timer interrupt (TII) shown in (b) of FIG. Thereby, the control period of the CPU 61 is substantially 200 μsec. The PWM pulse has a frequency of about 100 KHz.
[0115]
  Through the above control operation of the CPU 61, the DSP 48 generates a PWM pulse for turning on / off the switching element FET21 so that the output voltage value of the output voltage circuit VSEN21 input to the port Vf21 becomes a predetermined voltage, and supplies it to the drive circuit DRIV21. Output. The switching element FET21 is driven ON / OFF via the drive circuit DRIV21, and the transformer TR21 is excited. Then, the AC voltages induced in the secondary coil and the tertiary coil are rectified and smoothed, respectively, and a DC voltage (5V, 5VE, Vcc) is output. The DSP 48 always continues the ON duty calculation of switching ON / OFF and the pulse output of the duty so that the output voltage value (Vf21) becomes a predetermined voltage value 5V.
[0116]
  Similarly, the DSP 48 calculates a switching signal for turning on / off the switching element FET11 so that the output voltage value of the output voltage circuit VSEN11 input to the port Vf11 becomes a predetermined voltage 24V, and outputs it to the drive circuit DRIV11. The switching element FET11 is turned on / off via the drive circuit DRIV11, and the transformer TR11 is excited. The DSP 48 always continues the ON duty calculation of switching ON / OFF and the pulse output of the duty so that the output voltage value (Vf11) becomes a predetermined voltage value 24V.
[0117]
  Here, an operation flow when an overcurrent flows through the switching element FET11 or FET21 will be described.
[0118]
  FIG. 6C shows the contents of the external interrupt processing (PDI) of the CPU 61 when an overcurrent flows through the FET 11 or FET 21. As described above, when an overcurrent flows through the FET 11 or FET 21, the light emitting diode LD11 or LD21 shown in FIG. 4 emits light, the phototransistor P41 shown in FIG. 5 is turned on, and the signal PDPINT of the interrupt input port Iint1 of the DSP 48 is changed. , The high level H changes to the interrupt request level L. Then, after a delay of 3 to 4 clock cycles of the operating frequency of the CPU 61, the pulse generator 65 (event manager) sets the PWM output ports PWM11 and PWM21 in a hardware high impedance state and holds this output prohibit flag (1-bit data). ) Is set (H = 1), and a register for storing data for determining a PWM pulse period and a pulse duty is cleared. As a result, the PWM output ports PWM11 and PWM21 are in a switching ON / OFF stop state (output cutoff). As a result, the outputs of the drive drive circuits DRIV11 and DRIVE21 also shift to the OFF state, and the switching elements FET11 and FET21 are turned OFF.
[0119]
  The CPU 61 proceeds to the external interrupt (PDI) in FIG. 6C, but there is a delay of several μs until the execution of the interrupt program is started. In this interrupt processing, the output prohibition flag of the pulse generator 65 is canceled (cleared to 0) (25), data for PWM pulse output is set in the register of the pulse generator 65, and pulse output is started. (26). It takes several μs to execute this interrupt program. Through the above processing, the overcurrent flowing through the primary side switching elements FET11 and FET21 can be accurately detected by pulse-by-pulse, and protection control can be performed to prevent the switching power supply device, particularly the switching element from being destroyed or damaged. it can.
[0120]
  -Second Example-
  The configuration of the DSP 48 used in the second embodiment is shown in FIG. The configurations of the first power supply circuit 46 and the second power supply circuit 47 of the switching power supply device 41 of the second embodiment are the same as those shown in FIGS. However, the light emitting diode LD11 of the primary current detection circuit ISEN11 of the first power supply circuit 46 is coupled to the first insulating coupler 49 shown in FIG. 12 and irradiates the phototransistor PT41 with light. The light emitting diode LD21 of the primary current detection circuit ISEN21 of the second power supply circuit 47 is coupled to the second insulating coupler 50 and irradiates the phototransistor PT51 with light.
[0121]
  In the first embodiment described above, since only one input port (Iint1) is detected at the time of overcurrent detection, output of all PWM outputs is stopped even if an overcurrent is generated by any one switching element. Then, the drive circuits DRIVE11 and DRIVE21 are turned off.
[0122]
  On the other hand, in the second embodiment, the DSP 48 includes a plurality of overcurrent detection input ports Iint1 and Iint2, and individually provides an overcurrent signal to the drive circuit DRIVE11, The DRIVE 21 unit is intended to protect the switching element from overcurrent. That is, in the second embodiment, the same number of primary side current value detection circuits (ISEN11 + 49, ISEN21 + 50) as the PWM ports (PWM11, PWM21), and the input port for inputting the overcurrent detection signal of the primary side current value detection circuit ( Iint1, Iint2).
[0123]
  The DSP 48 shown in FIG. 12 includes two pulse generators 65 and 71. These functions are the same as those of the pulse generator shown in FIG. The outline of the control operation of the CPU 61 is the same as that of the first embodiment. However, in detail, the data defining the PWM pulse (PWM11) to be given to DRIVE 11 is set only in the pulse generator 65, and when the external interrupt signal PDPINT1 = L is generated, only the pulse generator 65 is generated by the interrupt 1. The aforementioned interrupt processing (PDI: (c) of FIG. 6) is performed. Similarly, the data defining the PWM pulse (PWM21) to be given to DRIVE 21 is set only in the pulse generator 71, and when the external interrupt signal PDPINT2 = L is generated, only the pulse generator 71 is caused by the interrupt 2 by the interrupt 2 described above. Interrupt processing (PDI: (c) of FIG. 6) is performed.
[0124]
  -Third Example-
  FIG. 13 shows a DSP 48 used in the third embodiment. This is obtained by adding an OR gate 76 to the DSP 48 shown in FIG. Only the primary overcurrent signal (PDPINT2 = L) of the second power supply circuit 47 is applied to the pulse generator 71, while the primary overcurrent signal of the first power supply circuit 46 is applied to the pulse generator 65. In addition to (PDPINT1 = L), the primary side overcurrent signal (PDPINT2 = L) of the second power supply circuit 47 is also applied through the OR gate 76. As a result, when the first power supply circuit 46 of 24 V output becomes a primary overcurrent, the switching element FET11 of the first power supply circuit 46 is turned off, but the switching element FET21 of the second power supply circuit 47 is kept on.
[0125]
  However, when the 5V output second power supply circuit 47 becomes a primary overcurrent, both the switching elements FET21 and FET11 of the second power supply circuit 47 and the first power supply circuit 46 are turned off. In accordance with this, when the second power supply circuit 47 becomes a primary overcurrent, the CPU 61 performs the above-described interrupt processing (PDI: (c) of FIG. 6) for the pulse generators 71 and 65 in response thereto. However, when the first power supply circuit 46 becomes a primary overcurrent, in response thereto, only the pulse generator 65 performs the above-described interrupt processing (PDI: (c) of FIG. 6).
[0126]
  By adding the OR gate 76, flexible primary overcurrent protection control can be realized in this way. In this embodiment, when the second power supply circuit 47 is for basic voltage output and the switching element FET21 generates an overcurrent, the switching element FET1 is not only turned on / off, but also the first power supply for power. The switching ON / OFF of the switching element FET11 of the circuit 46 is also stopped simultaneously. When an overcurrent is generated in the switching element FET11 of the first power supply circuit 46, flexible overcurrent protection control is realized in which only switching ON / OFF of the switching element FET11 is stopped.
[0127]
  -Fourth embodiment-
  In the fourth embodiment, primary side current detection circuits ISEN11 and ISEN21 shown in FIG. 14 are used. These detection circuits ISEN11 and ISEN21 output an analog detection signal (current signal) representing the primary side current level, and supply it to the A / D conversion input ports Id11 and Id21 of the DSP 48 shown in FIG.
[0128]
  In the DSP 48 shown in FIG. 15, the A / D converter 72 converts the current signal of the port Id11 into digital data and latches it into its output latch. At the same time as this latching, a conversion end signal is given to the digital comparator 73. The A / D converter 72 repeats the above-described conversion operation at a high speed while the first PWM pulse (PW11) A is at a level for instructing switching-on. Similarly, the A / D converter 74 converts the current signal of the port Id21 into digital data and latches it in its output latch. At the same time as this latch, a conversion end signal is supplied to the digital comparator 75. The A / D converter 74 repeats the above-described conversion operation at a high speed while the second PWM pulse (PW21) B is at a level for instructing switching on.
[0129]
  The CPU 61 sets (latches) data representing the first threshold Rf24Vpi for primary overcurrent determination of the first power supply circuit 46 in the digital comparator 73, and the second power supply circuit 47 in the digital comparator 75. The data representing the second threshold value Rf5Vpi for primary side overcurrent determination is set (latched).
[0130]
  The digital comparator 73 constantly generates an H determination output, but the conversion data of the A / D converter 72 when the A / D converter 72 gives a conversion end signal is equal to or higher than the first threshold value Rf24Vpi. Only when it is, the determination output is changed to L. This L is given to the pulse generator 65 and the CPU 61 as an interrupt request signal PDPINT1 = L, and these 65 and 61 operate in the same manner as in the second embodiment shown in FIG.
[0131]
  Similarly, the digital comparator 75 constantly generates a determination output of H, but the conversion data of the A / D converter 74 when the A / D converter 74 gives a conversion end signal is the second. Only when the threshold value is Rf5Vpi or higher, the determination output is switched to L. This L is given to the pulse generator 71 and the CPU 61 as an interrupt request signal PDPINT2 = L, and these 71 and 61 operate in the same manner as in the second embodiment shown in FIG.
[0132]
  In the fourth embodiment, the voltage value converted outputs from the current value detection circuits ISEN11 and ISEN21 are always input to the Id11 and Id21 terminals of the DSP 48, and the DSP 48 stores the operation program stored in the EEPROM of the CPU 61 in hardware. This is compared with the set first threshold value Rf24Vpi and second threshold value Rf5Vpi. These threshold values Rf24Vpi and Rf5Vpi are in a threshold register set on the operation program of the DSP 48, and the threshold value can be changed by rewriting it.
[0133]
  -Fifth embodiment-
  FIG. 16 shows a DSP 48 used in the fifth embodiment. This is obtained by adding an OR gate 76 to the DSP 48 shown in FIG. Only the primary overcurrent signal (PDPINT2 = L) of the second power supply circuit 47 is applied to the pulse generator 71, while the primary overcurrent signal of the first power supply circuit 46 is applied to the pulse generator 65. In addition to (PDPINT1 = L), the primary side overcurrent signal (PDPINT2 = L) of the second power supply circuit 47 is also applied through the OR gate 76. As a result, when the first power supply circuit 46 of 24 V output becomes a primary overcurrent, the switching element FET11 of the first power supply circuit 46 is turned off, but the switching element FET21 of the second power supply circuit 47 is kept on.
[0134]
  However, when the 5V output second power supply circuit 47 becomes a primary overcurrent, both the switching elements FET21 and FET11 of the second power supply circuit 47 and the first power supply circuit 46 are turned off. In accordance with this, when the second power supply circuit 47 becomes a primary overcurrent, the CPU 61 performs the above-described interrupt processing (PDI: (c) of FIG. 6) for the pulse generators 71 and 65 in response thereto. However, when the first power supply circuit 46 becomes a primary overcurrent, in response thereto, only the pulse generator 65 performs the above-described interrupt processing (PDI: (c) of FIG. 6).
[0135]
  -Sixth Example-
  FIG. 17 shows a DSP 48 used in the sixth embodiment. This is the one in which an OR gate 76 is added to the DSP 48 shown in FIG. 15 and the number of pulse generators is 65, but the primary overcurrent signal (PDPINT1 = L) of the first power circuit 46 and the second power circuit Any of the 47 primary side overcurrent signals (PDPINT2 = L) is supplied to the pulse generator 65 through the OR gate 76. The function of generating the primary side overcurrent signal (PDPINT1 = L, PDPINT2 = L) is the same as that of the DSP 48 shown in FIG. 15, but the control operation of the CPU 61 is that of the first embodiment shown in FIGS. It is the same.
[0136]
  -Seventh Example-
  FIG. 18 shows a DSP 48 used in the seventh embodiment. This is obtained by adding a data selector (selection gate) 77-80 to the DSP 48 shown in FIG. 15. Which of these selector inputs is used as the selector output, the CPU 61 gives selection specifying data to each selector. Determined by Thereby, the PWM output port destination (PWM11, PWM21) whose output is stopped in accordance with the input port destination (Id11, Id21) in which the overcurrent is detected can be set in software by rewriting the selection designation data in the DSP 48. Therefore, there is no restriction on the wiring layout of the switching power supply substrate, and the A / D input ports Id11 and Id21 (or the overcurrent signal input ports Iint1 and Iint2) to which the current detection signal is applied freely and the PWM pulse output ports PW11, It is possible to set the correspondence of PW21.
[0137]
  Further, flexible primary overcurrent protection control can be realized. For example, when the switching element for basic voltage output generates an overcurrent, not only the switching ON / OFF stop of the switching element but also the switching ON / OFF of the switching elements of other output voltage circuits are simultaneously stopped. When an overcurrent is generated in the switching element of the other output voltage circuit, flexible overcurrent protection control can be performed in which only switching ON / OFF of the switching element is stopped.
[Brief description of the drawings]
FIG. 1A is a perspective view showing an external appearance of an image forming apparatus including a printer PTR equipped with a power supply device 41 according to a first embodiment of the present invention, and FIG. 1B shows an outline of an image forming mechanism of the printer PTR. It is a block diagram.
FIG. 2 is a block diagram showing an outline of an electrical system of the image forming apparatus shown in FIG.
3 is a block diagram showing a configuration of a switching power supply device 41 of the first embodiment shown in FIG. 2;
4 is an electric circuit diagram showing a configuration of primary current detection circuits ISEN11 and ISEN21 shown in FIG. 3;
5 is a block diagram showing a configuration of a digital control unit 48 shown in FIG.
6 is a flowchart showing a control operation of a CPU 61 shown in FIG. 5, in which (a) shows a main routine and (b) and (c) show interrupt processing.
7 is a flowchart showing an interrupt process of the CPU 61 shown in FIG. 5 in response to the end of A / D conversion by the A / D converter 68. FIG.
FIG. 8 is a flowchart showing the content of “5V output control” (35) shown in FIG. 7;
FIG. 9 is a flowchart showing the content of “24V output control” (36) shown in FIG. 7;
FIG. 10 is a flowchart showing the contents of “5V secondary side overcurrent protection” (37) shown in FIG. 7;
FIG. 11 is a flowchart showing the contents of “overheat protection control” (39) shown in FIG. 7;
FIG. 12 is a block diagram showing the configuration of a DSP 48 used in the second embodiment.
FIG. 13 is a block diagram showing a configuration of a DSP 48 used in the third embodiment.
FIG. 14 is an electric circuit diagram showing a configuration of primary side current detection circuits ISEN11 and ISEN21 used in the fourth embodiment.
FIG. 15 is a block diagram showing a configuration of a DSP 48 used in the fourth embodiment.
FIG. 16 is a block diagram showing a configuration of a DSP 48 used in the fifth embodiment.
FIG. 17 is a block diagram showing a configuration of a DSP 48 used in the sixth embodiment.
FIG. 18 is a block diagram showing a configuration of a DSP 48 used in the seventh embodiment.
[Explanation of symbols]
PCa: PC PTR: Color printer
OPB: Operation panel SCR: Document scanner
ADF: Automatic document feeder 1: Photoconductor
2: Main charger 3: Laser scanner
4: Development device 5: Transfer charger
6: Transfer belt 7: Registration roller
8: Transfer separation charger 9: Conveyor belt
10: Fixing device 11: Sorter
12: Cleaning device 13: Cleaning blade
14: Optical sensor 15: Optical sensor
16: Temperature sensor 41: Switching power supply
PS1 to PS3: Feed line IN1, IN2: AC input terminal
45: DC converter circuit DB1: Full-wave rectifier diode bridge
RA1: Relay 46: First power supply circuit
DRIVE11: Driver 47: Second power supply circuit
DRIVE21: Driver
ISEN11, ISEN21: Current value detection circuit
VSEN11, VSEN21: Output voltage detection circuit
ISEN12, ISEN22: Secondary side overcurrent detection circuit

Claims (20)

A transformer, a primary side circuit that supplies switching power to the primary winding of the transformer in response to a PWM pulse, a secondary side circuit that rectifies a voltage generated in the secondary winding of the transformer and supplies power to a load; and A digital signal processing device including a digital processing pulse generator for generating a PWM pulse and a CPU for providing data defining the PWM pulse to the digital processing pulse generator,
Wherein a constant voltage to the resistor through the on-current of the primary circuit the current detection resistor, by connecting the constant-voltage through another resistor and diode and said current sense resistor energizing friendly to the current detection resistor , a voltage proportional to the voltage between said further resistor and a diode, is applied to the light emitting driver for energizing the light emitting element of a photocoupler including a light emitting element and the photoelectric conversion element, a light reception signal of the photoelectric conversion element over An overcurrent protection method in which a current signal is supplied to the digital signal processing device, and the pulse generator of the digital signal processing device stops its switching-on output in response to the overcurrent signal. The overcurrent signal is an interrupt signal for the digital signal processing device, the pulse generator stops its switching-on output in response to the interrupt signal, and then the CPU restarts the pulse output by the pulse generator, The overcurrent protection method according to claim 1, wherein the digital signal processing device performs protection control of switching power supply of the primary circuit by pulse-by-pulse . A transformer, a primary side circuit that supplies switching power to the primary winding of the transformer in response to a PWM pulse, a secondary side circuit that rectifies a voltage generated in the secondary winding of the transformer and supplies power to a load; and A digital signal processing device including a digital processing pulse generator for generating a PWM pulse and a CPU for providing data defining the PWM pulse to the digital processing pulse generator,
Wherein a constant voltage to the resistor through the on-current of the primary circuit the current detection resistor, by connecting the constant-voltage through another resistor and diode and said current sense resistor energizing friendly to the current detection resistor , a voltage proportional to the voltage between said further resistor and a diode, provided in the digital signal processing apparatus, the voltage is converted into digital data in the digital signal processor,-out preparative the digital data is larger than a predetermined value the overcurrent signal is generated, the pulse generator Ru stop its switching oN output in response to the overcurrent signal, the overcurrent protection method. The overcurrent protection method according to claim 3 , wherein, after the CPU stops the switching-on output in response to the overcurrent signal, the pulse generator restarts the PWM pulse generation.   In response to the overcurrent signal, the pulse generator maintains the PWM pulse output port as high impedance; the CPU starts an interrupt process in response to the overcurrent signal, and the interrupt process causes the 5. The overcurrent according to claim 1, 2, 3 or 4, wherein after the pulse generator stops switching on output, the high impedance of the pulse generator is released and data for PWM pulse output is set in the register. Protection method. Transformer ;
A primary circuit for switching power supply to the primary winding of the transformer in response to a PWM pulse ;
A secondary circuit for rectifying the voltage generated in the secondary winding of the transformer and supplying power to the load ;
A current detection resistor for detecting an on-current of the primary side circuit ;
A series circuit of a resistor and a diode different from the current detection resistor, connected between a constant voltage line and the current detection resistor, wherein the other resistor and the diode are passed in this order from the constant voltage line. a series circuit of indicia addition to energizing friendly towards the constant voltage of the constant voltage line to the current detection resistor Te;
A photocoupler including a light emitting element and a photoelectric conversion element, and generating a photoelectric conversion signal of the photoelectric conversion element by light emission of the light emitting element as an overcurrent signal;
A light emitting driver for energizing the light emitting element to emit light when a voltage between the another resistor and the diode increases; and
A digital signal processing device comprising: a pulse generator that generates the PWM pulse and stops the PWM pulse output in response to the overcurrent signal ; and a CPU that supplies the pulse generator with data for PWM pulse output ;
A power supply device comprising: The power supply device includes first and second circuits each including the transformer, a primary side circuit, a secondary side circuit, a current detection resistor, a light emitting element, and a light emitting driver; the photoelectric conversion element of the photocoupler includes 1 and also received from each of the light-emitting element of the second circuit; of the digital signal processing apparatus, the pulse generator generates the first and second PWM pulses applied to the first and second circuits, the photoelectric is intended to stop the first and second PWM pulses output in response to the overcurrent signal from the conversion element, wherein the CPU, the pulse generator data for the first and second PWM pulse output give; power supply device according to claim 6. The power supply device includes first and second circuits each including the transformer, a primary side circuit, a secondary side circuit, a current detection resistor, a photocoupler, and a light emitting driver; and the pulse generation of the digital signal processing device vessel, the first stop a PWM pulse output in response to the first over-current signal from the first circuit generates the first and second PWM pulses applied to the first and second circuit, the second circuit And stopping the second PWM pulse output in response to the second overcurrent signal, wherein the CPU provides data for the first and second PWM pulse outputs to the pulse generator ; 6. The power supply device according to 6 . Trance;
A primary circuit for switching power supply to the primary winding of the transformer in response to the PWM pulse;
A secondary circuit for rectifying the voltage generated in the secondary winding of the transformer and supplying power to the load;
A current detection resistor for detecting an on-current of the primary side circuit;
A series circuit of a resistor and a diode other than the current detection resistor, connected between a constant voltage line and the current detection resistor, wherein the other resistor and the diode are passed in this order from the constant voltage line. A series circuit for applying a constant voltage of the constant voltage line toward the current detection resistor so as to be energized;
and,
A / D conversion means for converting a voltage proportional to the voltage between the other resistor and the diode into digital data, a comparison means for generating an overcurrent signal when a value represented by the digital data exceeds a set value, and the PWM pulse A digital signal processor comprising: a pulse generator that generates a pulse and stops PWM pulse output in response to the overcurrent signal ; and a CPU that provides the pulse generator with data for PWM pulse output ;
A power supply device comprising: The power supply device includes first and second circuits each including the transformer, a primary side circuit, a secondary side circuit, a current detection resistor, a series circuit, and comparison means; the pulse generation of the digital signal processing device vessel is one in response to the first and second PWM pulse output also overcurrent signals from the first and second circuit generates the first and second PWM pulses applied to the first and second circuit 10. The power supply device according to claim 9 , wherein the CPU supplies data for first and second PWM pulse output to the pulse generator . The power supply, the transformer, the primary circuit, the secondary circuit, a current detection resistor, comprising first and second circuits each comprising comparing means and our series circuit; of the digital signal processing apparatus, the pulse generator, the first and second PWM pulses applied to the first and second circuit generates, stopping the first PWM pulse output in response to the first over-current signal from the first circuit, the second Stopping the second PWM pulse output in response to a second overcurrent signal from the circuit , the CPU providing data for the first and second PWM pulse outputs to the pulse generator ; The power supply device according to claim 9 . The pulse generator stops the first PWM pulse output in response to the first overcurrent signal from the first circuit, and the first and second in response to the second overcurrent signal from the second circuit. The power supply apparatus according to claim 8 or 11, wherein the PWM pulse output is stopped . The first circuit is a high power power supply circuit that outputs a high DC voltage for supplying power to a high load that consumes a large amount of power, and the second circuit is a low DC voltage for supplying power to a control circuit and elements that consume less power. The power supply device according to claim 7, claim 10, claim 11, or claim 12 , wherein the power supply device is a low-power power supply circuit that outputs.   The power supply device according to claim 13, wherein the second circuit has a voltage output terminal at which the load is turned off at the time of energy saving standby and an energy saving standby power supply terminal at which the load is continuously turned on at the time of energy saving standby.   7. The CPU restarts PWM pulse generation after the CPU is responsive to the overcurrent signal and the pulse generator stops switching on output; The power supply device according to claim 9, claim 10, claim 11, claim 12, claim 13, or claim 14.   In response to the overcurrent signal, the pulse generator maintains the PWM pulse output port as high impedance; the CPU starts an interrupt process in response to the overcurrent signal, and the interrupt process causes the 16. The power supply device according to claim 15, wherein after the pulse generator stops switching on output, the high impedance of the pulse generator is released and data for PWM pulse output is set in the register. The power supply device according to any one of claims 6 to 16; and is powered from a power supply device, an image forming means for forming an image represented by the image data; image forming apparatus including a.   The power supply device according to claim 14; image forming means for forming an image represented by image data supplied from the power supply device; and power supply from the first circuit of the power supply device to the image forming means during energy saving standby; and An image forming apparatus comprising: switch means for cutting off power supply from the voltage output terminal of the second circuit to the image forming means.   19. The image forming apparatus according to claim 17, further comprising a printer controller that converts print information given from outside into image data and supplies the image data to the image forming means.   20. The image forming apparatus according to claim 17, further comprising a document scanner that reads a document image, generates image data, and supplies the image data to the image forming unit.

Images