JP4221239B2 - Clock wiring drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock wiring driving circuit, and more particularly to a clock control system suitable for a clock control system using an I2CBUS protocol.
[0002]
[Prior art]
FIG. 11 shows a clock control system composed of a single master. One microcomputer unit (hereinafter referred to as MCU) 10 that supplies a clock used for synchronization of data transmission / reception as a master and a plurality of devices 20A, 20B, and 20C corresponding to slaves are serial clock lines (hereinafter referred to as SCL). It is connected to wiring and serial data (hereinafter referred to as SDA) wiring.
[0003]
Even in such a system composed of a single master, as shown in FIG. 12, when the wiring length of the SCL wiring and SDA wiring is long, the load capacitance C1 is between the SCL wiring, SDA wiring and the ground terminal. , C2 are parasitic, and pull-up resistors PR1 and PR2 must be connected between the SCL wiring and SDA wiring and the power supply voltage VDD terminal, and the transmission / reception clock rate may be lower than the set original clock rate. is there.
[0004]
In a system that requires high-speed transmission / reception, there has been a problem that the transfer rate of the clock decreases due to the load capacity of the SCL wiring, the pull-up resistance, and the like.
[0005]
Such a phenomenon is caused by the fact that the clock synchronization function corresponding to the clock control system configured by the multi-master in the I2CBUS protocol works similarly in the system configured by the single master.
[0006]
FIG. 13 shows a clock control system composed of multi-masters. In this system, not only the MCU 30 but also a device 40D exists as a master that supplies a clock, and is connected to a plurality of devices 40A, 40B, and 40C corresponding to slaves and SCL wirings and SDA wirings.
[0007]
A method of synchronizing clocks using the I2CBUS protocol will be described with reference to FIG.
[0008]
Here, it is assumed that two masters A and B supply a clock.
[0009]
(A) When the clock output of master B synchronizes the falling edge of the SCL wiring and the timing
At point a, when viewed from the master B, when the clock output of the other master A is pulled low at an earlier timing than its own clock output, the SCL wiring is affected by the influence of the clock output of the master A as early as possible. Pull to low. The master B detects the falling of the SCL wiring to low, clears the count of the high level period that has been performed so far, and starts counting of the low level period.
[0010]
(B) When the clock output of the master A synchronizes the rise of the SCL wiring and the timing
At point b, as viewed from the master A, the low level period ends and rises to a high level and an attempt is made to start counting the high level period, but the clock output of the other master B is still at the low level. If maintained, the SCL wiring is maintained at the low level due to the influence of the master B that is pulled low. In this case, the master A waits without starting counting the high level period from the time point b, and is set as a waiting time. Then, when the point C is reached, the low period of the master B ends and rises to a high level. When the SCL wiring rises due to this influence, the master A detects the high level of the SCL wiring. Start counting the period.
[0011]
FIG. 15 shows a circuit configuration of the MCU 100 that operates as a conventional clock wiring driving circuit (here, equivalent to the master A).
[0012]
The MCU 100 includes a CPU 101 and an I2CBUS control circuit 102. The I2CBUS control circuit 102 includes an SCL generation counter 103, an SCL frequency setting register 104, an SCL driver 105, an output transistor 106 including an N-channel transistor, a buffer 107, and an SCL sample. A circuit 108, an SCL synchronization circuit 109, and an SCL rising / falling synchronization period detection circuit 110.
[0013]
The output terminal of the output transistor 106 is connected to an SCL wiring provided outside the MCU 100. A pull-up resistor 111 is connected between the SCL wiring and the power supply voltage VDD terminal.
[0014]
The SCL frequency is determined by a program executed by the CPU 101 and written to the SCL frequency setting register 104. The count number is given to the SCL generation counter 103 according to the set frequency.
[0015]
The counter clock CLK is input to the SCL generation counter 103, and its output is input to the gate of the output transistor 106 via the SCL driver 105. When the output of the SCL generation counter 103 is at a high level, the output transistor 106 is turned on to lower the SCL wiring to a low level. When the output becomes a low level, the output transistor 106 is turned off and the pull-up resistor 111 causes the SCL wiring to rise to a high level. . The output of the SCL generation counter 103 is input to the SCL rising / falling synchronization period detection circuit 110.
[0016]
Here, the own clock output from the MCU 100, that is, the clock corresponding to the clock of the master A in FIG. 14, is the level of the output terminal of the output transistor 106 (the drain terminal of the N-channel transistor).
[0017]
First, rising synchronization is performed as follows. The signal level of the SCL wiring is input to the SCL sample circuit 108 to which the clock CLK is input via the buffer 107 for monitoring, the signal level of the SCL wiring is held in synchronization with the clock CLK, and the SCL rising / falling synchronization is performed. Input to the period detection circuit 110. Accordingly, when the signal level of the SCL wiring rises to a high level, the SCL sample circuit 108 holds this in synchronization with the clock CLK and outputs a high level signal.
[0018]
The SCL rising / falling synchronization period detection circuit 110 detects a period in which SCL rising synchronization should be performed. That is, the output of the SCL generation counter 103 is low level and its own clock is high level output, but this period is the SCL rising synchronization period while the output of the SCL sample circuit 108 is still maintaining low level. As a result, an SCL rising synchronization period signal which becomes the period logic “1” (hereinafter, logic “1” corresponds to the high level) is output to the SCL synchronization circuit 109. This SCL rising-synchronization period signal indicates that when the SCL rising-synchronization ends, that is, when the output of the SCL generation counter 103 is at a low level and its own clock becomes a high-level output, and the output of the SCL sample circuit 108 that monitors the SCL wiring is high. When it reaches the level, it will not be output.
[0019]
The SCL synchronization circuit 109 outputs a counter wait signal while the SCL rising synchronization period signal is given. As a result, the SCL generation counter 103 waits without starting to count the high level period Thigh. When the SCL rising synchronization period signal of logic “1” is not given, the SCL synchronization circuit 109 stops outputting the counter wait signal. As a result, the SCL generation counter 103 starts counting during the high level period Thigh. During this time, the SCL generation counter 103 maintains a low level output, and its own clock maintains a high level output. When the count value reaches the set value, the SCL generation counter 103 sets its output to the high level, and its own clock falls to the low level. At the same time, the counting of the low level period Tlow is started.
[0020]
Falling synchronization is performed as follows. When the signal level of the SCL wiring falls to a low level, the SCL sample circuit 108 holds and outputs a low level signal in synchronization with the clock CLK. The SCL rising / falling synchronization period detection circuit 110 detects a period during which SCL falling synchronization is to be performed, and outputs an SCL falling synchronization period signal during that period. That is, the output of the SCL generation counter 103 is low level and the clock of its own is maintained at high level and has not yet fallen to low level, but when the output of the SCL sample circuit 108 that monitors the SCL wiring becomes low level. , The SCL falling synchronization period signal is output to the SCL synchronization circuit 109. This SCL falling synchronization period signal is not output immediately when the output of the SCL generation counter 103 becomes high level and its own clock falls to low level.
[0021]
The SCL synchronization circuit 109 gives a counter clear signal to the SCL generation counter 103 when the SCL falling synchronization period signal is given. The SCL generation counter 103 counts the high level period Thigh until the counter clear signal is given. However, when the counter clear signal is given, the SCL generation counter 103 stops the count and starts counting the low level period Tlow. .
[0022]
The following documents disclose related prior art.
[0023]
[Patent Document 1]
Special table 2002-508645 gazette
[Patent Document 2]
U.S. Pat. No. 4,689,740
[0024]
[Problems to be solved by the invention]
The reason why the clock rate is lowered when the conventional clock wiring driving circuit is used in a clock transfer system operating as a single master will be described below.
[0025]
As described above, even when the clock wiring drive circuit is used in a clock transfer system that operates as a single master, the clock synchronization function based on the I2CBUS protocol is premised on a clock transfer system having a multi-master configuration. The clock synchronization method is designed on the assumption that there is no parasitic capacitance in the SCL wiring during the high period of the SCL wiring and the low period of the SCL. When the capacitance parasitic on the wiring is unloaded, the waveform of the SCL wiring rises steeply as shown in FIG. Therefore, the cycle Tcyc, which is the sum of the low level period Tlow from the time point a to b and the high level period Thigh from the time point b to c, is equal to the count number of the low level period Tlow and the high level period Thigh. It corresponds to the sum of the count number.
[0026]
However, if there is a round when the waveform of the SCL wiring rises as shown in FIG. 17, the own clock rises at the time point b, and the SCL wiring starts to rise, and reaches a high level at the time point c. SCL rise waiting time (count waiting time of high level period Thigh) occurs before it is considered that the clock rate is lowered. That is, the cycle Tcyc does not coincide with the sum of the count number of the low level period Tlow from the time point a to b and the count number of the high level period Thigh from the time point c to d, and further from the time point b. It becomes longer by the count waiting time of the high level period Thigh up to c.
[0027]
For example, when the set SCL frequency is 400 KHz (2500 [ns]) and 300 [ns] rounding occurs as the rise waiting time of the SCL wiring, the start of counting of the high level period high of the SCL wiring waits 300 [ns]. The actual frequency is 357 KHz (2500 + 300 [ns]).
[0028]
As described above, since the load capacity existing in the SCL wiring has not been considered in the past, in the clock transfer system operating as a single master, the clock synchronization function in the clock transfer system of the multi-master configuration acts, so that transmission / reception can be performed. There was a problem that the clock rate decreased.
[0029]
The same applies to the clock transfer system having a multi-master configuration. That is, even in a multi-master clock transfer system, there is a period in which a plurality of devices do not always output a clock, but only a single device outputs a clock as a master. Similarly, during the period of operation in the single master state, there is a problem that the clock synchronization function operates similarly and the transmission / reception clock rate decreases.
[0030]
In view of the above circumstances, an object of the present invention is to provide a clock wiring driving circuit capable of preventing a decrease in transmission / reception clock rate and realizing high-speed transmission / reception even when load capacitance exists in the wiring.
[0031]
[Means for Solving the Problems]
The clock wiring driving circuit of the present invention is
A rising synchronization on / off setting register that outputs a rising synchronization prohibition signal when rising synchronization is turned on or off with respect to the clock wiring and the rising synchronization off is set;
A clock for counting a rising period and a falling period of the clock, outputting a high level clock while counting the rising period, and outputting a low level clock while counting the falling period A clock generation counter that outputs an output signal;
An output terminal connected to the clock wiring, and an output section for driving the clock wiring given the clock output signal;
A sample circuit that holds and outputs the level of the clock wiring;
Using the output of the sample circuit and the output of the clock generation counter, from the point in time when the output terminal of the output unit rises to a high level and the clock wiring maintains a low level, the clock wiring then goes to a high level. A synchronization period detection circuit that outputs a rising synchronization period signal until the time of rising to
When the synchronization on / off setting register does not output the rising synchronization prohibition signal, a count wait signal is supplied to the clock generation counter while the rising synchronization period signal is applied, and the rising period of the clock is counted. When the synchronization on / off setting register outputs the rising synchronization prohibition signal, the count generation signal is not supplied to the clock generation counter regardless of the rising synchronization period signal, and the clock rising period A synchronization circuit that does not wait for the count;
And this
When rising synchronization off is set, a clock is output without synchronizing between the clock wiring and the level of the output terminal of the output unit.
[0032]
Here, the synchronization period detection circuit uses the output of the sample circuit and the output of the clock generation counter to maintain the output terminal of the output unit at a high level but the clock wiring to a low level. From the time when the output terminal falls to the time when the output terminal subsequently falls to a low level, a clock falling synchronization period signal is output,
The synchronization circuit provides a count clear signal to the clock generation counter when receiving the clock falling synchronization period signal regardless of whether or not the synchronization on / off setting register outputs the rising synchronization inhibition signal. And clear the count of the rising period of the clock,
Accordingly, the clock generation counter may be configured to output the clock output signal for outputting a low level clock when the count clear signal is given.
[0033]
The synchronization circuit includes a logic circuit to which the rising synchronization inhibition signal output from the synchronization on / off setting register and the rising synchronization period signal output from the synchronization period detection circuit are provided, and the logic circuit The count wait signal can be output while the rising synchronization inhibition signal is not input and the rising synchronization period signal is input.
[0034]
The clock wiring driving circuit of the present invention is
A rising synchronization on / off setting register that outputs a rising synchronization prohibition signal when rising synchronization is turned on or off with respect to the clock wiring and the rising synchronization off is set;
A clock for counting a rising period and a falling period of the clock, outputting a high level clock while counting the rising period, and outputting a low level clock while counting the falling period A clock generation counter that outputs an output signal;
An output terminal connected to the clock wiring, and an output section for driving the clock wiring given the clock output signal;
A rising synchronization inhibition period for outputting a rising synchronization inhibition period signal from when the clock output signal for outputting a high level clock is output from the clock generation counter until a predetermined rising synchronization inhibition period elapses A setting section;
A sample circuit that holds and outputs the level of the clock wiring;
Using the output of the sample circuit and the output of the clock generation counter, from the point in time when the output terminal of the output unit rises to a high level and the clock wiring maintains a low level, the clock wiring then goes to a high level. A synchronization period detection circuit that outputs a rising synchronization period signal until the time of rising to
When the synchronization on / off setting register outputs the rising synchronization inhibition signal, the rising synchronization inhibition signal is output while the rising synchronization inhibition period setting unit outputs the rising synchronization inhibition period signal. A signal output unit;
When the rising synchronization inhibition signal output unit does not output the rising synchronization inhibition signal, a count waiting signal is given to the clock generation counter while the clock rising synchronization period signal is given, and the rising period of the clock is increased. While waiting for counting, while the rising synchronization inhibition signal output unit outputs the rising synchronization inhibition signal, the count waiting signal is provided to the clock generation counter regardless of the clock rising synchronization period signal, and the clock generation counter A synchronization circuit that forcibly waits for the rising period count;
With this
When rise synchronization off is set, the rise period is forcibly counted without synchronization between the clock wiring and the level of the output terminal of the output unit until the rise synchronization inhibition period elapses. And after the rising synchronization prohibition period elapses, synchronization is established between the clock wiring and the level of the output terminal of the output unit.
[0035]
Here, the synchronization period detection circuit uses the output of the sample circuit and the output of the clock generation counter to maintain the output terminal of the output unit at a high level but the clock wiring to a low level. From the time when the output terminal falls to the time when the output terminal subsequently falls to a low level, a clock falling synchronization period signal is output,
The synchronization circuit provides a count clear signal to the clock generation counter when receiving the clock falling synchronization period signal regardless of whether the rising synchronization inhibition signal output unit outputs the rising synchronization inhibition signal or not. And clear the count of the rising period of the clock,
Accordingly, the clock generation counter may be configured to output the clock output signal for outputting a low level clock when the count clear signal is given.
[0036]
The rising synchronization prohibition period setting unit is
A plurality of flip-flops connected in series, sequentially transferring and outputting the clock output signal output from the clock generation counter at a predetermined timing;
The clock for receiving the clock output signal output from the clock generation counter and the clock output signal output after being transferred by the flip-flop and outputting a high level clock from the clock generation counter A first logic circuit that outputs the rising synchronization inhibition period signal from when an output signal is output until the rising synchronization inhibition period elapses;
The synchronization circuit includes:
A second logic circuit that is provided with the rising synchronization inhibition signal output from the rising synchronization inhibition signal output unit and the rising synchronization period signal output from the synchronization period detection circuit;
The second logic circuit outputs the count wait signal while the rising synchronization inhibition signal is input or while the rising synchronization inhibition signal is not input and the rising synchronization period signal is input. It can also be configured.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0038]
(1) First embodiment
First, the clock wiring driving circuit according to the first embodiment of the present invention will be described.
[0039]
This embodiment stops the clock rise synchronization function when used in a clock transfer system configured as a single master, and when used in a clock transfer system configured with a multi-master, the clock is the same as in the prior art. Rise synchronization. The clock falling synchronization is performed in any system as in the conventional case.
[0040]
As a clock wiring control circuit according to this embodiment, the configuration of an MCU 200 is shown in FIG.
[0041]
The MCU 200 includes a CPU 201 and an I2CBUS control circuit 202. The I2CBUS control circuit 202 includes an SCL generation counter 203, an SCL frequency setting register 204, an SCL driver 205, an output transistor 206, a buffer 207, an SCL sample circuit 208, and an SCL synchronization circuit 209. SCL rising / falling synchronization period detection circuit 210 and SCL synchronization on / off setting register 212.
[0042]
The output terminal of the output transistor 206 is connected to the SCL wiring provided outside the MCU 200. The level of the output clock of the MCU 200 corresponds to the level of the output terminal of the output transistor 206. A pull-up resistor 211 is connected between the SCL wiring and the power supply voltage VDD terminal.
[0043]
First, on / off of the SCL rising synchronization function is determined by a program command executed by the CPU 201. In order to turn off the SCL rising synchronization function, an off command is given to the SCL synchronization on / off setting register 212 and set. From the SCL synchronization on / off setting register 212, a rising synchronization inhibition signal of logic “1” is given to the SCL synchronization circuit 209. As a result, the count waiting signal is not output from the SCL synchronization circuit 209, and the SCL generation counter 203 performs a count operation without synchronization based on the counter clock CLK. The SCL frequency is determined by a program executed by the CPU 201 and written to the SCL frequency setting register 204. In accordance with the set frequency, the count number is given to the SCL generation counter 203, and the count operation is performed.
[0044]
When the SCL rising synchronization function is turned on by a program instruction executed by the CPU 201, the on instruction is given to the SCL synchronization on / off setting register 212 and set. The rising synchronization inhibition signal is not output from the SCL synchronization on / off setting register 212 to the SCL synchronization circuit 209. As a result, the SCL synchronization circuit 209 outputs a count wait signal. The operation in this case is the same as the operation described with reference to FIG.
[0045]
The counter clock CLK is input to the SCL generation counter 203, and the output is input to the gate of the output transistor 206 via the SCL driver 205. When the counter clock CLK becomes low level, the counter clock CLK is turned off and the output terminal of the output transistor 206 rises to high level.
[0046]
The output of the SCL generation counter 203 is input to the SCL rising / falling synchronization period detection circuit 210.
[0047]
Further, the signal level of the SCL wiring is input to the SCL sample circuit 208 to which the clock CLK is input via the buffer 207 and is held in synchronization with the clock CLK, and the output is supplied to the SCL rising / falling synchronization period detection circuit 210. Entered.
[0048]
When the signal level of the SCL wiring rises to a high level, the SCL sample circuit 208 holds the signal in synchronization with the clock CLK and outputs a high level signal. The SCL rising / falling synchronization period detection circuit 210 has an SCL rising synchronization period while the output of the SCL generation counter 203 is at a low level (its own clock output is at a high level) and the output of the SCL sample circuit 208 is at a low level. The signal is output to the SCL synchronization circuit 209.
[0049]
The SCL synchronization circuit 209 outputs a count wait signal while receiving the SCL rising synchronization period signal. As a result, the SCL generation counter 203 waits without starting to count the high level period Thigh. When the SCL synchronization circuit 209 is not given the SCL rising synchronization period signal, it stops outputting the counter wait signal. As a result, the SCL generation counter 203 starts counting during the high level period Thigh and maintains the high level output until the count value reaches the set value.
[0050]
As for the SCL falling, the rounding of the waveform due to the load capacitance is not affected on the SCL wiring, and the clock rate is not lowered, so that the synchronization is performed in the conventional manner.
[0051]
That is, when the signal level of the SCL wiring falls to a low level, the SCL sample circuit 208 holds the signal in synchronization with the clock CLK and outputs a low level signal. The SCL rising / falling synchronization period detection circuit 210 maintains the output of the SCL generation counter 203 at a low level (its own clock is at a high level) and does not fall to a low level, but the output of the SCL sample circuit 208 has a low level. Then, the SCL falling synchronization period signal is output to the SCL synchronization circuit 209.
[0052]
The SCL synchronization circuit 209 gives a counter clear signal to the SCL generation counter 203 when the SCL falling synchronization period signal is given. The SCL generation counter 203 counts the high level period Thigh until the counter clear signal is given. However, when the counter clear signal is given, the SCL generation counter 203 stops the count and starts counting the low level period Tlow. .
[0053]
FIG. 2 shows a more specific circuit configuration of the configuration of the clock wiring control circuit according to the first embodiment.
[0054]
The CPU 201 outputs a chip select signal CS and a write signal WR. The SCL synchronization on / off setting register 212 includes a flip-flop F / F4. When a chip select signal CS for selecting the chip and a write signal WR for turning off the SCL rising synchronization function are output from the CPU 201, the logic “1” is output. "Is output. As a result, the rise synchronization prohibition is set in the flip-flop F / F4, and the rise synchronization inhibition signal of logic “1” is output. When canceling the prohibition of the rising synchronization function, the reset signal RES is given from the CPU 201, the flip-flop F / F4 is reset, and the rising synchronization prohibition signal of logic “1” is not output.
[0055]
When the output from the SCL generation counter 203 is at a low level (its own clock is at a high level), but the output from the SCL sample circuit 208 is at a low level, the SCL rising / falling synchronization period detection circuit 210 receives a logic. A SCL rising synchronization period signal of “1” is output.
[0056]
The SCL synchronization circuit 209 has an AND circuit AN1. A logical “1” SCL rising synchronization period signal and an inverted version of the output from the SCL synchronization on / off setting register 212 are input to the AND circuit AN1. As a result, the SCL rising / falling synchronization period detection circuit 210 detects a rising synchronization period in which a high level signal is output from the SCL generation counter 203 and the signal level of the SCL wiring monitored by the SCL sample circuit 208 is still at a low level. Thus, the SCL rising synchronization period signal of logic “1” is output, the rising synchronization signal of logic “1” is not output, and the output from the SCL synchronization on / off setting register 212 is logic “0”. Only in some cases, a count wait signal of logic “1” is output and provided to the SCL generation counter 203. When a rising synchronization signal of logic “1” is output, an AND circuit is output even during a rising synchronization period in which a high level clock is output from the output terminal of the output transistor 206 and the level of the SCL wiring is still at a low level. A count wait signal of logic “1” is not output from AN1.
[0057]
The SCL generation counter 203 is connected to a plurality of stages in series for counting up, and flip-flops F / F1, F / F2,..., F / F3, and flip-flops F / F1, F, which sequentially shift the counter clock CLK. / F2,..., And a NOR circuit NR1 whose output side is connected to the reset terminal of F / F3.
[0058]
The NOR circuit NR1 outputs a logic “0” reset signal to the reset terminals of all flip-flops F / F1, F / F2,..., F / F3 during a period when the logic “1” count waiting signal is output. To reset and do not start counting. If the count wait signal of logic “1” is not output due to the rise synchronization inhibition, a reset signal of logic “0” is output from the NOR circuit NR1 to the reset terminals of the flip-flops F / F1, F / F2,. Output is stopped and the count operation is performed. When the output from the flip-flop F / F3 at the final stage, that is, the count value reaches the value set in the SCL frequency setting register 204, a logic “1” signal is input to the NOR circuit NR1, and the logic “0” The reset signal is input to the reset terminals of all the flip-flops F / F1 to F / F3, and the count operation is reset.
[0059]
With respect to the SCL falling, synchronization is performed as described above.
[0060]
When the signal level of the SCL wiring falls to a low level, the SCL sample circuit 208 holds the signal in synchronization with the clock CLK and outputs a low level signal.
[0061]
In the SCL rising / falling synchronization period detection circuit 210, the output of the SCL generation counter 203 is still kept at a low level (its own clock output is high), but the output of the SCL sample circuit 208 falls to a low level. If so, it is determined that it is the SCL falling synchronization period, and an SCL falling synchronization period signal of logic “1” is output to the SCL synchronization circuit 209.
[0062]
The SCL synchronization circuit 209 supplies the SCL falling synchronization period signal of logic “1” to the SCL generation counter 203 as a counter clear signal of logic “1”. The SCL generation counter 203 counts for a high level period Thigh until this counter clear signal is given, but when the counter clear signal is given, a signal of logic “0” is sent from the NOR circuit NR1 to the flip-flop F / Output to the reset terminals of F1, F / F2,..., F / F3, and the count operation in the high level period Thigh is reset. Thereafter, counting of the low level period Tlow is started.
[0063]
According to the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 2, the following operations and effects are achieved by prohibiting the falling edge synchronization.
[0064]
As shown in FIG. 3, the high-level period Thigh and the low-level period Tlow of the own clock output from the MCU 200 are 900 ns and 1600 ns as specified, and the SCL wiring level rises from the time point c to d. It is assumed that time is required up to the maximum standard value of 300 ns.
[0065]
The high level period Thigh and the low level period Tlow of the SCL wiring are determined as follows.
[0066]
First, assuming that the maximum rise time in the SCL wiring is Tr, the count number of the high level period Thigh is:
(Thigh count-Tr) ≧ Thigh minimum standard (1)
Set to satisfy.
[0067]
When the maximum fall time in the SCL wiring is Tf, the count number of the low level period Tlow is
(Tlow count-Tf) ≧ Tlow minimum standard (2)
Set to satisfy.
[0068]
For example, the clock of the SCL wiring is set to 400 kHz (period 2500 ns) in the high speed mode. In this case, the maximum standard of Tr is 300 ns, the maximum standard of Tf is 300 ns, the minimum standard of Tlow is 1300 ns, and the minimum standard of Thigh is 600 ns.
[0069]
From the above equation (1), from (Thigh count number−300) ≧ 600, the Thigh count number is set to 900 ns.
[0070]
Further, from the above equation (2), from (Tlow count number−300) ≧ 1300, the Tlow count number is set to 1600 ns.
[0071]
When the clock of the SCL wiring is 100 kHz (period 10000 ns) in the low speed mode, the maximum standard of Tr is 1000 ns, the maximum standard of Tf is 300 ns, the minimum standard of Tlow is 4700 ns, and the minimum standard of Thigh is 4000 ns.
[0072]
From the above equation (1), the count number of Thigh is set to 5000 ns from (Thigh count number−1000) ≧ 4000.
[0073]
Further, from the above equation (2), from (Tlow count number−300) ≧ 4700, the Tlow count number is set to 5000 ns.
[0074]
According to the first embodiment, there is no counting waiting time of the high level period Thigh generated in the conventional circuit described with reference to FIG. 17, and the clock rate is prevented from lowering.
[0075]
(2) Second embodiment
When the clock wiring drive circuit according to the first embodiment is used in a clock transfer system composed of a single master, it does not perform SCL rising synchronization at all, thereby preventing a decrease in clock rate as compared with the prior art. Can do. However, when used in a clock transfer system composed of multi-masters, it is impossible to synchronize between a plurality of clocks without performing SCL rising synchronization at all. . For this reason, in a system with a multi-master configuration, it is impossible to prevent a decrease in clock rate.
[0076]
On the other hand, this embodiment pays attention to the fact that even in a clock transfer system composed of multi-masters, there is a period in which only a single device outputs a clock and actually operates in a single master state. The SCL rise synchronization for a predetermined period is forcibly prohibited from counting the rise period, and the rise synchronization is performed after the predetermined period has elapsed, thereby preventing a decrease in the clock rate while operating in the single master state. It is characterized in that it can operate as a multi-master without any trouble by realizing a synchronous operation in the state of operating in the master state.
[0077]
As a clock wiring control circuit according to this embodiment, the configuration of the MCU 300 is shown in FIG.
[0078]
The MCU 300 includes a CPU 301 and an I2CBUS control circuit 302. The I2CBUS control circuit 302 includes an SCL generation counter 303, an SCL frequency setting register 304, an SCL driver 305, an output transistor 306, a buffer 307, an SCL sample circuit 308, and an SCL synchronization circuit 309. , An SCL rising / falling synchronization period detection circuit 310, an SCL synchronization on / off setting register 312, and a rising synchronization prohibition period setting unit 313. The rise synchronization prohibition period setting unit 313 includes an AND circuit AN21 and a plurality of flip-flops F / F21 to F / F23 connected in series.
[0079]
An output terminal of the output transistor 306 is connected to an SCL wiring provided outside the MCU 300. A pull-up resistor 311 is connected between the SCL wiring and the power supply voltage VDD terminal.
[0080]
As in the first embodiment, the output of the SCL generation counter 303 is input to the SCL rising / falling synchronization period detection circuit 310.
[0081]
The signal level of the SCL wiring is input to the SCL sample circuit 308 to which the clock CLK is input via the buffer 307, is held in synchronization with the clock CLK, and the output is input to the SCL rising / falling synchronization period detection circuit 310. Is done.
[0082]
When the signal level of the SCL wiring rises to a high level, the SCL sample circuit 308 holds the signal in synchronization with the clock CLK and outputs a high level signal. The SCL rising / falling synchronization period detection circuit 310 rises while the output of the SCL generation counter 303 is at a low level (its own clock output is high) and the output of the SCL sample circuit 308 is still at a low level. The synchronization period signal is output to the SCL synchronization circuit 309.
[0083]
The on / off state of the SCL rising synchronization function is determined by a program instruction executed by the CPU 301. In order to turn off the SCL rising synchronization function for a predetermined period, an off command is given to the SCL synchronization on / off setting register 312 and set. When a rising synchronization inhibition signal of logic “1” is output from the SCL synchronization on / off setting register 312, it is input to one input terminal of the AND circuit AN22. On the other hand, when the SCL rising synchronization function is turned on, an on command is given to the SCL synchronization on / off setting register 312 and set. The SCL synchronization on / off setting register 312 does not output the rising synchronization inhibition signal of logic “1”. The operation in this case is the same as that in the first embodiment.
[0084]
When the rising synchronization inhibition period setting unit 313 receives a low level signal from the SCL generation counter 303, it is inverted and a high level signal is input to one input terminal of the AND circuit AN21.
[0085]
The transfer clock is input to the flip-flops F / F21 to F23, and the high-level output input to the first-stage flip-flop F / F21 is sequentially transferred. The number of flip-flops is set so that the transfer time from the first flip-flop F / F21 to the final flip-flop F / F23 corresponds to the SCL rising synchronization inhibition period.
[0086]
When a high level signal is input from the SCL generation counter 303 to one input terminal of the AND circuit AN21, the low level output of the flip-flop F / F23 is inverted and the high level signal is input to the other input terminal. Since it is input, a high level is output from the AND circuit AN21. This is input to the other input terminal of the AND circuit AN22, and a high level rising synchronization inhibition signal is output from the AND circuit 22. When the SCL synchronization inhibition period elapses in the rising synchronization inhibition period setting unit 313, a high level signal is output from the flip-flop F / F23 and is input as a low level to the AND circuit AN21. Is output to the other input terminal of the AND circuit AN22. As a result, the rise synchronization inhibition signal of logic “1” is not output from the AND circuit AN22.
[0087]
During the period when the rising edge synchronization inhibition signal of logic “1” is given to one input terminal of the OR circuit OR11 of the SCL synchronization circuit 309, the SCL generation circuit 303 outputs a count wait signal from the SCL synchronization circuit 309. The count operation is forcibly waited without performing the synchronization operation.
[0088]
When the rising synchronization inhibition period elapses and the rising synchronization inhibition signal of logic “1” is not given to one terminal of the OR circuit OR11 of the SCL synchronization circuit 309, the SCL rising synchronization function is turned on. While the SCL rising / falling synchronization period detection circuit 310 is outputting a rising synchronization signal of logic “1”, it is input to one input terminal of the OR circuit OR11 and a count wait signal is output. When the rising synchronization signal of logic “1” is not output from the SCL rising / falling synchronization period detection circuit 310, the count wait signal is not output from the OR circuit OR 11. Thereby, the SCL generation counter 303 starts the counting operation of the rising period.
[0089]
In the SCL generation counter 303, counting of the high level period Thigh starts, a low level signal is output, and the output terminal of the output transistor 306 becomes high level. When the counting of the high level period Thigh ends, the SCL generation counter 303 outputs a high level, and the output terminal of the output transistor 306 falls to a low level.
[0090]
As for the SCL fall, as in the first embodiment, the SCL wiring is not affected by the rounding of the waveform due to the load capacitance, and the clock rate is not lowered.
[0091]
That is, when the signal level of the SCL wiring falls to a low level, the SCL sample circuit 308 holds the signal in synchronization with the clock CLK and outputs a low level signal. The SCL rising / falling synchronization period detection circuit 310 maintains the output of the SCL generation counter 303 at a low level (its own clock is at a high level) and does not fall to a low level, but the output of the SCL sample circuit 308 has a low level. Then, the SCL falling synchronization period signal is output to the SCL synchronization circuit 309.
[0092]
The SCL synchronization circuit 309 gives a counter clear signal to the SCL generation counter 303 when the SCL falling synchronization period signal is given. The SCL generation counter 303 counts the high level period Thigh until the counter clear signal is given. However, when the counter clear signal is given, the SCL generation counter 303 stops the count and starts counting the low level period Tlow. .
[0093]
The count numbers of the high level period Thigh and the low level period Tlow when the SCL rising synchronization is turned off for a predetermined time, that is, the SCL rising synchronization prohibition period according to the present embodiment will be described with reference to FIG. Here, it is assumed that the period during which the SCL rise synchronization is turned off is the maximum standard TrS of the rise time. Also, let Tf be the maximum fall time standard.
[0094]
The number of counts during the period Thigh when the SCL waveform is high is
Count number of high level period Thigh ≥ minimum standard of Thigh width (3)
And
[0095]
The number of counts during the period Tlow when the SCL waveform is low is:
(Tlow count-Tf) ≧ Tlow width minimum standard (4)
And
[0096]
In the second embodiment, a high level period Thigh and a low level period Tlow when the clock transfer system is actually operating in the single master state will be described with reference to FIG.
[0097]
For example, the clock of the SCL wiring is set to 400 kHz (period 2500 ns) in the high speed mode. In this case, the maximum standard of Tr is 300 ns, the maximum standard of Tf is 300 ns, the minimum standard of Tlow is 1300 ns, and the minimum standard of Thigh is 600 ns.
[0098]
From the above equation (3), since the Thigh count number ≧ 600, the Thigh count number is set to 600 ns.
[0099]
Further, from the above equation (4), from (Tlow count number−300) ≧ 1300, the Tlow count number is set to 1600 ns.
[0100]
When the clock of the SCL wiring is 100 kHz (period 10000 ns) in the low speed mode, the maximum standard of Tr is 1000 ns, the maximum standard of Tf is 300 ns, the minimum standard of Tlow is 4700 ns, and the minimum standard of Thigh is 4000 ns.
[0101]
From the above equation (3), since the Thigh count number ≧ 4000, the Thigh count number is set to 4000 ns.
[0102]
Further, from the above equation (4), from (Tlow count number−300) ≧ 4700, the Tlow count number is set to 5000 ns.
[0103]
In this way, in the clock transfer system configured as a multi-master, the SCL rising edge synchronization prohibition is prohibited only for a predetermined period in the period of operating in the single master state, so that the original clock rate (frequency 400 kHz, period The clock can be transferred without reducing 2500 ns).
[0104]
Next, in the second embodiment, a high-level period Thigh and a low-level period Tlow when the clock transfer system operates in a multi-master state will be described with reference to FIGS. In this case, unlike the case of operating as a single master, the clock rate may be reduced in some cases, but it will operate as a multi-master without any problems by performing SCL rising synchronization after a predetermined prohibition period. Is possible.
[0105]
Here, the clock of the SCL wiring is 400 kHz (period 2500 ns) in the high speed mode, the maximum standard of Tr is 300 ns, the maximum standard of Tf is 300 ns, the minimum standard of Tlow is 1300 ns, and the minimum standard of Thigh is 600 ns.
[0106]
(A) The SCL frequency, the high-level period Thigh, and the low-level period Tlow are all the same between the clock output by this apparatus and the clock output by another apparatus, and the own clock is the clock of another device. When standing up earlier
The condition for achieving synchronization without causing a decrease in the clock rate is that the clock output by this apparatus and the clock output by another apparatus have the same frequency, and the time required for the rising of the clock of the SCL wiring is 300 ns at maximum. This is the case when it falls within the following range.
[0107]
As shown in FIG. 7, at the time point a, the SCL (this device) becomes a low level, and the SCL wiring becomes a low level. The SCL (other device) stops counting the high level period Thigh in accordance with the falling-synchronization principle, and starts counting the low level period Tlow from this time point a.
[0108]
The SCL synchronized with the time point a (another device) tries to count Tlow = 1600 ns and Thigh = 900 ns as in the SCL of FIG. 7 (other device: after synchronization at the time point a).
[0109]
Both SCL (this device) and SCL (other devices) end the low level period Tlow count 1600 ns at time point c.
[0110]
From time c, the SCL (another device) starts counting for a high level period Thigh900 ns. The SCL (this device) starts a high-level period Thigh count 600 ns from the time point e after the time point e has elapsed since the time point c.
[0111]
As a result, at the time point f, both the SCL (this device) and the SCL (other devices) finish counting the high level period Thigh.
[0112]
Even if the SCL wiring is lost due to the load capacity (the maximum standard for rounding is 300 ns), synchronization can be realized without falling within 300 ns from time point c to time point e without reducing the clock rate. it can.
[0113]
(B) The SCL frequency, the high level period Thigh, and the low level period Tlow are all the same between the clock output by this apparatus and the clock output by another apparatus, and the clocks of the other apparatuses rise first. Case
At time point a, the SCL (this device) goes to a low level, and the SCL wiring goes to a low level. The SCL (another device) stops counting the high level period Thigh and starts counting the low level period Tlow according to the falling synchronization principle.
[0114]
Since the SCL synchronized with the time point a (another device) tries to count Tlow = 1700 ns and Thigh = 800 ns like the SCL (another device: after synchronization at the time point a), the following (other device) Is considered in SCL (other devices: after synchronization at time point a).
[0115]
SCL (this device) outputs a low level for a period of 1600 ns from time point a to time point c. SCL (another device) outputs a low level for a period of 1700 ns from time point a to time point d. As a result, the SCL wiring is at a low level for a period of 1700 ns, and the SCL (this device) has its own clock rising before the clocks of other devices. In the case of the conventional circuit, the TrS period is also a synchronization period, but becomes a synchronization inhibition period, and the SCL (this device) starts counting 600 ns from the time point f. The SCL (other device) starts counting 800 ns from the time point d, and finally ends the counting of the high level period Thigh at the time point h.
[0116]
In this case, the cycle Tcyc is maintained at 2500 ns, and synchronization is realized without causing a decrease in the clock rate.
[0117]
Here, when the SCL wiring cannot rise steeply from the time point d due to the influence of the load capacitance, it takes time to rise up to the time point g after 300 ns from the time point d, that is, 100 ns after the time point f, as indicated by the broken line. think of. In this case, during the period from the time point f to the time point g, the present apparatus waits for a count of the high level period Thigh and counts until 600 ns has elapsed from the time point g. As a result, Tcyc becomes 2600 ns and the clock rate is lowered, but the synchronous operation can be realized without any trouble. At this time, other devices start counting 800 ns from time point g, but since this device sets the SCL wiring to the low level at 600 ns, the high-level period Thigh is stopped at that time and the low-level output is output. become.
[0118]
(C) The frequency is the same (400 kHz, cycle 2500 ns) between the clock output by this device and the clock output by another device, and the high level period Thigh and the low level period Tlow are different.
As for the other devices, as described in FIG. 8, it is assumed that the falling synchronization is completed at the time point a. When the clock of the other device rises earlier than its own clock, the SCL (other device) waits for the count of the high level period Thigh in accordance with the rising synchronization principle during the period from the time point b to the time point c.
[0119]
In this case, the clock rate does not decrease and synchronization is performed without any trouble.
[0120]
(D) When the SCL frequency is different between the clock output from this device and the clock output from the other device (other device is 250 kHz, cycle is 4000 ns)
The SCL (this device) waits for the count of the high level period Thigh from the time point c to the time point d, and starts counting 600 ns of the high level period Thigh from the time point d. As a result, the SCL (this device) falls to the low level at time f, and the SCL wiring goes to the low level. The SCL (another device) stops counting the high level period Thigh at the time point f and starts counting the low level period Tlow.
[0121]
In this case, the clock rate is lowered, but the synchronous operation can be realized without any trouble.
[0122]
As described above, according to the second embodiment, in the clock transfer system composed of multi-masters, only a single device outputs a clock and operates in a single master state for a predetermined period SCL. Prohibiting rising synchronization prevents the clock rate from decreasing, and while operating in the multi-master state, prohibiting SCL rising synchronization for a predetermined period and then synchronizing may cause a decrease in clock rate. However, synchronization can be realized without any trouble.
[0123]
The above-described embodiment is an example, and does not limit the present invention. Various modifications can be made within the scope of the claims. For example, the frequency, the high level, the low level period, and the numerical value of the count waiting time in the above embodiment are merely examples.
[0124]
【The invention's effect】
As described above, the clock wiring drive circuit of the present invention can reduce the clock rate even when there is a load capacity in the clock wiring by turning off clock rising synchronization in a clock transfer system operating with a single master. It is possible to prevent and realize high-speed transmission / reception.
[0125]
Alternatively, the clock wiring drive circuit according to the present invention also turns off clock rising synchronization and forcibly waits for a high level period for a predetermined period, and then performs synchronization even in a clock transfer system composed of multi-masters. By starting counting, even in a multi-master configuration, when operating with a single master, even if there is a load capacity on the clock wiring, the clock rate is prevented from dropping and operating with a multi-master. In this state, the synchronous operation can be performed without any trouble.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a clock wiring driving circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a more specific circuit configuration of the clock wiring driving circuit according to the first embodiment.
FIG. 3 is a time chart showing counting of a high level period and a low level period in the clock wiring driving circuit shown in FIGS. 1 and 2;
FIG. 4 is a block diagram showing a configuration of a clock wiring driving circuit according to a second embodiment of the present invention.
FIG. 5 is a time chart showing a clock rate in the clock wiring driving circuit according to the second embodiment.
FIG. 6 is a time chart showing a clock rate when a load capacitance exists in the SCL wiring in the system operating as a single master in the clock wiring driving circuit according to the second embodiment.
7 shows a clock wiring driving circuit according to the second embodiment in which the SCL frequency, the high level period, and the low level of the output clock of the present apparatus and the output clock of another apparatus in a system that operates as a multi-master. The time chart which showed the clock rate when all the periods are the same and the clock of this apparatus rises before the clock of another apparatus.
FIG. 8 is a circuit diagram of the clock wiring drive circuit according to the second embodiment. In the system operating as a multi-master, the SCL frequency of the output clock of this device and the output clock of another device, the high level period, and the low level The time chart which showed the clock rate when all the periods are the same and the clock of another apparatus rises ahead of the clock of this apparatus.
FIG. 9 shows a clock wiring driving circuit according to the second embodiment in which the SCL frequency of the output clock of the present apparatus is the same as that of the output clock of another apparatus, and the high level period, Time chart showing the clock rate when the low level period is different.
FIG. 10 shows the clock rate when the SCL frequency of the output clock of this apparatus is different from the output clock of another apparatus in the system operating as a multi-master in the clock wiring driving circuit according to the second embodiment. Time chart.
FIG. 11 is a block diagram showing a configuration of a clock transfer system configured as a single master.
FIG. 12 is a block diagram showing a configuration when a load capacity exists in a clock transfer system configured as a single master.
FIG. 13 is a block diagram showing a configuration of a clock transfer system configured as a multi-master.
FIG. 14 is a time chart for explaining a clock synchronization method of I2CBUS.
FIG. 15 is a block diagram showing a configuration of a conventional clock wiring driving circuit.
FIG. 16 is a time chart showing a clock waveform when there is no wiring load capacitance;
FIG. 17 is a time chart showing a clock waveform and a problem in this case when a wiring load capacity exists.
[Explanation of symbols]
200, 300 MCU
201, 301 CPU
202, 302 I2CBUS control circuit
203, 303 SCL generation counter
204, 304 SCL frequency setting register
205, 305 SCL driver
206,306 Output transistor
207, 307 buffer
208, 308 SCL sample circuit
209, 309 SCL synchronization circuit
210, 310 SCL rising / falling synchronization period detection circuit
211, 311 Pull-up resistor
212, 312 SCL synchronous on / off setting register
313 Rise synchronization prohibition period setting section

Claims (6)

A circuit for driving a clock wiring,
A rising synchronization on / off setting register that outputs a rising synchronization prohibition signal when rising synchronization is turned on or off with respect to the clock wiring and the rising synchronization off is set;
A clock for counting a rising period and a falling period of the clock, outputting a high level clock while counting the rising period, and outputting a low level clock while counting the falling period A clock generation counter that outputs an output signal;
An output terminal connected to the clock wiring, and an output section for driving the clock wiring given the clock output signal;
A sample circuit that holds and outputs the level of the clock wiring;
Using the output of the sample circuit and the output of the clock generation counter, from the point in time when the output terminal of the output unit rises to a high level and the clock wiring maintains a low level, the clock wiring then goes to a high level. A synchronization period detection circuit that outputs a rising synchronization period signal until the time of rising to
When the synchronization on / off setting register does not output the rising synchronization prohibition signal, a count wait signal is supplied to the clock generation counter while the rising synchronization period signal is applied, and the rising period of the clock is counted. When the synchronization on / off setting register outputs the rising synchronization prohibition signal, the count generation signal is not supplied to the clock generation counter regardless of the rising synchronization period signal, and the clock rising period A synchronization circuit that does not wait for the count;
And a clock wiring driving circuit that outputs a clock without synchronization between the clock wiring and the level of the output terminal of the output section when rising synchronization off is set thereby . The synchronization period detection circuit uses the output of the sample circuit and the output of the clock generation counter to maintain the output terminal of the output unit at a high level, but the clock wiring falls to a low level. From the time point to the time point when the output terminal subsequently falls to a low level, a clock falling synchronization period signal is output,
The synchronization circuit provides a count clear signal to the clock generation counter when receiving the clock falling synchronization period signal regardless of whether or not the synchronization on / off setting register outputs the rising synchronization inhibition signal. And clear the count of the rising period of the clock,
2. The clock wiring drive circuit according to claim 1, wherein the clock generation counter outputs the clock output signal for outputting a low level clock when the count clear signal is given. The synchronization circuit includes a logic circuit to which the rising synchronization inhibition signal output from the synchronization on / off setting register and the rising synchronization period signal output from the synchronization period detection circuit are provided, and the logic circuit 3. The clock wiring drive circuit according to claim 1, wherein the count wait signal is output while the rising synchronization prohibition signal is not input and the rising synchronization period signal is input. A circuit for driving a clock wiring,
A rising synchronization on / off setting register that outputs a rising synchronization prohibition signal when rising synchronization is turned on or off with respect to the clock wiring and the rising synchronization off is set;
A clock for counting a rising period and a falling period of the clock, outputting a high level clock while counting the rising period, and outputting a low level clock while counting the falling period A clock generation counter that outputs an output signal;
An output terminal connected to the clock wiring, and an output section for driving the clock wiring given the clock output signal;
A rising synchronization inhibition period for outputting a rising synchronization inhibition period signal from when the clock output signal for outputting a high level clock is output from the clock generation counter until a predetermined rising synchronization inhibition period elapses A setting section;
A sample circuit that holds and outputs the level of the clock wiring;
Using the output of the sample circuit and the output of the clock generation counter, from the point in time when the output terminal of the output unit rises to a high level and the clock wiring maintains a low level, the clock wiring then goes to a high level. A synchronization period detection circuit that outputs a rising synchronization period signal until the time of rising to
When the synchronization on / off setting register outputs the rising synchronization inhibition signal, the rising synchronization inhibition signal is output while the rising synchronization inhibition period setting unit outputs the rising synchronization inhibition period signal. A signal output unit;
While the rising synchronization prohibition signal output unit outputs the rising synchronization prohibition signal, regardless of the presence of the rising synchronization period signal, the count generation signal is supplied to the clock generation counter, and the rising synchronization operation is not performed. Forcibly wait for counting of the rising period of the clock, and when the rising synchronization prohibition signal output unit does not output the rising synchronization prohibition signal, while the clock rising synchronization period signal is given, the count wait signal A synchronization circuit that waits for a count of the rising period of the clock,
When rising synchronization off is set by this, the rising edge is not synchronized between the clock wiring and the level of the output terminal of the output unit until the rising synchronization prohibition period elapses. A clock wiring driving circuit, which forcibly waits for a period count and synchronizes between the clock wiring and the level of the output terminal of the output unit after the rising synchronization prohibition period has elapsed. The synchronization period detection circuit uses the output of the sample circuit and the output of the clock generation counter to maintain the output terminal of the output unit at a high level, but the clock wiring falls to a low level. From the time point to the time point when the output terminal subsequently falls to a low level, a clock falling synchronization period signal is output,
The synchronization circuit provides a count clear signal to the clock generation counter when receiving the clock falling synchronization period signal regardless of whether the rising synchronization inhibition signal output unit outputs the rising synchronization inhibition signal or not. And clear the count of the rising period of the clock,
5. The clock wiring drive circuit according to claim 4, wherein the clock generation counter outputs the clock output signal for outputting a low level clock when the count clear signal is given. The rising synchronization prohibition period setting unit is
A plurality of flip-flops connected in series, sequentially transferring and outputting the clock output signal output from the clock generation counter at a predetermined timing;
The clock for receiving the clock output signal output from the clock generation counter and the clock output signal output after being transferred by the flip-flop and outputting a high level clock from the clock generation counter A first logic circuit that outputs the rising synchronization inhibition period signal from when an output signal is output until the rising synchronization inhibition period elapses;
The synchronization circuit includes:
A second logic circuit that is provided with the rising synchronization inhibition signal output from the rising synchronization inhibition signal output unit and the rising synchronization period signal output from the synchronization period detection circuit;
The second logic circuit outputs the count wait signal while the rising synchronization inhibition signal is input or while the rising synchronization inhibition signal is not input and the rising synchronization period signal is input. 6. The clock wiring drive circuit according to claim 4 or 5, wherein:

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