JP4215711B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a technology effective when applied to the manufacture of a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).

  Recent DRAMs have a so-called stacked capacitor structure in which an information storage capacitor element is disposed above a memory cell selection MISFET in order to compensate for a decrease in the amount of charge stored in the information storage capacitor element due to miniaturization of the memory cell. Is adopted. A DRAM employing this stacked capacitor structure is roughly divided into a capacitor under bitline (CUB) structure (for example, Japanese Patent Laid-Open No. 7-192723) in which an information storage capacitor is arranged below the bit line. And JP-A-8-204144) and a capacitor over bitline (COB) structure (for example, JP-A-7-122654) in which an information storage capacitor element is disposed above a bit line. (Kaihei 7-106437).

  Of the two types of stacked capacitor structures described above, the COB structure in which the information storage capacitor element is disposed above the bit line is more suitable for miniaturization of the memory cell than the CUB structure. This is because a CUB structure in which a bit line is arranged above the information storage capacitor element because it is necessary to increase the surface area by increasing the surface area of the structure in order to increase the amount of charge stored in the miniaturized information storage capacitor element. This is because the aspect ratio of the contact hole connecting the bit line and the memory cell selecting MISFET becomes extremely large, and it is difficult to open the hole.

Further, in recent large capacity DRAMs such as 64 megabits (Mbit) or 256 megabits, contacts for connecting a bit line or an information storage capacitive element and a substrate to a space of a gate electrode of a miniaturized memory cell selection MISFET. When forming the hole, the top and side walls of the gate electrode are covered with a silicon nitride film, and the contact hole is self-aligned with the space of the gate electrode by utilizing the etching rate difference between the silicon oxide film and the silicon nitride film. In order to employ a self-alignment contact (SAC) technique (for example, Japanese Patent Laid-Open No. 9-252098) that opens holes in the gate electrode or to promote a reduction in resistance of the gate electrode, the gate electrode is made of W (tungsten). A polymetal gate structure mainly composed of a refractory metal material such as JP-A-7-94716 Have or to adopt a multi-address).
JP-A-7-192723 JP-A-8-204144 JP-A-7-122654 JP-A-7-106437 Japanese Patent Laid-Open No. 9-252098 JP-A-7-094716

  As the present inventor has developed 256 megabit (Mbit) DRAM and 1 gigabit (Gbit) DRAM, the present inventor is considering reducing the bit line capacity as one countermeasure for increasing the refresh time interval. .

  The bit line capacitance component is divided into a pair of adjacent bit lines, a pair of substrates, a pair of storage electrodes, a pair of word lines, and a pair of plate electrodes. In the case of a COB structure in which an information storage capacitor element is disposed above a bit line. The capacitance component with respect to the word line is the main component. Therefore, in order to reduce the bit line capacitance, first, it is the highest priority to reduce the capacitance against the word line.

  As described above, in the conventional manufacturing process employing the self-aligned contact (SAC) technique, the upper portion and the side wall of the gate electrode are covered with a silicon nitride film having a high etching selectivity with respect to the silicon oxide film. However, since the relative dielectric constant of the silicon nitride film is about twice as large as that of the silicon oxide film, if the upper portion and the side wall of the gate electrode are covered with the silicon nitride film, the bit line capacity to the word line increases. End up.

  An object of the present invention is to provide a technique capable of reducing the bit line capacity in a DRAM with a reduced memory cell size.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
(1) A semiconductor integrated circuit device of the present invention is formed on a semiconductor board, and the active region of the island-shaped pattern surrounded by the surrounding device isolation region, across the active region, the first and the gate of the MISFET A second word line; a cap insulating film formed on each of the first and second word lines; a contact hole formed between the first and second word lines; and an interior of the contact hole A conductor formed on the conductor, a first insulating film formed around the conductor, a second insulating film formed between the conductor and the first and second word lines, A semiconductor integrated circuit device having a third insulating film formed between the first and second word lines on the element isolation region and defining the contact hole on the element isolation region side , Above First insulating film, the bottom of the contact hole is formed so as to surround the periphery of the conductor, in the upper portion of the contact hole, lower than the height of the conductor in the first and second word line sidewall The second insulating film is formed on the side wall of the third insulating film at substantially the same height as the conductor , and the second insulating film is formed at the bottom of the contact hole with the first insulating film and the first and second insulating films. The height of the cap insulating film is approximately the same as the height of the conductor, the film thickness thereof is smaller than the film thickness of the first insulating film, and the height of the cap insulating film is The height of the conductor is substantially the same.
(2) The method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps.
(A) a step of selectively forming an element isolation region on a semiconductor substrate to partition an active region of an island pattern;
( B ) forming a cap insulating film including a first silicon nitride film on the first conductor film after forming the first conductor film on the semiconductor substrate;
(C) by etching the first conductive film and the cap insulating film, the first covering the upper portion of the first and second word line and the previous SL first and second word lines crossing the active region Forming the first and second cap insulating films;
( D ) By performing impurity implantation on the semiconductor substrate, a second MISFET having a part of the first word line as a gate electrode and a part of the second word line as a gate electrode. Forming a MISFET of
( E ) A second silicon nitride film is formed to cover the first and second word lines and the first and second cap insulating films, and then between the first and second word lines. Forming a first silicon oxide film on the semiconductor substrate, and forming a mask pattern having a slit-like opening extending in a long side direction of the active region on the first silicon oxide film; ,
A mask pattern having an (f) said slit-shaped opening by etching the first oxide silicon film used as a mask, wherein the first and second MISFET sources, one of the upper portion of the drain region first An opening is formed, and a second opening is formed on the other upper portion of the source and drain regions, and at the same time, the first and second cap insulating films are exposed, and the second silicon nitride film is exposed. Forming a first sidewall insulating film ,
( G ) After forming the second silicon oxide film so as to cover the first and second opening portions, the first and second silicon oxide films are anisotropically etched . A second side wall insulating film made of a second silicon oxide film having a lower height than the first side wall insulating film on the side wall of the word line and thicker at the bottom than the first side wall insulating film is formed. The process of
( H ) forming a second conductor film on the entire surface ;
( I ) A step of planarizing with the first silicon nitride film constituting part of the first and second cap insulating films as a stopper .

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The height of the first insulating film formed around the conductor formed inside the contact hole is made lower than the height of the conductor, and the height of the cap insulating film formed on the word line is set to the height of the conductor. By making the height approximately the same, a sufficient contact area between the through hole formed in the upper portion of the contact hole and the conductor in the contact hole can be secured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is an overall plan view of a semiconductor chip 1A on which a DRAM (Dynamic Random Access Memory) of this embodiment is formed.

  A DRAM having a storage capacity of, for example, 256 Mbit is formed on the main surface of the rectangular semiconductor chip 1A. This DRAM has a storage section composed of a plurality of memory arrays (MARY) and a peripheral circuit section PC arranged around them. A plurality of bonding pads BP to which wires, bump electrodes, etc. are connected are arranged in a row at the center of the semiconductor chip 1A.

  FIG. 2 is a cross-sectional view of a semiconductor substrate (hereinafter referred to as a substrate) showing one end of the storage unit.

  For example, a p-type well 2 is formed on the main surface of a substrate 1 made of p-type single crystal silicon, and an element isolation groove 4 is formed in the p-type well 2. A plurality of memory cells are formed in the active region of the p-type well 2 whose periphery is defined by the element isolation trench 4. Each of the memory cells is composed of one memory cell selection MISFET Qt composed of an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) and one information storage capacitive element C formed on the memory cell selection MISFET Qt. . The memory cell selecting MISFET Qt is mainly composed of a gate insulating film 6, a gate electrode 7 constituting a word line WL in a region other than the active region, and a pair of n-type semiconductor regions (source and drain regions) 8. The gate electrode 7 (word line WL) is composed of, for example, a three-layer conductor film in which an n-type polycrystalline silicon film doped with P (phosphorus), a WN (tungsten nitride) film, and a W (tungsten) film are stacked. ing.

  A p-type well and an n-type well are formed in the substrate 1 of the peripheral circuit portion (PC) not shown in the drawing. An n-channel MISFET is formed in the active region of the p-type well, and a p-channel MISFET is formed in the active region of the n-type well. An n-channel type MISFET is mainly composed of a gate insulating film, a gate electrode, and a pair of n-type semiconductor regions (source and drain regions). A p-channel type MISFET is mainly composed of a gate insulating film, a gate electrode, and a pair of p-type semiconductor regions. (Source and drain regions). That is, the peripheral circuit unit (PC) is configured by a complementary MISFET in which an n-channel MISFET and a p-channel MISFET are combined.

  As shown in FIG. 2, two side wall insulating films 10 and 11 are formed on the side wall of the gate electrode 7 (word line WL) of the memory cell selecting MISFET Qt. Out of these sidewall insulating films 10 and 11, the outer first sidewall insulating film 11 is formed of a silicon oxide film having a film thickness of, for example, about 30 nm, and the inner second sidewall insulating film 10 is the first The silicon nitride film is thinner than the side wall insulating film 11 (for example, about 10 nm to 15 nm). The height of the side wall insulating film 11 made of the silicon oxide film is higher than the upper surface of the gate electrode 7 (word line WL) and the cap insulating film 9 covering the upper portion of the gate electrode 7 (word line WL). It is lower than the upper end.

  In the space of the gate electrode 7, contact holes (opening portions) 12 and 13 surrounded by the two-layer sidewall insulating films 10 and 11 are formed. Inside the contact holes 12 and 13, For example, a plug 14 made of an n-type polycrystalline silicon film doped with P (phosphorus) is buried.

  A silicon oxide film 31 is formed on the memory cell selection MISFET Qt, and a bit line BL for reading data of the memory cell is formed on the silicon oxide film 31. For example, the bit line BL is formed of a conductor film in which a W (tungsten) film is stacked on a TiN (titanium nitride) film. The bit line BL is electrically connected to one of the n-type semiconductor regions (source, drain) 8 of the memory cell selecting MISFET Qt through the through hole 32 formed in the silicon oxide film 31 and the contact hole 12 below the through hole 32. Yes. In the through hole 32, for example, a plug 33 made of a conductor film in which a W film is stacked on a TiN film is embedded.

  A silicon oxide film 34 and a silicon nitride film 35 are formed on the bit line BL, and an information storage capacitor element C is formed on the silicon nitride film 35. The information storage capacitive element C is formed inside a deep groove 40 formed by etching a thick silicon oxide film 39 on the upper part of the silicon nitride film 35, and includes a lower electrode 41, a capacitive insulating film 42, and an upper electrode 43. It is constituted by.

The lower electrode 41 of the information storage capacitor C is made of, for example, a Ru (ruthenium) film, and the n-type semiconductor region (source, drain) 8 of the memory cell selection MISFET Qt through the through hole 36 and the contact hole 13 therebelow. It is electrically connected to the other. Capacitive insulating film 42 is, for example _{BST (BaXSr1-XTiO 3; Barium} Strontium Titanate) is constituted by a membrane, the upper electrode 43 is constituted by, for example, Ru film.

  Next, a method for manufacturing the DRAM of the present embodiment configured as described above will be described in the order of steps with reference to FIGS.

First, in FIG. 3 (plan view showing one end portion of the storage unit), FIG. 4 (cross-sectional view along line AA in FIG. 3) and FIG. 5 (cross-sectional view along line BB in FIG. 3). As shown, an element isolation groove 4 is formed in the element isolation region of the main surface of the substrate 1. The element isolation trench 4 is formed by etching the main surface of the substrate 1 to form a trench having a depth of about 300 to 400 nm. Subsequently, a silicon oxide film 5 having a thickness of about 600 nm is formed by CVD on the substrate 1 including the inside of the trench. Then, the silicon oxide film 5 outside the trench is formed by polishing and removing by a chemical mechanical polishing (CMP) method. As shown in FIG. 3, by forming this element isolation groove 4, a large number of active regions L having a long and narrow island pattern surrounded by the element isolation groove 4 are formed at the same time.

  Next, as shown in FIGS. 6 and 7, P (phosphorus) ions are implanted into the substrate 1, and then the substrate 1 is heat-treated to diffuse this impurity into the substrate 1, thereby forming the p-type well 2. To do.

  Next, as shown in FIG. 8, the substrate 1 is thermally oxidized to form a gate insulating film 6 made of silicon oxide having a film thickness of about 6 nm to 7 nm on the surface of the p-type well 2. After the first conductor film 7A, which is a gate electrode material, is formed on the top, a first insulating film 9A, which is a cap insulating film material, is formed on the conductor film 7A.

  In order to form the conductor film 7A, for example, an n-type polycrystalline silicon film having a thickness of about 70 nm doped with P (phosphorus) is deposited on the gate insulating film 6 by the CVD method, and then the film thickness is formed thereon. A WN (tungsten nitride) film having a thickness of about 5 nm and a W (tungsten) film having a thickness of about 60 nm are deposited by sputtering. In order to form the insulating film 9A, a silicon nitride film may be deposited on the conductor film 9A by a CVD method as in the conventional self-aligned contact (SAC) technique. In the embodiment, for example, a silicon oxide film having a thickness of about 50 nm, a silicon nitride film having a thickness of about 70 nm, and a silicon oxide film having a thickness of about 80 nm are deposited by a CVD method. That is, the insulating film 9A is constituted by a three-layer insulating film in which a silicon nitride film is provided between two layers of silicon oxide films.

  Next, as shown in FIG. 9, the insulating film 9A is dry-etched using the photoresist film 20 as a mask, whereby the above-described three-layer insulating film (insulating film) is formed on the conductor film 7A in the region where the gate electrode is to be formed. A cap insulating film 9 constituted by the film 9A) is formed.

  Typically, silicon oxide has a higher etch selectivity to photoresist (to resist selectivity) than silicon nitride (silicon nitride is about 1.3 versus silicon oxide about 1.6). Therefore, when the cap insulating film material (insulating film 9A) is composed of two layers of silicon oxide film and one layer of silicon nitride film, the cap insulating film material is composed of only one layer of silicon nitride film. As a result, the selectivity ratio with respect to the resist is increased, and the film loss of the photoresist film 20 is reduced accordingly, so that the processing dimensional accuracy of the cap insulating film 9 is improved.

  Next, after removing the photoresist film 20, as shown in FIG. 10, the conductor film 7A is dry-etched using the cap insulating film 9 as a mask, thereby forming a polycrystalline silicon film, a WN film, and a W film. A gate electrode 7 (word line WL) to be formed is formed. A gate electrode 7 (word line WL) having a so-called polymetal structure mainly composed of a W film and a polycrystalline silicon film is formed of a polycrystalline silicon film or a polycide film (a laminate of a refractory metal silicide film and a polycrystalline silicon film). Since the electric resistance is lower than that of a gate electrode formed of a film, the signal delay of the word line can be reduced. Note that the WN film provided between the W film and the polycrystalline silicon film has a structure in which a high resistance silicide layer is formed at the interface between the W film and the polycrystalline silicon film during the high temperature heat treatment. Functions as a barrier layer to prevent. In addition to the WN film, for example, a TiN (titanium nitride) film can be used for the barrier layer.

  As shown in FIG. 11, the gate electrode 7 (word line WL) extends in a direction crossing the long side of the active region L, and the gate length is, for example, about 0.13 μm to 1.4 μm. The space with the electrode 7 (word line WL) is, for example, about 0.12 μm.

  Usually, the W film constituting a part of the gate electrode material (conductor film 7A) has an etching selection ratio with respect to silicon oxide (selection ratio 9 with respect to silicon oxide is higher than a selection ratio with respect to silicon nitride film (selection ratio with respect to silicon nitride) Large (the selectivity to silicon nitride is about 1.0, while the selectivity to silicon oxide is about 1.2) Therefore, when the uppermost portion of the cap insulating film 9 is made of a silicon oxide film, The selection ratio of the W film can be increased as compared with the case where the uppermost portion is formed of the silicon nitride film, whereby the gate electrode 7 can be processed with less film loss of the cap insulating film 9, Accordingly, the processing dimensional accuracy of the cap insulating film 9 and the processing dimensional accuracy of the gate electrode 7 can be improved. Therefore, when the cap insulating film 9 is composed of only one silicon nitride film. Base, it is possible to form the gate electrode 7 having a fine gate length with high dimensional accuracy. It is also possible to omit either one of silicon oxide film of 2 layers sandwiching the silicon nitride film.

  Next, as shown in FIG. 12, As (arsenic) is ion-implanted into the p-type well 2 to form n-type semiconductor regions (source and drain regions) 8 in the p-type well 2 on both sides of the gate electrode 7. Through the steps so far, the memory cell selecting MISFET Qt is substantially completed. Subsequently, a thin silicon nitride film 10A having a thickness of about 10 nm to 15 nm is deposited on the substrate 1 by a CVD method. The silicon nitride film 10A is formed by removing the silicon oxide film 5 inside the element isolation trench 4 when dry etching is performed to form a contact hole (opening portion) in the space of the gate electrode 7 in a later step. Used as an etching stopper to prevent. Therefore, if the amount of shaving of the silicon oxide film 5 does not matter, the silicon nitride film 10A need not be formed.

Next, as shown in FIG. 13, a silicon oxide film 21 having a film thickness of about 70 nm is deposited on the substrate 1 by a CVD method to embed the silicon oxide film 21 in the space of the gate electrode 7 (word line WL). The silicon oxide film 21 is used to make the MISFET (n-channel type MISFET and p-channel type MISFET) in the peripheral circuit portion into an LDD (lightly Doped Drain) structure. That is, although not shown, after the silicon oxide film 21 is deposited, the substrate 1 of the memory portion is covered with a photoresist film, and the silicon oxide film 21 of the peripheral circuit portion is anisotropically etched, so that A sidewall insulating film is formed on the sidewall of the gate electrode of the circuit portion. Thereafter, As or P is ion-implanted into the p-type well of the peripheral circuit portion to form a high impurity concentration n ⁺ -type semiconductor region (source, drain), and B is ion-implanted into the n-type well to increase the impurity concentration. A p ⁺ type semiconductor region (source, drain) is formed. Through the steps so far, the n-channel MISFET and the p-channel MISFET in the peripheral circuit section are substantially completed.

  Next, as shown in FIG. 14, after depositing a thick silicon oxide film 22 having a thickness of about 600 nm on the substrate 1 by the CVD method, the silicon oxide film 22 is polished and planarized by the chemical mechanical polishing method. The height of the surface of the silicon oxide film 22 is made uniform between the storage unit and a peripheral circuit unit (not shown). At this time, a silicon nitride film constituting a part of the cap insulating film 9 may be used as a polishing stopper, and the height of the surface of the silicon oxide film 22 may be set back to the upper surface of the cap insulating film 9.

  Next, as shown in FIGS. 15 and 16, a thin silicon oxide film 23 having a thickness of about 10 nm is deposited on the silicon oxide film 22 by the CVD method, and then a film is formed on the silicon oxide film 23 by the CVD method. After depositing a polycrystalline silicon film 24A having a thickness of about 70 nm, an antireflection film 25 having a thickness of about 60 nm and a photoresist film 26 having a thickness of about 400 nm are spin-coated on the polycrystalline silicon film 24A. The silicon oxide film 23 is deposited in order to repair minute scratches on the surface of the lower silicon oxide film 22 generated when polished by the chemical mechanical polishing method.

  Next, as shown in FIGS. 17 and 18, an etching resistant mask 24 is formed by dry etching a part of each of the antireflection film 25 and the polycrystalline silicon film 24A using the photoresist film 26 as a mask. . FIG. 19 is a plan view showing a pattern (a portion colored in gray) of the etching-resistant mask 24 constituted by the polycrystalline silicon film 24A. As shown in the figure, the etching resistant mask 24 has an elongated slit-like or groove-like opening 27 extending in the long side direction of the active region L across the storage portion. The reason why such a slit-shaped (groove-shaped) aperture 27 is provided in the etching resistant mask 24 for forming the contact holes (open apertures) 12 and 13 in the space of the gate electrode 7 will be described later.

  Next, after removing the photoresist film 26 and the antireflection film 25, as shown in FIGS. 20 and 21, the silicon oxide films 21, 22, and 23 in the opening 27 are formed using the etching resistant mask 24 as a mask. By dry etching, contact holes (openings) 12 and 13 are formed in the upper portion of the n-type semiconductor region (source / drain region) 8, that is, in the space of the gate electrode 7. One of the contact holes 12 and 13 (contact hole 12) is used to connect one of the n-type semiconductor regions (source and drain regions) 8 and the bit line BL, and the other (contact hole 13) is n-type. This is used to connect the other semiconductor region (source / drain region) 8 and the lower electrode 41 of the information storage capacitor C.

  The dry etching of the silicon oxide films 21, 22, and 23 is performed using the silicon nitride film 10A and the silicon nitride film constituting a part of the cap insulating film 9 as an etching stopper. As a result, it is possible to prevent a problem that the silicon oxide film 5 inside the element isolation trench 4 is scraped when the silicon oxide films 21, 22, and 23 are dry-etched, and the cap insulating film 9 is scraped to remove the gate electrode. 7 (word line WL) can be prevented from being exposed. Further, through the steps so far, the sidewall insulating film 10 composed of the silicon nitride film 10A is formed on the sidewall of the gate electrode 7 (word line WL).

  Next, as shown in FIGS. 22 and 23, after depositing a silicon oxide film 11A having a thickness of about 30 nm on the substrate 1 by the CVD method, the silicon oxide film 11A is anisotropically formed as shown in FIG. By etching, a sidewall insulating film 11 composed of a silicon oxide film 11A having a thickness of about 30 nm is formed on the sidewall of the gate electrode 7 (word line WL). At this time, as shown in FIG. 25, the sidewall insulating film formed of the silicon oxide film 11A is also formed on the sidewalls of the silicon oxide films 22 and 21 along the extending direction of the slit-shaped (groove-shaped) opening 27. 11 is formed.

  The anisotropic etching of the silicon oxide film 11A is performed using the silicon nitride film 10A and the silicon nitride film which is a part of the cap insulating film 9 as an etching stopper, as in the dry etching of the silicon oxide films 21, 22, and 23 described above. Do. Thereby, the height of the side wall insulating film 11 formed on the side wall of the gate electrode 7 becomes lower than the upper surface of the cap insulating film 9 (FIG. 24). At this time, the amount of anisotropic etching performed on the sidewall insulating film 11 takes into consideration the reduction of the cap insulating film 9 due to chemical mechanical polishing performed later using the silicon nitride film of the cap insulating film 9 as a stopper. However, the height difference between the upper end of the sidewall insulating film 11 and the upper surface of the cap insulating film 9 should be ensured so that the upper end of the sidewall insulating film 11 is surely lower than the upper surface of the cap insulating film 9. Is desirable. On the other hand, the side wall insulating film 11 formed on the side walls of the silicon oxide films 22 and 21 has a higher upper end position than the side wall insulating film 11 formed on the side wall of the gate electrode 7 (FIG. 25).

  By the steps so far, the two-layer sidewall insulating film 10 constituted by the thin silicon nitride film (10A) and the thicker silicon oxide film (11A) is formed on the sidewall of the gate electrode. 11 are formed. Further, the side wall insulating film 11 composed of the silicon oxide film (11A) has a height on the side wall of the gate electrode 7 lower than the upper surface of the cap insulating film 9, and therefore the contact hole 12 formed in the space of the gate electrode 7. In the cross section along the gate length direction of, 13, the upper diameter (a) is larger than the bottom diameter (b) (a> b) as shown in FIG.

  Next, as shown in FIGS. 26 and 27, the thin silicon nitride film 10A remaining at the bottoms of the contact holes 12 and 13 is removed by dry etching to remove the n-type semiconductor region (source / drain region) 8. After the surface is exposed, the surface of the n-type semiconductor region (source / drain region) 8 damaged by this dry etching is dry etched thinly.

  Next, as shown in FIG. 28 and FIG. 29, for example, an n-type polycrystalline silicon film 14A having a thickness of about 100 nm doped with P is deposited by the CVD method, so that the n-type polycrystalline silicon film 14A is deposited inside the contact holes 12 and 13. A crystalline silicon film 14A is embedded. If there is a contact hole having a diameter larger than that of the contact holes 12 and 13 in the peripheral circuit region (not shown), the thickness of the n-type polycrystalline silicon film 14A inside the contact hole is insufficient, and the n-type polycrystal is formed in the next step. Since the substrate 1 at the bottom of the contact hole in the peripheral circuit region may be scraped when the crystalline silicon film 14A is polished, a silicon oxide film having a thickness of about 200 nm is formed on the n-type polycrystalline silicon film 14A by, eg, CVD. May be further deposited.

  Next, as shown in FIGS. 30 and 31, the n-type polycrystalline silicon film 14A, the etching resistant mask 24 made of polycrystalline silicon, and the underlying silicon oxide films 21, 22, and 23 are polished by a chemical mechanical polishing method. Thus, the n-type polycrystalline silicon film 14A outside the contact holes 12 and 13 is removed, and the plug 14 composed of the n-type polycrystalline silicon film 14A is formed inside the contact holes 12 and 13. This chemical mechanical polishing is performed using a silicon nitride film which is a part of the cap insulating film 9 as a stopper.

  As described above, in this embodiment, first, the silicon oxide films 21, 22, and 23 are formed using the etching resistant mask 24 having the slit-shaped (groove-shaped) opening portion 27 extending in the long side direction of the active region L. Contact holes (openings) 12 and 13 are formed in the space of the gate electrode 7 by dry etching. Next, after the sidewall insulating film 11 composed of the silicon oxide film 11A is formed on the sidewalls of the gate electrode 7 and the silicon oxide films 22 and 21 constituting the wall surfaces of the contact holes 12 and 13, the contact holes 12 and 13 are formed. A plug 14 is formed in the inside of the.

  Further, in this embodiment, a part of the cap insulating film 9 is a laminated structure composed of a silicon nitride film, so that the silicon nitride film is stopped when the n-type polycrystalline silicon film 14A is subjected to chemical mechanical polishing. The film thickness of the cap insulating film 9 can be easily controlled.

  Further, since the cap insulating film 9 of this embodiment has a laminated structure in which a silicon oxide film is provided under the silicon nitride film used as a stopper in the chemical mechanical polishing, the gate electrode 7 is processed. At this time, the film thickness of the cap insulating film 9 at the end of the chemical mechanical polishing can be ensured while suppressing the film thickness of the silicon nitride film which is not preferable from the viewpoint of the resist selectivity ratio and the tungsten selectivity ratio.

  FIG. 32A is a schematic plan view of the contact hole 12 formed using the etching-resistant mask 24 having the slit-shaped (groove-shaped) opening portion 27 described above. Since the side wall insulating film 11 made of a silicon oxide film is formed on the side wall of the contact hole 12, an inner region (region colored in gray) of the side wall insulating film 11 is formed at the bottom of the contact hole 12. The exposed n-type semiconductor region 8 and the plug 14 are in contact with each other.

  On the other hand, FIG. 32B is a schematic plan view of the contact hole 12 formed using an etching resistant mask having a hole-shaped opening 30 in the contact hole opening region. Also in this case, since the side wall insulating film 11 is formed on the side wall of the contact hole 12, the n-type semiconductor in which the inner region (region colored in gray) of the side wall insulating film 11 is exposed at the bottom of the contact hole 12. The region 8 and the plug 14 are in contact with each other. However, the contact hole 12 formed using the etching-resistant mask having such a hole-shaped opening 30 has the position of the opening 30 shifted in the long side direction of the active region L due to misalignment of the photomask. In this case, as shown in FIG. 32C, a region where the n-type semiconductor region 8 and the plug 14 are in contact with each other becomes small. On the other hand, in the case of the contact hole 12 formed using the etching resistant mask having the slit-shaped (groove-shaped) opening 27 extending in the long side direction of the active region L, the contact hole 12 is opened by misalignment of the photomask. Even when the position of the hole 27 is shifted in the long side direction of the active region L, the region where the n-type semiconductor region 8 and the plug 14 are in contact with each other does not become small. That is, according to the present embodiment in which the contact hole 12 is formed using the etching resistant mask having the slit-shaped (groove-shaped) opening portion 27, the plug 14 embedded in the contact hole 12 and the n-type semiconductor region 8 are formed. Since the contact area can be ensured to the maximum, an increase in contact resistance between the plug 14 and the n-type semiconductor region 8 can be suppressed.

  The difference in contact area between the plug 14 and the n-type semiconductor region 8 due to the shape of the opening formed in the etching resistant mask is the same as that of the conventional self-aligned contact (SAC) technique. After forming a sidewall insulating film on the sidewall, a contact hole is formed in the space of the gate electrode, and after forming a contact hole in the space of the gate electrode as in this embodiment, the sidewall insulating film is formed on the sidewall of the gate electrode. It differs depending on the case of forming.

  FIG. 33A shows the width of the slit-like (groove-like) opening 27 and the hole-like shape when a contact hole is formed in the space of the gate electrode after the side wall insulating film is formed on the side wall of the gate electrode. It is a graph which shows the relationship between the diameter of the opening part 30, and the said contact area. As shown in the figure, in this case, the difference in contact area due to the shape of the aperture is small. On the other hand, FIG. 33B shows the width and hole of the slit-shaped (groove-shaped) opening 27 when a contact hole is formed in the space of the gate electrode and then a sidewall insulating film is formed on the side wall of the gate electrode. It is a graph which shows the relationship between the diameter of the shape-shaped opening part 30, and the said contact area. As shown in the figure, in this case, the difference in the contact area due to the shape of the opening portion becomes obvious, and the difference in the contact area becomes larger as the processing dimension becomes finer.

  Next, as shown in FIGS. 34 to 36, a silicon oxide film 31 having a thickness of about 300 nm is deposited on the substrate 1 by the CVD method, and then the contact hole 12 is formed using a photoresist film (not shown) as a mask. By dry-etching the upper silicon oxide film 31, a through hole 32 for connecting the bit line BL and the contact hole 12 to be formed later is formed. At this time, a contact hole for connecting the first layer wiring and the element is also formed in a peripheral circuit region (not shown). As a measure for preventing the plug 14 embedded in the contact hole 12 from being removed when the silicon oxide film 31 above the contact hole 12 is dry-etched, a silicon nitride film having a thickness of about 10 nm is formed under the silicon oxide film 31. The silicon nitride film may be etched after depositing (not shown) and dry etching the silicon oxide film 31 using the silicon nitride film as an etching stopper.

  Next, the plug 33 is formed inside the through hole 32. In order to form the plug 33, for example, a barrier metal film made of TiN or the like is deposited on the silicon oxide film 31 by the CVD method, and then a W film is deposited on the upper portion of the barrier metal film by the CVD method. After these films are buried inside 32, these films outside the through hole 32 are removed by a chemical mechanical polishing method. At this time, the plug 33 is also formed inside the contact hole in the peripheral circuit region (not shown).

  Next, as shown in FIGS. 37 to 39, the bit line BL is formed on the silicon oxide film 31. In order to form the bit line BL, for example, a TiN film (or WN film) having a thickness of about 10 nm and a W film having a thickness of about 50 nm are deposited on the silicon oxide film 31 by sputtering, and then the photoresist film is masked. Then, these films are dry-etched. The bit line BL is connected to one of the n-type semiconductor regions (source and drain regions) 8 of the memory cell selecting MISFET Qt through the plug 33 embedded in the through hole 32 and the plug 14 embedded in the contact hole 12. And electrically connected. The bit line BL can also be formed by a damascene method as described in Japanese Patent Application No. 11-115871, for example.

  As described above, in the DRAM of this embodiment, the sidewall insulating film 10 composed of the silicon nitride film and the sidewall insulating film 11 composed of the silicon oxide film are formed on the sidewall of the gate electrode 7 of the memory cell selecting MISFET Qt. The plug 14 is embedded in the space (contact hole 12, 13) of the gate electrode 7 surrounded by the sidewall insulating films 10, 11. As a result, the effective relative dielectric constant of the side wall insulating film is reduced as compared with the conventional self-aligned contact (SAC) technology in which the side wall insulating film is configured only by a silicon nitride film having a relative dielectric constant larger than that of the silicon oxide film. Therefore, the word line capacitance component, which is the main component of the bit line capacitance, can be reduced.

  In the DRAM of this embodiment, the cap insulating film 9 above the gate electrode 7 is composed of a laminated film of a silicon oxide film and a silicon nitride film. As a result, the effective relative dielectric constant of the cap insulating film is reduced as compared with the conventional self-aligned contact (SAC) technology in which the cap insulating film is configured only by a silicon nitride film having a relative dielectric constant larger than that of the silicon oxide film. Therefore, the capacitance component with respect to the word line can be further reduced.

  Next, as shown in FIG. 40, a silicon oxide film 34 having a thickness of about 300 nm is deposited on the upper portion of the bit line BL by a CVD method, and then the surface thereof is planarized by a chemical mechanical polishing method. Next, after depositing a silicon nitride film 35 having a thickness of about 50 nm on the silicon oxide film 34 by CVD, the silicon nitride film 35 and the silicon oxide films 35 and 31 are dry-etched to embed the plug 14. A through hole 36 is formed above the contact hole 13.

  Next, a plug 37 is formed inside the through hole 36, and a barrier metal film 38 is formed on the surface of the plug 37. In order to form the plug 37 and the barrier metal film 38, for example, an n-type polycrystalline silicon film doped with P is deposited on the silicon nitride film 35 by the CVD method to form an n-type polycrystalline silicon in the through hole 36. After filling the film, the n-type polycrystalline silicon film outside the through hole 36 is removed by dry etching. At this time, the n-type polycrystalline silicon film inside the through hole 36 is over-etched, and the surface of the plug 37 is set back below the surface of the silicon nitride film 35 so that the barrier metal film 38 is formed on the plug 37. Reserve space for embedding. Next, a TiN film is deposited on the silicon nitride film 35 by sputtering to bury a TaN (tantalum nitride) film on the plug 37 in the through hole 36, and then the TaN film outside the through hole 36. Is removed by chemical mechanical polishing.

  The barrier metal film 38 interposed between the lower electrode of the information storage capacitor element C to be formed in the upper part of the through hole 36 in a later process and the plug 37 is formed in the capacitor insulating film formation process of the information storage capacitor element C. In order to prevent an undesired reaction from occurring at the interface between the Ru film constituting the lower electrode and the polycrystalline silicon film constituting the plug 37 during the high temperature heat treatment.

  As described above, of the two side wall insulating films 10 and 11 formed on the side wall of the gate electrode 7, the outer side wall insulating film 11 has a height at the side wall of the gate electrode 7 higher than that of the upper surface of the cap insulating film 9. Therefore, in the cross section of the contact holes 12 and 13 along the gate length direction, the upper diameter is larger than the bottom diameter (see FIG. 24). That is, the diameter of the plug 14 embedded in the contact holes 12 and 13 is larger at the top than at the bottom of the contact holes 12 and 13.

  Thereby, when the through hole 36 is formed above the contact hole 13, even if the center of the through hole 36 is displaced from the center of the contact hole 13 due to misalignment of the photomask, the surface area of the contact hole 13 is large. A sufficient contact area between the two can be ensured.

  Thereafter, an information storage capacitive element C composed of the lower electrode 41, the capacitive insulating film 42 and the upper electrode 43 is formed above the through hole 36, and the plug 37 and the contact hole 13 embedded in the through hole 36 are formed. By electrically connecting the lower electrode 41 of the information storage capacitive element C and the other of the n-type semiconductor regions (source and drain regions) 8 of the memory cell selection MISFET Qt through the plug 14 embedded therein, The DRAM memory cell shown in FIG. 2 is completed.

  In order to form the information storage capacitor element C, for example, as shown in FIG. 41, a thick silicon oxide film 39 having a thickness of about 1 μm is deposited on the silicon nitride film 35 by the CVD method, and then a photoresist film is formed. The silicon oxide film 39 is dry etched using the mask to form a groove 40 above the through hole 36. Etching of the silicon oxide film 39 is performed using the silicon nitride film 35 as an etching stopper so that the underlying silicon oxide film 34 is not etched.

  Next, after removing the photoresist film, a Ru film having a thickness of about 70 nm to 80 nm is deposited on the silicon oxide film 39 including the inside of the trench 40 by a CVD method. Next, in order to prevent the Ru film inside the trench 40 from being removed, a photoresist film is embedded inside the trench 40, and then the Ru film outside the trench 40 not covered with the photoresist film is dry-etched. The photoresist film embedded in the trench 40 is removed by ashing to form the lower electrode 41 composed of a Ru film on the side wall and bottom surface of the trench 40.

Next, a capacitive insulating film 42 is formed on the silicon oxide film 39 including the inside of the trench 40 in which the lower electrode 41 is formed. The capacitor insulating film 42 is formed of a BST film having a thickness of about 20 nm deposited by, for example, a CVD method. The capacitor insulating film 42 is made of a high (strong) dielectric film made of a perovskite metal oxide such as BaTiO ₃ (barium titanate), PbTiO ₃ (lead titanate), PZT, PLT, or PLZT, in addition to the BST film. It can also be configured. Next, the upper electrode 43 is formed on the capacitive insulating film 42. The upper electrode 43 is composed of a Ru film having a thickness of about 200 nm deposited by, for example, a CVD method or a sputtering method. Through the steps so far, the information storage capacitive element C is completed, which includes the lower electrode 41 made of the Ru film, the capacitive insulating film 42 made of the BST film, and the upper electrode 43 made of the Ru film. Thereafter, an Al wiring of about two layers is formed on the upper part of the information storage capacitor C with an interlayer insulating film interposed therebetween, and a passivation film is formed on the uppermost Al wiring, but illustration thereof is omitted.

(Embodiment 2)
A method of manufacturing the DRAM of this embodiment will be described in the order of steps with reference to FIGS. First, as shown in FIG. 42, a memory cell selecting MISFET Qt is formed by the same method as in the first embodiment, and subsequently silicon oxide films 21 to 23 are formed on the memory cell selecting MISFET Qt. Then, an etching resistant mask 24 is formed. The steps so far are the same as the steps shown in FIGS. 3 to 18 of the first embodiment.

  Next, as shown in FIG. 43, contact holes (openings) 12 and 13 are formed in the space of the gate electrode 7 by dry etching the silicon oxide films 21, 22 and 23 using the etching resistant mask 24 as a mask. Form. At this time, in the present embodiment, the silicon nitride film 10A covering the upper part of the n-type semiconductor region (source / drain region) 8 is also etched, and the n-type semiconductor region is formed at the bottom of the contact holes (openings) 12 and 13. The surface of (source / drain region) 8 is exposed. Similar to the first embodiment, the sidewall insulating film 10 composed of the silicon nitride film 10A is formed on the sidewall of the gate electrode 7 (word line WL) by the steps so far.

  Next, after thinly dry-etching the surface of the n-type semiconductor region (source / drain region) 8 damaged by the dry etching, a film thickness of about 30 nm is formed on the substrate 1 by CVD as shown in FIG. A silicon oxide film 11A is deposited, and then, as shown in FIG. 45, the silicon oxide film 11A is anisotropically etched to form a silicon oxide film having a thickness of about 30 nm on the side wall of the gate electrode 7 (word line WL). A sidewall insulating film 11 composed of 11A is formed. The subsequent steps are the same as those in the first embodiment.

  Thus, in the manufacturing method of this embodiment, the sidewall insulating film 11 is formed on the sidewall of the gate electrode 7 (word line WL) after the silicon nitride film 10A at the bottom of the contact holes 12 and 13 is removed. The silicon nitride film 10A does not remain at the bottom of the insulating film 11 (FIG. 45).

  On the other hand, in the manufacturing method of the first embodiment in which the silicon nitride film 10A at the bottom of the contact holes 12 and 13 is removed after the sidewall insulating film 11 is formed on the sidewall of the gate electrode 7 (word line WL), the sidewall insulating film 11 is removed. The silicon nitride film 10A remains at the bottom (FIG. 26). Thus, when the silicon nitride film 10A remains at the side wall end of the gate electrode 7 (word line WL), the interface between the silicon nitride film 10A and the underlying gate insulating film 6 is charged, and the leakage current of the memory cell It becomes a factor to fluctuate.

  Therefore, according to the manufacturing method of this embodiment in which the silicon nitride film 10A is not left at the side wall end portion of the gate electrode 7 (word line WL), the above-described problems can be prevented and the variation in characteristics of the memory cell can be suppressed. .

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used for manufacturing a semiconductor integrated circuit device having a DRAM.

1 is an overall plan view of a semiconductor chip on which a DRAM according to an embodiment of the present invention is formed. It is principal part sectional drawing of the semiconductor substrate which shows the structure of DRAM which is one embodiment of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. (A) is a schematic plan view of a contact hole formed using an anti-etching mask having a slit-shaped (groove-shaped) aperture, and (b) and (c) are anti-resistance having a hole-shaped aperture. It is a schematic plan view of the contact hole formed using the etching mask. (A) shows the width of the slit-shaped (groove-shaped) hole portion and the hole-shaped hole portion in the case where the contact hole is formed in the space of the gate electrode after the side wall insulating film is formed on the side wall of the gate electrode. FIG. 6B is a graph showing the relationship between the diameter of the gate electrode and the contact area, and FIG. 5B shows a slit shape (groove shape) when a contact hole is formed in the space of the gate electrode and a sidewall insulating film is formed on the side wall of the gate electrode. Is a graph showing the relationship between the width of the opening portion and the diameter of the hole-like opening portion and the contact area. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is other embodiment of this invention.

Explanation of symbols

1 semiconductor substrate 1A semiconductor chip 2 p-type well 4 element isolation trench 5 silicon oxide film 6 gate insulating film 7 gate electrode 7A conductor film 8 n-type semiconductor region (source, drain)
9 Cap insulating film 9A Insulating film 10 Side wall insulating film 10A Silicon nitride film 11 Side wall insulating film 11A Silicon nitride films 12, 13 Contact hole (opening portion)
14 Plug 14A n-type polycrystalline silicon film 20 Photoresist films 21, 22, 23 Silicon oxide film 24A Polycrystalline silicon film 24 Anti-etching mask 25 Antireflection film 26 Photoresist film 27 Opening part 30 Opening part 31 Silicon oxide film 32 Through-hole 33 Plug 34 Silicon oxide film 35 Silicon nitride film 36 Through-hole 37 Plug 38 Barrier metal film 39 Silicon oxide film 40 Groove 41 Lower electrode 42 Capacitor insulating film 43 Upper electrode BL Bit line BP Bonding pad C Information storage capacitor L Active area MARY Memory array PC Peripheral circuit part WL Word line

Claims (10)

Formed on a semiconductor board, and the active region of the island-like pattern peripherally-surrounded by the element isolation region, across the active region, a first and a second word line which is a gate of the MISFET,
A cap insulating film formed on each of the first and second word lines;
A contact hole formed between the first and second word lines;
A conductor formed in the contact hole; a first insulating film formed around the conductor; and a first insulating film formed between the conductor and the first and second word lines. Two insulating films ;
A semiconductor integrated circuit device including a third insulating film formed between the first and second word lines on the element isolation region and defining the contact hole on the element isolation region side. There,
The first insulating film is formed at the bottom of the contact hole so as to surround the conductor, and at the top of the contact hole, the first insulating film is formed on the sidewalls of the first and second word lines. Less than the height, formed on the side wall of the third insulating film substantially the same as the height of the conductor ,
The second insulating film is formed between the first insulating film and the first and second word lines at the bottom of the contact hole, and the height thereof is substantially the same as the height of the conductor. Then, the film thickness is formed thinner than the film thickness of the first insulating film,
The semiconductor integrated circuit device according to claim 1, wherein a height of the cap insulating film is substantially the same as a height of the conductor. 2. The semiconductor integrated circuit device according to claim 1, wherein the first and third insulating films are insulating films mainly composed of a silicon oxide film, and the second insulating film is mainly composed of a silicon nitride film. A semiconductor integrated circuit device which is an insulating film . 3. The semiconductor integrated circuit device according to claim 1, wherein a first MISFET having a part of the first word line as a gate electrode and a part of the second word line are gated on the semiconductor substrate. and a second MISFET is formed to the electrode, the conductor formed inside the contact hole, the first and second MISFET source, the Ru is electrically connected to one of the drain region A semiconductor integrated circuit device, wherein the first plug is a second plug electrically connected to the other plug .   4. The semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device has a bit line electrically connected to one of the first and second plugs and a capacitor electrically connected to the other. A semiconductor integrated circuit device comprising a DRAM memory cell. A method of manufacturing a semiconductor integrated circuit device having the following steps;
(A) a step of selectively forming an element isolation region on a semiconductor substrate to partition an active region of an island pattern;
( B ) forming a cap insulating film including a first silicon nitride film on the first conductor film after forming the first conductor film on the semiconductor substrate;
(C) by etching the first conductive film and the cap insulating film, the first covering the upper portion of the first and second word line and the previous SL first and second word lines crossing the active region Forming the first and second cap insulating films;
( D ) By performing impurity implantation on the semiconductor substrate, a first MISFET having a part of the first word line as a gate electrode and a second part having a part of the second word line as a gate electrode. Forming a MISFET of
( E ) A second silicon nitride film is formed to cover the first and second word lines and the first and second cap insulating films, and then between the first and second word lines. Forming a first silicon oxide film on the semiconductor substrate, and forming a mask pattern having a slit-like opening extending in a long side direction of the active region on the first silicon oxide film; ,
A mask pattern having an (f) said slit-shaped opening by etching the first silicon oxide film as a mask, the first and second MISFET source, one of the upper portion of the drain region first An opening is formed, and a second opening is formed on the other upper portion of the source and drain regions, and at the same time, the first and second cap insulating films are exposed, and the second silicon nitride film is exposed. Forming a first sidewall insulating film ,
( G ) After forming the second silicon oxide film so as to cover the first and second opening portions, the first and second silicon oxide films are anisotropically etched . A second side wall insulating film made of a second silicon oxide film having a lower height than the first side wall insulating film on the side wall of the word line and thicker at the bottom than the first side wall insulating film is formed. The process of
( H ) forming a second conductor film on the entire surface ;
( I ) A step of planarizing with the first silicon nitride film constituting part of the first and second cap insulating films as a stopper . 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5 , wherein the step (i) is performed by a CMP method or an etch back method. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein in the step (f), the etching of the first silicon oxide film is performed by using the second silicon nitride film and the first and second cap insulating films. A method for manufacturing a semiconductor integrated circuit device, comprising: using a first silicon nitride film constituting a part of the etching stopper as an etching stopper. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein in the step (g), anisotropic etching of the second silicon oxide film is performed and parts of the first and second cap insulating films are formed. A method of manufacturing a semiconductor integrated circuit device, comprising: using the first silicon nitride film as an etching stopper. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the cap insulating film is a laminated film of a silicon oxide film and a silicon nitride film .   Further, a bit line electrically connected to one of the source and drain regions through the second conductor film in the first opening is formed, and the second conductor in the second opening is formed. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 5, further comprising a step of forming a capacitive element electrically connected to the other of the source and drain regions through a film.

Images