JP4211677B2 - Multiplexing switching circuit - Google Patents

Description

  The present invention relates to a multiplex switching circuit, and more particularly to a multiplex switching circuit capable of detecting both an on failure and an off failure of the switching circuit.

  In the conventional multiplexed switching circuit, both of the multiplexed final stage switching elements are simultaneously turned on and off by one control signal for the multiplexed switching circuit. Further, as described in [Patent Document 1], when the upper and lower arms of the power conversion device are composed of two IGBTs Q1 and Q2, Q3 and Q4 connected in series, for example, the timing of the turn-on operation of Q2 is earlier than Q1. As a result, when it is detected that Q1 is overvoltage, there is a gate driving device for a voltage driven semiconductor element in which Q1 is turned on by a gate driving device GDU1 at a voltage higher than a normal forward bias voltage.

JP 2001-119926 A

  For example, as described in [Patent Document 1], the conventional multiplexed switching circuit has only one on / off control command to the multiplexed switching circuit, and can perform only on / off control simultaneously in both systems in failure diagnosis. An off-fault and an on-fault in both systems can be detected, but a single on-fault cannot be detected when either one of them is on alone. This single on-failure detection is a particularly important problem in systems that absolutely want to avoid turning on accidentally.

  An object of the present invention is to provide a multiplexed switching circuit that can detect an on-failure independently.

  To achieve the above object, the present invention provides a communication control circuit that transmits and receives control data to and from a host control device, and an on command signal from a control command decoder that decodes a control command received from the host control device by the communication control circuit. The first and second base drive circuits for outputting a high level pulse having a preset time width, the emitter of the NPN transistor connected to the first base drive circuit, and the second base drive circuit The collector of the NPN transistor is connected, and the output side is connected to the communication control circuit via a control target load and an output detection circuit.

  In addition, a multiplexed switching circuit or multiplexed switching element can be controlled on and off independently, and a single switching circuit or switching element path is turned on and a switching circuit output voltage is detected to detect switching. When an on-state of both systems is detected from the output of the circuit, an on-failure of a single system can be detected by diagnosing an on-failure of a switching circuit that has not given an on command.

  According to the present invention, the one-system on failure of the multiplexed switching circuit can be detected, so that the abnormal circuit can be removed before malfunctioning, and the reliability of the system is improved.

  An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of a multiplexing switching circuit of the present embodiment.

As shown in FIG. 1, the multiplexing switching circuit of this embodiment is connected to a serial data transmission line 5 via a serial data transmission buffer amplifier 2 and a serial data reception buffer amplifier 4 in a host controller 1. A buffer amplifier control signal line 3 is connected to the serial data transmission buffer amplifier 2. The host controller 1 receives a load drive command 85 from another computer. Further, an ON failure signal and an OFF failure signal are transmitted to the failure indicator 6.

  A plurality of multiplexed switching circuits are connected to the serial data transmission line 5. In FIG. 1, two multiplexed switching circuits are shown as representatives.

  Since the first multiplexed switching circuit 100 and the second multiplexed switching circuit 110 have the same configuration, the configuration of the first multiplexed switching circuit 100 will be described.

The serial data transmission line 5 and the serial communication control circuit 7 of the first multiplexing switching circuit 100 are connected via a serial data reception buffer amplifier 17 and a serial data transmission buffer amplifier 18. A buffer amplifier control signal line 19 is connected to the serial data transmission buffer amplifier 18. The serial communication control circuit 7 is connected to the control command decoder 9 so as to transmit an on / off control command signal, and is also connected by an output timing signal line 15.

  The control command decoder 9 and the OR circuit 86a are connected by the A system circuit on command signal line 10 and the both systems circuit on command signal line 11, and the control command decoder 9 and the OR circuit 86b are connected by the B system circuit on command signal line 12. , Both system circuit on command signal line 11 is connected. The OR circuit 86a is connected to the A system switching circuit 21 by the A system circuit on command signal line 13, and the OR circuit 86b is connected to the B system switching circuit 91 by the B system circuit on command signal line 14.

The A system switching circuit 21 and the B system switching circuit 91 have the same configuration, and the A system switching circuit 21 includes a one-shot timer 23, a buffer amplifier 24, a resistor 25,
A PNP transistor 26 and a resistor 27 are connected in series to an A-system base drive circuit 20, and an A-system NPN transistor 22 is connected in series to the A-system base drive circuit 20. Timer 41, buffer amplifier 42, resistor 43,
The PNP transistor 44 and the resistor 45 are connected in series to a B system base driving circuit 90, and the B system NPN transistor 46 is connected in series to the B system base driving circuit 90. Here, bipolar transistors are used for the PNP transistors 26 and 44, the A system NPN transistor, and the B system NPN transistor. Further, the A-system NPN transistor and the B-system NPN transistor may be configured such that two MOS transistors are connected in series and two gate drive circuits are independently controlled to be turned on / off.

  The emitter of the A system NPN transistor 22 and the collector of the B system NPN transistor 46 are connected, and a surge absorber 28 is connected between the output side of the A system switching circuit 21 and the output side of the B system switching circuit 91. The output side of the A-system switching circuit 21 is connected to the control target load 30 and to the output detection circuit 38. The control target load 30 is connected to the high voltage side of the load power supply 31. The output side of the B system switching circuit 91 is grounded and connected to the low voltage side of the load power supply 31.

  The output detection circuit 38 is connected to a resistor 33 connected to the output side of the A-system switching circuit 21 and a comparator 39 connected to the resistor 33 and grounded via the resistor 34. A reference voltage is input to one side of the comparator 39. The output detection circuit 38 is connected to the serial communication control circuit 7 by a switching circuit on / off data line 88. A signal from the address setting unit 16 is input to the serial communication control circuit 7.

The host control device 1 periodically executes a fault diagnosis of the switching circuit during standby when the control target load 30 is not driven on and off. When there is a load drive command 85, control for driving the control target load 30 is executed in accordance with the load drive command 85. The failure indicator 6 displays the address of the multiplexed switching circuit having an abnormality, the on-failure occurrence location, and the presence / absence of an off-failure according to a command from the host controller 1.

  The multiplexed switching circuit configured as described above operates as follows.

  The host controller 1 sends control data for fault diagnosis or control data for load driving to the multiplex switching circuit 100 via the serial data transmission buffer amplifier 2, the serial data reception buffer amplifier 4, and the serial data transmission line 5. Send and receive. FIG. 3 is a diagram illustrating an example of a data format for one frame of serial data transmitted by the host controller 1. One frame is composed of a head bit, a multiplexed switching circuit address, and a control command. FIG. 5 is a diagram showing an example of a data format transmitted by the multiplexing switching circuit. One frame is composed of a head bit, a multiplexed switching circuit address, and switching circuit on / off data. The correspondence between the control command bit pattern and the control command is predetermined as shown in FIG.

  Except that the host controller 1 outputs serial data to the serial data transmission line 5, the output of the serial data transmission buffer amplifier 2 is set to high impedance by the buffer amplifier control signal line 3, and the transmission data from the multiplexing switching circuit 100 is transmitted. Can be received normally.

  On the other hand, the first multiplexing switching circuit 100 receives failure diagnosis control data or load drive control data from the host controller 1 via the serial data reception buffer amplifier 17, the serial data transmission buffer amplifier 18, and the serial data transmission line 5. The switching circuit ON / OFF data from the switching circuit ON / OFF data line 88 is transmitted to the host controller 1 at the time of failure diagnosis.

  The serial communication control circuit 7 outputs an on / off control command 8 to the control command decoder 9 via the parallel bus. However, the serial communication control circuit 7 is configured not to receive address designation data other than the address set by the address setter 16.

The serial data transmitted by the host controller 1 incorporates the address of the multiplexing switching circuit. The control command decoder 9 decodes the content of the on / off control command signal 8 and selects any one of the A system circuit on command signal line 10, the both systems circuit on command signal line 11, and the B system circuit on command signal line 12. Output to one. The output from the control command decoder 9 is controlled by the output timing signal, and is reset after being output for a set time.

The output from the control command decoder 9 is logically operated by the OR circuits 86 a and 86 b and is output to the A system circuit on command signal line 13 and the B system circuit on command signal line 14. That is, when an A system circuit ON command signal is output from the A system circuit ON command signal line 10, the signal is output to the A system circuit ON command signal line 13, and the B system circuit ON command signal line 12 is used. When the command is output, the signal is output to the B system circuit on command signal line 14, and when the both system circuit on command signal line 11 is output, the A system circuit on command signal line 13 and the B system circuit on. It is output to the command signal line 14.

  The output of the A system circuit on command signal line 13 is input to the one-shot timer 23 of the A system base drive circuit 20. The one-shot timer 23 is triggered at the rising edge of the A-system on command and outputs a high level pulse having a preset time width. The pulse width is a short pulse width that does not cause the control target load 30 to respond, and is set so that only failure diagnosis is performed. The output of the one-shot timer 23 is amplified by the buffer amplifier 24 and is output to the base side of the PNP transistor 26 via the resistor 25 as a signal whose polarity is inverted with respect to the input signal.

  Since the collector of the PNP transistor 26 is connected to the base of the A system NPN transistor 22 via the resistor 27, the A system NPN transistor 22 is turned on while the output of the one-shot timer 23 is high.

  The B-system switching circuit 91 has the same configuration as that of the A-system switching circuit 21, and the one-shot timer 41 is triggered at the rising edge of the B-system ON command and operates in the same manner as the A-system switching circuit 21. The system NPN transistor 46 is turned on.

As described above, the A system NPN transistor 22 is turned on for the set time width of the one-shot timer 23 by one pulse output of the A system circuit on command, and the B system NPN transistor is turned on by one pulse output of the B system on command. 46 turns on the set time width of the one-shot timer 41. Further, the A system NPN transistor 22 is turned on for the set time width of the one-shot timer 23 and the B system NPN transistor 46 is turned on for the set time width of the one-shot timer 41 by one pulse output of the both-system circuit on command. At this time, since the set time of the one-shot timers 23 and 41 is shorter than the time width in which the control target load 30 can be driven, the control target load 30 is not driven even if both transistors are turned on during failure diagnosis.

  The output detection circuit 38 receives an ON signal when both the outputs of the A-system switching circuit 21 and the B-system switching circuit 91 are ON, and receives an OFF signal when either one is OFF. The output detection circuit 38 monitors the output voltage of the multiplexing switching circuit, and outputs a low level switching circuit on / off data line 88 when the multiplexing switching circuit is turned on and when it is off. The output detection circuit 38 includes resistors 33 and 34 for dividing the input voltage and a comparator 39. The switching circuit on / off data line 88 is connected to the serial communication control circuit 7 at the timing of the falling edge of the output timing signal line 15. The output state when the ON command signal is given to one or both systems of the multiplexed switching circuit can be captured in the serial communication control circuit 7.

  The serial communication control circuit 7 adds the address of its own circuit to the captured switching circuit on / off data line 88 and transmits it to the serial data transmission line 5. When data is transmitted, the output of the serial data transmission buffer amplifier 18 is enabled by the buffer amplifier control signal, and when data is not transmitted, the output of the serial data transmission buffer amplifier 18 is set to high impedance through the serial data transmission line 5. Avoid data collisions. The surge absorber 28 suppresses a surge voltage generated when both system transistors are turned on and off.

  Next, a failure diagnosis operation for detecting an ON failure of the A system switching circuit 21 will be described. FIG. 2 is a diagram illustrating an output command pattern and a determination result for failure diagnosis.

  The host controller 1 transmits a B system circuit ON command to which the address of the first multiplexing switching circuit 100 is added to the serial data transmission line 5. The serial communication control circuit 7 of the first multiplexing switching circuit 100 recognizes the address of its own circuit and receives control command data. The received control command data is converted into parallel data on / off control command signal 8 and output to control command decoder 9.

  As shown in FIG. 4, the control command decoder 9 decodes the on / off control command signal 8 and outputs a B system circuit on command to the B system circuit on command signal line 12. The B system circuit on command signal line 14 becomes high level, the one shot timer 41 is triggered, and the B system NPN transistor 46 is turned on for a set time of the one shot timer 41.

  At this time, any one of the one-shot timer 23, the buffer amplifier 24, the resistor 25, the PNP transistor 26, and the resistor 27 of the A system switching circuit 21 is turned on, and the A system switching circuit 21 is an off command. Nevertheless, when the switching circuit output voltage 32 is at a high level, the switching circuit on / off data line 88 is turned on, and the on signal is taken into the serial communication control circuit 7 and transmitted to the serial data transmission line 5 together with the address of its own circuit. Is done.

  The host controller 1 compares the B-system circuit on command of the first multiplex switching circuit 100, which is the transmitted data, with the received switching circuit on / off data from the first multiplex switching circuit 100, as shown in FIG. Then, it is determined that the A-system NPN transistor 22 has an on-failure, and the address of the multiplexed switching circuit corresponding to the failure indicator 6 and the lamp indicating the on-failure are turned on. When the switching circuit ON / OFF data line 88 indicates OFF, it is normal and no failure display is performed.

  The failure diagnosis operation for detecting the on-failure of the B system switching circuit 91 performs the same failure diagnosis operation by reversing the A system and the B system. As described above, since the ON command is given separately for the A system and the B system, it is possible to detect the ON failure of the A system and the B system alone.

  Next, a failure diagnosis operation for detecting an OFF failure of the A system switching circuit 21 or the B system switching circuit 91 will be described.

  The host controller 1 transmits a dual-system circuit ON command to which the address of the first multiplexing switching circuit 100 is added on the serial data transmission line 5. The serial communication control circuit 7 of the first multiplexing switching circuit 100 recognizes the address of its own circuit and receives control command data. The received control command data is converted into parallel data on / off control command signal 8 and output to control command decoder 9.

The control command decoder 9 decodes the on / off control command signal 8 and outputs a both-system circuit on command to the both-system circuit on command signal line 11. Both the A-system circuit on command signal line 13 and the B-system circuit on command signal line 14 become high level, and the one-shot timer 23 and the one-shot timer 41 are triggered, and the A-system NPN transistor 22 and the B-system NPN transistor 46 Both are turned on for the set time of the one-shot timer.

  At this time, if the A system or the B system has an off-fault, the output of the off-fault switching circuit is turned off, and the switching circuit output voltage 32 is at a low level. The signal is taken into the serial communication control circuit 7 and transmitted to the serial data transmission line 5 together with the address of its own circuit.

  The host controller 1 compares the both-system circuit ON command of the first multiplex switching circuit, which is the transmitted data, with the received switching circuit ON / OFF data from the first multiplex switching circuit, and compares the A-system NPN transistor 22 or B The system NPN transistor 46 is determined to be off-fault, and the address display of the multiplexed switching circuit corresponding to the fault indicator and the off-fault lamp are turned on. When the switching circuit ON / OFF data line 88 indicates ON, there is no OFF failure in both the A system and the B system, and the fault display is not performed.

  Next, the operation for driving the control target load will be described. The host controller 1 transmits a dual-system circuit ON command to which the address of the first multiplexing switching circuit 100 is added on the serial data transmission line 5. The serial communication control circuit 7 of the first multiplexing switching circuit 100 recognizes the address of its own circuit and receives control command data. The received control command data is converted into parallel data on / off control command signal 8 and output to control command decoder 9.

The control command decoder 9 decodes the on / off control command signal 8 and outputs a both-system circuit on command signal line 11. Due to the both-system circuit on command, both the A-system circuit on command signal line 13 and the B-system circuit on command signal line 14 become high level, and the one-shot timer 23 and the one-shot timer 41 are triggered, and the A-system NPN transistor 22 And the B system NPN transistor 46 are turned on. Within the set time of the one-shot timers 23 and 41, the host control device 1 transmits the both-system circuit on command signal of the first multiplexing switching circuit 100 again. As a result, the one-shot timers 23 and 41 are triggered again, and the A-system NPN transistor 22 and the B-system NPN transistor 46 are kept on.

  As described above, the host controller 1 transmits the both-system circuit ON command of the first multiplexing switching circuit 100 within the set time of the one-shot timers 23 and 41, so that the A-system NPN transistor 22 and the B-system NPN transistor are transmitted. 46 is further turned on, and the control target load 30 is driven when the response possible time width of the control target load 30 is reached. Since the response time of the control target load 30 has been investigated in advance, and the number of retriggers of the one-shot timers 23 and 41 is set in advance, by sending a both-system circuit on command of the determined number of retriggers The control target load 30 can be driven.

  Here, even when the control target load 30 is driven, an off-fault diagnosis can be performed, so that an off-fault diagnosis can be performed every time the multiplexed switching circuit is accessed.

  The operation of the circuit of the second multiplexed switching circuit 110 is performed in the same manner as the first multiplexed switching circuit 100 described above.

FIG. 6 is a diagram showing the relationship between the data transmission procedure at the time of failure diagnosis and the operation of the switching transistor, and shows the transmission procedure at the time of failure diagnosis of two multiplexed switching circuits. Reference numerals 1X to 6X represent control command data frames from the host controller 1 to the multiplexing switching circuit shown in FIG. 3, respectively. Reference numerals 1Y to 6Y represent the multiplexing switching circuit to the host controller shown in FIG. A transmission data frame is shown.

  When the multiplexed switching circuit receives the data with the matching address, it transmits the failure data to the host controller 1 as a response. The multiplexing switching circuit does not receive the data transmitted by itself. Thus, the multiplexing switching circuit performs data transmission in response to the host controller 1, and the host controller 1 controls the transmission line.

The host controller 1 receives data from all multiplexed switching circuits whose addresses are input to the serial communication control circuit. 6 indicates an ON command for the A-system switching circuit 21 of the first multiplexing switching circuit 100, 2X indicates an ON command for the A-system switching circuit 61 of the second multiplexing switching circuit 110, and 3X indicates the first command. On-command for the B-system switching circuit 91 of the multiplex switching circuit 100, 4X is an on-command for the B-system switching circuit 99 of the second multiplex switching circuit 110, and 5X is a both-system switching circuit of the first multiplex switching circuit 100. The ON command, 6X, is an ON command for both switching circuits of the second multiplexed switching circuit 110.

  When diagnosing an ON failure, control is performed so that ON commands of both transistors in the same circuit do not overlap. Reference numerals 1Y and 3Y indicate on-fault diagnostic data for the first multiplexed switching circuit 100, reference numerals 2Y and 4Y indicate on-fault diagnostic data for the second multiplexed switching circuit 110, and reference numeral 5Y indicates an off-fault diagnostic data for the first multiplexed switching circuit 100. The data 6Y is off-failure diagnosis data of the second multiplexing switching circuit 110. A symbol Tw indicates a set time of a time width in which the load to be controlled by the one-shot timer of each circuit cannot respond.

  FIG. 7 shows the transmission procedure and the operation of the switching transistor when driving a load. FIG. 7 shows the operation of the first multiplexing switching circuit 100. Reference numeral 5X is an ON command for both switching circuits of the first multiplexing switching circuit, reference numeral 5Y is OFF failure diagnosis data for the first multiplexing switching circuit, and reference numeral Tw is a set time of a one-shot timer of each circuit. In order to drive the load, as shown in FIG. 7, both system switching circuit ON commands are continuously transmitted within the time width Tw.

  According to this embodiment, bipolar transistors can be duplexed in series, and an ON failure can be detected and the reliability is improved. In addition, since the multiplexed switching circuits can be switched independently for each system, the failure diagnosis can detect not only the off-failure but also the on-failure, so that a highly reliable switching circuit can be configured. .

It is a block diagram of the multiplexing circuit which is one Example of this invention. It is a figure which shows the output command pattern and determination result of failure diagnosis. It is a figure which shows the data format which a high-order control apparatus transmits. It is a figure which shows the correspondence of a control command bit pattern and a control command. It is a figure which shows the data format which a multiplexing switch circuit transmits. It is a figure which shows the transmission procedure at the time of a failure diagnosis. It is a figure which shows the transmission procedure at the time of load drive.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... High-order controller, 2, 18, 58 ... Serial data transmission buffer amplifier, 3, 19, 59 ... Buffer amplifier control signal line, 4, 17, 57 ... Serial data reception buffer amplifier, 5 ... Serial data transmission line, 6 ... failure indicator, 7, 47 ... serial communication control circuit, 8, 48 ... on / off control command signal, 9, 49 ... control command decoder, 10, 13, 50, 53 ... A system circuit on command signal line, 11, 51 ... Both system circuit on command signal line, 12, 14, 52, 54 ... B system circuit on command signal line, 15,55 ... Output timing signal line, 16,56 ... Address setter, 20, 60 ... A system base drive Circuit, 21, 61 ... A system switching circuit,
22, 62... A system NPN transistor, 23, 41, 63, 80... One shot timer, 24, 42, 64, 81... Buffer amplifier, 25, 27, 33, 34, 43, 45, 65, 67, 72, 73, 82, 84 ... resistors, 26, 44, 66, 83 ... PNP transistors, 28, 68 ... surge absorber, 30, 70 ... load to be controlled, 31 ... power supply for load,
32, 71 ... switching circuit output voltage, 38, 77 ... output detection circuit, 39, 78 ... comparator, 46 ... B system NPN transistor, 85 ... load drive command, 86, 87 ... OR circuit, 88 ... switching circuit on / off data line 91, 99... B system switching circuit.

Claims (6)

  A communication control circuit that transmits and receives control data to and from the host control device, a control command decoder that decodes a control command from the host control device received by the communication control circuit, and an ON command signal from the control command decoder First and second base driving circuits for outputting a high level pulse having a predetermined time width, an emitter of an NPN transistor connected to the first base driving circuit, and an NPN connected to the second base driving circuit A multiplexing switching circuit in which a collector of a transistor is connected and an output side is connected to the communication control circuit via a load to be controlled and an output detection circuit. A communication control circuit for transmitting / receiving control data to / from a host controller, the emitter of the first NPN transistor and the collector of the second NPN transistor being connected, and the collector of the first NPN transistor and the second A load and a power supply for the load are connected in series between the emitters of the two NPN transistors, and the control command from the host controller received via the communication control circuit is decoded before the first and second NPN transistors. The first and second base drive circuits that output high-level pulses with a preset time width in response to an ON command signal from the control command decoder are provided individually, and further have an output detection circuit to control the output side A multiplexed switching circuit connected to the communication control circuit via a target load and the output detection circuit.   2. The multiplexed switching circuit according to claim 1, wherein the first and second base drive circuits are connected to a one-shot timer, a buffer amplifier, and an NPN transistor.   When the negative terminal of the power source of the base drive circuit is connected to the emitter of the second NPN transistor or the common terminal of the power source for load, and the control command is a command to drive the load, the first and second 3. The multiplexed switching circuit according to claim 2, wherein an ON command is given so that both NPN transistors have a response time width of a load to be controlled.   Provided between the control command decoder and the first base drive circuit are a first circuit on command signal line, a two-system circuit on command signal line, and a first OR circuit, and the control command decoder and the second base drive circuit The multiplexed switching circuit according to claim 1, wherein a second circuit-on command signal line, a both-system circuit-on command signal line, and a second OR circuit are provided between the two.   When the control command is a failure diagnosis, the first base drive circuit is configured to give an ON command having a time width shorter than a response possible time width of the load to be controlled to the first and second base drive circuits. The control data of any one of an on command, an on command of the second base drive circuit, and a both-systems circuit on command for commanding on the first and second base drive circuits is received from the host controller. Or the multiplexing switching circuit according to 2;

Images