JP4199746B2 - Computer system, exclusive control method, and program - Google Patents

Description

  The present invention relates to a computer system having an exclusive control function, an exclusive control method, and a program.

  Conventionally, in a computer system, exclusive control is used as a method for avoiding data inconsistency caused by a plurality of processors (calculation means) accessing the same data.

FIG. 8 shows a lock acquisition image in such conventional exclusive control.
As shown in FIG. 8, in general exclusive control, a plurality of locks such as lock address 1 and lock address 2 access the same cache block.

Also, as conventional exclusive control, lock instruction information is registered in association with a cache block by a processing unit, and when other processors access the same data, access permission is determined and controlled based on the registered lock instruction information. There are some (see, for example, Patent Document 1).
JP-A-6-175981

  However, in the conventional exclusive control described above with reference to FIG. 8, when access to the same cache block competes, the memory read in the exclusive control structure differs depending on the memory stores of the exclusive control structure 1 and the exclusive control structure 2. There was a risk of becoming a cash miss factor at the time. This cache miss increases in proportion to the memory read amount.

  In addition, when waiting due to contention for access to the same cache block occurs in this way, there is a problem that the processing efficiency as a multiprocessor is lowered.

  In addition, the above-mentioned Patent Document 1 does not take into account the prevention of cache miss due to access competition to the same cache block.

  The present invention has been made in view of such a situation, and a computer system capable of preventing a cache miss due to access conflict to the same cache block and minimizing waiting time due to access conflict, An object is to provide an exclusive control method and a program.

To achieve this object, the computer system according to the first aspect of the present invention is a computer system having a plurality of calculation means and a function of performing exclusive control, and there is no cache entry address. Cache entry address calculating means (for example, step S2 in FIG. 2) for calculating the entry address of the cache, and if there is no cache entry address, the cache entry address is calculated using the entry address calculated by the cache entry address calculating means. Lock content setting means for setting a lock address in block units, and access conflict in which a lock acquisition request is issued from another calculation means to the lock address after the lock address is acquired by one calculation means and the lock acquisition state is obtained If this occurs, the other Priority processing execution means for executing a higher processing priority to calculating means earlier (e.g., step S14 in FIG. 6) and a, the cache entry address calculation means, the number of said plurality of calculation means and the cache structure The cache entry address is calculated according to the cache block capacity measured by the measurement program for investigating

When the occurrence of a failure is notified, it is preferable to provide a diagnostic device that releases the lock at the lock address set by the lock address setting unit for the calculation unit in which the failure has occurred.

  An exclusive control area used for exclusive control in the storage means is provided, and the exclusive control area described above preferably uses the number of the plurality of calculating means as the maximum number of entries.

The exclusive control method according to the second aspect of the present invention is an exclusive control method in a system having a plurality of calculation means and a function of performing exclusive control, and when the cache entry address does not exist A cache entry address calculation step (for example, step S2 in FIG. 2) for calculating the cache entry address and one calculation using the entry address calculated in the cache entry address calculation step when there is no cache entry address An exclusive control process that obtains a lock address in cache block units by the means and enters the lock acquisition state, and an access conflict occurs after the exclusive control process that causes a lock acquisition request from another calculation means to the lock address , The other calculation means perform the higher priority processing Cache priority processing execution step of executing (e.g., step S14 in FIG. 6) and provided with, in the cache entry address calculating step, the number of said plurality of calculation means and, measured by the measurement program to investigate the cache structure The cache entry address is calculated according to the block capacity .

It is preferable to provide a diagnosis step of releasing the lock at the lock address acquired in the exclusive control step for the calculation means in which the failure has been notified when the occurrence of the failure is notified.

  In the above priority processing execution step, it is preferable that the number of the plurality of calculation means described above is set to the maximum number of entries for the exclusive control area used for exclusive control.

The exclusive control program according to the third aspect of the present invention is an exclusive control program in a system having a plurality of calculation means and a function of performing exclusive control, and there is no cache entry address in the computer. In this case, the cache entry address calculation process (for example, step S2 in FIG. 2) for calculating the entry address of the cache and the entry address calculated by the cache entry address calculation process when the cache entry address does not exist are used. An exclusive control process in which a lock address for each cache block is acquired by one calculation means and the lock acquisition state is entered, and an access conflict occurs after the exclusive control process in which a lock acquisition request is issued from another calculation means to the lock address The other calculator There priority processing execution process for executing a higher processing priority to previously (e.g., step S14 in FIG. 6) and allowed to run, with the cache entry address calculation process, the number of said plurality of calculation means and the cache structure The cache entry address is calculated according to the cache block capacity measured by the measurement program for investigating .

When the occurrence of a failure is notified, it is preferable to cause the computer to execute a diagnostic process for releasing the lock at the lock address acquired by the exclusive control process for the calculation means in which the failure has occurred.

  In the above priority processing execution processing, it is preferable that the number of the plurality of calculation means described above is set to the maximum number of entries for the exclusive control region used for exclusive control.

  As described above, according to the present invention, it is possible to prevent a cache miss due to access contention to the same cache block and to minimize waiting time due to access contention.

Next, an embodiment to which a computer system, an exclusive control method, and a program according to the present invention are applied will be described in detail with reference to the drawings.
The computer system of the present embodiment exemplifies a suitable system that improves the processing efficiency of the multiprocessor by reducing the access competition to the same cache block in the exclusive control operation and increasing the cache residence rate.

First, an overview of an exclusive control method using a cache entry address in the present embodiment will be described with reference to FIG.
The cache entry address generation unit 11 checks whether the configuration information of the cache 10 of the processor 1 exists, and stores the information in the cache information storage unit 21 when the cache entry address of the cache 10 exists. If the configuration information of the cache 10 does not exist, a measurement program for investigating the cache structure is activated to calculate the cache entry address of the cache 10 and store it in the cache information storage unit 21.

  In the present embodiment, the cache entry address calculated by the cache entry address generation unit 11 is used even when the configuration information of the cache 10 does not exist at the time of exclusive control of a data area accessed by a plurality of processors. The exclusive control is performed in units of cache blocks by using the address bits of the corresponding exclusive control area, and the access conflict to the same cache block is completely eliminated to improve the multiprocessor performance. Further, when there is an access conflict in the exclusive control area, the processing efficiency of the multiprocessor is improved by giving priority to other high priority interrupt processing.

Next, the configuration of the present embodiment will be described in detail with reference to the drawings.
Referring to FIG. 1, a computer system according to this embodiment includes a processor 1 that executes a program, a storage device 2 that stores programs and data, a diagnostic device 3, a cache entry address generation unit 11, and exclusive control. The execution means 12 is comprised.

The processor 1 includes a cache entry address generation unit 11 and an exclusive control execution unit 12.
The storage device 2 includes a program storage unit 20, a cache information storage unit 21 that stores the cache entry address generated by the cache entry address generation unit 11, an exclusive control area 22, and a data access area 23 that requires exclusive control. including. The program storage unit 20 stores programs of the cache entry address generation unit 11 and the exclusive control execution unit 12.
The diagnostic device 3 performs failure processing when a processor failure occurs.

Each of the above-described parts generally operates as follows.
As shown in FIG. 2, the cache entry address generation means 11 checks whether the configuration information of the cache 10 of the processor 1 exists (step S1). If the cache entry address of the cache 10 exists (step S1; Yes) The information is stored in the cache information storage unit 21 (step S3).

  When the configuration information of the cache 10 does not exist (step S1; No), a measurement program for investigating the cache structure is started, the cache entry address of the cache 10 is calculated (step S2), and the cache information storage unit 21 is entered. Store (step S3).

The cache entry address generation means 11 operates only once when the system is started up, and stores the cache entry address of the cache 10 and the lock entry address necessary for exclusive control from the number of processors connected to the system. Store in the unit 21.
When executing exclusive control, the lock entry valid information stored in the cache information storage unit 21 is used as exclusive control information (step S4).

In the exclusive control in the present embodiment, as shown in FIG. 3, a lock address is acquired for each cache block (locking as exclusive control is performed). That is, in the embodiment of the present invention, the lock addresses corresponding to the cache block are generated without using the lock addresses 2 and 4 in the conventional exclusive control described above with reference to FIG.
In the example illustrated in FIG. 3, a block capacity of 32 bytes and a maximum number of processors of 4 are illustrated as an example.

In this embodiment, the lock address corresponding to the cache block is used as the lock entry address as the lock entry address.
An example of acquiring the lock entry address according to this embodiment is shown in FIG.

  The exclusive control executing means 12 extracts an address corresponding to the address bit corresponding to the lock entry valid information stored in the cache information storage unit 21 when accessing the data access area 23 that needs exclusive control. Then, an entry corresponding to the cache block in the exclusive control area 22 is calculated. Further, since the number of entries in the exclusive control area 22 does not need to be secured for all cache blocks, it is only necessary to secure the same number of entries as the number of processors of the system that simultaneously accesses the memory as the maximum number of entries. When acquiring exclusive control, if the corresponding entry in the exclusive control area 22 is read and the lock acquisition state is “other than FF”, access to the data access area is suspended and a process or a process with high priority is suspended. Start up. If the lock is not acquired “FF”, “processor number” indicating that the corresponding entry in the exclusive control area is in the lock acquisition state is stored.

Next, the operation according to the present embodiment will be described in detail with reference to the drawings.
FIG. 5 is a diagram showing a layout example of the exclusive control area according to the present invention.

  In the following description of the operation, it is assumed that the cache block is 32 bytes. In the following description, the address bit width is 32 bits, the number of valid processors is four, and the processor numbers are 00 to 03.

When the cache entry address generation unit 11 is activated from the program storage unit 20 at the time of starting the system, the cache block is examined. When the cache entry address generation means 11 determines that the cache block of the cache 10 is 32 bytes, as shown in <Example 1> of FIG. 4, from the lower bits of the address of the cache block unit of the address bits for accessing the memory Cache information with the mask information of the effective bit of the lock entry address as 2 bits of 25 to 26 bits corresponding to the number of valid processors (if the number of processors is not the second factor, round up to the second factor) Store in the storage unit 21.
In the exclusive control area 22, entries necessary for exclusive control are secured for the number of valid processors in units of cache blocks. At this time, the lock acquisition state is initialized to the non-acquisition state “FF”.

Next, the exclusive control operation according to the present embodiment will be described with reference to the flowchart of FIG.
First, when exclusive control to an address (bits 25 to 26 = “00”) for accessing the data access area is executed by the processor “00”, the exclusive information is locked from the cache information storage unit 21 by the exclusive control execution means 12. The entry information (see <Example 2> in FIG. 4) is taken out and a lock entry address is generated (step S11).
When the exclusive control area 22 of the corresponding entry 00 is in the lock non-acquisition state “FF”, the lock acquisition state “00” is set. At this time, since the number of valid processors is four, a maximum of four lock entries are secured. At this time, the lock entry address is assumed to be 0, and the area other than the lock entry 00 shown in FIG. 5 is assumed to be in the lock acquisition state.

  In this state, when the exclusive control of the same address as the processor “00” is performed by the processor “01”, the corresponding entry 00 in the exclusive control area 22 is first read (step S12). At this time, since the entry 00 is already locked (“lock acquisition state”) (step S13; Yes), the acquisition of the lock is stopped, and a process with higher priority, such as other interrupt processing, is executed ( Step S14).

  When the execution of a process having a higher priority than the exclusive control for which an execution request has been made, such as the interrupt process, is completed (step S15; Yes), the process from step S12 described above is repeated again, and entry 00 becomes “lock acquisition state”. If not, as in step S11 described above, the exclusive control execution means 12 extracts the lock entry information from the cache information storage unit 21, generates a lock entry address for the processor "01", and generates the cache information storage unit 21. To store.

  If the processor “01” executes exclusive control to the address corresponding to the lock entry address (“01”) in a state where the entry “00” is in the “lock acquisition state” by the processor “00”, the lock is performed. Since it is in an unacquired state, lock acquisition is possible.

  Next, the operation when a failure occurs in one processor will be described with reference to the flowchart of FIG. In this description, it is assumed that a failure has occurred in the processor “00”.

  When the failure of the processor “00” is notified to the diagnosis device 3, four lock entries in the exclusive control area 22 are searched (step S21). Since the number of the processor in which the failure has occurred is stored in the lock entry 00, the diagnostic device 3 releases the lock in the lock entry information of the processor number (step S22).

  In this way, by performing exclusive control for each registered address of the cache block, access to the data access area 23 that requires exclusive control is completely suppressed, the cache residence rate is increased, and access conflict during exclusive control is prevented. By minimizing, the processing efficiency of the multiprocessor can be improved. It is also possible to perform optimum exclusive control according to the cache structure of the processor while maintaining the SW (software) binary code without having a dedicated processing unit necessary for speeding up the exclusive control.

As described above, according to the embodiment of the present invention described above, the following effects can be obtained.
The first effect is that the waiting time due to access contention for performing exclusive control can be minimized.
This is because exclusive control is performed in units of cache block registration addresses.

The second effect is that it is not necessary to provide a dedicated processing unit in the cache memory or the like for exclusive control.
This is because the exclusive control means can be realized as a program. For this reason, an unnecessary increase in hardware resources for performing exclusive control can be suppressed.

A third effect is that the cache block used in the exclusive control can be easily changed according to the cache structure, and can flexibly cope with the change in the cache structure.
This is because exclusive control is performed based on the calculated cache information.
In this way, lock instruction information is not registered in the processing unit in the cache memory in accordance with the cache structure, so that even if the cache capacity or entry changes, the hardware resource does not change. can do.

The fourth effect is that exclusive control suitable for the cache structure of the processor is possible without changing the SW execution file (binary code).
This is because the cache information of the processor is examined in advance and used as exclusive control information.

A fifth effect is that the number of cache blocks used in exclusive control can be minimized.
This is because the usage amount of the cache block necessary for exclusive control is calculated according to the number of processors.

  As described above, according to the embodiment of the present invention, when an access conflict due to exclusive control occurs, an interrupt or other processing is preferentially processed, so that a waiting time due to access conflict can be minimized.

  Also, as described above with reference to FIG. 3, since the lock address is acquired in units of cache blocks, it is possible to reliably prevent cache misses due to access competition to the same cache block.

  As another embodiment of the invention, a plurality of lock controls can be realized by using the empty bits of the lock entry address bits of the above-described embodiment as a lock type display.

  As described above, the embodiments of the present invention can be applied to uses such as improving the processing efficiency of a multiprocessor system. Further, the present invention can also be applied to uses such as a function for realizing exclusive control suitable for a processor without changing the binary code of the program.

Each of the above-described embodiments is a preferred embodiment of the present invention, and the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention.
For example, in the above-described embodiment, it has been described that four processors (calculation means) “00” to “03” are provided. However, the number of processors is not limited to this number as long as a plurality of processors are provided. Also good.

In each of the above-described embodiments, the program has been described as being stored in the program storage unit 20, but the present invention is not limited to this as long as it is a computer-readable recording medium. For example, a floppy (registered trademark) It may be stored in a disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, EEPROM, or the like.
That is, each function described above according to each embodiment of the present invention may be realized by a CPU or the like of various computer systems performing a process by a program supplied from the above-described recording medium.
In this case, the present invention is applied even when an information group including a program is supplied to the output device from the recording medium described above or from an external recording medium via a network.
That is, the program code itself read from the recording medium realizes the novel function of the present invention, and the recording medium storing the program code and the signal read from the recording medium constitute the present invention. It will be.

  According to the program according to the present invention, each function in the computer system as each embodiment according to the present invention described above can be realized by a computer controlled by the program.

It is a figure which shows the structural example of the computer system as embodiment of this invention. It is a flowchart which shows the access operation to the cache in this embodiment. It is a figure which shows the lock acquisition image in the exclusive control by this embodiment. It is a figure which shows the example of the lock entry address in this embodiment. It is a figure which shows the example of a layout of the exclusive control area | region by this embodiment. It is a flowchart which shows the exclusive control operation | movement by this embodiment. It is a flowchart which shows the operation | movement at the time of the failure generation by this embodiment. It is a figure which shows the lock acquisition image in the conventional exclusive control.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Processor 10 Cache 11 Cache entry address generation means 12 Exclusive control execution means 2 Storage device 20 Program storage portion 21 Cache information storage portion 22 Exclusive control area 23 Data access area 3 Diagnostic device

Claims (9)

A computer system having a plurality of calculation means and a function of performing exclusive control,
A cache entry address calculating means for calculating an entry address of the cache when there is no cache entry address;
Lock address setting means for setting a lock address for each cache block using the entry address calculated by the cache entry address calculation means when there is no cache entry address ;
When an access conflict occurs in which a lock acquisition request is made from another calculation means after the lock address is acquired by one calculation means and the lock acquisition state is set, the priority is given to the other calculation means. Priority processing execution means for executing the higher processing first ,
The cache entry address calculation means calculates the cache entry address according to the number of the plurality of calculation means and the cache block capacity measured by a measurement program for investigating the cache structure. .   2. The computer system according to claim 1, further comprising: a diagnostic device that releases a lock at a lock address set by the lock address setting unit when the occurrence of a failure is notified of the calculation unit in which the failure has occurred. . Provided with an exclusive control area used for exclusive control in the storage means,
3. The computer system according to claim 1, wherein the exclusive control area sets the number of the plurality of calculation means as a maximum number of entries. An exclusive control method in a system having a plurality of calculation means and a function of performing exclusive control,
A cache entry address calculating step for calculating an entry address of the cache when the entry address of the cache does not exist;
An exclusive control step in which a lock address in units of cache blocks is acquired by one calculation means using the entry address calculated in the cache entry address calculation step when there is no cache entry address, and a lock acquisition state is obtained;
Priority processing execution in which, when an access conflict occurs in which the lock acquisition request is made from the other calculation means at the lock address after the exclusive control step, the other calculation means executes the higher priority processing first. A process ,
In the cache entry address calculating step, the cache entry address is calculated according to the number of the plurality of calculation means and the cache block capacity measured by a measurement program for investigating the cache structure. Method.   5. The exclusive control method according to claim 4, further comprising a diagnostic step of releasing a lock at the lock address acquired in the exclusive control step for the calculation means in which the failure has been notified when the occurrence of the failure is notified. .   6. The exclusive control method according to claim 4, wherein, in the priority processing execution step, the number of the plurality of calculation units is set to the maximum number of entries for an exclusive control region used for exclusive control. An exclusive control program in a system having a plurality of calculation means and a function of performing exclusive control,
On the computer,
A cache entry address calculation process for calculating an entry address of the cache when there is no cache entry address;
An exclusive control process in which a lock address for each cache block is acquired by one calculation means using the entry address calculated in the cache entry address calculation process when a cache entry address does not exist, and a lock acquisition state is obtained;
Execution of priority processing in which, when an access conflict occurs in which the lock acquisition request is made from the other calculation means at the lock address after the exclusive control process, the other calculation means executes the higher priority processing first. to execute the processing,
In the cache entry address calculation process, the cache entry address is calculated according to the number of the plurality of calculation means and the cache block capacity measured by a measurement program for investigating the cache structure. program. 8. The computer according to claim 7, wherein when the occurrence of a failure is notified, the computer is caused to execute a diagnosis process for releasing the lock at the lock address acquired by the exclusive control process for the calculation means in which the failure has occurred. Exclusive control program.   9. The exclusive control program according to claim 7, wherein, in the priority process execution process, the number of the plurality of calculation units is set to the maximum number of entries for an exclusive control area used for exclusive control.

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