JP4188492B2 - Dynamic focus circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a CRT for a television receiver and a display device, and more particularly to a dynamic focus circuit in a device having a function of changing the deflection width of either one of horizontal and / or vertical.
[0002]
[Prior art]
FIG. 3 shows an example of a conventional dynamic focus circuit. A portion surrounded by a broken line is a part of the flyback transformer (FBT) 1, and a bias voltage (high voltage on the order of several KV) when applying the dynamic focus signal (DF) to the grid terminal (GT) of the CRT is shown. Only the circuit part which generate | occur | produces is shown.
[0003]
In this FBT circuit section, a high voltage pulse is generated by the high voltage wires L1, L2, L3 and the rectifier diodes D1, D2, D3, Dn, and a DC high voltage is obtained on the cathode side of the diode Dn due to the distributed capacitance (not shown). Further, bleeder resistors R1, VR, and R2 are provided between the ground side (GND) and a predetermined bias voltage is set at the center of the semi-fixed resistor (VR). A dynamic focus signal amplified via the coupling capacitor C1 is superimposed on the bias voltage and applied to the grid terminal.
[0004]
For the dynamic focus signal, a horizontal correction signal and a vertical correction signal obtained by mixing a parabolic wave and a sawtooth wave at a certain ratio in each of a horizontal period and a vertical period input from a synchronization signal processing circuit (not shown) are added by an adder 3. The added output is amplified to a large amplitude of several hundreds Vpp (peak-to-peak) by the dynamic focus amplifier 2. As described above, this dynamic focus signal is applied to one side of the coupling capacitor (the side that is not the semi-fixed resistor VR).
[0005]
FIG. 3 shows only parabolic components as horizontal and vertical correction signals for simplicity. The bias voltage and the dynamic focus signal described above must have appropriate values determined by the CRT used. Therefore, the parabolic wave, the sawtooth wave, and the bias voltage of the correction signal of the horizontal period and the vertical period are adjusted to be appropriate values at the grid terminal of the CRT by adjustment at the factory.
[0006]
FIG. 4 shows another example of a conventional dynamic focus circuit. As shown in the figure, this circuit is obtained by connecting a circuit in which a clamp diode Dc and a bias resistor Rc are connected in parallel to the circuit of FIG. 3 to a semi-fixed resistor VR. As will be described later, the lower end of the bias voltage is suppressed by clamping the lower end of the waveform of the dynamic focus signal by the clamp diode Dc and the bias resistor Rc.
[0007]
By the way, in recent television receivers, there are a wide range of display angles of view (16: 9) and (4: 3), and various display frequencies for personal computers have been variously used in the past. It is necessary to display a video signal of the number of pixels. Thus, in order to display various deflection widths on the same CRT and obtain an optimum focus in each, it is necessary to change the amplitude of the dynamic focus signal in accordance with the deflection width.
[0008]
On the other hand, the AC component of the dynamic focus signal can be changed at an appropriate change rate in conjunction with the amplitude of the dynamic focus signal in the synchronization signal processing circuit when the user performs an operation to change the deflection width (view angle). It can be easily realized. However, the DC component of the dynamic focus signal has a problem as described below.
[0009]
5A and 5B are waveform diagrams of voltages at the grid terminals. In the actual waveform, the horizontal and vertical components are superimposed, but since it is a linear addition, only one of them needs to be considered. As shown in (a) and (b), the amplitude is increased by the synchronization signal processing circuit in proportion to the deflection width. In this case, in order to keep the focus of the entire CRT tube surface at an appropriate value, Thus, it is necessary to keep the DC potential at the center of the screen (the lowest end of the parabolic wave opened upward) so as not to fluctuate. However, in the configuration of FIG. 3, when the amplitude of the dynamic focus signal is changed, the lowest end of the parabolic wave fluctuates as shown in FIG. 5A, and as a result, the focus of the entire tube surface is shifted. This causes a problem.
[0010]
Even if there is such a problem, conventionally, even when the deflection width is changed, even if the amplitude of the dynamic focus signal is kept at a fixed value or is changed in conjunction with the change of the deflection width. The main design is to use the characteristics shown in FIG. 5A without any countermeasures, or to allow a focus shift.
On the other hand, there is a configuration shown in FIG. 4 as an example of a circuit configuration of an apparatus that requires relatively high definition. In the circuit of FIG. 4, by using the center of the semi-fixed resistor (VR), the lower end of the waveform of the dynamic focus signal is clamped to obtain a characteristic that does not change the lowermost end as shown in FIG. 5B. . In the configuration of FIG. 4, a clamp diode Dc and a bias resistor Rc are connected in parallel between the FBT circuit portion of FIG. 3 and the coupling capacitor. With this configuration, the deflection width can be changed without causing a focus shift.
[0011]
[Problems to be solved by the invention]
However, the circuit configuration of FIG. 4 has a price problem. That is, since the semi-fixed resistor VR and the clamp diode Dc are connected to the high voltage portion of several KV of the FBT circuit portion 1 and dangerous, it is necessary to fill with the insulating material built in the FBT circuit portion 1. However, in general, the FBT is a dedicated component supplied with a common built-in component and based on the mass production effect. Therefore, the FBT with a special specification in which the clamp diode Dc and the bias resistor Rc are filled with an insulating material is added. However, it was not always easily available at a low price. Therefore, the configuration of FIG. 4 has a problem in terms of price, which is a big problem in the product field where price competition is intense. Therefore, there has been a demand for an inexpensive circuit countermeasure to replace the configuration of FIG.
[0012]
The object of the present invention has been made in view of the above problems, and in a high-definition television receiver or display device with a variable deflection width, even if the deflection width is changed without requiring a special specification for the FBT. An object of the present invention is to provide an inexpensive dynamic focus circuit that does not cause a focus shift.
[0013]
[Means for Solving the Problems]
According to the present invention, a flyback transformer FBT that generates a DC high voltage to apply a dynamic focus signal to a grid terminal of a CRT, and a high-voltage divided by a bleeder resistor to generate a bias voltage suitable for the CRT. In a dynamic focus circuit including at least a coupling capacitor C1 for superimposing an AC waveform of the dynamic focus signal and a dynamic focus amplifier 2 that is input to the coupling capacitor and outputs a dynamic focus signal having a large amplitude suitable for a CRT. ,
Dynamic focus DC correction means 4 for controlling the voltage on the ground side of the bleeder resistor so as to obtain an appropriate bias voltage at the grid terminal GT based on the dynamic focus signal DF from the dynamic focus amplifier 2 is provided. Features.
[0014]
Preferably, the dynamic focus DC correction unit receives a dynamic focus signal from the dynamic focus amplifier, receives an average value detection unit 41 for detecting a voltage average value thereof, and a bias voltage from the average value detection unit, A DC inversion amplifying unit 42 for obtaining a DC inversion output in comparison with the ground potential;
The DC bias voltage generated in the dynamic focus signal of the grid terminal when the voltage on the ground side of the bleeder resistor is controlled by the output voltage from the DC inversion amplifier 42 and the deflection width of the display field angle of the CRT changes. Correct the deviation.
[0015]
More preferably, the average value detection unit 41 is connected between a capacitor C5 that receives a dynamic focus signal from the dynamic focus amplifier at one end, and the other end of the capacitor C5 and the ground side. A resistor R5, a diode D5 having a cathode connected to a common connection point of the capacitor C5 and the resistor R5, and a capacitor C6 connected between an anode side and a ground side of the diode D5. The average value voltage is output from the common connection point of D5 and capacitor C6.
[0016]
More preferably, the DC inversion amplifying unit 42 connects a resistor R6 received at one end receiving the average value voltage from the average value detecting unit 41 and the other end of the resistor R6 to a negative terminal. A differential amplifier 421 having a positive terminal grounded; and a resistor R7 connected to the output side of the differential amplifier 421 and the other end of the resistor R6. The output side of the differential amplifier is connected to the bleeder. The ground side of the resistor is connected.
[0017]
More preferably, the bleeder resistor includes a resistor R1, a semi-fixed resistor VR, and a resistor R2 connected in series, an adjustment terminal of the semi-fixed resistor VR is connected to the grid terminal, and the other end of the resistor R2 Is connected to the dynamic focus DC correction means,
When the combined resistance of the resistor up to the adjustment terminal of the semi-fixed resistor VR and the resistor R1 is Rt, and the combined resistance of the resistor up to the adjustment terminal of the semi-fixed resistor VR and the resistor R2 is Ru, Resistor R6 and resistor R7 are
R7 / R6 = (Rt + Ru) / Rt
Selected to meet.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a dynamic focus circuit including a dynamic focus DC correction circuit according to the present invention. As shown in the figure, in the present invention, a dynamic focus DC correction circuit 4 is newly added to the ground side (GND) of the bleeder resistors R1, VR, R2 of the FBT circuit unit 1 as shown in the circuit configuration of FIG. It is something to add.
[0019]
The dynamic focus DC correction circuit 4 receives the dynamic focus signal DF from the dynamic focus focus amplifier 2, detects the DC bias voltage (average value of the waveform), amplifies the DC, and lowers the bleeder resistance (ground side). To control the voltage. The output characteristics shown in FIG. 5B are obtained from the grid terminal by controlling the lower end voltage.
[0020]
FIG. 2 is a detailed configuration diagram as an embodiment of the dynamic focus DC correction circuit of FIG. As shown in the figure, the dynamic focus DC correction circuit 4 of the present invention is composed of two blocks including an average value detection unit 41 and a DC inversion amplification unit 42.
The average value detection unit 41 receives a dynamic focus signal from the dynamic focus amplifier 2 and rebias it to 0 (V) by the capacitor D5 and the resistor R5. In the waveform at the connection point of C5 and R5 shown in the figure, the potential portion of “V”, which is a potential portion below GND (portion below 0 (V)) reflects necessary bias voltage information. Is detected and held by a diode D5 connected to the connection point in the direction shown in the figure, a capacitor C6 connected to the other end of the diode D5 and GND.
[0021]
Next, in the DC inverting amplifier 42, the “V” voltage is input to the negative terminal on the input side of the differential amplifier 421 via the resistor R6, and compared with the GND potential input to the positive terminal, and the resistor R6. , R7 to obtain a DC inverted output voltage.
Here, the resistors R6 and R7 are between resistance values Rt and Ru from both ends of the bleeder resistor in the FBT to the semi-fixed resistor VR,
R7 / R6 = (Rt + Ru) / Rt (1)
The resistance values of the resistors R6 and R7 are selected so that the relationship satisfying In this case, the correction error is smaller when the center of the semi-fixed resistor VR is closer to the VR position after the final dynamic focus adjustment.
[0022]
With such a configuration, when the “V” voltage fluctuates by adjusting the amplitude of the dynamic focus signal, the lower end voltage of the bleeder resistor is corrected, and the waveform change in the form of FIG. Even when the width is changed, a dynamic focus voltage without a focus shift can be obtained.
[0023]
【The invention's effect】
According to the present invention, in a conventional CRT system television receiver or display device, in many cases, a shift in dynamic focus occurs in principle in response to diversification of display angle of view (deflection width in CRT). Even so, it was acceptable. However, this shift in focus has become unacceptable as the resolution of the display device increases. According to the present invention, when the deflection width is varied, the conventional FBT can be used as it is to correct the DC shift of the dynamic focus, and high definition can be dealt with.
[Brief description of the drawings]
FIG. 1 shows a dynamic focus circuit including a dynamic focus DC correction circuit according to the present invention.
2 is a detailed configuration diagram as an embodiment of the dynamic focus DC correction circuit of FIG. 1; FIG.
FIG. 3 is an example of a conventional dynamic focus circuit.
FIG. 4 is another example of a conventional dynamic focus circuit.
FIGS. 5A and 5B are waveform diagrams of grid terminal voltages. FIG.
[Explanation of symbols]
1 ... Flyback transformer (FBT)
2 ... dynamic focus amplifier 3 ... adder 4 ... dynamic focus DC correction circuit 41 ... average value detection unit 42 ... DC inversion amplification unit

Claims (5)

A flyback transformer that generates a DC high voltage to apply a dynamic focus signal to the grid terminal of the CRT, and a high-voltage divided by a bleeder resistor to generate a bias voltage suitable for the CRT, and an AC waveform of the dynamic focus signal In a dynamic focus circuit including at least a coupling capacitor for superimposing and a dynamic focus amplifier that outputs a dynamic focus signal that is input to the coupling capacitor and has a large amplitude suitable for a CRT,
Dynamic focus DC correction means for controlling a voltage on the ground side of the bleeder resistor so as to obtain an appropriate bias voltage at the grid terminal based on a dynamic focus signal from the dynamic focus amplifier. Focus circuit. The dynamic focus DC correction means includes:
An average value detection unit that inputs a dynamic focus signal from the dynamic focus amplifier and detects the voltage average value;
A DC inversion amplification unit that receives an average value bias voltage from the average value detection unit and compares it with a ground potential to obtain a DC inversion output;
When the voltage on the ground side of the bleeder resistor is controlled by the DC inversion output voltage from the DC inversion amplification unit and the deflection width of the display field angle of the CRT changes, the DC generated in the dynamic focus signal at the grid terminal The dynamic focus circuit according to claim 1, wherein a deviation in bias voltage is corrected. The average value detection unit includes a capacitor (C5) that receives a dynamic focus signal from the dynamic focus amplifier at one end, and a resistor connected between the other end of the capacitor (C5) and the ground side. (R5), a diode (D5) having a cathode connected to a common connection point of the capacitor (C5) and the resistor (R5), and a capacitor connected between the anode side and the ground side of the diode (D5) The dynamic focus circuit according to claim 2, wherein an average value voltage is output from a common connection point between the diode (D5) and the capacitor (C6). The DC inversion amplifying unit connects a resistor (R6) received at one end receiving the average value voltage from the average value detecting unit and the other end of the resistor (R6) to a negative terminal to connect the positive side A differential amplifier having a terminal grounded, and an output side of the differential amplifier and a resistor (R7) connected to the other end of the resistor (R6). The output side of the differential amplifier is connected to the bleeder. The dynamic focus circuit according to claim 2, wherein the ground side of the resistor is connected. The bleeder resistor includes a resistor (R1), a semi-fixed resistor (VR), and a resistor (R2) connected in series, and an adjustment terminal of the semi-fixed resistor (VR) is connected to the grid terminal, and the resistor (R2) ) Is connected to the dynamic focus DC correction means,
The combined resistance of the resistor up to the adjustment terminal of the semi-fixed resistor (VR) and the resistor (R1) is Rt, and the combined resistance of the resistor up to the adjustment terminal of the semi-fixed resistor (VR) and the resistor (R2). Where Ru is the resistance (R6) and resistance (R7)
R7 / R6 = (Rt + Ru) / Rt
The dynamic focus circuit according to claim 4, which is selected so as to satisfy

Images