JP4181363B2 - Nonvolatile semiconductor memory device and data writing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to a nonvolatile semiconductor memory device, and particularly relates to a nonvolatile semiconductor memory device that stores a plurality of data levels.
[Prior art]
In a nonvolatile semiconductor memory device, when writing is performed to a memory cell to be written by a program operation, charges are injected into the floating gate of the memory cell transistor, and the threshold voltage rises. As a result, even when a voltage equal to or lower than the threshold is applied to the gate, no current flows, and a state where data “0” is written is achieved. In general, there are variations in the threshold voltage and write speed of memory cells in the erased state. Accordingly, when a program operation is performed by applying a predetermined write voltage and the threshold voltage is verified so as to be equal to or higher than the verify level, the threshold voltage of the memory cell after writing has a certain distribution above the verify level.
[0002]
In general, the program is simultaneously executed for a large number of memory cells (for example, 1024 bytes: 4096 in the case of 4-bit multilevel of 2 bits / cell). Therefore, for 4096 bit lines, data indicating “write / not write” is previously loaded into the page buffer. The verification is to determine whether or not the threshold value of these cells has become higher than the verification level threshold value. When the threshold value becomes higher than the verification level threshold value, the verification is OK. Thereafter, data indicating “not written” is assigned to the bit line so that the threshold value does not shift any more when the memory cells that are not verified are continuously written. Therefore, the threshold value is fixed to the cell that has been verified OK at that time.
[0003]
In the case of a non-volatile semiconductor memory device having multi-level memory cells that express multi-levels by setting memory cells to different threshold voltages, if the threshold voltage has a wide distribution, the interval between adjacent level values is narrow. It becomes difficult to perform reliable data recording. Therefore, it is desirable to achieve as narrow a threshold voltage distribution as possible.
[0004]
For example, in a multi-level memory cell having a bit distribution of 4 levels, there are four levels of values, Erase, Level 0, Level 1, and Level 2.
[0005]
In order to write four levels of data, for example, data is first loaded into the page buffer, and data is stored in the write buffer WB for the write target memory cells of Level 0 to Level 2. Program and verify are executed for the write target memory cell using the Level 0 potential pulse, and Level 0 is written. Next, with respect to the write target memory cells of Level 1 and Level 2, program and verify are executed using the potential pulse of Level 1, and Level 1 is written. Finally, programming and verifying are performed for the memory cell to be written with Level 2 using the potential pulse of Level 2, and writing with Level 2 is executed.
[Problems to be solved by the invention]
In the above write operation, the write speed and the threshold voltage distribution are in conflict with each other.
[0006]
First, regarding the writing speed, it is preferable that the writing operation can be completed in as short a time as possible. For this purpose, it is desirable to use a large step voltage when the program voltage is increased step by step in the write operation. However, when a large step voltage is used, there is a problem in that the threshold voltage distribution after the end of writing becomes wider than when the threshold voltage is set in small increments using a small step voltage. As described above, when the threshold voltage has a wide distribution, there is a problem that the interval between adjacent level values becomes narrow and it is difficult to perform reliable data recording. Conversely, when a small step voltage is used to narrow the threshold voltage distribution, there is a problem that the writing speed is slowed and the operation efficiency is deteriorated.
[0007]
In view of the above, an object of the present invention is to provide a nonvolatile semiconductor memory device that can complete a write operation in a short time and can generate a relatively narrow threshold voltage distribution.
[Means for Solving the Problems]
A non-volatile semiconductor memory device according to the present invention includes a memory cell array including non-volatile memory cells, a write circuit for writing different levels of data into the memory cell, and the write circuit by controlling the write circuits. One of the levels is a write target, and the first write operation is performed on a write target memory cell corresponding to the write target level and all levels greater than the write target. The write voltage is executed while increasing by the first step voltage, and the write voltage at the timing when at least one threshold voltage of the write target memory cell exceeds the verify voltage is stored while executing the first write operation. And storing the first write operation and the write voltage in each of the plurality of levels. For , Sequentially from the lowest to the highest After running, the multiple levels One level is set as a write target, and the memory cell corresponding to the write target level is set in the memory cell. Starting from a voltage determined based on the stored write voltage, the write voltage is increased by a second step voltage smaller than the first step voltage to execute a second write operation. The second write operation is sequentially executed from the lowest of the plurality of levels to the higher A control circuit is included.
[0008]
In the nonvolatile semiconductor memory device, first, a rough threshold distribution is formed by executing a write operation using a large step voltage, and then a threshold distribution is obtained by executing a write operation using a small step voltage. It becomes possible to shape the width. At this time, by storing the write voltage when the rough threshold distribution is formed, the write start voltage at the time of programming using a small step voltage can be set to an appropriate value. Therefore, in the present invention, the write operation can be completed in a short time and a threshold distribution having a desired width can be formed.
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0009]
FIG. 1 is a flowchart showing a first embodiment of a write operation to a multilevel memory cell according to the present invention. FIG. 1 corresponds to a case where the bit distribution has four levels. FIG. 2 is a diagram showing a bit distribution when executing writing into a memory cell in the flowchart of FIG.
[0010]
FIG. 2A is a diagram illustrating a bit distribution to be achieved after executing writing of a memory cell. Here, the horizontal axis indicates the threshold voltage of the memory cell transistor, and the vertical axis indicates the number of bits (number of memory cells). As shown in FIG. 2A, after writing, there are four levels of values E (Erase), L0 (Level 0), L1 (Level 1), and L2 (Level 2). Here, the left threshold of the level L0 distribution is V0_2 (eg, 0.4V), the left threshold of the level L1 distribution is V1_2 (eg, 1.3V), and the left threshold of the level L2 distribution is V2_2 (eg, 2.V). 3V). The spread of each distribution is assumed to be 0.3V.
[0011]
Referring to the flowchart of FIG. 1, in step ST1, an initial voltage Vstart, which is the first voltage applied to the word line during programming, is determined from the cell write characteristics of the memory cell transistor and the word line write characteristics, and the program voltage Vpg is set. Set to initial voltage Vstart. N is initialized to 0.
[0012]
In step ST2, the verify is executed with the verify voltage V0_1 (for example, 0V). In step ST3, it is determined whether N is 1. In the initial state, since N is 0, the process proceeds to step ST4, and it is determined whether or not the threshold voltage of the write target cell exceeds the verify voltage V0_1. If not, the process proceeds to step ST5, and the write target cells of L0, L1, and L2 are programmed using the program voltage Vpg. Next, in step ST6, the program voltage Vpg is increased by the step voltage Vsp0 for L0. Here, Vsp0 is, for example, 0.5V. Since the maximum value of the target threshold distribution at level L0 is 0.7V, the threshold voltage after writing is set so as not to exceed 0.7V. The step voltage is 0.5V with respect to the verify voltage of 0V. Is set, the threshold voltage does not exceed 0.7V.
[0013]
Thereafter, the process returns to step ST2, and the above processing is repeated until even one write target cell exceeds the verify voltage V0_1, that is, until the determination in step ST4 becomes Yes. FIG. 2B shows a state immediately before the write target cell exceeds the verify voltage V0_1.
[0014]
If even one write target cell exceeds the verify voltage V0_1, the process proceeds to step ST7, and a voltage obtained by subtracting the step voltage Vsp0 from the program voltage Vpg is stored as the set voltage VS0. Here, the step voltage Vsp0 is reduced because the step voltage Vsp0 is added after the program of step ST5. Therefore, the set voltage VS0 stored here is a program voltage when the first cell exceeds the verify voltage V0_1. Actually, when the first write target cell passes verification, the number of pulses applied so far is stored. Also, by setting N = 1 in step ST7, it is set to skip steps ST4 and ST7 when the next loop is executed.
[0015]
Next, in step ST8, it is determined whether or not all the write target cells have passed the verification. If not, the program returns to step ST5 to execute the program operation, and the subsequent operations are repeated. If all cells pass in step ST8, the process proceeds to the next stage. FIG. 2C shows a state in which all the write target cells have passed the verification.
[0016]
In FIG. 1, step ST1 to step ST8 are collectively referred to as step 1, step 4 from step ST9 to step ST12 is collectively referred to as step 2, and step ST13 to step ST27 are collectively referred to as step 3.
[0017]
In step ST9, the step voltage Vsp1 for L1 is added to the stored setting voltage VS0 to set it as the program voltage Vpg. Here, Vsp1 is 1.0 V, for example. Next, in step ST10, the write target cells of L1 and L2 are programmed using the program voltage Vpg. Vsp1 is set to 1.0 V, but this may be set so that the maximum threshold after writing does not exceed the maximum value of the target threshold distribution of L1. Since the set voltage VS0 is a program voltage when the first cell exceeds the verify voltage V0_1 (0V), when programmed by adding Vsp1 (1.0V) to this voltage VS0, it is the cell having the highest threshold. However, it does not exceed 0.5V + 1.0V. FIG. 2D shows a state immediately after executing the program operation in step ST10.
[0018]
Verification is not necessary after the program operation in step ST10, but it may be executed. Further, the program operation may be executed twice or more, but in this case, the verify operation is essential. The verify voltage may be 0.6 V obtained by subtracting 1 V from the maximum value of the L1 target threshold.
[0019]
In step ST11, the step voltage Vsp2 for L2 is added to the program voltage Vpg to set it as the program voltage Vpg. Here, Vsp2 is set to 1.0 V, for example. Next, in step ST12, the write target cell of L2 is programmed using the program voltage Vpg. Vsp2 is set to 1.0 V, but this may be set so that the maximum threshold after writing does not exceed the maximum value of the target threshold distribution of L2. As in the case of L1, verification is not necessary after the program operation in step ST12, but it may be executed. FIG. 2E shows a state immediately after executing the program operation in step ST12.
[0020]
After the above operation, the last step 3 is executed. In step 3, as shown in FIG. 2E, three broad distributions roughly set for L0, L1, and L2 are converted into L0, L1, and L2 by fine program operation with a small step voltage. This is the step of shaping into a narrow distribution corresponding to.
[0021]
First, in step ST13, VS0 + Vsp1 + Vsp2-Vsp5 is set as the program voltage Vpg. At this time, since VS0 + Vsp1 + Vsp2 is a program voltage at the time of execution of step ST12, this voltage (actually, the number of applied pulses) may be stored and used for voltage setting in step ST13. Here, the step voltage Vsp5 is, for example, 0.2V. The step voltage Vsp5 may be set to a voltage that is small enough to achieve the desired width of the target threshold distribution.
[0022]
In step ST14, the verify is executed with the verify voltage V2_2, and in step ST15, it is determined whether or not the verify result is passed. If not passed, the process proceeds to step ST16, and the write target cell of L2 is programmed using the program voltage Vpg. Next, in step ST7, the program voltage Vpg is increased by the step voltage Vsp5. Thereafter, the process returns to step ST14 and the verify process is repeated. FIG. 2 (f) is a diagram showing a state in which the write operation for level L2 is completed.
[0023]
When the verification is passed and the writing of the level L2 is completed, the writing of the level L1 is executed in steps ST18 to ST22. The write operation is the same as that at the level L2. However, VS0 + Vsp1-Vsp4 is used as the initial setting value of the program voltage Vpg, and Vsp4 is set to 0.2 V, for example. FIG. 2G is a diagram showing a state where the write operation for level L1 is completed.
[0024]
When the writing of the level L1 is completed, the writing of the level L0 is executed in steps ST23 to ST27. The write operation is the same as that at the level L2. However, VS0-Vsp3 is used as the initial setting value of the program voltage Vpg, and Vsp3 is set to 0.2 V, for example. FIG. 2H shows a state in which the write operation for level L0 has been completed.
[0025]
Thus, the write operation for levels L0 to L2 is completed. Contrary to the above operation, when writing is started from L0 and L2 is written later, the L0 side receives program disturb and shifts to a higher threshold voltage. If writing is started from L2 and L0 is written later as in the above operation, the threshold values of the L0 and L1 cells are slightly shifted at the time of writing of L2, but thereafter the writing operation to L0 and L1 is executed. Therefore, the influence of the shift is almost eliminated.
[0026]
The step voltage is first reduced as the program start voltage, such as “−Vsp5” in step ST13, “−Vsp4” in step ST18, and “−Vsp3” in step ST23. Is as close to 0.2V as possible. Accordingly, in consideration of the maximum value of the threshold distribution and the program time, an adjustment may be made to reduce twice the step voltage or not at all.
[0027]
By the above operation, first, a rough threshold distribution is formed by executing a write operation for L0 to L2 using a large step voltage, and then a threshold value is generated by executing a write operation for L0 to L2 using a small step voltage. The distribution can be shaped to a desired width. By storing the program voltage when the rough threshold distribution is formed at this time, the program start voltage when programming using a small step voltage can be set to an appropriate value. Therefore, in the present invention, the write operation can be completed in a short time and a threshold distribution having a desired width can be formed.
[0028]
FIG. 3 is a flowchart showing a second embodiment of the write operation to the multilevel memory cell according to the present invention. FIG. 4 is a diagram showing a bit distribution when executing writing to the memory cell in the flowchart of FIG.
[0029]
FIG. 4A is a diagram showing a bit distribution to be achieved after executing writing of a memory cell. Here, the threshold value at the left end of the distribution of level L0 is V0_2 (eg, 0.6V), the threshold value at the left end of the distribution of level L1 is V1_2 (eg, 1.8V), and the threshold value at the left end of the distribution of level L2 is V2_2 (eg, 3.V). 2V). The spread of each distribution is assumed to be 0.4V.
[0030]
Referring to the flowchart of FIG. 3, steps ST1 to ST8 are the same as steps ST1 to ST8 of the first embodiment of FIG. The verify voltage V0_1 is 0 V, for example, and the step voltage Vsp0 is 0.75 V, for example. By this processing, a rough threshold distribution corresponding to the level L0 is formed for the write target cells L0 to L2. FIG. 4B shows a state immediately before the write target cell exceeds the verify voltage V0_1, and FIG. 4C shows a state in which a rough threshold distribution corresponding to the level L0 is formed.
[0031]
Steps ST9 to ST16 are the same as steps ST1 to ST8 in the first embodiment of FIG. The step voltage Vsp1 is set to, for example, 1.0 V with some margin in consideration that the difference between the maximum threshold voltage value of L1 of 2.2 V and the maximum threshold voltage value of L0 of 1.0 V is 1.2 V. . The verify voltage V1_1 is set to 1.0 V, for example, in consideration of the threshold voltage maximum value L2 of L1 and the step voltage 1.2V. The program start voltage is a voltage obtained by adding the step voltage Vsp1 to VS0 stored in step ST7. By this processing, a rough threshold distribution corresponding to the level L1 is formed for the write target cells of L1 and L2. FIG. 4D shows a state in which a rough threshold distribution corresponding to the level L1 is formed.
[0032]
Steps ST17 to ST24 are the same as steps ST1 to ST8 of the first embodiment of FIG. The step voltage Vsp2 is set to, for example, 1.25V with some margin in consideration that the difference between the maximum threshold voltage value of L2 of 3.6V and the maximum threshold voltage value of L0 of 2.2V is 1.4V. . The verify voltage V2_1 is set to, for example, 2.2V in consideration of the threshold voltage maximum value L2 of 3.6V and the step voltage 1.25V. The program start voltage is a voltage obtained by adding the step voltage Vsp2 to VS1 stored in step ST15. By this processing, a rough threshold distribution corresponding to the level L2 is formed for the write target cell of L2. FIG. 4E shows a state in which a rough threshold distribution corresponding to the level L2 is formed.
[0033]
In the second embodiment shown in FIG. 3, as will be described below, the second process of roughly forming the threshold distribution is executed, and before the final write operation for forming the desired threshold distribution, to some extent Processing for narrowing the width of the threshold distribution is performed. In FIG. 3, this process is step 2.
[0034]
Steps ST25 to ST32 are processes for narrowing the width of the threshold distribution corresponding to the level L1. The step voltage Vsp1_2 is set to 0.5 V, for example. The verify voltage V1_2 is set to 1.5 V, for example, in consideration of the threshold voltage maximum value L2 of L1 and the step voltage 0.5V. The program start voltage is a voltage obtained by adding the step voltage Vsp1_2 to VS1 stored in step ST15. By this processing, the threshold distribution corresponding to the level L1 is narrowed for the write target cell of L1. FIG. 4F shows a state in which the rough threshold distribution corresponding to the level L1 is narrowly formed.
[0035]
Steps ST34 to ST40 are processes for narrowing the width of the threshold distribution corresponding to the level L2. The step voltage Vsp2_2 is set to 0.5 V, for example. The verify voltage V2_2 is set to, for example, 2.9V in consideration of the threshold voltage maximum value L1 of 3.6V and the step voltage of 0.5V. The program start voltage is a voltage obtained by adding the step voltage Vsp2_2 to VS2 stored in step ST23. By this process, the threshold distribution corresponding to the level L2 is narrowed for the write target cell of L2. FIG. 4G shows a state in which the rough threshold distribution corresponding to the level L2 is narrowly formed.
[0036]
For the distribution corresponding to L0, the step voltage Vsp0 used at first is not as large as 0.75 V, so the process of forming a narrower rough threshold distribution is omitted.
[0037]
After the above processing, in step 3, the same write operation as in step 3 of FIG. 1 is executed. That is, three broad distributions roughly set for L0, L1, and L2 are shaped into narrow distributions corresponding to L0, L1, and L2 by a fine program operation with a small step voltage.
[0038]
In this writing process, the step voltages Vsp3, Vsp4, and Vsp5 to be used are set to 0.25V. The verify voltage is 0.6V for L0, 1.8V for L1, and 3.2V for L2. The program start voltage is set for L0, L1, and L2 using VS0 obtained in step ST7, VS1 obtained in step ST31, and VS2 obtained in step ST39, respectively.
[0039]
FIG. 4H is a diagram illustrating a state where the write operation is completed.
[0040]
With the above operation, first, a rough threshold distribution is formed by executing a write operation on L0 to L2 using a large step voltage, and then the threshold distribution is narrowed using an intermediate step voltage, and finally a small step voltage is formed. The threshold distribution can be shaped to a desired width by executing a write operation on L0 to L2 using. By storing the program voltage when the rough threshold distribution is formed at this time, the program start voltage when programming using a small step voltage can be set to an appropriate value. Therefore, in the present invention, the write operation can be completed in a short time and a threshold distribution having a desired width can be formed.
[0041]
FIG. 5 is a flowchart showing a third embodiment of the write operation to the multilevel memory cell according to the present invention. FIG. 6 is a diagram showing a bit distribution when executing writing into the memory cell in the flowchart of FIG.
[0042]
FIG. 6A is a diagram showing a bit distribution to be achieved after executing writing of a memory cell. Here, the left threshold of the level L0 distribution is V0_2 (eg, 0.6V), the left threshold of the level L1 distribution is V1_2 (eg, 1.8V), and the left threshold of the level L2 distribution is V2_2 (eg, 3.V). 2V). The spread of each distribution is assumed to be 0.4V.
[0043]
Referring to the flowchart of FIG. 5, in step ST1, an initial voltage Vstart, which is the first voltage applied to the word line during programming, is determined from the cell write characteristics of the memory cell transistor and the word line write characteristics, and the program voltage Vpg is set. Set to initial voltage Vstart.
[0044]
In step ST2, the verify is executed with the verify voltage V0_1 (for example, 0V). In step ST3, it is determined whether or not the threshold value of the write target cell exceeds the verify voltage V0_1. If not, the process proceeds to step ST4, and the write target cells of L0, L1, and L2 are programmed using the program voltage Vpg. Next, in step ST5, the program voltage Vpg is increased by the step voltage Vsp0 for L0. Here, Vsp0 is set to 0.75 V, for example, as in the second embodiment.
[0045]
Thereafter, the process returns to step ST2, and the above processing is repeated until even one write target cell exceeds the verify voltage V0_1, that is, until the determination in step ST3 is Yes. FIG. 6B shows a state immediately after the write target cell exceeds the verify voltage V0_1. If even one write target cell exceeds the verify voltage V0_1, the process proceeds to step ST6, and a voltage obtained by subtracting the step voltage Vsp0 from the program voltage Vpg is stored as the set voltage VS0.
[0046]
This completes the process for forming a rough threshold distribution for L0. As described above, since the process is completed in a state where even one cell to be written exceeds the verify voltage V0_1, as shown in FIG. 6B, there are many cells whose threshold is lower than the verify voltage V0_1.
[0047]
Steps ST7 to ST12 are the same processes as steps ST1 to ST6. As in the second embodiment, the step voltage Vsp1 is set to 1.0 V, for example, and the verify voltage V1_1 is set to 1.0 V, for example. The program start voltage is a voltage obtained by adding the step voltage Vsp1 to VS0 stored in step ST6. FIG. 2C shows a state in which steps ST7 to ST12 have been completed and a rough threshold distribution for L1 has been formed.
[0048]
Steps ST13 to ST18 are the same processes as steps ST1 to ST6. As in the second embodiment, the step voltage Vsp2 is set to 1.25V, for example, and the verify voltage V2_1 is set to 2.2V, for example. The program start voltage is a voltage obtained by adding the step voltage Vsp2 to VS1 stored in step ST12. FIG. 2D shows a state in which steps ST13 to ST18 have been completed and a rough threshold distribution for L2 has been formed.
[0049]
In the third embodiment shown in FIG. 5, as will be described below, the threshold distribution position is further changed to the final threshold distribution position by executing a second rough process of forming the threshold distribution. Keep it close. In FIG. 5, this process is step 2.
[0050]
The operation in step 2 in FIG. 5 (steps ST19 to ST36) is the same as the operation in step 1 in FIG. 5 (steps ST1 to ST18), and the details are omitted. The threshold voltage and verify voltage used are the same as the threshold voltage and verify voltage used in step 2 of the second embodiment of FIG. However, in FIG. 5, the process of narrowing the threshold distribution width is performed for L0. In this case, the step voltage Vsp0_2 is set to 0.5 V, for example, and the verify voltage V0_2 is set to 0.3 V, for example. . FIGS. 6E to 6G show how the threshold distribution is shifted by this processing.
[0051]
After the above processing, in step 3, the same write operation as in step 3 of FIG. 3 is executed. That is, three broad distributions roughly set for L0, L1, and L2 are shaped into narrow distributions corresponding to L0, L1, and L2 by a fine program operation with a small step voltage. At this time, the step voltage and verify voltage used are the same as those in the second embodiment. The program start voltage is set for L0, L1, and L2 using VS0 obtained in step ST24, VS1 obtained in step ST30, and VS2 obtained in step ST36, respectively.
[0052]
FIG. 6H is a diagram illustrating a state where the write operation is completed.
[0053]
By the above operation, first, a rough threshold distribution is formed by executing a write operation for L0 to L2 in two stages using a large step voltage, and then a write operation for L0 to L2 using a small step voltage. By executing, the threshold distribution can be shaped to a desired width. By storing the program voltage when the rough threshold distribution is formed at this time, the program start voltage when programming using a small step voltage can be set to an appropriate value. Therefore, in the present invention, the write operation can be completed in a short time and a threshold distribution having a desired width can be formed.
[0054]
FIG. 7 is a flowchart showing a fourth embodiment of the write operation to the multilevel memory cell according to the present invention. FIG. 8 is a diagram showing a bit distribution when executing writing of a memory cell in the flowchart of FIG.
[0055]
FIG. 8A is a diagram showing a bit distribution to be achieved after executing writing of a memory cell. Here, the threshold value at the left end of the distribution of level L0 is V0_2 (eg, 0.6V), the threshold value at the left end of the distribution of level L1 is V1_2 (eg, 1.8V), and the threshold value at the left end of the distribution of level L2 is V2_2 (eg, 3.V). 2V). The spread of each distribution is assumed to be 0.4V.
[0056]
Referring to the flowchart of FIG. 7, in step ST1, an initial voltage Vstart which is the first voltage applied to the word line at the time of programming is determined from the cell write characteristics of the memory cell transistor and the write characteristics of the word line, and the program voltage Vpg is set. Set to initial voltage Vstart. Also, N0, N1, and N2 are initialized to 0.
[0057]
In step ST2, the verify is executed with the verify voltage V0_1 (for example, 0V). In step ST3, it is determined whether N0 is 1. In the initial state, since N0 is 0, the process proceeds to step ST4, and it is determined whether or not the threshold voltage of the write target cell exceeds the verify voltage V0_1. If not, the process proceeds to step ST5, and the write target cells of L0, L1, and L2 are programmed using the program voltage Vpg. Next, in step ST6, the program voltage Vpg is increased by the step voltage Vsp_1. Here, Vsp_1 is set to 0.75 V, for example. This step voltage Vsp_1 is used in common for the programming operations of the levels L0 to L2, and accordingly, an appropriate value is set so as not to cause any problem for any of the levels L0 to L2.
[0058]
Thereafter, the process returns to step ST2, and the above processing is repeated until even one write target cell exceeds the verify voltage V0_1, that is, until the determination in step ST4 becomes Yes. FIG. 8B shows a state immediately before the write target cell exceeds the verify voltage V0_1.
[0059]
If even one write target cell exceeds the verify voltage V0_1, the process proceeds to step ST7, and a voltage obtained by subtracting the step voltage Vsp_1 from the program voltage Vpg is stored as the set voltage VS0. Further, by setting N0 = 1, it is set to skip steps ST4 and ST7 when the next loop is executed.
[0060]
Next, in step ST8, the verify is executed with the verify voltage V1_1 (for example, 1.2V). In step ST9, it is determined whether N1 is 1. In the initial state, since N1 is 0, the process proceeds to step ST10, and it is determined whether or not the threshold voltage of the write target cell exceeds the verify voltage V1_1. If not, the program returns to step ST5 to execute the program operation for the write target cells of L0, L1, and L2, and the subsequent steps are executed again. This operation is repeated until even one write target cell exceeds the verify voltage V1_1, that is, until the determination in step ST10 becomes Yes. FIG. 8C shows a state immediately after the write target cell exceeds the verify voltage V1_1.
[0061]
If even one write target cell exceeds the verify voltage V1_1, the process proceeds to step ST11, and a voltage obtained by subtracting the step voltage Vsp_1 from the program voltage Vpg is stored as the set voltage VS1. Further, by setting N1 = 1, it is set to skip steps ST10 and ST11 when the next loop is executed.
[0062]
Next, in step ST12, the verify is executed with the verify voltage V2_1 (for example, 2.6V). In step ST13, it is determined whether N2 is 1. In the initial state, since N2 is 0, the process proceeds to step ST14, where it is determined whether or not the threshold voltage of the write target cell exceeds the verify voltage V2_1. If not, the program returns to step ST5 to execute the program operation for the write target cells of L0, L1, and L2, and the subsequent steps are executed again. This operation is repeated until even one cell to be written exceeds the verify voltage V2_1, that is, until the determination in step ST14 becomes Yes. FIG. 8D shows a state immediately after the write target cell exceeds the verify voltage V2_1.
[0063]
If even one write target cell exceeds the verify voltage V2_1, the process proceeds to step ST15, and a voltage obtained by subtracting the step voltage Vsp_1 from the program voltage Vpg is stored as the set voltage VS2. Further, by setting N2 = 1, it is set to skip steps ST14 and ST15 when the next loop is executed.
[0064]
Next, in step ST16, it is determined whether or not all the write target cells have passed the verification. If not, the program returns to step ST5 to execute the program operation, and the subsequent operations are repeated. If all cells pass in step ST16, the process proceeds to the next stage. FIG. 2E shows a state in which all the write target cells pass the verification.
[0065]
After the above processing, in step 2, the write operation similar to step 3 in FIG. That is, by executing the write operation in the order of L0, L1, and L2, and executing a fine program operation with a small step voltage, the roughly set three broad distributions are shaped into corresponding narrow distributions. At this time, the step voltage and the verify voltage used are the same as those in the second embodiment except for the verify voltage of L0. The verify voltage of L0 is set lower by 0.05V in consideration of the influence of program disturb. The program start voltage is set for L0, L1, and L2 using VS0 obtained in step ST7, VS1 obtained in step ST11, and VS2 obtained in step ST15, respectively.
[0066]
FIG. 8F is a diagram showing a state where the write operation is completed.
[0067]
With the above operation, first, a rough threshold distribution is formed by collectively executing write operations for L0 to L2 using a large step voltage, and then a write operation for L0 to L2 is performed using a small step voltage. Thus, the threshold distribution can be shaped to a desired width. By storing the program voltage when the rough threshold distribution is formed at this time, the program start voltage when programming using a small step voltage can be set to an appropriate value. Therefore, in the present invention, the write operation can be completed in a short time and a threshold distribution having a desired width can be formed.
[0068]
FIG. 9 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device to which the present invention is applied.
[0069]
9 includes a control circuit 21, a command register 22, an I / O control circuit 23, an address register 24, a status register 25, a memory cell array 26, a row address decoder 27, a row address buffer 28, and a column decoder. 29, a data register 30, a sense amplifier 31, a column address buffer 32, a high voltage generation circuit 33, a logic control 34, and a ready / busy register 35.
[0070]
The logic control 34 receives control signals such as chip enable / CE, command latch enable CLE, address latch enable ALE, write enable / WE, read enable / RE, write protect / WP, spare area enable / SE from the outside, and these A logic control signal is supplied to the control circuit 21 based on the control signal.
[0071]
The I / O control circuit 23 exchanges input / output signals I / O0 to I / O7 with the outside. The I / O control circuit 23 receives an address signal, a data signal, and a command signal from the outside, and supplies the address signal to the address register 24, the data signal to the data register 30, and the command signal to the command register 22. The address register 24 supplies the row address to the row address buffer 28 and supplies the column address to the column address buffer 32.
[0072]
The control circuit 21 receives a logic control signal from the logic control 34 and also receives a command from the command register 22, operates as a state machine based on these logic control signal and command, and controls each part of the nonvolatile semiconductor memory device 20. Control the behavior.
[0073]
The control circuit 21 controls the memory cell array 26, the row address decoder 27, the column decoder 29, and the like in order to read data from the address of the memory cell array 26 indicated by the address register 24. In addition, the control circuit 21 controls the memory cell array 26, the row address decoder 27, the column decoder 29, and the like in order to write data to the write address of the memory cell array 26. In addition, the control circuit 21 controls the memory cell array 26, the row address decoder 27, the column decoder 29 and the like in order to erase the designated area of the memory cell array 26 in a predetermined unit. The write processing of the first to fourth embodiments described above is executed by the control circuit 21 controlling each circuit unit.
[0074]
The memory cell array 26 includes an array of memory cell transistors, word lines, bit lines, and the like, and stores data in each memory cell transistor. At the time of data reading, data from the memory cell specified by the activated word line is read to the bit line. At the time of programming or erasing, the word line and the bit line are set to appropriate potentials according to the respective operations, thereby executing the charge injection or charge extraction operation for the memory cells.
[0075]
The sense amplifier 31 operates under the control of the control circuit 21, and the data current supplied from the memory cell array 26 is compared with the reference current according to the designation by the row address decoder 27 and the column decoder 29, so that the data becomes 0. Or 1 is determined. The determination result is stored as read data in the data register 30 and is further supplied from the data register 30 to the I / O control circuit 23.
[0076]
Further, in the verify operation accompanying the program operation and the erase operation, the current of data supplied from the memory cell array 26 in accordance with the designation by the row address decoder 27 and the column decoder 29 is compared with the reference current for program verify and erase verify. Is done. In the program operation, write data is stored in the data register 30, and charge injection into the memory cell is executed by setting the word line and bit line of the memory cell array 26 to appropriate potentials based on this data. As will be described later, in the present invention, a circuit for detecting that even one write target cell exceeds the verify voltage is provided around the data register 30 and the sense amplifier 31.
[0077]
The status register 25 is a register that stores status information related to the operation of the nonvolatile semiconductor memory device 20. By reading the contents of the register from the outside via the I / O control circuit 23, whether the device is in a ready state or not It can be determined whether the mode is the write protection mode or the program / erase operation is in progress. The ready / busy register 35 stores a flag indicating whether the device is ready or busy, and in response to this, a ready / busy signal is output to the outside. The high voltage generation circuit 33 is a circuit that generates a high potential used for a program operation and an erase operation.
[0078]
FIG. 10 is a diagram showing the configuration around the page buffer used in the present invention.
[0079]
10 corresponds to a part of the memory cell array 26, sense amplifier 31, and data register 30 shown in FIG. 9, and includes a write / read circuit 41, a data latch 42, a data latch 43, and a write / read temporary latch 44. , A verify detection transistor 45, a capacitor 46, transistors 47 and 48, a plurality of switch circuits 49, a memory cell 50, a bit line BL, and a word line WL.
[0080]
At the time of data writing, 2-bit data is stored in the data latches 42 and 43 from the data bus via the switch circuit 49. By this 2-bit data, four levels of E, L0, L1, and L2 are expressed. Furthermore, a write instruction is stored in the write / read temporary latch 44 from the data bus via the switch circuit 49. That is, when the write operation is executed, the write / read temporary latch 44 is set so that the node NVp becomes HIGH.
[0081]
The write / read circuit 41 controls the potential of the bit line BL in accordance with the presence / absence of writing, and executes the program operation by applying the program voltage Vpg to the word line WL. Thereafter, a verify voltage is applied to the word line WL, and the write / read circuit 41 checks the data read from the bit line BL. When the verification is passed, the write / read circuit 41 pulls the node NVp to LOW, and accordingly the transistor 45 is turned off. The transistors 45 are wired NOR with respect to memory cells corresponding to one page of page buffer. When verification is passed for all the memory cells, all the transistors 45 are turned off, and the terminal VerifyOK / NG becomes HIGH.
[0082]
In the page buffer of FIG. 10, it is necessary to detect that the first cell has exceeded the verify potential in order to realize the first to fourth embodiments. The problem here is that the write / read temporary latch 44 is set so that the node NVp becomes LOW for a cell that is not a write target. That is, it is necessary to distinguish the state of being LOW.
[0083]
The circuit shown in FIG. 10 is configured to detect the state in which the verification is passed and the node NVp is LOW by cutting off the DC component of the node NVn by the capacitor 46 and detecting only the potential change. FIG. 11 is a timing waveform diagram showing an operation of detecting a change of node NVp to LOW in the circuit of FIG.
[0084]
As shown in FIG. 11A, the program operation is executed by applying a predetermined voltage Vpgm to the word line, and then the verify read (FIG. 11B) is executed by applying the verify voltage V_verify. In this verify operation, when the read data is passed and the node NVp (FIG. 11 (d)) becomes LOW, the node NVn (FIG. 11 (e)) becomes HIGH, and the node Ng ( The potential in FIG. 11 (f) increases. The potential of the node Ng is initially set to LOW in advance by setting Set_V_1stP (FIG. 11C) to HIGH to make the transistor 47 conductive. Therefore, when the potential of the node Ng rises as described above, the transistor 48 that has been off until then becomes conductive, and the terminal Verify_1stP becomes LOW.
[0085]
Therefore, by monitoring the potential of Verify_1stP, it is possible to detect that the first cell has exceeded the verify potential.
[0086]
As described above, in the present invention, by using the page buffer shown in FIG. 10, it is possible to detect a state in which even one cell has passed verification. Therefore, in response to this detection, the program voltage at that time (or information indicating the program voltage such as the number of applied pulses) is stored in the memory, and this information is used to obtain the desired voltage in a short time as described in the above embodiment. It is possible to form a threshold distribution having a width.
[0087]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
[0088]
The present invention includes the following contents.
(Supplementary note 1) a memory cell array including nonvolatile memory cells;
A write circuit for writing different levels of data into the memory cell;
By controlling the write circuit, the first write operation is executed while increasing the write voltage by the first step voltage with one of the plurality of levels as a write target, and the first write operation is executed. While storing the write voltage at a predetermined timing, starting from a voltage determined based on the stored write voltage with the one level as a write target, the write voltage is smaller than the first step voltage. Control circuit for increasing the step voltage by 2 and executing the second write operation
A non-volatile semiconductor memory device comprising:
(Supplementary note 2) The nonvolatile semiconductor memory device according to supplementary note 1, wherein the predetermined timing is a timing at which at least one threshold voltage of a memory cell to be written exceeds a predetermined verify voltage.
(Supplementary Note 3) A node provided for each memory cell, the potential of which changes when the threshold voltage of the corresponding memory cell exceeds the verify voltage;
Potential change detection circuit for detecting change in node potential
The nonvolatile semiconductor memory device according to appendix 2, further comprising:
(Appendix 4) The potential change detection circuit
A capacitor having a first end connected to the node;
Transistor whose gate is connected to the second end of the capacitor
The nonvolatile semiconductor memory device according to appendix 3, characterized by comprising:
(Supplementary Note 5) The control circuit sequentially executes the first write operation with respect to the plurality of levels, and then sequentially executes the second write operation with respect to the plurality of levels. The nonvolatile semiconductor memory device according to appendix 1, wherein a write voltage is different for each of the plurality of levels.
(Supplementary note 6) The control circuit further stores the write voltage at a predetermined timing while executing the second write operation, and determines the one level as a write target based on the further stored write voltage The nonvolatile semiconductor memory device according to appendix 1, wherein the third write operation is executed by starting from the voltage to be increased and increasing the write voltage by a third step voltage smaller than the second step voltage.
(Supplementary note 7) The nonvolatile semiconductor memory according to supplementary note 1, wherein the control circuit terminates the first write operation when at least one threshold voltage of a memory cell to be written exceeds a predetermined verify voltage. apparatus.
(Supplementary note 8) The nonvolatile semiconductor memory device according to supplementary note 1, wherein the control circuit sequentially executes the second write operation from a plurality of higher levels to a lower one.
(Supplementary note 9) The nonvolatile memory according to supplementary note 1, wherein the control circuit stores the write voltage with reference to a write voltage at a time when the first one of the memory cells to be written exceeds a predetermined verify voltage. Semiconductor memory device.
(Supplementary note 10) A method of writing different levels of data in a nonvolatile memory cell,
Executing a first write operation while increasing a write voltage by a first step voltage with one level of the plurality of levels as a write target;
Storing the write voltage at a predetermined timing while executing the first write operation;
Performing the first write operation and storing the write voltage for each of the plurality of levels;
Starting from a voltage determined based on the stored write voltage with a certain level as a write target, the write voltage is increased by a second step voltage smaller than the first step voltage to perform a second write operation Run
A data writing method comprising each step.
(Supplementary Note 11) The first write operation is sequentially performed on the plurality of levels, and then the second write operation is sequentially performed on the plurality of levels. The stored write voltage is the plurality of levels. The data writing method according to appendix 10, wherein the data writing method is different for each level.
(Supplementary Note 12) While executing the second write operation, the write voltage at a predetermined timing is further stored, and the one level is set as a write target, starting from a voltage determined based on the further stored write voltage The data writing method according to appendix 10, wherein the third write operation is executed by increasing the write voltage by a third step voltage smaller than the second step voltage.
(Supplementary note 13) The data writing method according to supplementary note 10, wherein the second write operation is sequentially executed from the plurality of higher levels to the lower level.
【The invention's effect】
In the nonvolatile semiconductor memory device according to the present invention, first, a rough threshold distribution is formed by executing a write operation using a large step voltage, and then a threshold distribution is generated by executing a write operation using a small step voltage. It becomes possible to shape to a desired width. At this time, by storing the write voltage when the rough threshold distribution is formed, the write start voltage at the time of programming using a small step voltage can be set to an appropriate value. Therefore, in the present invention, the write operation can be completed in a short time and a threshold distribution having a desired width can be formed.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a first embodiment of a write operation to a multilevel memory cell according to the present invention.
FIG. 2 is a diagram showing a bit distribution when executing writing to a memory cell in the flowchart of FIG. 1;
FIG. 3 is a flowchart showing a second embodiment of a write operation to a multi-level memory cell according to the present invention.
4 is a diagram showing a bit distribution at the time of executing writing of a memory cell in the flowchart of FIG. 3. FIG.
FIG. 5 is a flowchart showing a third embodiment of the write operation to the multi-level memory cell according to the present invention.
6 is a diagram showing a bit distribution when executing writing of a memory cell in the flowchart of FIG. 5; FIG.
FIG. 7 is a flowchart showing a fourth embodiment of the write operation to the multi-level memory cell according to the present invention.
FIG. 8 is a diagram showing a bit distribution when executing writing to a memory cell in the flowchart of FIG. 7;
FIG. 9 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device to which the present invention is applied.
FIG. 10 is a diagram showing a configuration around a page buffer used in the present invention.
11 is a timing waveform diagram showing an operation of detecting a change of node NVp to LOW in the circuit of FIG. 10;
[Explanation of symbols]
20 Nonvolatile semiconductor memory device
21 Control circuit
22 Command register
23 I / O control circuit
24 Address register
25 Status register
26 Memory cell array
27 Row address decoder
28 Row address buffer
29 Column decoder
30 Data register
31 sense amplifier
32 column address buffer
33 High voltage generator
34 Logic control
35 Ready / Busy Register

Claims (11)

A memory cell array including non-volatile memory cells;
A write circuit for writing different levels of data into the memory cell;
By controlling the write circuit, the first level is set to the write target memory cell corresponding to the write target level and all levels higher than the write target, with one level of the plurality of levels as the write target. The first write operation is executed while increasing the write voltage by a first step voltage, and at least one threshold value of the memory cell to be written is executed while the first write operation is executed. The write voltage at a timing when the voltage exceeds the verify voltage is stored, and the first write operation and the storage of the write voltage are changed from the lower one of the plurality of levels to the higher one for each of the plurality of levels. after sequentially executed, as write target one level among the plurality of levels, menu corresponding to the level of the write target Starting from the voltage determined based on the stored write voltage to write the voltage running second write operation is increased step voltage less than the second step voltage of said one by one in the Riseru, said 2. A nonvolatile semiconductor memory device comprising: a control circuit that sequentially executes the plurality of write operations from the lowest level to the higher level . A node whose potential changes when the threshold voltage of the corresponding memory cell provided for each memory cell exceeds the verify voltage;
The nonvolatile semiconductor memory device according to claim 1, further comprising a potential change detection circuit that detects a change in the node potential. The potential change detection circuit includes:
A capacitor having a first end connected to the node;
The nonvolatile semiconductor memory device according to claim 2, further comprising: a transistor having a gate connected to the second end of the capacitor.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the stored write voltage is different for each of the plurality of levels.   The control circuit further stores the write voltage at a timing when at least one threshold voltage of the memory cell to be written exceeds the verify voltage while executing the second write operation, and for each of the plurality of levels The third write operation is performed by starting from a voltage determined based on the further stored write voltage and increasing the write voltage by a third step voltage smaller than the second step voltage. The nonvolatile semiconductor memory device according to claim 1.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the control circuit ends the first write operation when at least one threshold voltage of a memory cell to be written exceeds a predetermined verify voltage.   6. The non-volatile semiconductor memory device according to claim 5, wherein the control circuit sequentially executes the third write operation from the plurality of higher levels to the lower levels.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the control circuit stores the write voltage with reference to the write voltage at the time when the first one of the memory cells to be written exceeds a predetermined verify voltage. . A method for writing different levels of data into a non-volatile memory cell,
A first write operation performed on a write target memory cell corresponding to the write target level and all levels greater than the write target, with one level of the plurality of levels as a write target, The write operation of 1 is executed while increasing the write voltage by the first step voltage,
Storing the write voltage at a timing when at least one threshold voltage of the memory cell to be written exceeds a verify voltage while executing the first write operation;
Sequentially executing the first write operation and storage of the write voltage for each of the plurality of levels from the lowest to the highest of the plurality of levels ;
One level of the plurality of levels is set as a write target , and a write voltage is applied to a memory cell corresponding to the write target level starting from a voltage determined based on the stored write voltage. A second write operation is executed by increasing a second step voltage smaller than the step voltage, and the second write operation includes steps for sequentially executing the plurality of levels from the lowest to the highest. How to write data. A memory cell array including non-volatile memory cells;
A write circuit for writing different levels of data into the memory cell;
By controlling the write circuit, a first write operation is performed on a write target memory cell corresponding to all of the plurality of levels by setting a minimum level among the plurality of levels as a write target. The write operation is performed while increasing the write voltage by a first step voltage, and at the timing when at least one threshold voltage of the write target memory cell exceeds the verify voltage while executing the first write operation. After storing the write voltage and executing the first write operation and the storage of the write voltage, one level other than the minimum level among the plurality of levels is set as a write target, and the level of the write target and the write In the memory cell to be written corresponding to all levels larger than the target, the stored write voltage is set to A fourth write operation is performed at a voltage determined in accordance with the fourth write operation, and the fourth write operation is performed on each of the levels other than the minimum level among the plurality of levels from the lowest to the highest of the plurality of levels. Are sequentially executed, and one level of the plurality of levels is set as a write target, and the memory cell corresponding to the write target level is written starting from a voltage determined based on the stored write voltage. A control for executing a second write operation by increasing the voltage by a second step voltage smaller than the first step voltage , and sequentially executing the second write operation from the higher one of the plurality of levels to the lower one A nonvolatile semiconductor memory device including a circuit. A method for writing different levels of data into a non-volatile memory cell,
A first write operation performed on a memory cell to be written corresponding to all of the plurality of levels by setting a minimum level among the plurality of levels as a write target, wherein the first write operation sets a write voltage to a first level. Execute while increasing the step voltage by
Storing the write voltage at a timing when at least one threshold voltage of the memory cell to be written exceeds a verify voltage while executing the first write operation;
The write voltage stored in the write target memory cell corresponding to the write target level and all levels greater than the write target, with one level other than the minimum level among the plurality of levels as the write target. A fourth write operation is performed at a voltage determined based on the second write operation, and the fourth write operation is performed from the lowest of the plurality of levels to each of the levels other than the minimum level of the plurality of levels. Run sequentially,
One level of the plurality of levels is set as a write target , and a write voltage is applied to a memory cell corresponding to the write target level starting from a voltage determined based on the stored write voltage. A second write operation is performed by increasing a second step voltage smaller than the step voltage, and the second write operation includes each step of sequentially executing the plurality of levels from the higher to the lower ones. How to write data.

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